adin1200_driver.h
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1 /**
2  * @file adin1200_driver.h
3  * @brief ADIN1200 Ethernet PHY driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _ADIN1200_DRIVER_H
32 #define _ADIN1200_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef ADIN1200_PHY_ADDR
39  #define ADIN1200_PHY_ADDR 0
40 #elif (ADIN1200_PHY_ADDR < 0 || ADIN1200_PHY_ADDR > 31)
41  #error ADIN1200_PHY_ADDR parameter is not valid
42 #endif
43 
44 //ADIN1200 PHY registers
45 #define ADIN1200_MII_CONTROL 0x00
46 #define ADIN1200_MII_STATUS 0x01
47 #define ADIN1200_PHY_ID_1 0x02
48 #define ADIN1200_PHY_ID_2 0x03
49 #define ADIN1200_AUTONEG_ADV 0x04
50 #define ADIN1200_LP_ABILITY 0x05
51 #define ADIN1200_AUTONEG_EXP 0x06
52 #define ADIN1200_TX_NEXT_PAGE 0x07
53 #define ADIN1200_LP_RX_NEXT_PAGE 0x08
54 #define ADIN1200_MSTR_SLV_STATUS 0x0A
55 #define ADIN1200_EXT_STATUS 0x0F
56 #define ADIN1200_EXT_REG_PTR 0x10
57 #define ADIN1200_EXT_REG_DATA 0x11
58 #define ADIN1200_PHY_CTRL_1 0x12
59 #define ADIN1200_PHY_CTRL_STATUS_1 0x13
60 #define ADIN1200_RX_ERR_CNT 0x14
61 #define ADIN1200_PHY_CTRL_STATUS_2 0x15
62 #define ADIN1200_PHY_CTRL_2 0x16
63 #define ADIN1200_PHY_CTRL_3 0x17
64 #define ADIN1200_IRQ_MASK 0x18
65 #define ADIN1200_IRQ_STATUS 0x19
66 #define ADIN1200_PHY_STATUS_1 0x1A
67 #define ADIN1200_LED_CTRL_1 0x1B
68 #define ADIN1200_LED_CTRL_2 0x1C
69 #define ADIN1200_LED_CTRL_3 0x1D
70 #define ADIN1200_PHY_STATUS_2 0x1F
71 
72 //ADIN1200 Extended registers
73 #define ADIN1200_EEE_CAPABILITY 0x8000
74 #define ADIN1200_EEE_ADV 0x8001
75 #define ADIN1200_EEE_LP_ABILITY 0x8002
76 #define ADIN1200_EEE_RSLVD 0x8008
77 #define ADIN1200_MSE_A 0x8402
78 #define ADIN1200_FLD_EN 0x8E27
79 #define ADIN1200_FLD_STAT_LAT 0x8E38
80 #define ADIN1200_RX_MII_CLK_STOP_EN 0x9400
81 #define ADIN1200_PCS_STATUS_1 0x9401
82 #define ADIN1200_FC_EN 0x9403
83 #define ADIN1200_FC_IRQ_EN 0x9406
84 #define ADIN1200_FC_TX_SEL 0x9407
85 #define ADIN1200_FC_MAX_FRM_SIZE 0x9408
86 #define ADIN1200_FC_FRM_CNT_H 0x940A
87 #define ADIN1200_FC_FRM_CNT_L 0x940B
88 #define ADIN1200_FC_LEN_ERR_CNT 0x940C
89 #define ADIN1200_FC_ALGN_ERR_CNT 0x940D
90 #define ADIN1200_FC_SYMB_ERR_CNT 0x940E
91 #define ADIN1200_FC_OSZ_CNT 0x940F
92 #define ADIN1200_FC_USZ_CNT 0x9410
93 #define ADIN1200_FC_ODD_CNT 0x9411
94 #define ADIN1200_FC_ODD_PRE_CNT 0x9412
95 #define ADIN1200_FC_DRIBBLE_BITS_CNT 0x9413
96 #define ADIN1200_FC_FALSE_CARRIER_CNT 0x9414
97 #define ADIN1200_FG_EN 0x9415
98 #define ADIN1200_FG_CNTRL_RSTRT 0x9416
99 #define ADIN1200_FG_CONT_MODE_EN 0x9417
100 #define ADIN1200_FG_IRQ_EN 0x9418
101 #define ADIN1200_FG_FRM_LEN 0x941A
102 #define ADIN1200_FG_IFG_LEN 0x941B
103 #define ADIN1200_FG_NFRM_H 0x941C
104 #define ADIN1200_FG_NFRM_L 0x941D
105 #define ADIN1200_FG_DONE 0x941E
106 #define ADIN1200_FIFO_SYNC 0x9427
107 #define ADIN1200_SOP_CTRL 0x9428
108 #define ADIN1200_SOP_RX_DEL 0x9429
109 #define ADIN1200_SOP_TX_DEL 0x942A
110 #define ADIN1200_DPTH_MII_BYTE 0x9602
111 #define ADIN1200_LPI_WAKE_ERR_CNT 0xA000
112 #define ADIN1200_B_10_E_EN 0xB403
113 #define ADIN1200_B_10_TX_TST_MODE 0xB412
114 #define ADIN1200_B_100_TX_TST_MODE 0xB413
115 #define ADIN1200_CDIAG_RUN 0xBA1B
116 #define ADIN1200_CDIAG_XPAIR_DIS 0xBA1C
117 #define ADIN1200_CDIAG_DTLD_RSLTS_0 0xBA1D
118 #define ADIN1200_CDIAG_DTLD_RSLTS_1 0xBA1E
119 #define ADIN1200_CDIAG_FLT_DIST_0 0xBA21
120 #define ADIN1200_CDIAG_FLT_DIST_1 0xBA22
121 #define ADIN1200_CDIAG_CBL_LEN_EST 0xBA25
122 #define ADIN1200_LED_PUL_STR_DUR 0xBC00
123 
124 //ADIN1200 Subsystem registers
125 #define ADIN1200_GE_SFT_RST 0xFF0C
126 #define ADIN1200_GE_SFT_RST_CFG_EN 0xFF0D
127 #define ADIN1200_GE_CLK_CFG 0xFF1F
128 #define ADIN1200_GE_RGMII_CFG 0xFF23
129 #define ADIN1200_GE_RMII_CFG 0xFF24
130 #define ADIN1200_GE_PHY_BASE_CFG 0xFF26
131 #define ADIN1200_GE_LNK_STAT_INV_EN 0xFF3C
132 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL 0xFF3D
133 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL 0xFF3E
134 #define ADIN1200_GE_IO_INT_N_OR_CNTRL 0xFF3F
135 #define ADIN1200_GE_IO_LED_A_OR_CNTRL 0xFF41
136 
137 //MII Control register
138 #define ADIN1200_MII_CONTROL_SFT_RST 0x8000
139 #define ADIN1200_MII_CONTROL_LOOPBACK 0x4000
140 #define ADIN1200_MII_CONTROL_SPEED_SEL_LSB 0x2000
141 #define ADIN1200_MII_CONTROL_AUTONEG_EN 0x1000
142 #define ADIN1200_MII_CONTROL_SFT_PD 0x0800
143 #define ADIN1200_MII_CONTROL_ISOLATE 0x0400
144 #define ADIN1200_MII_CONTROL_RESTART_ANEG 0x0200
145 #define ADIN1200_MII_CONTROL_DPLX_MODE 0x0100
146 #define ADIN1200_MII_CONTROL_COLTEST 0x0080
147 #define ADIN1200_MII_CONTROL_SPEED_SEL_MSB 0x0040
148 #define ADIN1200_MII_CONTROL_UNIDIR_EN 0x0020
149 
150 //MII Status register
151 #define ADIN1200_MII_STATUS_T_4_SPRT 0x8000
152 #define ADIN1200_MII_STATUS_FD_100_SPRT 0x4000
153 #define ADIN1200_MII_STATUS_HD_100_SPRT 0x2000
154 #define ADIN1200_MII_STATUS_FD_10_SPRT 0x1000
155 #define ADIN1200_MII_STATUS_HD_10_SPRT 0x0800
156 #define ADIN1200_MII_STATUS_FD_T_2_SPRT 0x0400
157 #define ADIN1200_MII_STATUS_HD_T_2_SPRT 0x0200
158 #define ADIN1200_MII_STATUS_EXT_STAT_SPRT 0x0100
159 #define ADIN1200_MII_STATUS_UNIDIR_ABLE 0x0080
160 #define ADIN1200_MII_STATUS_MF_PREAM_SUP_ABLE 0x0040
161 #define ADIN1200_MII_STATUS_AUTONEG_DONE 0x0020
162 #define ADIN1200_MII_STATUS_REM_FLT_LAT 0x0010
163 #define ADIN1200_MII_STATUS_AUTONEG_ABLE 0x0008
164 #define ADIN1200_MII_STATUS_LINK_STAT_LAT 0x0004
165 #define ADIN1200_MII_STATUS_JABBER_DET_LAT 0x0002
166 #define ADIN1200_MII_STATUS_EXT_CAPABLE 0x0001
167 
168 //PHY Identifier 1 register
169 #define ADIN1200_PHY_ID_1_PHY_ID_1 0xFFFF
170 #define ADIN1200_PHY_ID_1_PHY_ID_1_DEFAULT 0x0283
171 
172 //PHY Identifier 2 register
173 #define ADIN1200_PHY_ID_2_PHY_ID_2_OUI 0xFC00
174 #define ADIN1200_PHY_ID_2_PHY_ID_2_OUI_DEFAULT 0xBC00
175 #define ADIN1200_PHY_ID_2_MODEL_NUM 0x03F0
176 #define ADIN1200_PHY_ID_2_MODEL_NUM_DEFAULT 0x0020
177 #define ADIN1200_PHY_ID_2_REV_NUM 0x000F
178 #define ADIN1200_PHY_ID_2_REV_NUM_DEFAULT 0x0000
179 
180 //Autonegotiation Advertisement register
181 #define ADIN1200_AUTONEG_ADV_NEXT_PAGE_ADV 0x8000
182 #define ADIN1200_AUTONEG_ADV_REM_FLT_ADV 0x2000
183 #define ADIN1200_AUTONEG_ADV_EXT_NEXT_PAGE_ADV 0x1000
184 #define ADIN1200_AUTONEG_ADV_APAUSE_ADV 0x0800
185 #define ADIN1200_AUTONEG_ADV_PAUSE_ADV 0x0400
186 #define ADIN1200_AUTONEG_ADV_T_4_ADV 0x0200
187 #define ADIN1200_AUTONEG_ADV_FD_100_ADV 0x0100
188 #define ADIN1200_AUTONEG_ADV_HD_100_ADV 0x0080
189 #define ADIN1200_AUTONEG_ADV_FD_10_ADV 0x0040
190 #define ADIN1200_AUTONEG_ADV_HD_10_ADV 0x0020
191 #define ADIN1200_AUTONEG_ADV_SELECTOR_ADV 0x001F
192 #define ADIN1200_AUTONEG_ADV_SELECTOR_ADV_DEFAULT 0x0001
193 
194 //Autonegotiation Link Partner Base Page Ability register
195 #define ADIN1200_LP_ABILITY_LP_NEXT_PAGE 0x8000
196 #define ADIN1200_LP_ABILITY_LP_ACK 0x4000
197 #define ADIN1200_LP_ABILITY_LP_REM_FLT 0x2000
198 #define ADIN1200_LP_ABILITY_LP_EXT_NEXT_PAGE_ABLE 0x1000
199 #define ADIN1200_LP_ABILITY_LP_APAUSE_ABLE 0x0800
200 #define ADIN1200_LP_ABILITY_LP_PAUSE_ABLE 0x0400
201 #define ADIN1200_LP_ABILITY_LP_T_4_ABLE 0x0200
202 #define ADIN1200_LP_ABILITY_LP_FD_100_ABLE 0x0100
203 #define ADIN1200_LP_ABILITY_LP_HD_100_ABLE 0x0080
204 #define ADIN1200_LP_ABILITY_LP_FD_10_ABLE 0x0040
205 #define ADIN1200_LP_ABILITY_LP_HD_10_ABLE 0x0020
206 #define ADIN1200_LP_ABILITY_LP_SELECTOR 0x001F
207 
208 //Autonegotiation Expansion register
209 #define ADIN1200_AUTONEG_EXP_RX_NP_LOC_ABLE 0x0040
210 #define ADIN1200_AUTONEG_EXP_RX_NP_LOC 0x0020
211 #define ADIN1200_AUTONEG_EXP_PAR_DET_FLT 0x0010
212 #define ADIN1200_AUTONEG_EXP_LP_NP_ABLE 0x0008
213 #define ADIN1200_AUTONEG_EXP_NP_ABLE 0x0004
214 #define ADIN1200_AUTONEG_EXP_PAGE_RX_LAT 0x0002
215 #define ADIN1200_AUTONEG_EXP_LP_AUTONEG_ABLE 0x0001
216 
217 //Autonegotiation Next Page Transmit register
218 #define ADIN1200_TX_NEXT_PAGE_NP_NEXT_PAGE 0x8000
219 #define ADIN1200_TX_NEXT_PAGE_NP_MSG_PAGE 0x2000
220 #define ADIN1200_TX_NEXT_PAGE_NP_ACK_2 0x1000
221 #define ADIN1200_TX_NEXT_PAGE_NP_TOGGLE 0x0800
222 #define ADIN1200_TX_NEXT_PAGE_NP_CODE 0x07FF
223 
224 //Autonegotiation Link Partner Received Next Page register
225 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_NEXT_PAGE 0x8000
226 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_ACK 0x4000
227 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_MSG_PAGE 0x2000
228 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_ACK_2 0x1000
229 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_TOGGLE 0x0800
230 #define ADIN1200_LP_RX_NEXT_PAGE_LP_NP_CODE 0x07FF
231 
232 //Master Slave Status register
233 #define ADIN1200_MSTR_SLV_STATUS_LOC_RCVR_STATUS 0x2000
234 #define ADIN1200_MSTR_SLV_STATUS_REM_RCVR_STATUS 0x1000
235 #define ADIN1200_MSTR_SLV_STATUS_LP_FD_1000_ABLE 0x0800
236 #define ADIN1200_MSTR_SLV_STATUS_LP_HD_1000_ABLE 0x0400
237 #define ADIN1200_MSTR_SLV_STATUS_IDLE_ERR_CNT 0x00FF
238 
239 //Extended Status register
240 #define ADIN1200_EXT_STATUS_FD_1000_X_SPRT 0x8000
241 #define ADIN1200_EXT_STATUS_HD_1000_X_SPRT 0x4000
242 #define ADIN1200_EXT_STATUS_FD_1000_SPRT 0x2000
243 #define ADIN1200_EXT_STATUS_HD_1000_SPRT 0x1000
244 
245 //PHY Control 1 register
246 #define ADIN1200_PHY_CTRL_1_AUTO_MDI_EN 0x0400
247 #define ADIN1200_PHY_CTRL_1_MAN_MDIX 0x0200
248 #define ADIN1200_PHY_CTRL_1_DIAG_CLK_EN 0x0004
249 
250 //PHY Control Status 1 register
251 #define ADIN1200_PHY_CTRL_STATUS_1_LB_ALL_DIG_SEL 0x1000
252 #define ADIN1200_PHY_CTRL_STATUS_1_LB_LD_SEL 0x0400
253 #define ADIN1200_PHY_CTRL_STATUS_1_LB_REMOTE_EN 0x0200
254 #define ADIN1200_PHY_CTRL_STATUS_1_ISOLATE_RX 0x0100
255 #define ADIN1200_PHY_CTRL_STATUS_1_LB_EXT_EN 0x0080
256 #define ADIN1200_PHY_CTRL_STATUS_1_LB_TX_SUP 0x0040
257 #define ADIN1200_PHY_CTRL_STATUS_1_LB_MII_LS_OK 0x0001
258 
259 //PHY Control Status 2 register
260 #define ADIN1200_PHY_CTRL_STATUS_2_NRG_PD_EN 0x0008
261 #define ADIN1200_PHY_CTRL_STATUS_2_NRG_PD_TX_EN 0x0004
262 #define ADIN1200_PHY_CTRL_STATUS_2_PHY_IN_NRG_PD 0x0002
263 
264 //PHY Control 2 register
265 #define ADIN1200_PHY_CTRL_2_DN_SPEED_TO_10_EN 0x0400
266 #define ADIN1200_PHY_CTRL_2_GROUP_MDIO_EN 0x0040
267 
268 //PHY Control 3 register
269 #define ADIN1200_PHY_CTRL_3_LINK_EN 0x2000
270 #define ADIN1200_PHY_CTRL_3_NUM_SPEED_RETRY 0x1C00
271 
272 //Interrupt Mask register
273 #define ADIN1200_IRQ_MASK_CBL_DIAG_IRQ_EN 0x0400
274 #define ADIN1200_IRQ_MASK_MDIO_SYNC_IRQ_EN 0x0200
275 #define ADIN1200_IRQ_MASK_AN_STAT_CHNG_IRQ_EN 0x0100
276 #define ADIN1200_IRQ_MASK_FC_FG_IRQ_EN 0x0080
277 #define ADIN1200_IRQ_MASK_PAGE_RX_IRQ_EN 0x0040
278 #define ADIN1200_IRQ_MASK_IDLE_ERR_CNT_IRQ_EN 0x0020
279 #define ADIN1200_IRQ_MASK_FIFO_OU_IRQ_EN 0x0010
280 #define ADIN1200_IRQ_MASK_RX_STAT_CHNG_IRQ_EN 0x0008
281 #define ADIN1200_IRQ_MASK_LNK_STAT_CHNG_IRQ_EN 0x0004
282 #define ADIN1200_IRQ_MASK_SPEED_CHNG_IRQ_EN 0x0002
283 #define ADIN1200_IRQ_MASK_HW_IRQ_EN 0x0001
284 
285 //Interrupt Status register
286 #define ADIN1200_IRQ_STATUS_CBL_DIAG_IRQ_STAT 0x0400
287 #define ADIN1200_IRQ_STATUS_MDIO_SYNC_IRQ_STAT 0x0200
288 #define ADIN1200_IRQ_STATUS_AN_STAT_CHNG_IRQ_STAT 0x0100
289 #define ADIN1200_IRQ_STATUS_FC_FG_IRQ_STAT 0x0080
290 #define ADIN1200_IRQ_STATUS_PAGE_RX_IRQ_STAT 0x0040
291 #define ADIN1200_IRQ_STATUS_IDLE_ERR_CNT_IRQ_STAT 0x0020
292 #define ADIN1200_IRQ_STATUS_FIFO_OU_IRQ_STAT 0x0010
293 #define ADIN1200_IRQ_STATUS_RX_STAT_CHNG_IRQ_STAT 0x0008
294 #define ADIN1200_IRQ_STATUS_LNK_STAT_CHNG_IRQ_STAT 0x0004
295 #define ADIN1200_IRQ_STATUS_SPEED_CHNG_IRQ_STAT 0x0002
296 #define ADIN1200_IRQ_STATUS_IRQ_PENDING 0x0001
297 
298 //PHY Status 1 register
299 #define ADIN1200_PHY_STATUS_1_PHY_IN_STNDBY 0x8000
300 #define ADIN1200_PHY_STATUS_1_PAR_DET_FLT_STAT 0x2000
301 #define ADIN1200_PHY_STATUS_1_AUTONEG_STAT 0x1000
302 #define ADIN1200_PHY_STATUS_1_PAIR_01_SWAP 0x0800
303 #define ADIN1200_PHY_STATUS_1_B_10_POL_INV 0x0400
304 #define ADIN1200_PHY_STATUS_1_HCD_TECH 0x0380
305 #define ADIN1200_PHY_STATUS_1_HCD_TECH_10BT_HD 0x0000
306 #define ADIN1200_PHY_STATUS_1_HCD_TECH_10BT_FD 0x0080
307 #define ADIN1200_PHY_STATUS_1_HCD_TECH_100BTX_HD 0x0100
308 #define ADIN1200_PHY_STATUS_1_HCD_TECH_100BTX_FD 0x0180
309 #define ADIN1200_PHY_STATUS_1_LINK_STAT 0x0040
310 #define ADIN1200_PHY_STATUS_1_TX_EN_STAT 0x0020
311 #define ADIN1200_PHY_STATUS_1_RX_DV_STAT 0x0010
312 #define ADIN1200_PHY_STATUS_1_COL_STAT 0x0008
313 #define ADIN1200_PHY_STATUS_1_AUTONEG_SUP 0x0004
314 #define ADIN1200_PHY_STATUS_1_LP_PAUSE_ADV 0x0002
315 #define ADIN1200_PHY_STATUS_1_LP_APAUSE_ADV 0x0001
316 
317 //LED Control 1 register
318 #define ADIN1200_LED_CTRL_1_LED_A_EXT_CFG_EN 0x0400
319 #define ADIN1200_LED_CTRL_1_LED_PAT_PAUSE_DUR 0x00F0
320 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_DUR_SEL 0x000C
321 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_DUR_SEL_32MS 0x0000
322 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_DUR_SEL_64MS 0x0004
323 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_DUR_SEL_102MS 0x0008
324 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_DUR_SEL_USER 0x000C
325 #define ADIN1200_LED_CTRL_1_LED_OE_N 0x0002
326 #define ADIN1200_LED_CTRL_1_LED_PUL_STR_EN 0x0001
327 
328 //LED Control 2 register
329 #define ADIN1200_LED_CTRL_2_LED_A_CFG 0x001F
330 #define ADIN1200_LED_CTRL_2_LED_A_CFG_BLINK_100 0x0003
331 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_LINK 0x0004
332 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_TX 0x0005
333 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_RX 0x0006
334 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_ACT 0x0007
335 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_FD 0x0008
336 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_COL 0x0009
337 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_LINK_BLINK_ACT 0x000A
338 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_LINK_BLINK_RX 0x000B
339 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_FD_BLINK_COL 0x000C
340 #define ADIN1200_LED_CTRL_2_LED_A_CFG_BLINK 0x000D
341 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON 0x000E
342 #define ADIN1200_LED_CTRL_2_LED_A_CFG_OFF 0x000F
343 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_10_BLINK_100 0x0010
344 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_10_BLINK_ACT 0x0012
345 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_100_BLINK_ACT 0x0013
346 #define ADIN1200_LED_CTRL_2_LED_A_CFG_BLINK_ACT 0x0019
347 #define ADIN1200_LED_CTRL_2_LED_A_CFG_BLINK_TX 0x001A
348 #define ADIN1200_LED_CTRL_2_LED_A_CFG_BLINK_10 0x001B
349 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_100 0x001C
350 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_100_BLINK_10 0x001D
351 #define ADIN1200_LED_CTRL_2_LED_A_CFG_ON_10 0x001E
352 
353 //LED Control 3 register
354 #define ADIN1200_LED_CTRL_3_LED_PAT_SEL 0xC000
355 #define ADIN1200_LED_CTRL_3_LED_PAT_SEL_DEFAULT 0x0000
356 #define ADIN1200_LED_CTRL_3_LED_PAT_TICK_DUR 0x3F00
357 #define ADIN1200_LED_CTRL_3_LED_PAT_TICK_DUR_DEFAULT 0x1800
358 #define ADIN1200_LED_CTRL_3_LED_PAT 0x00FF
359 #define ADIN1200_LED_CTRL_3_LED_PAT_DEFAULT 0x0055
360 
361 //PHY Status 2 register
362 #define ADIN1200_PHY_STATUS_2_PAIR_1_POL_INV 0x0800
363 #define ADIN1200_PHY_STATUS_2_PAIR_0_POL_INV 0x0400
364 
365 //Energy Efficient Ethernet Capability register
366 #define ADIN1200_EEE_CAPABILITY_EEE_10_G_KR_SPRT 0x0040
367 #define ADIN1200_EEE_CAPABILITY_EEE_10_G_KX_4_SPRT 0x0020
368 #define ADIN1200_EEE_CAPABILITY_EEE_1000_KX_SPRT 0x0010
369 #define ADIN1200_EEE_CAPABILITY_EEE_10_G_SPRT 0x0008
370 #define ADIN1200_EEE_CAPABILITY_EEE_1000_SPRT 0x0004
371 #define ADIN1200_EEE_CAPABILITY_EEE_100_SPRT 0x0002
372 
373 //Energy Efficient Ethernet Advertisement register
374 #define ADIN1200_EEE_ADV_EEE_10_G_KR_ADV 0x0040
375 #define ADIN1200_EEE_ADV_EEE_10_G_KX_4_ADV 0x0020
376 #define ADIN1200_EEE_ADV_EEE_1000_KX_ADV 0x0010
377 #define ADIN1200_EEE_ADV_EEE_10_G_ADV 0x0008
378 #define ADIN1200_EEE_ADV_EEE_1000_ADV 0x0004
379 #define ADIN1200_EEE_ADV_EEE_100_ADV 0x0002
380 
381 //Energy Efficient Ethernet Link Partner Ability register
382 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_10_G_KR_ABLE 0x0040
383 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_10_G_KX_4_ABLE 0x0020
384 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_1000_KX_ABLE 0x0010
385 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_10_G_ABLE 0x0008
386 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_1000_ABLE 0x0004
387 #define ADIN1200_EEE_LP_ABILITY_LP_EEE_100_ABLE 0x0002
388 
389 //Energy Efficient Ethernet Resolved register
390 #define ADIN1200_EEE_RSLVD_EEE_RSLVD 0x0001
391 
392 //Mean Square Error A register
393 #define ADIN1200_MSE_A_MSE_A 0x00FF
394 
395 //Enhanced Link Detection Enable register
396 #define ADIN1200_FLD_EN_FLD_PCS_ERR_B_100_EN 0x0080
397 #define ADIN1200_FLD_EN_FLD_SLCR_OUT_STUCK_B_100_EN 0x0020
398 #define ADIN1200_FLD_EN_FLD_SLCR_IN_ZDET_B_100_EN 0x0008
399 #define ADIN1200_FLD_EN_FLD_SLCR_IN_INVLD_B_100_EN 0x0002
400 
401 //Enhanced Link Detection Latched Status register
402 #define ADIN1200_FLD_STAT_LAT_FAST_LINK_DOWN_LAT 0x2000
403 
404 //Receive MII Clock Stop Enable register
405 #define ADIN1200_RX_MII_CLK_STOP_EN_RX_MII_CLK_STOP_EN 0x0400
406 
407 //Physical Coding Sublayer (PCS) Status 1 register
408 #define ADIN1200_PCS_STATUS_1_TX_LPI_RCVD 0x0800
409 #define ADIN1200_PCS_STATUS_1_RX_LPI_RCVD 0x0400
410 #define ADIN1200_PCS_STATUS_1_TX_LPI 0x0200
411 #define ADIN1200_PCS_STATUS_1_RX_LPI 0x0100
412 #define ADIN1200_PCS_STATUS_1_TX_MII_CLK_STOP_CPBL 0x0040
413 
414 //Frame Checker Enable register
415 #define ADIN1200_FC_EN_FC_EN 0x0001
416 
417 //Frame Checker Interrupt Enable register
418 #define ADIN1200_FC_IRQ_EN_FC_IRQ_EN 0x0001
419 
420 //Frame Checker Transmit Select register
421 #define ADIN1200_FC_TX_SEL_FC_TX_SEL 0x0001
422 
423 //Frame Generator Enable register
424 #define ADIN1200_FG_EN_FG_EN 0x0001
425 
426 //Frame Generator Control and Restart register
427 #define ADIN1200_FG_CNTRL_RSTRT_FG_RSTRT 0x0008
428 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL 0x0007
429 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_NO_FRAMES 0x0000
430 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_RANDOM 0x0001
431 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_ALL_ZEROS 0x0002
432 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_ALL_ONES 0x0003
433 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_ALT 0x0004
434 #define ADIN1200_FG_CNTRL_RSTRT_FG_CNTRL_DEC 0x0005
435 
436 //Frame Generator Continuous Mode Enable register
437 #define ADIN1200_FG_CONT_MODE_EN_FG_CONT_MODE_EN 0x0001
438 
439 //Frame Generator Interrupt Enable register
440 #define ADIN1200_FG_IRQ_EN_FG_IRQ_EN 0x0001
441 
442 //Frame Generator Interframe Gap Length register
443 #define ADIN1200_FG_IFG_LEN_FG_IFG_LEN 0x00FF
444 
445 //Frame Generator Done register
446 #define ADIN1200_FG_DONE_FG_DONE 0x0001
447 
448 //FIFO Sync register
449 #define ADIN1200_FIFO_SYNC_FIFO_SYNC 0x0001
450 
451 //Start of Packet Control register
452 #define ADIN1200_SOP_CTRL_SOP_N_8_CYCM_1 0x0070
453 #define ADIN1200_SOP_CTRL_SOP_NCYC_EN 0x0008
454 #define ADIN1200_SOP_CTRL_SOP_SFD_EN 0x0004
455 #define ADIN1200_SOP_CTRL_SOP_RX_EN 0x0002
456 #define ADIN1200_SOP_CTRL_SOP_TX_EN 0x0001
457 
458 //Start of Packet Receive Detection Delay register
459 #define ADIN1200_SOP_RX_DEL_SOP_RX_10_DEL_NCYC 0xF800
460 #define ADIN1200_SOP_RX_DEL_SOP_RX_100_DEL_NCYC 0x07C0
461 
462 //Start of Packet Transmit Detection Delay register
463 #define ADIN1200_SOP_TX_DEL_SOP_TX_10_DEL_N_8_NS 0x1F00
464 #define ADIN1200_SOP_TX_DEL_SOP_TX_100_DEL_N_8_NS 0x00F0
465 
466 //Control of FIFO Depth for MII Modes register
467 #define ADIN1200_DPTH_MII_BYTE_DPTH_MII_BYTE 0x0001
468 
469 //Base 10e Enable register
470 #define ADIN1200_B_10_E_EN_B_10_E_EN 0x0001
471 
472 //10BASE-T Transmit Test Mode register
473 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE 0x0007
474 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE_DISABLED 0x0000
475 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE_10MHZ_DIM_0 0x0001
476 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE_10MHZ_DIM_1 0x0002
477 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE_5MHZ_DIM_0 0x0003
478 #define ADIN1200_B_10_TX_TST_MODE_B_10_TX_TST_MODE_5MHZ_DIM_1 0x0004
479 
480 //100BASE-TX Transmit Test Mode register
481 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE 0x0007
482 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE_DISABLED 0x0000
483 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE_MLT3_16NS_DIM_0 0x0001
484 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE_MLT3_16NS_DIM_1 0x0002
485 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE_MLT3_112NS_DIM_0 0x0003
486 #define ADIN1200_B_100_TX_TST_MODE_B_100_TX_TST_MODE_MLT3_112NS_DIM_1 0x0004
487 
488 //Run Automated Cable Diagnostics register
489 #define ADIN1200_CDIAG_RUN_CDIAG_RUN 0x0001
490 
491 //Cable Diagnostics Cross Pair Fault Checking Disable register
492 #define ADIN1200_CDIAG_XPAIR_DIS_CDIAG_XPAIR_DIS 0x0001
493 
494 //Cable Diagnostics Results 0 register
495 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_BSY 0x0400
496 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_XSIM_1 0x0080
497 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_SIM 0x0040
498 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_XSHRT_1 0x0008
499 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_SHRT 0x0004
500 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_OPN 0x0002
501 #define ADIN1200_CDIAG_DTLD_RSLTS_0_CDIAG_RSLT_0_GD 0x0001
502 
503 //Cable Diagnostics Results 1 register
504 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_BSY 0x0400
505 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_XSIM_0 0x0080
506 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_SIM 0x0040
507 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_XSHRT_0 0x0008
508 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_SHRT 0x0004
509 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_OPN 0x0002
510 #define ADIN1200_CDIAG_DTLD_RSLTS_1_CDIAG_RSLT_1_GD 0x0001
511 
512 //Cable Diagnostics Fault Distance Pair 0 register
513 #define ADIN1200_CDIAG_FLT_DIST_0_CDIAG_FLT_DIST_0 0x00FF
514 
515 //Cable Diagnostics Fault Distance Pair 1 register
516 #define ADIN1200_CDIAG_FLT_DIST_1_CDIAG_FLT_DIST_1 0x00FF
517 
518 //Cable Diagnostics Cable Length Estimate register
519 #define ADIN1200_CDIAG_CBL_LEN_EST_CDIAG_CBL_LEN_EST 0x00FF
520 
521 //LED Pulse Stretching Duration register
522 #define ADIN1200_LED_PUL_STR_DUR_LED_PUL_STR_DUR 0x003F
523 
524 //Subsystem Software Reset register
525 #define ADIN1200_GE_SFT_RST_GE_SFT_RST 0x0001
526 
527 //Subsystem Software Reset Configuration Enable register
528 #define ADIN1200_GE_SFT_RST_CFG_EN_GE_SFT_RST_CFG_EN 0x0001
529 
530 //Subsystem Clock Configuration register
531 #define ADIN1200_GE_CLK_CFG_GE_CLK_RCVR_125_EN 0x0020
532 #define ADIN1200_GE_CLK_CFG_GE_CLK_FREE_125_EN 0x0010
533 #define ADIN1200_GE_CLK_CFG_GE_CLK_HRT_RCVR_EN 0x0004
534 #define ADIN1200_GE_CLK_CFG_GE_CLK_HRT_FREE_EN 0x0002
535 #define ADIN1200_GE_CLK_CFG_GE_CLK_25_EN 0x0001
536 
537 //Subsystem RGMII Configuration register
538 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_100_LOW_LTNCY_EN 0x0400
539 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_10_LOW_LTNCY_EN 0x0200
540 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_RX_SEL 0x01C0
541 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_GTX_SEL 0x0038
542 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_RX_ID_EN 0x0004
543 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_TX_ID_EN 0x0002
544 #define ADIN1200_GE_RGMII_CFG_GE_RGMII_EN 0x0001
545 
546 //Subsystem RMII Configuration register
547 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_RST 0x0080
548 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH 0x0070
549 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_4_BITS 0x0000
550 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_8_BITS 0x0010
551 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_12_BITS 0x0020
552 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_16_BITS 0x0030
553 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_20_BITS 0x0040
554 #define ADIN1200_GE_RMII_CFG_GE_RMII_FIFO_DPTH_24_BITS 0x0050
555 #define ADIN1200_GE_RMII_CFG_GE_RMII_TXD_CHK_EN 0x0008
556 #define ADIN1200_GE_RMII_CFG_GE_RMII_CRS_EN 0x0004
557 #define ADIN1200_GE_RMII_CFG_GE_RMII_BAD_SSD_RX_ER_EN 0x0002
558 #define ADIN1200_GE_RMII_CFG_GE_RMII_EN 0x0001
559 
560 //Subsystem PHY Base Configuration register
561 #define ADIN1200_GE_PHY_BASE_CFG_GE_FLD_100_EN_CFG 0x0400
562 #define ADIN1200_GE_PHY_BASE_CFG_GE_PHY_SFT_PD_CFG 0x0008
563 
564 //Subsystem Link Status Invert Enable register
565 #define ADIN1200_GE_LNK_STAT_INV_EN_GE_LNK_STAT_INV_EN 0x0001
566 
567 //Subsystem GP_CLK Pin Override Control register
568 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL 0x0007
569 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_DEFAULT 0x0000
570 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_LINK_STATUS 0x0001
571 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_TX_SOF 0x0002
572 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_RX_SOF 0x0003
573 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_CRS 0x0004
574 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_COL 0x0005
575 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_RX_ER 0x0006
576 #define ADIN1200_GE_IO_GP_CLK_OR_CNTRL_GE_IO_GP_CLK_OR_CNTRL_PHY_CLK 0x0007
577 
578 //Subsystem LINK_ST Pin Override Control register
579 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL 0x0007
580 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_DEFAULT 0x0000
581 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_LINK_STATUS 0x0001
582 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_TX_SOF 0x0002
583 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_RX_SOF 0x0003
584 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_CRS 0x0004
585 #define ADIN1200_GE_IO_GP_OUT_OR_CNTRL_GE_IO_GP_OUT_OR_CNTRL_COL 0x0005
586 
587 //Subsystem INT_N Pin Override Control register
588 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL 0x0007
589 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_DEFAULT 0x0000
590 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_LINK_STATUS 0x0001
591 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_TX_SOF 0x0002
592 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_RX_SOF 0x0003
593 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_CRS 0x0004
594 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_COL 0x0005
595 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_TX_ER 0x0006
596 #define ADIN1200_GE_IO_INT_N_OR_CNTRL_GE_IO_INT_N_OR_CNTRL_INT_N 0x0007
597 
598 //Subsystem LED_0 Pin Override Control register
599 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL 0x000F
600 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_DEFAULT 0x0000
601 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_LINK_STATUS 0x0001
602 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_TX_SOF 0x0002
603 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_RX_SOF 0x0003
604 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_CRS 0x0004
605 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_COL 0x0005
606 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_TX_ER 0x0006
607 #define ADIN1200_GE_IO_LED_A_OR_CNTRL_GE_IO_LED_A_OR_CNTRL_LED_0 0x0007
608 
609 //C++ guard
610 #ifdef __cplusplus
611 extern "C" {
612 #endif
613 
614 //ADIN1200 Ethernet PHY driver
615 extern const PhyDriver adin1200PhyDriver;
616 
617 //ADIN1200 related functions
618 error_t adin1200Init(NetInterface *interface);
619 void adin1200InitHook(NetInterface *interface);
620 
621 void adin1200Tick(NetInterface *interface);
622 
623 void adin1200EnableIrq(NetInterface *interface);
624 void adin1200DisableIrq(NetInterface *interface);
625 
626 void adin1200EventHandler(NetInterface *interface);
627 
628 void adin1200WritePhyReg(NetInterface *interface, uint8_t address,
629  uint16_t data);
630 
631 uint16_t adin1200ReadPhyReg(NetInterface *interface, uint8_t address);
632 
633 void adin1200DumpPhyReg(NetInterface *interface);
634 
635 void adin1200WriteExtReg(NetInterface *interface, uint16_t address,
636  uint16_t data);
637 
638 uint16_t adin1200ReadExtReg(NetInterface *interface, uint16_t address);
639 
640 //C++ guard
641 #ifdef __cplusplus
642 }
643 #endif
644 
645 #endif
void adin1200InitHook(NetInterface *interface)
ADIN1200 custom configuration.
void adin1200EventHandler(NetInterface *interface)
ADIN1200 event handler.
const PhyDriver adin1200PhyDriver
ADIN1200 Ethernet PHY driver.
void adin1200WriteExtReg(NetInterface *interface, uint16_t address, uint16_t data)
Write extended register.
void adin1200EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t adin1200ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void adin1200DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void adin1200Tick(NetInterface *interface)
ADIN1200 timer handler.
uint16_t adin1200ReadExtReg(NetInterface *interface, uint16_t address)
Read extended register.
void adin1200WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
error_t adin1200Init(NetInterface *interface)
ADIN1200 PHY transceiver initialization.
void adin1200DisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
#define NetInterface
Definition: net.h:36
Network interface controller abstraction layer.
Ethernet PHY driver.
Definition: nic.h:308