32 #define TRACE_LEVEL NIC_TRACE_LEVEL
37 #include "interrupt.h"
47 #if defined(__ICCARM__)
50 #pragma data_alignment = 4
53 #pragma data_alignment = 4
56 #pragma data_alignment = 8
59 #pragma data_alignment = 8
81 static uint_t txBufferIndex;
83 static uint_t rxBufferIndex;
120 volatile uint32_t status;
123 TRACE_INFO(
"Initializing AVR32 Ethernet MAC...\r\n");
126 nicDriverInterface = interface;
135 AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
137 AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
140 if(interface->phyDriver != NULL)
143 error = interface->phyDriver->init(interface);
145 else if(interface->switchDriver != NULL)
148 error = interface->switchDriver->init(interface);
163 AVR32_MACB.sa1b = interface->macAddr.b[0] |
164 (interface->macAddr.b[1] << 8) |
165 (interface->macAddr.b[2] << 16) |
166 (interface->macAddr.b[3] << 24);
168 AVR32_MACB.sa1t = interface->macAddr.b[4] |
169 (interface->macAddr.b[5] << 8);
176 AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_BIG_MASK | AVR32_MACB_NCFGR_UNI_MASK |
177 AVR32_MACB_NCFGR_MTI_MASK;
183 AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK |
184 AVR32_MACB_TSR_BEX_MASK | AVR32_MACB_TSR_TGO_MASK |
185 AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK |
186 AVR32_MACB_TSR_UBR_MASK;
189 AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK |
190 AVR32_MACB_RSR_BNA_MASK;
193 AVR32_MACB.idr = 0xFFFFFFFF;
196 AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK |
197 AVR32_MACB_IER_TXERR_MASK | AVR32_MACB_IER_RLE_MASK |
198 AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK |
199 AVR32_MACB_IER_RCOMP_MASK;
202 status = AVR32_MACB.isr;
210 AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
228 #if defined(USE_EVK1105)
237 AVR32_MACB.usrio &= ~AVR32_MACB_USRIO_RMII_MASK;
276 rxBufferDesc[i].
status = 0;
285 AVR32_MACB.tbqp = (uint32_t) txBufferDesc;
287 AVR32_MACB.rbqp = (uint32_t) rxBufferDesc;
303 if(interface->phyDriver != NULL)
306 interface->phyDriver->tick(interface);
308 else if(interface->switchDriver != NULL)
311 interface->switchDriver->tick(interface);
328 Enable_global_interrupt();
331 if(interface->phyDriver != NULL)
334 interface->phyDriver->enableIrq(interface);
336 else if(interface->switchDriver != NULL)
339 interface->switchDriver->enableIrq(interface);
356 Disable_global_interrupt();
359 if(interface->phyDriver != NULL)
362 interface->phyDriver->disableIrq(interface);
364 else if(interface->switchDriver != NULL)
367 interface->switchDriver->disableIrq(interface);
401 volatile uint32_t isr;
402 volatile uint32_t tsr;
403 volatile uint32_t rsr;
410 isr = AVR32_MACB.isr;
411 tsr = AVR32_MACB.tsr;
412 rsr = AVR32_MACB.rsr;
416 if((tsr & (AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK |
417 AVR32_MACB_TSR_BEX_MASK | AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK |
418 AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK)) != 0)
421 AVR32_MACB.tsr = tsr;
424 if((txBufferDesc[txBufferIndex].status &
MACB_TX_USED) != 0)
432 if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK |
433 AVR32_MACB_RSR_BNA_MASK)) != 0)
436 nicDriverInterface->nicEvent =
TRUE;
457 rsr = AVR32_MACB.rsr;
460 if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK)) != 0)
463 AVR32_MACB.rsr = rsr;
505 if((txBufferDesc[txBufferIndex].status &
MACB_TX_USED) == 0)
534 AVR32_MACB.ncr |= AVR32_MACB_NCR_TSTART_MASK;
537 if((txBufferDesc[txBufferIndex].status &
MACB_TX_USED) != 0)
575 j = rxBufferIndex + i;
598 if((rxBufferDesc[j].status &
MACB_RX_EOF) != 0 && sofIndex != UINT_MAX)
612 if(eofIndex != UINT_MAX)
616 else if(sofIndex != UINT_MAX)
629 for(i = 0; i < j; i++)
632 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
691 uint32_t hashTable[2];
698 AVR32_MACB.sa1b = interface->macAddr.b[0] |
699 (interface->macAddr.b[1] << 8) |
700 (interface->macAddr.b[2] << 16) |
701 (interface->macAddr.b[3] << 24);
703 AVR32_MACB.sa1t = interface->macAddr.b[4] |
704 (interface->macAddr.b[5] << 8);
715 entry = &interface->macAddrFilter[i];
724 k = (
p[0] >> 6) ^
p[0];
725 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
726 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
727 k ^= (
p[3] >> 6) ^
p[3];
728 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
729 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
735 hashTable[k / 32] |= (1 << (k % 32));
740 AVR32_MACB.hrb = hashTable[0];
741 AVR32_MACB.hrt = hashTable[1];
744 TRACE_DEBUG(
" HRB = %08" PRIX32
"\r\n", AVR32_MACB.hrb);
745 TRACE_DEBUG(
" HRT = %08" PRIX32
"\r\n", AVR32_MACB.hrt);
763 config = AVR32_MACB.ncfgr;
768 config |= AVR32_MACB_NCFGR_SPD_MASK;
772 config &= ~AVR32_MACB_NCFGR_SPD_MASK;
778 config |= AVR32_MACB_NCFGR_FD_MASK;
782 config &= ~AVR32_MACB_NCFGR_FD_MASK;
786 AVR32_MACB.ncfgr = config;
812 temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
814 temp |= (
regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
816 temp |=
data & AVR32_MACB_MAN_DATA_MASK;
819 AVR32_MACB.man = temp;
821 while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
852 temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
854 temp |= (
regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
857 AVR32_MACB.man = temp;
859 while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
864 data = AVR32_MACB.man & AVR32_MACB_MAN_DATA_MASK;
uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
__weak_func void avr32EthInitGpio(NetInterface *interface)
GPIO configuration.
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
AVR32 Ethernet MAC driver.
void avr32EthIrqWrapper(void)
#define AVR32_ETH_RX_BUFFER_COUNT
#define AVR32_ETH_TX_BUFFER_COUNT
#define AVR32_ETH_IRQ_PRIORITY
#define AVR32_ETH_TX_BUFFER_SIZE
#define MACB_RX_OWNERSHIP
#define AVR32_ETH_RX_BUFFER_SIZE
@ ERROR_FAILURE
Generic error code.
#define ETH_MAX_FRAME_SIZE
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
Receive buffer descriptor.
Transmit buffer descriptor.
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.