ksz8567_driver.h
Go to the documentation of this file.
1 /**
2  * @file ksz8567_driver.h
3  * @brief KSZ8567 7-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _KSZ8567_DRIVER_H
32 #define _KSZ8567_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ8567_PORT1 1
39 #define KSZ8567_PORT2 2
40 #define KSZ8567_PORT3 3
41 #define KSZ8567_PORT4 4
42 #define KSZ8567_PORT5 5
43 #define KSZ8567_PORT6 6
44 #define KSZ8567_PORT7 7
45 
46 //Port masks
47 #define KSZ8567_PORT_MASK 0x7F
48 #define KSZ8567_PORT1_MASK 0x01
49 #define KSZ8567_PORT2_MASK 0x02
50 #define KSZ8567_PORT3_MASK 0x04
51 #define KSZ8567_PORT4_MASK 0x08
52 #define KSZ8567_PORT5_MASK 0x10
53 #define KSZ8567_PORT6_MASK 0x20
54 #define KSZ8567_PORT7_MASK 0x40
55 
56 //SPI command byte
57 #define KSZ8567_SPI_CMD_WRITE 0x40000000
58 #define KSZ8567_SPI_CMD_READ 0x60000000
59 #define KSZ8567_SPI_CMD_ADDR 0x001FFFE0
60 
61 //Size of static and dynamic MAC tables
62 #define KSZ8567_STATIC_MAC_TABLE_SIZE 16
63 #define KSZ8567_DYNAMIC_MAC_TABLE_SIZE 4096
64 
65 //Tail tag rules (host to KSZ8567)
66 #define KSZ8567_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x0400
67 #define KSZ8567_TAIL_TAG_PORT_BLOCKING_OVERRIDE 0x0200
68 #define KSZ8567_TAIL_TAG_PRIORITY 0x0180
69 #define KSZ8567_TAIL_TAG_DEST_PORT7 0x0040
70 #define KSZ8567_TAIL_TAG_DEST_PORT6 0x0020
71 #define KSZ8567_TAIL_TAG_DEST_PORT5 0x0010
72 #define KSZ8567_TAIL_TAG_DEST_PORT4 0x0008
73 #define KSZ8567_TAIL_TAG_DEST_PORT3 0x0004
74 #define KSZ8567_TAIL_TAG_DEST_PORT2 0x0002
75 #define KSZ8567_TAIL_TAG_DEST_PORT1 0x0001
76 
77 //Tail tag rules (KSZ8567 to host)
78 #define KSZ8567_TAIL_TAG_PTP_MSG 0x80
79 #define KSZ8567_TAIL_TAG_SRC_PORT 0x07
80 
81 //KSZ8567 PHY registers
82 #define KSZ8567_BMCR 0x00
83 #define KSZ8567_BMSR 0x01
84 #define KSZ8567_PHYID1 0x02
85 #define KSZ8567_PHYID2 0x03
86 #define KSZ8567_ANAR 0x04
87 #define KSZ8567_ANLPAR 0x05
88 #define KSZ8567_ANER 0x06
89 #define KSZ8567_ANNPR 0x07
90 #define KSZ8567_ANLPNPR 0x08
91 #define KSZ8567_MMDACR 0x0D
92 #define KSZ8567_MMDAADR 0x0E
93 #define KSZ8567_RLB 0x11
94 #define KSZ8567_LINKMD 0x12
95 #define KSZ8567_DPMAPCSS 0x13
96 #define KSZ8567_RXERCTR 0x15
97 #define KSZ8567_ICSR 0x1B
98 #define KSZ8567_AUTOMDI 0x1C
99 #define KSZ8567_PHYCON 0x1F
100 
101 //KSZ8567 MMD registers
102 #define KSZ8567_MMD_SIGNAL_QUALITY_CH_A 0x01, 0xAC
103 #define KSZ8567_MMD_LED_MODE 0x02, 0x00
104 #define KSZ8567_MMD_EEE_ADV 0x07, 0x3C
105 #define KSZ8567_MMD_QUIET_WIRE_CONFIG0 0x1C, 0x25
106 #define KSZ8567_MMD_QUIET_WIRE_CONFIG1 0x1C, 0x26
107 #define KSZ8567_MMD_QUIET_WIRE_CONFIG2 0x1C, 0x27
108 #define KSZ8567_MMD_QUIET_WIRE_CONFIG3 0x1C, 0x28
109 #define KSZ8567_MMD_QUIET_WIRE_CONFIG4 0x1C, 0x29
110 #define KSZ8567_MMD_QUIET_WIRE_CONFIG5 0x1C, 0x2A
111 #define KSZ8567_MMD_QUIET_WIRE_CONFIG6 0x1C, 0x2B
112 #define KSZ8567_MMD_QUIET_WIRE_CONFIG7 0x1C, 0x2C
113 #define KSZ8567_MMD_QUIET_WIRE_CONFIG8 0x1C, 0x2D
114 #define KSZ8567_MMD_QUIET_WIRE_CONFIG9 0x1C, 0x2E
115 #define KSZ8567_MMD_QUIET_WIRE_CONFIG10 0x1C, 0x2F
116 #define KSZ8567_MMD_QUIET_WIRE_CONFIG11 0x1C, 0x30
117 #define KSZ8567_MMD_QUIET_WIRE_CONFIG12 0x1C, 0x31
118 #define KSZ8567_MMD_QUIET_WIRE_CONFIG13 0x1C, 0x32
119 #define KSZ8567_MMD_QUIET_WIRE_CONFIG14 0x1C, 0x33
120 #define KSZ8567_MMD_QUIET_WIRE_CONFIG15 0x1C, 0x34
121 
122 //KSZ8567 Switch registers
123 #define KSZ8567_CHIP_ID0 0x0000
124 #define KSZ8567_CHIP_ID1 0x0001
125 #define KSZ8567_CHIP_ID2 0x0002
126 #define KSZ8567_CHIP_ID3 0x0003
127 #define KSZ8567_PME_PIN_CTRL 0x0006
128 #define KSZ8567_GLOBAL_INT_STAT 0x0010
129 #define KSZ8567_GLOBAL_INT_MASK 0x0014
130 #define KSZ8567_GLOBAL_PORT_INT_STAT 0x0018
131 #define KSZ8567_GLOBAL_PORT_INT_MASK 0x001C
132 #define KSZ8567_SERIAL_IO_CTRL 0x0100
133 #define KSZ8567_OUT_CLK_CTRL 0x0103
134 #define KSZ8567_IBA_CTRL 0x0104
135 #define KSZ8567_IO_DRIVE_STRENGTH 0x010D
136 #define KSZ8567_IBA_OP_STAT1 0x0110
137 #define KSZ8567_LED_OVERRIDE 0x0120
138 #define KSZ8567_LED_OUTPUT 0x0124
139 #define KSZ8567_LED2_0_LED2_1_SRC 0x0128
140 #define KSZ8567_PWR_DOWN_CTRL0 0x0201
141 #define KSZ8567_LED_STRAP_IN 0x0210
142 #define KSZ8567_SWITCH_OP 0x0300
143 #define KSZ8567_SWITCH_MAC_ADDR0 0x0302
144 #define KSZ8567_SWITCH_MAC_ADDR1 0x0303
145 #define KSZ8567_SWITCH_MAC_ADDR2 0x0304
146 #define KSZ8567_SWITCH_MAC_ADDR3 0x0305
147 #define KSZ8567_SWITCH_MAC_ADDR4 0x0306
148 #define KSZ8567_SWITCH_MAC_ADDR5 0x0307
149 #define KSZ8567_SWITCH_MTU 0x0308
150 #define KSZ8567_SWITCH_ISP_TPID 0x030A
151 #define KSZ8567_AVB_CBS_STRATEGY 0x030E
152 #define KSZ8567_SWITCH_LUE_CTRL0 0x0310
153 #define KSZ8567_SWITCH_LUE_CTRL1 0x0311
154 #define KSZ8567_SWITCH_LUE_CTRL2 0x0312
155 #define KSZ8567_SWITCH_LUE_CTRL3 0x0313
156 #define KSZ8567_ALU_TABLE_INT 0x0314
157 #define KSZ8567_ALU_TABLE_MASK 0x0315
158 #define KSZ8567_ALU_TABLE_ENTRY_INDEX0 0x0316
159 #define KSZ8567_ALU_TABLE_ENTRY_INDEX1 0x0318
160 #define KSZ8567_ALU_TABLE_ENTRY_INDEX2 0x031A
161 #define KSZ8567_UNKNOWN_UNICAST_CTRL 0x0320
162 #define KSZ8567_UNKONWN_MULTICAST_CTRL 0x0324
163 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL 0x0328
164 #define KSZ8567_SWITCH_MAC_CTRL0 0x0330
165 #define KSZ8567_SWITCH_MAC_CTRL1 0x0331
166 #define KSZ8567_SWITCH_MAC_CTRL2 0x0332
167 #define KSZ8567_SWITCH_MAC_CTRL3 0x0333
168 #define KSZ8567_SWITCH_MAC_CTRL4 0x0334
169 #define KSZ8567_SWITCH_MAC_CTRL5 0x0335
170 #define KSZ8567_SWITCH_MIB_CTRL 0x0336
171 #define KSZ8567_802_1P_PRIO_MAPPING0 0x0338
172 #define KSZ8567_802_1P_PRIO_MAPPING1 0x0339
173 #define KSZ8567_802_1P_PRIO_MAPPING2 0x033A
174 #define KSZ8567_802_1P_PRIO_MAPPING3 0x033B
175 #define KSZ8567_IP_DIFFSERV_PRIO_EN 0x033E
176 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING0 0x0340
177 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING1 0x0341
178 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING2 0x0342
179 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING3 0x0343
180 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING4 0x0344
181 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING5 0x0345
182 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING6 0x0346
183 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING7 0x0347
184 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING8 0x0348
185 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING9 0x0349
186 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING10 0x034A
187 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING11 0x034B
188 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING12 0x034C
189 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING13 0x034D
190 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING14 0x034E
191 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING15 0x034F
192 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING16 0x0350
193 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING17 0x0351
194 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING18 0x0352
195 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING19 0x0353
196 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING20 0x0354
197 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING21 0x0355
198 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING22 0x0356
199 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING23 0x0357
200 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING24 0x0358
201 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING25 0x0359
202 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING26 0x035A
203 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING27 0x035B
204 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING28 0x035C
205 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING29 0x035D
206 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING30 0x035E
207 #define KSZ8567_IP_DIFFSERV_PRIO_MAPPING31 0x035F
208 #define KSZ8567_GLOBAL_PORT_MIRROR_SNOOP_CTRL 0x0370
209 #define KSZ8567_WRED_DIFFSERV_COLOR_MAPPING 0x0378
210 #define KSZ8567_PTP_EVENT_MSG_PRIO 0x037C
211 #define KSZ8567_PTP_NON_EVENT_MSG_PRIO 0x037D
212 #define KSZ8567_QUEUE_MGMT_CTRL0 0x0390
213 #define KSZ8567_VLAN_TABLE_ENTRY0 0x0400
214 #define KSZ8567_VLAN_TABLE_ENTRY1 0x0404
215 #define KSZ8567_VLAN_TABLE_ENTRY2 0x0408
216 #define KSZ8567_VLAN_TABLE_INDEX 0x040C
217 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL 0x040E
218 #define KSZ8567_ALU_TABLE_INDEX0 0x0410
219 #define KSZ8567_ALU_TABLE_INDEX1 0x0414
220 #define KSZ8567_ALU_TABLE_CTRL 0x0418
221 #define KSZ8567_STATIC_MCAST_TABLE_CTRL 0x041C
222 #define KSZ8567_ALU_TABLE_ENTRY1 0x0420
223 #define KSZ8567_STATIC_TABLE_ENTRY1 0x0420
224 #define KSZ8567_ALU_TABLE_ENTRY2 0x0424
225 #define KSZ8567_STATIC_TABLE_ENTRY2 0x0424
226 #define KSZ8567_RES_MCAST_TABLE_ENTRY2 0x0424
227 #define KSZ8567_ALU_TABLE_ENTRY3 0x0428
228 #define KSZ8567_STATIC_TABLE_ENTRY3 0x0428
229 #define KSZ8567_ALU_TABLE_ENTRY4 0x042C
230 #define KSZ8567_STATIC_TABLE_ENTRY4 0x042C
231 #define KSZ8567_GLOBAL_PTP_CLK_CTRL 0x0500
232 #define KSZ8567_GLOBAL_PTP_RTC_CLK_PHASE 0x0502
233 #define KSZ8567_GLOBAL_PTP_RTC_CLK_NS_H 0x0504
234 #define KSZ8567_GLOBAL_PTP_RTC_CLK_NS_L 0x0506
235 #define KSZ8567_GLOBAL_PTP_RTC_CLK_S_H 0x0508
236 #define KSZ8567_GLOBAL_PTP_RTC_CLK_S_L 0x050A
237 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_H 0x050C
238 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_L 0x050E
239 #define KSZ8567_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_H 0x0510
240 #define KSZ8567_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_L 0x0512
241 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1 0x0514
242 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2 0x0516
243 #define KSZ8567_GLOBAL_PTP_DOMAIN_VERSION 0x0518
244 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX 0x0520
245 #define KSZ8567_GPIO_STATUS_MONITOR0 0x0524
246 #define KSZ8567_GPIO_STATUS_MONITOR1 0x0528
247 #define KSZ8567_TS_CTRL_STAT 0x052C
248 #define KSZ8567_TOU_TARGET_TIME_NS 0x0530
249 #define KSZ8567_TOU_TARGET_TIME_S 0x0534
250 #define KSZ8567_TOU_CTRL1 0x0538
251 #define KSZ8567_TOU_CTRL2 0x053C
252 #define KSZ8567_TOU_CTRL3 0x0540
253 #define KSZ8567_TOU_CTRL4 0x0544
254 #define KSZ8567_TOU_CTRL5 0x0548
255 #define KSZ8567_TS_STAT_CTRL 0x0550
256 #define KSZ8567_TS_SAMPLE1_TIME_NS 0x0554
257 #define KSZ8567_TS_SAMPLE1_TIME_S 0x0558
258 #define KSZ8567_TS_SAMPLE1_TIME_PHASE 0x055C
259 #define KSZ8567_TS_SAMPLE2_TIME_NS 0x0560
260 #define KSZ8567_TS_SAMPLE2_TIME_S 0x0564
261 #define KSZ8567_TS_SAMPLE2_TIME_PHASE 0x0568
262 #define KSZ8567_TS_SAMPLE3_TIME_NS 0x056C
263 #define KSZ8567_TS_SAMPLE3_TIME_S 0x0570
264 #define KSZ8567_TS_SAMPLE3_TIME_PHASE 0x0574
265 #define KSZ8567_TS_SAMPLE4_TIME_NS 0x0578
266 #define KSZ8567_TS_SAMPLE4_TIME_S 0x057C
267 #define KSZ8567_TS_SAMPLE4_TIME_PHASE 0x0580
268 #define KSZ8567_TS_SAMPLE5_TIME_NS 0x0584
269 #define KSZ8567_TS_SAMPLE5_TIME_S 0x0588
270 #define KSZ8567_TS_SAMPLE5_TIME_PHASE 0x058C
271 #define KSZ8567_TS_SAMPLE6_TIME_NS 0x0590
272 #define KSZ8567_TS_SAMPLE6_TIME_S 0x0594
273 #define KSZ8567_TS_SAMPLE6_TIME_PHASE 0x0598
274 #define KSZ8567_TS_SAMPLE7_TIME_NS 0x059C
275 #define KSZ8567_TS_SAMPLE7_TIME_S 0x05A0
276 #define KSZ8567_TS_SAMPLE7_TIME_PHASE 0x05A4
277 #define KSZ8567_TS_SAMPLE8_TIME_NS 0x05A8
278 #define KSZ8567_TS_SAMPLE8_TIME_S 0x05AC
279 #define KSZ8567_TS_SAMPLE8_TIME_PHASE 0x05B0
280 #define KSZ8567_PORT1_DEFAULT_TAG0 0x1000
281 #define KSZ8567_PORT1_DEFAULT_TAG1 0x1001
282 #define KSZ8567_PORT1_PME_WOL_EVENT 0x1013
283 #define KSZ8567_PORT1_PME_WOL_EN 0x1017
284 #define KSZ8567_PORT1_INT_STATUS 0x101B
285 #define KSZ8567_PORT1_INT_MASK 0x101F
286 #define KSZ8567_PORT1_OP_CTRL0 0x1020
287 #define KSZ8567_PORT1_STATUS 0x1030
288 #define KSZ8567_PORT1_MAC_CTRL0 0x1400
289 #define KSZ8567_PORT1_MAC_CTRL1 0x1401
290 #define KSZ8567_PORT1_IG_RATE_LIMIT_CTRL 0x1403
291 #define KSZ8567_PORT1_PRIO0_IG_LIMIT_CTRL 0x1410
292 #define KSZ8567_PORT1_PRIO1_IG_LIMIT_CTRL 0x1411
293 #define KSZ8567_PORT1_PRIO2_IG_LIMIT_CTRL 0x1412
294 #define KSZ8567_PORT1_PRIO3_IG_LIMIT_CTRL 0x1413
295 #define KSZ8567_PORT1_PRIO4_IG_LIMIT_CTRL 0x1414
296 #define KSZ8567_PORT1_PRIO5_IG_LIMIT_CTRL 0x1415
297 #define KSZ8567_PORT1_PRIO6_IG_LIMIT_CTRL 0x1416
298 #define KSZ8567_PORT1_PRIO7_IG_LIMIT_CTRL 0x1417
299 #define KSZ8567_PORT1_QUEUE0_EG_LIMIT_CTRL 0x1420
300 #define KSZ8567_PORT1_QUEUE1_EG_LIMIT_CTRL 0x1421
301 #define KSZ8567_PORT1_QUEUE2_EG_LIMIT_CTRL 0x1422
302 #define KSZ8567_PORT1_QUEUE3_EG_LIMIT_CTRL 0x1423
303 #define KSZ8567_PORT1_MIB_CTRL_STAT 0x1500
304 #define KSZ8567_PORT1_MIB_DATA 0x1504
305 #define KSZ8567_PORT1_ACL_ACCESS0 0x1600
306 #define KSZ8567_PORT1_ACL_ACCESS1 0x1601
307 #define KSZ8567_PORT1_ACL_ACCESS2 0x1602
308 #define KSZ8567_PORT1_ACL_ACCESS3 0x1603
309 #define KSZ8567_PORT1_ACL_ACCESS4 0x1604
310 #define KSZ8567_PORT1_ACL_ACCESS5 0x1605
311 #define KSZ8567_PORT1_ACL_ACCESS6 0x1606
312 #define KSZ8567_PORT1_ACL_ACCESS7 0x1607
313 #define KSZ8567_PORT1_ACL_ACCESS8 0x1608
314 #define KSZ8567_PORT1_ACL_ACCESS9 0x1609
315 #define KSZ8567_PORT1_ACL_ACCESS10 0x160A
316 #define KSZ8567_PORT1_ACL_ACCESS11 0x160B
317 #define KSZ8567_PORT1_ACL_ACCESS12 0x160C
318 #define KSZ8567_PORT1_ACL_ACCESS13 0x160D
319 #define KSZ8567_PORT1_ACL_ACCESS14 0x160E
320 #define KSZ8567_PORT1_ACL_ACCESS15 0x160F
321 #define KSZ8567_PORT1_ACL_BYTE_EN_MSB 0x1610
322 #define KSZ8567_PORT1_ACL_BYTE_EN_LSB 0x1611
323 #define KSZ8567_PORT1_ACL_ACCESS_CTRL0 0x1612
324 #define KSZ8567_PORT1_MIRRORING_CTRL 0x1800
325 #define KSZ8567_PORT1_PRIO_CTRL 0x1801
326 #define KSZ8567_PORT1_IG_MAC_CTRL 0x1802
327 #define KSZ8567_PORT1_AUTH_CTRL 0x1803
328 #define KSZ8567_PORT1_PTR 0x1804
329 #define KSZ8567_PORT1_PRIO_TO_QUEUE_MAPPING 0x1808
330 #define KSZ8567_PORT1_POLICE_CTRL 0x180C
331 #define KSZ8567_PORT1_POLICE_QUEUE_RATE 0x1820
332 #define KSZ8567_PORT1_POLICE_QUEUE_BURST_SIZE 0x1824
333 #define KSZ8567_PORT1_WRED_PKT_MEM_CTRL0 0x1830
334 #define KSZ8567_PORT1_WRED_PKT_MEM_CTRL1 0x1834
335 #define KSZ8567_PORT1_WRED_QUEUE_CTRL0 0x1840
336 #define KSZ8567_PORT1_WRED_QUEUE_CTRL1 0x1844
337 #define KSZ8567_PORT1_WRED_QUEUE_PERF_MON_CTRL 0x1848
338 #define KSZ8567_PORT1_TX_QUEUE_INDEX 0x1900
339 #define KSZ8567_PORT1_TX_QUEUE_PVID 0x1904
340 #define KSZ8567_PORT1_TX_QUEUE_CTRL0 0x1914
341 #define KSZ8567_PORT1_TX_QUEUE_CTRL1 0x1915
342 #define KSZ8567_PORT1_TX_CREDIT_SHAPER_CTRL0 0x1916
343 #define KSZ8567_PORT1_TX_CREDIT_SHAPER_CTRL1 0x1918
344 #define KSZ8567_PORT1_TX_CREDIT_SHAPER_CTRL2 0x191A
345 #define KSZ8567_PORT1_TAS_CTRL 0x1920
346 #define KSZ8567_PORT1_TAS_EVENT_INDEX 0x1923
347 #define KSZ8567_PORT1_TAS_EVENT 0x1924
348 #define KSZ8567_PORT1_CTRL0 0x1A00
349 #define KSZ8567_PORT1_CTRL1 0x1A04
350 #define KSZ8567_PORT1_CTRL2 0x1B00
351 #define KSZ8567_PORT1_MSTP_PTR 0x1B01
352 #define KSZ8567_PORT1_MSTP_STATE 0x1B04
353 #define KSZ8567_PORT1_PTP_RX_LATENCY 0x1C00
354 #define KSZ8567_PORT1_PTP_TX_LATENCY 0x1C02
355 #define KSZ8567_PORT1_PTP_ASYM_CORRECTION 0x1C04
356 #define KSZ8567_PORT1_PTP_XDLY_REQ_TSH 0x1C08
357 #define KSZ8567_PORT1_PTP_XDLY_REQ_TSL 0x1C0A
358 #define KSZ8567_PORT1_PTP_SYNC_TSH 0x1C0C
359 #define KSZ8567_PORT1_PTP_SYNC_TSL 0x1C0E
360 #define KSZ8567_PORT1_PTP_PDLY_RESP_TSH 0x1C10
361 #define KSZ8567_PORT1_PTP_PDLY_RESP_TSL 0x1C12
362 #define KSZ8567_PORT1_PTP_TS_INT_STAT 0x1C14
363 #define KSZ8567_PORT1_PTP_TS_INT_EN 0x1C16
364 #define KSZ8567_PORT1_PTP_LINK_DELAY 0x1C18
365 #define KSZ8567_PORT2_DEFAULT_TAG0 0x2000
366 #define KSZ8567_PORT2_DEFAULT_TAG1 0x2001
367 #define KSZ8567_PORT2_PME_WOL_EVENT 0x2013
368 #define KSZ8567_PORT2_PME_WOL_EN 0x2017
369 #define KSZ8567_PORT2_INT_STATUS 0x201B
370 #define KSZ8567_PORT2_INT_MASK 0x201F
371 #define KSZ8567_PORT2_OP_CTRL0 0x2020
372 #define KSZ8567_PORT2_STATUS 0x2030
373 #define KSZ8567_PORT2_MAC_CTRL0 0x2400
374 #define KSZ8567_PORT2_MAC_CTRL1 0x2401
375 #define KSZ8567_PORT2_IG_RATE_LIMIT_CTRL 0x2403
376 #define KSZ8567_PORT2_PRIO0_IG_LIMIT_CTRL 0x2410
377 #define KSZ8567_PORT2_PRIO1_IG_LIMIT_CTRL 0x2411
378 #define KSZ8567_PORT2_PRIO2_IG_LIMIT_CTRL 0x2412
379 #define KSZ8567_PORT2_PRIO3_IG_LIMIT_CTRL 0x2413
380 #define KSZ8567_PORT2_PRIO4_IG_LIMIT_CTRL 0x2414
381 #define KSZ8567_PORT2_PRIO5_IG_LIMIT_CTRL 0x2415
382 #define KSZ8567_PORT2_PRIO6_IG_LIMIT_CTRL 0x2416
383 #define KSZ8567_PORT2_PRIO7_IG_LIMIT_CTRL 0x2417
384 #define KSZ8567_PORT2_QUEUE0_EG_LIMIT_CTRL 0x2420
385 #define KSZ8567_PORT2_QUEUE1_EG_LIMIT_CTRL 0x2421
386 #define KSZ8567_PORT2_QUEUE2_EG_LIMIT_CTRL 0x2422
387 #define KSZ8567_PORT2_QUEUE3_EG_LIMIT_CTRL 0x2423
388 #define KSZ8567_PORT2_MIB_CTRL_STAT 0x2500
389 #define KSZ8567_PORT2_MIB_DATA 0x2504
390 #define KSZ8567_PORT2_ACL_ACCESS0 0x2600
391 #define KSZ8567_PORT2_ACL_ACCESS1 0x2601
392 #define KSZ8567_PORT2_ACL_ACCESS2 0x2602
393 #define KSZ8567_PORT2_ACL_ACCESS3 0x2603
394 #define KSZ8567_PORT2_ACL_ACCESS4 0x2604
395 #define KSZ8567_PORT2_ACL_ACCESS5 0x2605
396 #define KSZ8567_PORT2_ACL_ACCESS6 0x2606
397 #define KSZ8567_PORT2_ACL_ACCESS7 0x2607
398 #define KSZ8567_PORT2_ACL_ACCESS8 0x2608
399 #define KSZ8567_PORT2_ACL_ACCESS9 0x2609
400 #define KSZ8567_PORT2_ACL_ACCESS10 0x260A
401 #define KSZ8567_PORT2_ACL_ACCESS11 0x260B
402 #define KSZ8567_PORT2_ACL_ACCESS12 0x260C
403 #define KSZ8567_PORT2_ACL_ACCESS13 0x260D
404 #define KSZ8567_PORT2_ACL_ACCESS14 0x260E
405 #define KSZ8567_PORT2_ACL_ACCESS15 0x260F
406 #define KSZ8567_PORT2_ACL_BYTE_EN_MSB 0x2610
407 #define KSZ8567_PORT2_ACL_BYTE_EN_LSB 0x2611
408 #define KSZ8567_PORT2_ACL_ACCESS_CTRL0 0x2612
409 #define KSZ8567_PORT2_MIRRORING_CTRL 0x2800
410 #define KSZ8567_PORT2_PRIO_CTRL 0x2801
411 #define KSZ8567_PORT2_IG_MAC_CTRL 0x2802
412 #define KSZ8567_PORT2_AUTH_CTRL 0x2803
413 #define KSZ8567_PORT2_PTR 0x2804
414 #define KSZ8567_PORT2_PRIO_TO_QUEUE_MAPPING 0x2808
415 #define KSZ8567_PORT2_POLICE_CTRL 0x280C
416 #define KSZ8567_PORT2_POLICE_QUEUE_RATE 0x2820
417 #define KSZ8567_PORT2_POLICE_QUEUE_BURST_SIZE 0x2824
418 #define KSZ8567_PORT2_WRED_PKT_MEM_CTRL0 0x2830
419 #define KSZ8567_PORT2_WRED_PKT_MEM_CTRL1 0x2834
420 #define KSZ8567_PORT2_WRED_QUEUE_CTRL0 0x2840
421 #define KSZ8567_PORT2_WRED_QUEUE_CTRL1 0x2844
422 #define KSZ8567_PORT2_WRED_QUEUE_PERF_MON_CTRL 0x2848
423 #define KSZ8567_PORT2_TX_QUEUE_INDEX 0x2900
424 #define KSZ8567_PORT2_TX_QUEUE_PVID 0x2904
425 #define KSZ8567_PORT2_TX_QUEUE_CTRL0 0x2914
426 #define KSZ8567_PORT2_TX_QUEUE_CTRL1 0x2915
427 #define KSZ8567_PORT2_TX_CREDIT_SHAPER_CTRL0 0x2916
428 #define KSZ8567_PORT2_TX_CREDIT_SHAPER_CTRL1 0x2918
429 #define KSZ8567_PORT2_TX_CREDIT_SHAPER_CTRL2 0x291A
430 #define KSZ8567_PORT2_TAS_CTRL 0x2920
431 #define KSZ8567_PORT2_TAS_EVENT_INDEX 0x2923
432 #define KSZ8567_PORT2_TAS_EVENT 0x2924
433 #define KSZ8567_PORT2_CTRL0 0x2A00
434 #define KSZ8567_PORT2_CTRL1 0x2A04
435 #define KSZ8567_PORT2_CTRL2 0x2B00
436 #define KSZ8567_PORT2_MSTP_PTR 0x2B01
437 #define KSZ8567_PORT2_MSTP_STATE 0x2B04
438 #define KSZ8567_PORT2_PTP_RX_LATENCY 0x2C00
439 #define KSZ8567_PORT2_PTP_TX_LATENCY 0x2C02
440 #define KSZ8567_PORT2_PTP_ASYM_CORRECTION 0x2C04
441 #define KSZ8567_PORT2_PTP_XDLY_REQ_TSH 0x2C08
442 #define KSZ8567_PORT2_PTP_XDLY_REQ_TSL 0x2C0A
443 #define KSZ8567_PORT2_PTP_SYNC_TSH 0x2C0C
444 #define KSZ8567_PORT2_PTP_SYNC_TSL 0x2C0E
445 #define KSZ8567_PORT2_PTP_PDLY_RESP_TSH 0x2C10
446 #define KSZ8567_PORT2_PTP_PDLY_RESP_TSL 0x2C12
447 #define KSZ8567_PORT2_PTP_TS_INT_STAT 0x2C14
448 #define KSZ8567_PORT2_PTP_TS_INT_EN 0x2C16
449 #define KSZ8567_PORT2_PTP_LINK_DELAY 0x2C18
450 #define KSZ8567_PORT3_DEFAULT_TAG0 0x3000
451 #define KSZ8567_PORT3_DEFAULT_TAG1 0x3001
452 #define KSZ8567_PORT3_PME_WOL_EVENT 0x3013
453 #define KSZ8567_PORT3_PME_WOL_EN 0x3017
454 #define KSZ8567_PORT3_INT_STATUS 0x301B
455 #define KSZ8567_PORT3_INT_MASK 0x301F
456 #define KSZ8567_PORT3_OP_CTRL0 0x3020
457 #define KSZ8567_PORT3_STATUS 0x3030
458 #define KSZ8567_PORT3_MAC_CTRL0 0x3400
459 #define KSZ8567_PORT3_MAC_CTRL1 0x3401
460 #define KSZ8567_PORT3_IG_RATE_LIMIT_CTRL 0x3403
461 #define KSZ8567_PORT3_PRIO0_IG_LIMIT_CTRL 0x3410
462 #define KSZ8567_PORT3_PRIO1_IG_LIMIT_CTRL 0x3411
463 #define KSZ8567_PORT3_PRIO2_IG_LIMIT_CTRL 0x3412
464 #define KSZ8567_PORT3_PRIO3_IG_LIMIT_CTRL 0x3413
465 #define KSZ8567_PORT3_PRIO4_IG_LIMIT_CTRL 0x3414
466 #define KSZ8567_PORT3_PRIO5_IG_LIMIT_CTRL 0x3415
467 #define KSZ8567_PORT3_PRIO6_IG_LIMIT_CTRL 0x3416
468 #define KSZ8567_PORT3_PRIO7_IG_LIMIT_CTRL 0x3417
469 #define KSZ8567_PORT3_QUEUE0_EG_LIMIT_CTRL 0x3420
470 #define KSZ8567_PORT3_QUEUE1_EG_LIMIT_CTRL 0x3421
471 #define KSZ8567_PORT3_QUEUE2_EG_LIMIT_CTRL 0x3422
472 #define KSZ8567_PORT3_QUEUE3_EG_LIMIT_CTRL 0x3423
473 #define KSZ8567_PORT3_MIB_CTRL_STAT 0x3500
474 #define KSZ8567_PORT3_MIB_DATA 0x3504
475 #define KSZ8567_PORT3_ACL_ACCESS0 0x3600
476 #define KSZ8567_PORT3_ACL_ACCESS1 0x3601
477 #define KSZ8567_PORT3_ACL_ACCESS2 0x3602
478 #define KSZ8567_PORT3_ACL_ACCESS3 0x3603
479 #define KSZ8567_PORT3_ACL_ACCESS4 0x3604
480 #define KSZ8567_PORT3_ACL_ACCESS5 0x3605
481 #define KSZ8567_PORT3_ACL_ACCESS6 0x3606
482 #define KSZ8567_PORT3_ACL_ACCESS7 0x3607
483 #define KSZ8567_PORT3_ACL_ACCESS8 0x3608
484 #define KSZ8567_PORT3_ACL_ACCESS9 0x3609
485 #define KSZ8567_PORT3_ACL_ACCESS10 0x360A
486 #define KSZ8567_PORT3_ACL_ACCESS11 0x360B
487 #define KSZ8567_PORT3_ACL_ACCESS12 0x360C
488 #define KSZ8567_PORT3_ACL_ACCESS13 0x360D
489 #define KSZ8567_PORT3_ACL_ACCESS14 0x360E
490 #define KSZ8567_PORT3_ACL_ACCESS15 0x360F
491 #define KSZ8567_PORT3_ACL_BYTE_EN_MSB 0x3610
492 #define KSZ8567_PORT3_ACL_BYTE_EN_LSB 0x3611
493 #define KSZ8567_PORT3_ACL_ACCESS_CTRL0 0x3612
494 #define KSZ8567_PORT3_MIRRORING_CTRL 0x3800
495 #define KSZ8567_PORT3_PRIO_CTRL 0x3801
496 #define KSZ8567_PORT3_IG_MAC_CTRL 0x3802
497 #define KSZ8567_PORT3_AUTH_CTRL 0x3803
498 #define KSZ8567_PORT3_PTR 0x3804
499 #define KSZ8567_PORT3_PRIO_TO_QUEUE_MAPPING 0x3808
500 #define KSZ8567_PORT3_POLICE_CTRL 0x380C
501 #define KSZ8567_PORT3_POLICE_QUEUE_RATE 0x3820
502 #define KSZ8567_PORT3_POLICE_QUEUE_BURST_SIZE 0x3824
503 #define KSZ8567_PORT3_WRED_PKT_MEM_CTRL0 0x3830
504 #define KSZ8567_PORT3_WRED_PKT_MEM_CTRL1 0x3834
505 #define KSZ8567_PORT3_WRED_QUEUE_CTRL0 0x3840
506 #define KSZ8567_PORT3_WRED_QUEUE_CTRL1 0x3844
507 #define KSZ8567_PORT3_WRED_QUEUE_PERF_MON_CTRL 0x3848
508 #define KSZ8567_PORT3_TX_QUEUE_INDEX 0x3900
509 #define KSZ8567_PORT3_TX_QUEUE_PVID 0x3904
510 #define KSZ8567_PORT3_TX_QUEUE_CTRL0 0x3914
511 #define KSZ8567_PORT3_TX_QUEUE_CTRL1 0x3915
512 #define KSZ8567_PORT3_TX_CREDIT_SHAPER_CTRL0 0x3916
513 #define KSZ8567_PORT3_TX_CREDIT_SHAPER_CTRL1 0x3918
514 #define KSZ8567_PORT3_TX_CREDIT_SHAPER_CTRL2 0x391A
515 #define KSZ8567_PORT3_TAS_CTRL 0x3920
516 #define KSZ8567_PORT3_TAS_EVENT_INDEX 0x3923
517 #define KSZ8567_PORT3_TAS_EVENT 0x3924
518 #define KSZ8567_PORT3_CTRL0 0x3A00
519 #define KSZ8567_PORT3_CTRL1 0x3A04
520 #define KSZ8567_PORT3_CTRL2 0x3B00
521 #define KSZ8567_PORT3_MSTP_PTR 0x3B01
522 #define KSZ8567_PORT3_MSTP_STATE 0x3B04
523 #define KSZ8567_PORT3_PTP_RX_LATENCY 0x3C00
524 #define KSZ8567_PORT3_PTP_TX_LATENCY 0x3C02
525 #define KSZ8567_PORT3_PTP_ASYM_CORRECTION 0x3C04
526 #define KSZ8567_PORT3_PTP_XDLY_REQ_TSH 0x3C08
527 #define KSZ8567_PORT3_PTP_XDLY_REQ_TSL 0x3C0A
528 #define KSZ8567_PORT3_PTP_SYNC_TSH 0x3C0C
529 #define KSZ8567_PORT3_PTP_SYNC_TSL 0x3C0E
530 #define KSZ8567_PORT3_PTP_PDLY_RESP_TSH 0x3C10
531 #define KSZ8567_PORT3_PTP_PDLY_RESP_TSL 0x3C12
532 #define KSZ8567_PORT3_PTP_TS_INT_STAT 0x3C14
533 #define KSZ8567_PORT3_PTP_TS_INT_EN 0x3C16
534 #define KSZ8567_PORT3_PTP_LINK_DELAY 0x3C18
535 #define KSZ8567_PORT4_DEFAULT_TAG0 0x4000
536 #define KSZ8567_PORT4_DEFAULT_TAG1 0x4001
537 #define KSZ8567_PORT4_PME_WOL_EVENT 0x4013
538 #define KSZ8567_PORT4_PME_WOL_EN 0x4017
539 #define KSZ8567_PORT4_INT_STATUS 0x401B
540 #define KSZ8567_PORT4_INT_MASK 0x401F
541 #define KSZ8567_PORT4_OP_CTRL0 0x4020
542 #define KSZ8567_PORT4_STATUS 0x4030
543 #define KSZ8567_PORT4_MAC_CTRL0 0x4400
544 #define KSZ8567_PORT4_MAC_CTRL1 0x4401
545 #define KSZ8567_PORT4_IG_RATE_LIMIT_CTRL 0x4403
546 #define KSZ8567_PORT4_PRIO0_IG_LIMIT_CTRL 0x4410
547 #define KSZ8567_PORT4_PRIO1_IG_LIMIT_CTRL 0x4411
548 #define KSZ8567_PORT4_PRIO2_IG_LIMIT_CTRL 0x4412
549 #define KSZ8567_PORT4_PRIO3_IG_LIMIT_CTRL 0x4413
550 #define KSZ8567_PORT4_PRIO4_IG_LIMIT_CTRL 0x4414
551 #define KSZ8567_PORT4_PRIO5_IG_LIMIT_CTRL 0x4415
552 #define KSZ8567_PORT4_PRIO6_IG_LIMIT_CTRL 0x4416
553 #define KSZ8567_PORT4_PRIO7_IG_LIMIT_CTRL 0x4417
554 #define KSZ8567_PORT4_QUEUE0_EG_LIMIT_CTRL 0x4420
555 #define KSZ8567_PORT4_QUEUE1_EG_LIMIT_CTRL 0x4421
556 #define KSZ8567_PORT4_QUEUE2_EG_LIMIT_CTRL 0x4422
557 #define KSZ8567_PORT4_QUEUE3_EG_LIMIT_CTRL 0x4423
558 #define KSZ8567_PORT4_MIB_CTRL_STAT 0x4500
559 #define KSZ8567_PORT4_MIB_DATA 0x4504
560 #define KSZ8567_PORT4_ACL_ACCESS0 0x4600
561 #define KSZ8567_PORT4_ACL_ACCESS1 0x4601
562 #define KSZ8567_PORT4_ACL_ACCESS2 0x4602
563 #define KSZ8567_PORT4_ACL_ACCESS3 0x4603
564 #define KSZ8567_PORT4_ACL_ACCESS4 0x4604
565 #define KSZ8567_PORT4_ACL_ACCESS5 0x4605
566 #define KSZ8567_PORT4_ACL_ACCESS6 0x4606
567 #define KSZ8567_PORT4_ACL_ACCESS7 0x4607
568 #define KSZ8567_PORT4_ACL_ACCESS8 0x4608
569 #define KSZ8567_PORT4_ACL_ACCESS9 0x4609
570 #define KSZ8567_PORT4_ACL_ACCESS10 0x460A
571 #define KSZ8567_PORT4_ACL_ACCESS11 0x460B
572 #define KSZ8567_PORT4_ACL_ACCESS12 0x460C
573 #define KSZ8567_PORT4_ACL_ACCESS13 0x460D
574 #define KSZ8567_PORT4_ACL_ACCESS14 0x460E
575 #define KSZ8567_PORT4_ACL_ACCESS15 0x460F
576 #define KSZ8567_PORT4_ACL_BYTE_EN_MSB 0x4610
577 #define KSZ8567_PORT4_ACL_BYTE_EN_LSB 0x4611
578 #define KSZ8567_PORT4_ACL_ACCESS_CTRL0 0x4612
579 #define KSZ8567_PORT4_MIRRORING_CTRL 0x4800
580 #define KSZ8567_PORT4_PRIO_CTRL 0x4801
581 #define KSZ8567_PORT4_IG_MAC_CTRL 0x4802
582 #define KSZ8567_PORT4_AUTH_CTRL 0x4803
583 #define KSZ8567_PORT4_PTR 0x4804
584 #define KSZ8567_PORT4_PRIO_TO_QUEUE_MAPPING 0x4808
585 #define KSZ8567_PORT4_POLICE_CTRL 0x480C
586 #define KSZ8567_PORT4_POLICE_QUEUE_RATE 0x4820
587 #define KSZ8567_PORT4_POLICE_QUEUE_BURST_SIZE 0x4824
588 #define KSZ8567_PORT4_WRED_PKT_MEM_CTRL0 0x4830
589 #define KSZ8567_PORT4_WRED_PKT_MEM_CTRL1 0x4834
590 #define KSZ8567_PORT4_WRED_QUEUE_CTRL0 0x4840
591 #define KSZ8567_PORT4_WRED_QUEUE_CTRL1 0x4844
592 #define KSZ8567_PORT4_WRED_QUEUE_PERF_MON_CTRL 0x4848
593 #define KSZ8567_PORT4_TX_QUEUE_INDEX 0x4900
594 #define KSZ8567_PORT4_TX_QUEUE_PVID 0x4904
595 #define KSZ8567_PORT4_TX_QUEUE_CTRL0 0x4914
596 #define KSZ8567_PORT4_TX_QUEUE_CTRL1 0x4915
597 #define KSZ8567_PORT4_TX_CREDIT_SHAPER_CTRL0 0x4916
598 #define KSZ8567_PORT4_TX_CREDIT_SHAPER_CTRL1 0x4918
599 #define KSZ8567_PORT4_TX_CREDIT_SHAPER_CTRL2 0x491A
600 #define KSZ8567_PORT4_TAS_CTRL 0x4920
601 #define KSZ8567_PORT4_TAS_EVENT_INDEX 0x4923
602 #define KSZ8567_PORT4_TAS_EVENT 0x4924
603 #define KSZ8567_PORT4_CTRL0 0x4A00
604 #define KSZ8567_PORT4_CTRL1 0x4A04
605 #define KSZ8567_PORT4_CTRL2 0x4B00
606 #define KSZ8567_PORT4_MSTP_PTR 0x4B01
607 #define KSZ8567_PORT4_MSTP_STATE 0x4B04
608 #define KSZ8567_PORT4_PTP_RX_LATENCY 0x4C00
609 #define KSZ8567_PORT4_PTP_TX_LATENCY 0x4C02
610 #define KSZ8567_PORT4_PTP_ASYM_CORRECTION 0x4C04
611 #define KSZ8567_PORT4_PTP_XDLY_REQ_TSH 0x4C08
612 #define KSZ8567_PORT4_PTP_XDLY_REQ_TSL 0x4C0A
613 #define KSZ8567_PORT4_PTP_SYNC_TSH 0x4C0C
614 #define KSZ8567_PORT4_PTP_SYNC_TSL 0x4C0E
615 #define KSZ8567_PORT4_PTP_PDLY_RESP_TSH 0x4C10
616 #define KSZ8567_PORT4_PTP_PDLY_RESP_TSL 0x4C12
617 #define KSZ8567_PORT4_PTP_TS_INT_STAT 0x4C14
618 #define KSZ8567_PORT4_PTP_TS_INT_EN 0x4C16
619 #define KSZ8567_PORT4_PTP_LINK_DELAY 0x4C18
620 #define KSZ8567_PORT5_DEFAULT_TAG0 0x5000
621 #define KSZ8567_PORT5_DEFAULT_TAG1 0x5001
622 #define KSZ8567_PORT5_PME_WOL_EVENT 0x5013
623 #define KSZ8567_PORT5_PME_WOL_EN 0x5017
624 #define KSZ8567_PORT5_INT_STATUS 0x501B
625 #define KSZ8567_PORT5_INT_MASK 0x501F
626 #define KSZ8567_PORT5_OP_CTRL0 0x5020
627 #define KSZ8567_PORT5_STATUS 0x5030
628 #define KSZ8567_PORT5_MAC_CTRL0 0x5400
629 #define KSZ8567_PORT5_MAC_CTRL1 0x5401
630 #define KSZ8567_PORT5_IG_RATE_LIMIT_CTRL 0x5403
631 #define KSZ8567_PORT5_PRIO0_IG_LIMIT_CTRL 0x5410
632 #define KSZ8567_PORT5_PRIO1_IG_LIMIT_CTRL 0x5411
633 #define KSZ8567_PORT5_PRIO2_IG_LIMIT_CTRL 0x5412
634 #define KSZ8567_PORT5_PRIO3_IG_LIMIT_CTRL 0x5413
635 #define KSZ8567_PORT5_PRIO4_IG_LIMIT_CTRL 0x5414
636 #define KSZ8567_PORT5_PRIO5_IG_LIMIT_CTRL 0x5415
637 #define KSZ8567_PORT5_PRIO6_IG_LIMIT_CTRL 0x5416
638 #define KSZ8567_PORT5_PRIO7_IG_LIMIT_CTRL 0x5417
639 #define KSZ8567_PORT5_QUEUE0_EG_LIMIT_CTRL 0x5420
640 #define KSZ8567_PORT5_QUEUE1_EG_LIMIT_CTRL 0x5421
641 #define KSZ8567_PORT5_QUEUE2_EG_LIMIT_CTRL 0x5422
642 #define KSZ8567_PORT5_QUEUE3_EG_LIMIT_CTRL 0x5423
643 #define KSZ8567_PORT5_MIB_CTRL_STAT 0x5500
644 #define KSZ8567_PORT5_MIB_DATA 0x5504
645 #define KSZ8567_PORT5_ACL_ACCESS0 0x5600
646 #define KSZ8567_PORT5_ACL_ACCESS1 0x5601
647 #define KSZ8567_PORT5_ACL_ACCESS2 0x5602
648 #define KSZ8567_PORT5_ACL_ACCESS3 0x5603
649 #define KSZ8567_PORT5_ACL_ACCESS4 0x5604
650 #define KSZ8567_PORT5_ACL_ACCESS5 0x5605
651 #define KSZ8567_PORT5_ACL_ACCESS6 0x5606
652 #define KSZ8567_PORT5_ACL_ACCESS7 0x5607
653 #define KSZ8567_PORT5_ACL_ACCESS8 0x5608
654 #define KSZ8567_PORT5_ACL_ACCESS9 0x5609
655 #define KSZ8567_PORT5_ACL_ACCESS10 0x560A
656 #define KSZ8567_PORT5_ACL_ACCESS11 0x560B
657 #define KSZ8567_PORT5_ACL_ACCESS12 0x560C
658 #define KSZ8567_PORT5_ACL_ACCESS13 0x560D
659 #define KSZ8567_PORT5_ACL_ACCESS14 0x560E
660 #define KSZ8567_PORT5_ACL_ACCESS15 0x560F
661 #define KSZ8567_PORT5_ACL_BYTE_EN_MSB 0x5610
662 #define KSZ8567_PORT5_ACL_BYTE_EN_LSB 0x5611
663 #define KSZ8567_PORT5_ACL_ACCESS_CTRL0 0x5612
664 #define KSZ8567_PORT5_MIRRORING_CTRL 0x5800
665 #define KSZ8567_PORT5_PRIO_CTRL 0x5801
666 #define KSZ8567_PORT5_IG_MAC_CTRL 0x5802
667 #define KSZ8567_PORT5_AUTH_CTRL 0x5803
668 #define KSZ8567_PORT5_PTR 0x5804
669 #define KSZ8567_PORT5_PRIO_TO_QUEUE_MAPPING 0x5808
670 #define KSZ8567_PORT5_POLICE_CTRL 0x580C
671 #define KSZ8567_PORT5_POLICE_QUEUE_RATE 0x5820
672 #define KSZ8567_PORT5_POLICE_QUEUE_BURST_SIZE 0x5824
673 #define KSZ8567_PORT5_WRED_PKT_MEM_CTRL0 0x5830
674 #define KSZ8567_PORT5_WRED_PKT_MEM_CTRL1 0x5834
675 #define KSZ8567_PORT5_WRED_QUEUE_CTRL0 0x5840
676 #define KSZ8567_PORT5_WRED_QUEUE_CTRL1 0x5844
677 #define KSZ8567_PORT5_WRED_QUEUE_PERF_MON_CTRL 0x5848
678 #define KSZ8567_PORT5_TX_QUEUE_INDEX 0x5900
679 #define KSZ8567_PORT5_TX_QUEUE_PVID 0x5904
680 #define KSZ8567_PORT5_TX_QUEUE_CTRL0 0x5914
681 #define KSZ8567_PORT5_TX_QUEUE_CTRL1 0x5915
682 #define KSZ8567_PORT5_TX_CREDIT_SHAPER_CTRL0 0x5916
683 #define KSZ8567_PORT5_TX_CREDIT_SHAPER_CTRL1 0x5918
684 #define KSZ8567_PORT5_TX_CREDIT_SHAPER_CTRL2 0x591A
685 #define KSZ8567_PORT5_TAS_CTRL 0x5920
686 #define KSZ8567_PORT5_TAS_EVENT_INDEX 0x5923
687 #define KSZ8567_PORT5_TAS_EVENT 0x5924
688 #define KSZ8567_PORT5_CTRL0 0x5A00
689 #define KSZ8567_PORT5_CTRL1 0x5A04
690 #define KSZ8567_PORT5_CTRL2 0x5B00
691 #define KSZ8567_PORT5_MSTP_PTR 0x5B01
692 #define KSZ8567_PORT5_MSTP_STATE 0x5B04
693 #define KSZ8567_PORT5_PTP_RX_LATENCY 0x5C00
694 #define KSZ8567_PORT5_PTP_TX_LATENCY 0x5C02
695 #define KSZ8567_PORT5_PTP_ASYM_CORRECTION 0x5C04
696 #define KSZ8567_PORT5_PTP_XDLY_REQ_TSH 0x5C08
697 #define KSZ8567_PORT5_PTP_XDLY_REQ_TSL 0x5C0A
698 #define KSZ8567_PORT5_PTP_SYNC_TSH 0x5C0C
699 #define KSZ8567_PORT5_PTP_SYNC_TSL 0x5C0E
700 #define KSZ8567_PORT5_PTP_PDLY_RESP_TSH 0x5C10
701 #define KSZ8567_PORT5_PTP_PDLY_RESP_TSL 0x5C12
702 #define KSZ8567_PORT5_PTP_TS_INT_STAT 0x5C14
703 #define KSZ8567_PORT5_PTP_TS_INT_EN 0x5C16
704 #define KSZ8567_PORT5_PTP_LINK_DELAY 0x5C18
705 #define KSZ8567_PORT6_DEFAULT_TAG0 0x6000
706 #define KSZ8567_PORT6_DEFAULT_TAG1 0x6001
707 #define KSZ8567_PORT6_PME_WOL_EVENT 0x6013
708 #define KSZ8567_PORT6_PME_WOL_EN 0x6017
709 #define KSZ8567_PORT6_INT_STATUS 0x601B
710 #define KSZ8567_PORT6_INT_MASK 0x601F
711 #define KSZ8567_PORT6_OP_CTRL0 0x6020
712 #define KSZ8567_PORT6_STATUS 0x6030
713 #define KSZ8567_PORT6_XMII_CTRL0 0x6300
714 #define KSZ8567_PORT6_XMII_CTRL1 0x6301
715 #define KSZ8567_PORT6_MAC_CTRL0 0x6400
716 #define KSZ8567_PORT6_MAC_CTRL1 0x6401
717 #define KSZ8567_PORT6_IG_RATE_LIMIT_CTRL 0x6403
718 #define KSZ8567_PORT6_PRIO0_IG_LIMIT_CTRL 0x6410
719 #define KSZ8567_PORT6_PRIO1_IG_LIMIT_CTRL 0x6411
720 #define KSZ8567_PORT6_PRIO2_IG_LIMIT_CTRL 0x6412
721 #define KSZ8567_PORT6_PRIO3_IG_LIMIT_CTRL 0x6413
722 #define KSZ8567_PORT6_PRIO4_IG_LIMIT_CTRL 0x6414
723 #define KSZ8567_PORT6_PRIO5_IG_LIMIT_CTRL 0x6415
724 #define KSZ8567_PORT6_PRIO6_IG_LIMIT_CTRL 0x6416
725 #define KSZ8567_PORT6_PRIO7_IG_LIMIT_CTRL 0x6417
726 #define KSZ8567_PORT6_QUEUE0_EG_LIMIT_CTRL 0x6420
727 #define KSZ8567_PORT6_QUEUE1_EG_LIMIT_CTRL 0x6421
728 #define KSZ8567_PORT6_QUEUE2_EG_LIMIT_CTRL 0x6422
729 #define KSZ8567_PORT6_QUEUE3_EG_LIMIT_CTRL 0x6423
730 #define KSZ8567_PORT6_MIB_CTRL_STAT 0x6500
731 #define KSZ8567_PORT6_MIB_DATA 0x6504
732 #define KSZ8567_PORT6_ACL_ACCESS0 0x6600
733 #define KSZ8567_PORT6_ACL_ACCESS1 0x6601
734 #define KSZ8567_PORT6_ACL_ACCESS2 0x6602
735 #define KSZ8567_PORT6_ACL_ACCESS3 0x6603
736 #define KSZ8567_PORT6_ACL_ACCESS4 0x6604
737 #define KSZ8567_PORT6_ACL_ACCESS5 0x6605
738 #define KSZ8567_PORT6_ACL_ACCESS6 0x6606
739 #define KSZ8567_PORT6_ACL_ACCESS7 0x6607
740 #define KSZ8567_PORT6_ACL_ACCESS8 0x6608
741 #define KSZ8567_PORT6_ACL_ACCESS9 0x6609
742 #define KSZ8567_PORT6_ACL_ACCESS10 0x660A
743 #define KSZ8567_PORT6_ACL_ACCESS11 0x660B
744 #define KSZ8567_PORT6_ACL_ACCESS12 0x660C
745 #define KSZ8567_PORT6_ACL_ACCESS13 0x660D
746 #define KSZ8567_PORT6_ACL_ACCESS14 0x660E
747 #define KSZ8567_PORT6_ACL_ACCESS15 0x660F
748 #define KSZ8567_PORT6_ACL_BYTE_EN_MSB 0x6610
749 #define KSZ8567_PORT6_ACL_BYTE_EN_LSB 0x6611
750 #define KSZ8567_PORT6_ACL_ACCESS_CTRL0 0x6612
751 #define KSZ8567_PORT6_MIRRORING_CTRL 0x6800
752 #define KSZ8567_PORT6_PRIO_CTRL 0x6801
753 #define KSZ8567_PORT6_IG_MAC_CTRL 0x6802
754 #define KSZ8567_PORT6_AUTH_CTRL 0x6803
755 #define KSZ8567_PORT6_PTR 0x6804
756 #define KSZ8567_PORT6_PRIO_TO_QUEUE_MAPPING 0x6808
757 #define KSZ8567_PORT6_POLICE_CTRL 0x680C
758 #define KSZ8567_PORT6_POLICE_QUEUE_RATE 0x6820
759 #define KSZ8567_PORT6_POLICE_QUEUE_BURST_SIZE 0x6824
760 #define KSZ8567_PORT6_WRED_PKT_MEM_CTRL0 0x6830
761 #define KSZ8567_PORT6_WRED_PKT_MEM_CTRL1 0x6834
762 #define KSZ8567_PORT6_WRED_QUEUE_CTRL0 0x6840
763 #define KSZ8567_PORT6_WRED_QUEUE_CTRL1 0x6844
764 #define KSZ8567_PORT6_WRED_QUEUE_PERF_MON_CTRL 0x6848
765 #define KSZ8567_PORT6_TX_QUEUE_INDEX 0x6900
766 #define KSZ8567_PORT6_TX_QUEUE_PVID 0x6904
767 #define KSZ8567_PORT6_TX_QUEUE_CTRL0 0x6914
768 #define KSZ8567_PORT6_TX_QUEUE_CTRL1 0x6915
769 #define KSZ8567_PORT6_TX_CREDIT_SHAPER_CTRL0 0x6916
770 #define KSZ8567_PORT6_TX_CREDIT_SHAPER_CTRL1 0x6918
771 #define KSZ8567_PORT6_TX_CREDIT_SHAPER_CTRL2 0x691A
772 #define KSZ8567_PORT6_TAS_CTRL 0x6920
773 #define KSZ8567_PORT6_TAS_EVENT_INDEX 0x6923
774 #define KSZ8567_PORT6_TAS_EVENT 0x6924
775 #define KSZ8567_PORT6_CTRL0 0x6A00
776 #define KSZ8567_PORT6_CTRL1 0x6A04
777 #define KSZ8567_PORT6_CTRL2 0x6B00
778 #define KSZ8567_PORT6_MSTP_PTR 0x6B01
779 #define KSZ8567_PORT6_MSTP_STATE 0x6B04
780 #define KSZ8567_PORT6_PTP_RX_LATENCY 0x6C00
781 #define KSZ8567_PORT6_PTP_TX_LATENCY 0x6C02
782 #define KSZ8567_PORT6_PTP_ASYM_CORRECTION 0x6C04
783 #define KSZ8567_PORT6_PTP_XDLY_REQ_TSH 0x6C08
784 #define KSZ8567_PORT6_PTP_XDLY_REQ_TSL 0x6C0A
785 #define KSZ8567_PORT6_PTP_SYNC_TSH 0x6C0C
786 #define KSZ8567_PORT6_PTP_SYNC_TSL 0x6C0E
787 #define KSZ8567_PORT6_PTP_PDLY_RESP_TSH 0x6C10
788 #define KSZ8567_PORT6_PTP_PDLY_RESP_TSL 0x6C12
789 #define KSZ8567_PORT6_PTP_TS_INT_STAT 0x6C14
790 #define KSZ8567_PORT6_PTP_TS_INT_EN 0x6C16
791 #define KSZ8567_PORT6_PTP_LINK_DELAY 0x6C18
792 #define KSZ8567_PORT7_DEFAULT_TAG0 0x7000
793 #define KSZ8567_PORT7_DEFAULT_TAG1 0x7001
794 #define KSZ8567_PORT7_PME_WOL_EVENT 0x7013
795 #define KSZ8567_PORT7_PME_WOL_EN 0x7017
796 #define KSZ8567_PORT7_INT_STATUS 0x701B
797 #define KSZ8567_PORT7_INT_MASK 0x701F
798 #define KSZ8567_PORT7_OP_CTRL0 0x7020
799 #define KSZ8567_PORT7_STATUS 0x7030
800 #define KSZ8567_PORT7_SGMII_ADDR 0x7200
801 #define KSZ8567_PORT7_SGMII_DATA 0x7206
802 #define KSZ8567_PORT7_XMII_CTRL0 0x7300
803 #define KSZ8567_PORT7_XMII_CTRL1 0x7301
804 #define KSZ8567_PORT7_MAC_CTRL0 0x7400
805 #define KSZ8567_PORT7_MAC_CTRL1 0x7401
806 #define KSZ8567_PORT7_IG_RATE_LIMIT_CTRL 0x7403
807 #define KSZ8567_PORT7_PRIO0_IG_LIMIT_CTRL 0x7410
808 #define KSZ8567_PORT7_PRIO1_IG_LIMIT_CTRL 0x7411
809 #define KSZ8567_PORT7_PRIO2_IG_LIMIT_CTRL 0x7412
810 #define KSZ8567_PORT7_PRIO3_IG_LIMIT_CTRL 0x7413
811 #define KSZ8567_PORT7_PRIO4_IG_LIMIT_CTRL 0x7414
812 #define KSZ8567_PORT7_PRIO5_IG_LIMIT_CTRL 0x7415
813 #define KSZ8567_PORT7_PRIO6_IG_LIMIT_CTRL 0x7416
814 #define KSZ8567_PORT7_PRIO7_IG_LIMIT_CTRL 0x7417
815 #define KSZ8567_PORT7_QUEUE0_EG_LIMIT_CTRL 0x7420
816 #define KSZ8567_PORT7_QUEUE1_EG_LIMIT_CTRL 0x7421
817 #define KSZ8567_PORT7_QUEUE2_EG_LIMIT_CTRL 0x7422
818 #define KSZ8567_PORT7_QUEUE3_EG_LIMIT_CTRL 0x7423
819 #define KSZ8567_PORT7_MIB_CTRL_STAT 0x7500
820 #define KSZ8567_PORT7_MIB_DATA 0x7504
821 #define KSZ8567_PORT7_ACL_ACCESS0 0x7600
822 #define KSZ8567_PORT7_ACL_ACCESS1 0x7601
823 #define KSZ8567_PORT7_ACL_ACCESS2 0x7602
824 #define KSZ8567_PORT7_ACL_ACCESS3 0x7603
825 #define KSZ8567_PORT7_ACL_ACCESS4 0x7604
826 #define KSZ8567_PORT7_ACL_ACCESS5 0x7605
827 #define KSZ8567_PORT7_ACL_ACCESS6 0x7606
828 #define KSZ8567_PORT7_ACL_ACCESS7 0x7607
829 #define KSZ8567_PORT7_ACL_ACCESS8 0x7608
830 #define KSZ8567_PORT7_ACL_ACCESS9 0x7609
831 #define KSZ8567_PORT7_ACL_ACCESS10 0x760A
832 #define KSZ8567_PORT7_ACL_ACCESS11 0x760B
833 #define KSZ8567_PORT7_ACL_ACCESS12 0x760C
834 #define KSZ8567_PORT7_ACL_ACCESS13 0x760D
835 #define KSZ8567_PORT7_ACL_ACCESS14 0x760E
836 #define KSZ8567_PORT7_ACL_ACCESS15 0x760F
837 #define KSZ8567_PORT7_ACL_BYTE_EN_MSB 0x7610
838 #define KSZ8567_PORT7_ACL_BYTE_EN_LSB 0x7611
839 #define KSZ8567_PORT7_ACL_ACCESS_CTRL0 0x7612
840 #define KSZ8567_PORT7_MIRRORING_CTRL 0x7800
841 #define KSZ8567_PORT7_PRIO_CTRL 0x7801
842 #define KSZ8567_PORT7_IG_MAC_CTRL 0x7802
843 #define KSZ8567_PORT7_AUTH_CTRL 0x7803
844 #define KSZ8567_PORT7_PTR 0x7804
845 #define KSZ8567_PORT7_PRIO_TO_QUEUE_MAPPING 0x7808
846 #define KSZ8567_PORT7_POLICE_CTRL 0x780C
847 #define KSZ8567_PORT7_POLICE_QUEUE_RATE 0x7820
848 #define KSZ8567_PORT7_POLICE_QUEUE_BURST_SIZE 0x7824
849 #define KSZ8567_PORT7_WRED_PKT_MEM_CTRL0 0x7830
850 #define KSZ8567_PORT7_WRED_PKT_MEM_CTRL1 0x7834
851 #define KSZ8567_PORT7_WRED_QUEUE_CTRL0 0x7840
852 #define KSZ8567_PORT7_WRED_QUEUE_CTRL1 0x7844
853 #define KSZ8567_PORT7_WRED_QUEUE_PERF_MON_CTRL 0x7848
854 #define KSZ8567_PORT7_TX_QUEUE_INDEX 0x7900
855 #define KSZ8567_PORT7_TX_QUEUE_PVID 0x7904
856 #define KSZ8567_PORT7_TX_QUEUE_CTRL0 0x7914
857 #define KSZ8567_PORT7_TX_QUEUE_CTRL1 0x7915
858 #define KSZ8567_PORT7_TX_CREDIT_SHAPER_CTRL0 0x7916
859 #define KSZ8567_PORT7_TX_CREDIT_SHAPER_CTRL1 0x7918
860 #define KSZ8567_PORT7_TX_CREDIT_SHAPER_CTRL2 0x791A
861 #define KSZ8567_PORT7_TAS_CTRL 0x7920
862 #define KSZ8567_PORT7_TAS_EVENT_INDEX 0x7923
863 #define KSZ8567_PORT7_TAS_EVENT 0x7924
864 #define KSZ8567_PORT7_CTRL0 0x7A00
865 #define KSZ8567_PORT7_CTRL1 0x7A04
866 #define KSZ8567_PORT7_CTRL2 0x7B00
867 #define KSZ8567_PORT7_MSTP_PTR 0x7B01
868 #define KSZ8567_PORT7_MSTP_STATE 0x7B04
869 #define KSZ8567_PORT7_PTP_RX_LATENCY 0x7C00
870 #define KSZ8567_PORT7_PTP_TX_LATENCY 0x7C02
871 #define KSZ8567_PORT7_PTP_ASYM_CORRECTION 0x7C04
872 #define KSZ8567_PORT7_PTP_XDLY_REQ_TSH 0x7C08
873 #define KSZ8567_PORT7_PTP_XDLY_REQ_TSL 0x7C0A
874 #define KSZ8567_PORT7_PTP_SYNC_TSH 0x7C0C
875 #define KSZ8567_PORT7_PTP_SYNC_TSL 0x7C0E
876 #define KSZ8567_PORT7_PTP_PDLY_RESP_TSH 0x7C10
877 #define KSZ8567_PORT7_PTP_PDLY_RESP_TSL 0x7C12
878 #define KSZ8567_PORT7_PTP_TS_INT_STAT 0x7C14
879 #define KSZ8567_PORT7_PTP_TS_INT_EN 0x7C16
880 #define KSZ8567_PORT7_PTP_LINK_DELAY 0x7C18
881 
882 //KSZ8567 Switch register access macros
883 #define KSZ8567_PORTn_DEFAULT_TAG0(port) (0x0000 + ((port) * 0x1000))
884 #define KSZ8567_PORTn_DEFAULT_TAG1(port) (0x0001 + ((port) * 0x1000))
885 #define KSZ8567_PORTn_PME_WOL_EVENT(port) (0x0013 + ((port) * 0x1000))
886 #define KSZ8567_PORTn_PME_WOL_EN(port) (0x0017 + ((port) * 0x1000))
887 #define KSZ8567_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
888 #define KSZ8567_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
889 #define KSZ8567_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
890 #define KSZ8567_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
891 #define KSZ8567_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
892 #define KSZ8567_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
893 #define KSZ8567_PORTn_MAC_CTRL0(port) (0x0400 + ((port) * 0x1000))
894 #define KSZ8567_PORTn_MAC_CTRL1(port) (0x0401 + ((port) * 0x1000))
895 #define KSZ8567_PORTn_IG_RATE_LIMIT_CTRL(port) (0x0403 + ((port) * 0x1000))
896 #define KSZ8567_PORTn_PRIO0_IG_LIMIT_CTRL(port) (0x0410 + ((port) * 0x1000))
897 #define KSZ8567_PORTn_PRIO1_IG_LIMIT_CTRL(port) (0x0411 + ((port) * 0x1000))
898 #define KSZ8567_PORTn_PRIO2_IG_LIMIT_CTRL(port) (0x0412 + ((port) * 0x1000))
899 #define KSZ8567_PORTn_PRIO3_IG_LIMIT_CTRL(port) (0x0413 + ((port) * 0x1000))
900 #define KSZ8567_PORTn_PRIO4_IG_LIMIT_CTRL(port) (0x0414 + ((port) * 0x1000))
901 #define KSZ8567_PORTn_PRIO5_IG_LIMIT_CTRL(port) (0x0415 + ((port) * 0x1000))
902 #define KSZ8567_PORTn_PRIO6_IG_LIMIT_CTRL(port) (0x0416 + ((port) * 0x1000))
903 #define KSZ8567_PORTn_PRIO7_IG_LIMIT_CTRL(port) (0x0417 + ((port) * 0x1000))
904 #define KSZ8567_PORTn_QUEUE0_EG_LIMIT_CTRL(port) (0x0420 + ((port) * 0x1000))
905 #define KSZ8567_PORTn_QUEUE1_EG_LIMIT_CTRL(port) (0x0421 + ((port) * 0x1000))
906 #define KSZ8567_PORTn_QUEUE2_EG_LIMIT_CTRL(port) (0x0422 + ((port) * 0x1000))
907 #define KSZ8567_PORTn_QUEUE3_EG_LIMIT_CTRL(port) (0x0423 + ((port) * 0x1000))
908 #define KSZ8567_PORTn_MIB_CTRL_STAT(port) (0x0500 + ((port) * 0x1000))
909 #define KSZ8567_PORTn_MIB_DATA(port) (0x0504 + ((port) * 0x1000))
910 #define KSZ8567_PORTn_ACL_ACCESS0(port) (0x0600 + ((port) * 0x1000))
911 #define KSZ8567_PORTn_ACL_ACCESS1(port) (0x0601 + ((port) * 0x1000))
912 #define KSZ8567_PORTn_ACL_ACCESS2(port) (0x0602 + ((port) * 0x1000))
913 #define KSZ8567_PORTn_ACL_ACCESS3(port) (0x0603 + ((port) * 0x1000))
914 #define KSZ8567_PORTn_ACL_ACCESS4(port) (0x0604 + ((port) * 0x1000))
915 #define KSZ8567_PORTn_ACL_ACCESS5(port) (0x0605 + ((port) * 0x1000))
916 #define KSZ8567_PORTn_ACL_ACCESS6(port) (0x0606 + ((port) * 0x1000))
917 #define KSZ8567_PORTn_ACL_ACCESS7(port) (0x0607 + ((port) * 0x1000))
918 #define KSZ8567_PORTn_ACL_ACCESS8(port) (0x0608 + ((port) * 0x1000))
919 #define KSZ8567_PORTn_ACL_ACCESS9(port) (0x0609 + ((port) * 0x1000))
920 #define KSZ8567_PORTn_ACL_ACCESS10(port) (0x060A + ((port) * 0x1000))
921 #define KSZ8567_PORTn_ACL_ACCESS11(port) (0x060B + ((port) * 0x1000))
922 #define KSZ8567_PORTn_ACL_ACCESS12(port) (0x060C + ((port) * 0x1000))
923 #define KSZ8567_PORTn_ACL_ACCESS13(port) (0x060D + ((port) * 0x1000))
924 #define KSZ8567_PORTn_ACL_ACCESS14(port) (0x060E + ((port) * 0x1000))
925 #define KSZ8567_PORTn_ACL_ACCESS15(port) (0x060F + ((port) * 0x1000))
926 #define KSZ8567_PORTn_ACL_BYTE_EN_MSB(port) (0x0610 + ((port) * 0x1000))
927 #define KSZ8567_PORTn_ACL_BYTE_EN_LSB(port) (0x0611 + ((port) * 0x1000))
928 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0(port) (0x0612 + ((port) * 0x1000))
929 #define KSZ8567_PORTn_MIRRORING_CTRL(port) (0x0800 + ((port) * 0x1000))
930 #define KSZ8567_PORTn_PRIO_CTRL(port) (0x0801 + ((port) * 0x1000))
931 #define KSZ8567_PORTn_IG_MAC_CTRL(port) (0x0802 + ((port) * 0x1000))
932 #define KSZ8567_PORTn_AUTH_CTRL(port) (0x0803 + ((port) * 0x1000))
933 #define KSZ8567_PORTn_PTR(port) (0x0804 + ((port) * 0x1000))
934 #define KSZ8567_PORTn_PRIO_TO_QUEUE_MAPPING(port) (0x0808 + ((port) * 0x1000))
935 #define KSZ8567_PORTn_POLICE_CTRL(port) (0x080C + ((port) * 0x1000))
936 #define KSZ8567_PORTn_POLICE_QUEUE_RATE(port) (0x0820 + ((port) * 0x1000))
937 #define KSZ8567_PORTn_POLICE_QUEUE_BURST_SIZE(port) (0x0824 + ((port) * 0x1000))
938 #define KSZ8567_PORTn_WRED_PKT_MEM_CTRL0(port) (0x0830 + ((port) * 0x1000))
939 #define KSZ8567_PORTn_WRED_PKT_MEM_CTRL1(port) (0x0834 + ((port) * 0x1000))
940 #define KSZ8567_PORTn_WRED_QUEUE_CTRL0(port) (0x0840 + ((port) * 0x1000))
941 #define KSZ8567_PORTn_WRED_QUEUE_CTRL1(port) (0x0844 + ((port) * 0x1000))
942 #define KSZ8567_PORTn_WRED_QUEUE_PERF_MON_CTRL(port) (0x0848 + ((port) * 0x1000))
943 #define KSZ8567_PORTn_TX_QUEUE_INDEX(port) (0x0900 + ((port) * 0x1000))
944 #define KSZ8567_PORTn_TX_QUEUE_PVID(port) (0x0904 + ((port) * 0x1000))
945 #define KSZ8567_PORTn_TX_QUEUE_CTRL0(port) (0x0914 + ((port) * 0x1000))
946 #define KSZ8567_PORTn_TX_QUEUE_CTRL1(port) (0x0915 + ((port) * 0x1000))
947 #define KSZ8567_PORTn_TX_CREDIT_SHAPER_CTRL0(port) (0x0916 + ((port) * 0x1000))
948 #define KSZ8567_PORTn_TX_CREDIT_SHAPER_CTRL1(port) (0x0918 + ((port) * 0x1000))
949 #define KSZ8567_PORTn_TX_CREDIT_SHAPER_CTRL2(port) (0x091A + ((port) * 0x1000))
950 #define KSZ8567_PORTn_TAS_CTRL(port) (0x0920 + ((port) * 0x1000))
951 #define KSZ8567_PORTn_TAS_EVENT_INDEX(port) (0x0923 + ((port) * 0x1000))
952 #define KSZ8567_PORTn_TAS_EVENT(port) (0x0924 + ((port) * 0x1000))
953 #define KSZ8567_PORTn_CTRL0(port) (0x0A00 + ((port) * 0x1000))
954 #define KSZ8567_PORTn_CTRL1(port) (0x0A04 + ((port) * 0x1000))
955 #define KSZ8567_PORTn_CTRL2(port) (0x0B00 + ((port) * 0x1000))
956 #define KSZ8567_PORTn_MSTP_PTR(port) (0x0B01 + ((port) * 0x1000))
957 #define KSZ8567_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
958 #define KSZ8567_PORTn_PTP_RX_LATENCY(port) (0x0C00 + ((port) * 0x1000))
959 #define KSZ8567_PORTn_PTP_TX_LATENCY(port) (0x0C02 + ((port) * 0x1000))
960 #define KSZ8567_PORTn_PTP_ASYM_CORRECTION(port) (0x0C04 + ((port) * 0x1000))
961 #define KSZ8567_PORTn_PTP_XDLY_REQ_TSH(port) (0x0C08 + ((port) * 0x1000))
962 #define KSZ8567_PORTn_PTP_XDLY_REQ_TSL(port) (0x0C0A + ((port) * 0x1000))
963 #define KSZ8567_PORTn_PTP_SYNC_TSH(port) (0x0C0C + ((port) * 0x1000))
964 #define KSZ8567_PORTn_PTP_SYNC_TSL(port) (0x0C0E + ((port) * 0x1000))
965 #define KSZ8567_PORTn_PTP_PDLY_RESP_TSH(port) (0x0C10 + ((port) * 0x1000))
966 #define KSZ8567_PORTn_PTP_PDLY_RESP_TSL(port) (0x0C12 + ((port) * 0x1000))
967 #define KSZ8567_PORTn_PTP_TS_INT_STAT(port) (0x0C14 + ((port) * 0x1000))
968 #define KSZ8567_PORTn_PTP_TS_INT_EN(port) (0x0C16 + ((port) * 0x1000))
969 #define KSZ8567_PORTn_PTP_LINK_DELAY(port) (0x0C18 + ((port) * 0x1000))
970 #define KSZ8567_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
971 
972 //PHY Basic Control register
973 #define KSZ8567_BMCR_RESET 0x8000
974 #define KSZ8567_BMCR_LOOPBACK 0x4000
975 #define KSZ8567_BMCR_SPEED_SEL 0x2000
976 #define KSZ8567_BMCR_AN_EN 0x1000
977 #define KSZ8567_BMCR_POWER_DOWN 0x0800
978 #define KSZ8567_BMCR_ISOLATE 0x0400
979 #define KSZ8567_BMCR_RESTART_AN 0x0200
980 #define KSZ8567_BMCR_DUPLEX_MODE 0x0100
981 #define KSZ8567_BMCR_COL_TEST 0x0080
982 
983 //PHY Basic Status register
984 #define KSZ8567_BMSR_100BT4 0x8000
985 #define KSZ8567_BMSR_100BTX_FD 0x4000
986 #define KSZ8567_BMSR_100BTX_HD 0x2000
987 #define KSZ8567_BMSR_10BT_FD 0x1000
988 #define KSZ8567_BMSR_10BT_HD 0x0800
989 #define KSZ8567_BMSR_EXTENDED_STATUS 0x0100
990 #define KSZ8567_BMSR_MF_PREAMBLE_SUPPR 0x0040
991 #define KSZ8567_BMSR_AN_COMPLETE 0x0020
992 #define KSZ8567_BMSR_REMOTE_FAULT 0x0010
993 #define KSZ8567_BMSR_AN_CAPABLE 0x0008
994 #define KSZ8567_BMSR_LINK_STATUS 0x0004
995 #define KSZ8567_BMSR_JABBER_DETECT 0x0002
996 #define KSZ8567_BMSR_EXTENDED_CAPABLE 0x0001
997 
998 //PHY ID High register
999 #define KSZ8567_PHYID1_DEFAULT 0x0022
1000 
1001 //PHY ID Low register
1002 #define KSZ8567_PHYID2_DEFAULT 0x1631
1003 
1004 //PHY Auto-Negotiation Advertisement register
1005 #define KSZ8567_ANAR_NEXT_PAGE 0x8000
1006 #define KSZ8567_ANAR_REMOTE_FAULT 0x2000
1007 #define KSZ8567_ANAR_PAUSE 0x0C00
1008 #define KSZ8567_ANAR_100BT4 0x0200
1009 #define KSZ8567_ANAR_100BTX_FD 0x0100
1010 #define KSZ8567_ANAR_100BTX_HD 0x0080
1011 #define KSZ8567_ANAR_10BT_FD 0x0040
1012 #define KSZ8567_ANAR_10BT_HD 0x0020
1013 #define KSZ8567_ANAR_SELECTOR 0x001F
1014 #define KSZ8567_ANAR_SELECTOR_DEFAULT 0x0001
1015 
1016 //PHY Auto-Negotiation Link Partner Ability register
1017 #define KSZ8567_ANLPAR_NEXT_PAGE 0x8000
1018 #define KSZ8567_ANLPAR_ACK 0x4000
1019 #define KSZ8567_ANLPAR_REMOTE_FAULT 0x2000
1020 #define KSZ8567_ANLPAR_PAUSE 0x0C00
1021 #define KSZ8567_ANLPAR_100BT4 0x0200
1022 #define KSZ8567_ANLPAR_100BTX_FD 0x0100
1023 #define KSZ8567_ANLPAR_100BTX_HD 0x0080
1024 #define KSZ8567_ANLPAR_10BT_FD 0x0040
1025 #define KSZ8567_ANLPAR_10BT_HD 0x0020
1026 #define KSZ8567_ANLPAR_SELECTOR 0x001F
1027 #define KSZ8567_ANLPAR_SELECTOR_DEFAULT 0x0001
1028 
1029 //PHY Auto-Negotiation Expansion Status register
1030 #define KSZ8567_ANER_PAR_DETECT_FAULT 0x0010
1031 #define KSZ8567_ANER_LP_NEXT_PAGE_ABLE 0x0008
1032 #define KSZ8567_ANER_NEXT_PAGE_ABLE 0x0004
1033 #define KSZ8567_ANER_PAGE_RECEIVED 0x0002
1034 #define KSZ8567_ANER_LP_AN_ABLE 0x0001
1035 
1036 //PHY Auto-Negotiation Next Page register
1037 #define KSZ8567_ANNPR_NEXT_PAGE 0x8000
1038 #define KSZ8567_ANNPR_MSG_PAGE 0x2000
1039 #define KSZ8567_ANNPR_ACK2 0x1000
1040 #define KSZ8567_ANNPR_TOGGLE 0x0800
1041 #define KSZ8567_ANNPR_MESSAGE 0x07FF
1042 
1043 //PHY Auto-Negotiation Link Partner Next Page Ability register
1044 #define KSZ8567_ANLPNPR_NEXT_PAGE 0x8000
1045 #define KSZ8567_ANLPNPR_ACK 0x4000
1046 #define KSZ8567_ANLPNPR_MSG_PAGE 0x2000
1047 #define KSZ8567_ANLPNPR_ACK2 0x1000
1048 #define KSZ8567_ANLPNPR_TOGGLE 0x0800
1049 #define KSZ8567_ANLPNPR_MESSAGE 0x07FF
1050 
1051 //PHY MMD Setup register
1052 #define KSZ8567_MMDACR_FUNC 0xC000
1053 #define KSZ8567_MMDACR_FUNC_ADDR 0x0000
1054 #define KSZ8567_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
1055 #define KSZ8567_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
1056 #define KSZ8567_MMDACR_FUNC_DATA_POST_INC_W 0xC000
1057 #define KSZ8567_MMDACR_DEVAD 0x001F
1058 
1059 //PHY Remote Loopback register
1060 #define KSZ8567_RLB_REMOTE_LOOPBACK 0x0100
1061 
1062 //PHY LinkMD register
1063 #define KSZ8567_LINKMD_TEST_EN 0x8000
1064 #define KSZ8567_LINKMD_PAIR 0x3000
1065 #define KSZ8567_LINKMD_PAIR_A 0x0000
1066 #define KSZ8567_LINKMD_PAIR_B 0x1000
1067 #define KSZ8567_LINKMD_PAIR_C 0x2000
1068 #define KSZ8567_LINKMD_PAIR_D 0x3000
1069 #define KSZ8567_LINKMD_STATUS 0x0300
1070 #define KSZ8567_LINKMD_STATUS_NORMAL 0x0000
1071 #define KSZ8567_LINKMD_STATUS_OPEN 0x0100
1072 #define KSZ8567_LINKMD_STATUS_SHORT 0x0200
1073 #define KSZ8567_LINKMD_RESULT 0x00FF
1074 
1075 //PHY Digital PMA/PCS Status register
1076 #define KSZ8567_DPMAPCSS_1000BT_LINK_STATUS 0x0002
1077 #define KSZ8567_DPMAPCSS_100BTX_LINK_STATUS 0x0001
1078 
1079 //Port Interrupt Control/Status register
1080 #define KSZ8567_ICSR_JABBER_IE 0x8000
1081 #define KSZ8567_ICSR_RECEIVE_ERROR_IE 0x4000
1082 #define KSZ8567_ICSR_PAGE_RECEIVED_IE 0x2000
1083 #define KSZ8567_ICSR_PAR_DETECT_FAULT_IE 0x1000
1084 #define KSZ8567_ICSR_LP_ACK_IE 0x0800
1085 #define KSZ8567_ICSR_LINK_DOWN_IE 0x0400
1086 #define KSZ8567_ICSR_REMOTE_FAULT_IE 0x0200
1087 #define KSZ8567_ICSR_LINK_UP_IE 0x0100
1088 #define KSZ8567_ICSR_JABBER_IF 0x0080
1089 #define KSZ8567_ICSR_RECEIVE_ERROR_IF 0x0040
1090 #define KSZ8567_ICSR_PAGE_RECEIVED_IF 0x0020
1091 #define KSZ8567_ICSR_PAR_DETECT_FAULT_IF 0x0010
1092 #define KSZ8567_ICSR_LP_ACK_IF 0x0008
1093 #define KSZ8567_ICSR_LINK_DOWN_IF 0x0004
1094 #define KSZ8567_ICSR_REMOTE_FAULT_IF 0x0002
1095 #define KSZ8567_ICSR_LINK_UP_IF 0x0001
1096 
1097 //PHY Auto MDI/MDI-X register
1098 #define KSZ8567_AUTOMDI_MDI_SET 0x0080
1099 #define KSZ8567_AUTOMDI_SWAP_OFF 0x0040
1100 
1101 //PHY Control register
1102 #define KSZ8567_PHYCON_JABBER_EN 0x0200
1103 #define KSZ8567_PHYCON_SPEED_100BTX 0x0020
1104 #define KSZ8567_PHYCON_SPEED_10BT 0x0010
1105 #define KSZ8567_PHYCON_DUPLEX_STATUS 0x0008
1106 
1107 //MMD Signal Quality register
1108 #define KSZ8567_MMD_SIGNAL_QUALITY_CH_A_QUALITY_INDICATOR 0x7F00
1109 
1110 //MMD LED Mode register
1111 #define KSZ8567_MMD_LED_MODE_LED_MODE 0x0010
1112 #define KSZ8567_MMD_LED_MODE_LED_MODE_TRI_COLOR_DUAL 0x0000
1113 #define KSZ8567_MMD_LED_MODE_LED_MODE_SINGLE 0x0010
1114 #define KSZ8567_MMD_LED_MODE_RESERVED 0x000F
1115 #define KSZ8567_MMD_LED_MODE_RESERVED_DEFAULT 0x0001
1116 
1117 //MMD EEE Advertisement register
1118 #define KSZ8567_MMD_EEE_ADV_1000BT_EEE_EN 0x0004
1119 #define KSZ8567_MMD_EEE_ADV_100BT_EEE_EN 0x0002
1120 
1121 //Global Chip ID 0 register
1122 #define KSZ8567_CHIP_ID0_DEFAULT 0x00
1123 
1124 //Global Chip ID 1 register
1125 #define KSZ8567_CHIP_ID1_DEFAULT 0x85
1126 
1127 //Global Chip ID 2 register
1128 #define KSZ8567_CHIP_ID2_DEFAULT 0x67
1129 
1130 //Global Chip ID 3 register
1131 #define KSZ8567_CHIP_ID3_REVISION_ID 0xF0
1132 #define KSZ8567_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
1133 
1134 //PME Pin Control register
1135 #define KSZ8567_PME_PIN_CTRL_PME_PIN_OUT_EN 0x02
1136 #define KSZ8567_PME_PIN_CTRL_PME_PIN_OUT_POL 0x01
1137 
1138 //Global Interrupt Status register
1139 #define KSZ8567_GLOBAL_INT_STAT_LUE 0x80000000
1140 #define KSZ8567_GLOBAL_INT_STAT_GPIO_TRIG_TS_UNIT 0x40000000
1141 
1142 //Global Interrupt Mask register
1143 #define KSZ8567_GLOBAL_INT_MASK_LUE 0x80000000
1144 #define KSZ8567_GLOBAL_INT_MASK_GPIO_TRIG_TS_UNIT 0x40000000
1145 
1146 //Global Port Interrupt Status register
1147 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT7 0x00000040
1148 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT6 0x00000020
1149 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT5 0x00000010
1150 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT4 0x00000008
1151 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT3 0x00000004
1152 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT2 0x00000002
1153 #define KSZ8567_GLOBAL_PORT_INT_STAT_PORT1 0x00000001
1154 
1155 //Global Port Interrupt Mask register
1156 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT7 0x00000040
1157 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT6 0x00000020
1158 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT5 0x00000010
1159 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT4 0x00000008
1160 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT3 0x00000004
1161 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT2 0x00000002
1162 #define KSZ8567_GLOBAL_PORT_INT_MASK_PORT1 0x00000001
1163 
1164 //Serial I/O Control register
1165 #define KSZ8567_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPR 0x04
1166 #define KSZ8567_SERIAL_IO_CTRL_AUTO_SPI_DATA_OUT_EDGE_SEL 0x02
1167 #define KSZ8567_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL 0x01
1168 #define KSZ8567_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_FALLING 0x00
1169 #define KSZ8567_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_RISING 0x01
1170 
1171 //Output Clock Control register
1172 #define KSZ8567_OUT_CLK_CTRL_REC_CLK_RDY 0x80
1173 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC 0x1C
1174 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_XI 0x00
1175 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_PORT1 0x04
1176 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_PORT2 0x08
1177 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_PORT3 0x0C
1178 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_PORT4 0x10
1179 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_SRC_PORT5 0x14
1180 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_EN 0x02
1181 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_FREQ 0x01
1182 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_FREQ_25MHZ 0x00
1183 #define KSZ8567_OUT_CLK_CTRL_SYNCLKO_FREQ_125MHZ 0x01
1184 
1185 //In-Band Management Control register
1186 #define KSZ8567_IBA_CTRL_IBA_EN 0x80000000
1187 #define KSZ8567_IBA_CTRL_DEST_MAC_ADDR_MATCH_EN 0x40000000
1188 #define KSZ8567_IBA_CTRL_IBA_RESET 0x20000000
1189 #define KSZ8567_IBA_CTRL_RESP_PRIO_QUEUE 0x00C00000
1190 #define KSZ8567_IBA_CTRL_RESP_PRIO_QUEUE_DEFAULT 0x00400000
1191 #define KSZ8567_IBA_CTRL_IBA_COMM 0x00070000
1192 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT1 0x00000000
1193 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT2 0x00010000
1194 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT3 0x00020000
1195 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT4 0x00030000
1196 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT5 0x00040000
1197 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT6 0x00050000
1198 #define KSZ8567_IBA_CTRL_IBA_COMM_PORT7 0x00060000
1199 #define KSZ8567_IBA_CTRL_TPID 0x0000FFFF
1200 #define KSZ8567_IBA_CTRL_TPID_DEFAULT 0x000040FE
1201 
1202 //I/O Drive Strength register
1203 #define KSZ8567_IO_DRIVE_STRENGTH_HIGH_SPEED_DRIVE_STRENGTH 0x70
1204 #define KSZ8567_IO_DRIVE_STRENGTH_LOW_SPEED_DRIVE_STRENGTH 0x07
1205 
1206 //In-Band Management Operation Status 1 register
1207 #define KSZ8567_IBA_OP_STAT1_GOOD_PKT_DETECT 0x80000000
1208 #define KSZ8567_IBA_OP_STAT1_RESP_PKT_TX_DONE 0x40000000
1209 #define KSZ8567_IBA_OP_STAT1_EXEC_DONE 0x20000000
1210 #define KSZ8567_IBA_OP_STAT1_MAC_ADDR_MISMATCH_ERR 0x00004000
1211 #define KSZ8567_IBA_OP_STAT1_ACCESS_FORMAT_ERR 0x00002000
1212 #define KSZ8567_IBA_OP_STAT1_ACCESS_CODE_ERR 0x00001000
1213 #define KSZ8567_IBA_OP_STAT1_ACCESS_CMD_ERR 0x00000800
1214 #define KSZ8567_IBA_OP_STAT1_OVERSIZE_PKT_ERR 0x00000400
1215 #define KSZ8567_IBA_OP_STAT1_ACCESS_CODE_ERR_LOC 0x0000007F
1216 
1217 //LED Override register
1218 #define KSZ8567_LED_OVERRIDE_OVERRIDE 0x000003FF
1219 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED1_0 0x00000001
1220 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED1_1 0x00000002
1221 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED2_0 0x00000004
1222 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED2_1 0x00000008
1223 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED3_0 0x00000010
1224 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED3_1 0x00000020
1225 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED4_0 0x00000040
1226 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED4_1 0x00000080
1227 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED5_0 0x00000100
1228 #define KSZ8567_LED_OVERRIDE_OVERRIDE_LED5_1 0x00000200
1229 
1230 //LED Output register
1231 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL 0x000003FF
1232 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED1_0 0x00000001
1233 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED1_1 0x00000002
1234 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED2_0 0x00000004
1235 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED2_1 0x00000008
1236 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED3_0 0x00000010
1237 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED3_1 0x00000020
1238 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED4_0 0x00000040
1239 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED4_1 0x00000080
1240 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED5_0 0x00000100
1241 #define KSZ8567_LED_OUTPUT_GPIO_OUT_CTRL_LED5_1 0x00000200
1242 
1243 //LED2_0/LED2_1 Source register
1244 #define KSZ8567_LED2_0_LED2_1_SRC_LED2_1_SRC 0x00000008
1245 #define KSZ8567_LED2_0_LED2_1_SRC_LED2_0_SRC 0x00000004
1246 
1247 //Power Down Control 0 register
1248 #define KSZ8567_PWR_DOWN_CTRL0_PLL_PWR_DOWN 0x20
1249 #define KSZ8567_PWR_DOWN_CTRL0_PWR_MGMT_MODE 0x18
1250 #define KSZ8567_PWR_DOWN_CTRL0_PWR_MGMT_MODE_NORMAL 0x00
1251 #define KSZ8567_PWR_DOWN_CTRL0_PWR_MGMT_MODE_EDPD 0x08
1252 #define KSZ8567_PWR_DOWN_CTRL0_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
1253 
1254 //LED Strap-In register
1255 #define KSZ8567_LED_STRAP_IN_STRAP_IN 0x000003FF
1256 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED1_0 0x00000001
1257 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED1_1 0x00000002
1258 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED2_0 0x00000004
1259 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED2_1 0x00000008
1260 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED3_0 0x00000010
1261 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED3_1 0x00000020
1262 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED4_0 0x00000040
1263 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED4_1 0x00000080
1264 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED5_0 0x00000100
1265 #define KSZ8567_LED_STRAP_IN_STRAP_IN_LED5_1 0x00000200
1266 
1267 //Switch Operation register
1268 #define KSZ8567_SWITCH_OP_DOUBLE_TAG_EN 0x80
1269 #define KSZ8567_SWITCH_OP_SOFT_HARD_RESET 0x02
1270 #define KSZ8567_SWITCH_OP_START_SWITCH 0x01
1271 
1272 //Switch Maximum Transmit Unit register
1273 #define KSZ8567_SWITCH_MTU_MTU 0x3FFF
1274 #define KSZ8567_SWITCH_MTU_MTU_DEFAULT 0x07D0
1275 
1276 //Switch ISP TPID register
1277 #define KSZ8567_SWITCH_ISP_TPID_ISP_TAG_TPID 0xFFFF
1278 
1279 //AVB Credit Based Shaper Strategy register
1280 #define KSZ8567_AVB_CBS_STRATEGY_SHAPING_CREDIT_ACCOUNTING 0x0002
1281 #define KSZ8567_AVB_CBS_STRATEGY_POLICING_CREDIT_ACCOUNTING 0x0001
1282 
1283 //Switch Lookup Engine Control 0 register
1284 #define KSZ8567_SWITCH_LUE_CTRL0_VLAN_EN 0x80
1285 #define KSZ8567_SWITCH_LUE_CTRL0_DROP_INVALID_VID 0x40
1286 #define KSZ8567_SWITCH_LUE_CTRL0_AGE_COUNT 0x38
1287 #define KSZ8567_SWITCH_LUE_CTRL0_AGE_COUNT_DEFAULT 0x20
1288 #define KSZ8567_SWITCH_LUE_CTRL0_RESERVED_MCAST_LOOKUP_EN 0x04
1289 #define KSZ8567_SWITCH_LUE_CTRL0_HASH_OPTION 0x03
1290 #define KSZ8567_SWITCH_LUE_CTRL0_HASH_OPTION_NONE 0x00
1291 #define KSZ8567_SWITCH_LUE_CTRL0_HASH_OPTION_CRC 0x01
1292 #define KSZ8567_SWITCH_LUE_CTRL0_HASH_OPTION_XOR 0x02
1293 
1294 //Switch Lookup Engine Control 1 register
1295 #define KSZ8567_SWITCH_LUE_CTRL1_UNICAST_LEARNING_DIS 0x80
1296 #define KSZ8567_SWITCH_LUE_CTRL1_SELF_ADDR_FILT 0x40
1297 #define KSZ8567_SWITCH_LUE_CTRL1_FLUSH_ALU_TABLE 0x20
1298 #define KSZ8567_SWITCH_LUE_CTRL1_FLUSH_MSTP_ENTRIES 0x10
1299 #define KSZ8567_SWITCH_LUE_CTRL1_MCAST_SRC_ADDR_FILT 0x08
1300 #define KSZ8567_SWITCH_LUE_CTRL1_AGING_EN 0x04
1301 #define KSZ8567_SWITCH_LUE_CTRL1_FAST_AGING 0x02
1302 #define KSZ8567_SWITCH_LUE_CTRL1_LINK_DOWN_FLUSH 0x01
1303 
1304 //Switch Lookup Engine Control 2 register
1305 #define KSZ8567_SWITCH_LUE_CTRL2_DOUBLE_TAG_MCAST_TRAP 0x40
1306 #define KSZ8567_SWITCH_LUE_CTRL2_DYNAMIC_ENTRY_EG_VLAN_FILT 0x20
1307 #define KSZ8567_SWITCH_LUE_CTRL2_STATIC_ENTRY_EG_VLAN_FILT 0x10
1308 #define KSZ8567_SWITCH_LUE_CTRL2_FLUSH_OPTION 0x0C
1309 #define KSZ8567_SWITCH_LUE_CTRL2_FLUSH_OPTION_NONE 0x00
1310 #define KSZ8567_SWITCH_LUE_CTRL2_FLUSH_OPTION_DYNAMIC 0x04
1311 #define KSZ8567_SWITCH_LUE_CTRL2_FLUSH_OPTION_STATIC 0x08
1312 #define KSZ8567_SWITCH_LUE_CTRL2_FLUSH_OPTION_BOTH 0x0C
1313 #define KSZ8567_SWITCH_LUE_CTRL2_MAC_ADDR_PRIORITY 0x03
1314 
1315 //Switch Lookup Engine Control 3 register
1316 #define KSZ8567_SWITCH_LUE_CTRL3_AGE_PERIOD 0xFF
1317 #define KSZ8567_SWITCH_LUE_CTRL3_AGE_PERIOD_DEFAULT 0x4B
1318 
1319 //Address Lookup Table Interrupt register
1320 #define KSZ8567_ALU_TABLE_INT_LEARN_FAIL 0x04
1321 #define KSZ8567_ALU_TABLE_INT_ALMOST_FULL 0x02
1322 #define KSZ8567_ALU_TABLE_INT_WRITE_FAIL 0x01
1323 
1324 //Address Lookup Table Mask register
1325 #define KSZ8567_ALU_TABLE_MASK_LEARN_FAIL 0x04
1326 #define KSZ8567_ALU_TABLE_MASK_ALMOST_FULL 0x02
1327 #define KSZ8567_ALU_TABLE_MASK_WRITE_FAIL 0x01
1328 
1329 //Address Lookup Table Entry Index 0 register
1330 #define KSZ8567_ALU_TABLE_ENTRY_INDEX0_ALMOST_FULL_ENTRY_INDEX 0x0FFF
1331 #define KSZ8567_ALU_TABLE_ENTRY_INDEX0_FAIL_WRITE_INDEX 0x03FF
1332 
1333 //Address Lookup Table Entry Index 1 register
1334 #define KSZ8567_ALU_TABLE_ENTRY_INDEX1_FAIL_LEARN_INDEX 0x03FF
1335 
1336 //Address Lookup Table Entry Index 2 register
1337 #define KSZ8567_ALU_TABLE_ENTRY_INDEX2_CPU_ACCESS_INDEX 0x03FF
1338 
1339 //Unknown Unicast Control register
1340 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD 0x80000000
1341 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP 0x0000007F
1342 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT1 0x00000001
1343 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT2 0x00000002
1344 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT3 0x00000004
1345 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT4 0x00000008
1346 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT5 0x00000010
1347 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT6 0x00000020
1348 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT7 0x00000040
1349 #define KSZ8567_UNKNOWN_UNICAST_CTRL_FWD_MAP_ALL 0x0000007F
1350 
1351 //Unknown Multicast Control register
1352 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD 0x80000000
1353 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP 0x0000007F
1354 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT1 0x00000001
1355 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT2 0x00000002
1356 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT3 0x00000004
1357 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT4 0x00000008
1358 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT5 0x00000010
1359 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT6 0x00000020
1360 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT7 0x00000040
1361 #define KSZ8567_UNKONWN_MULTICAST_CTRL_FWD_MAP_ALL 0x0000007F
1362 
1363 //Unknown VLAN ID Control register
1364 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD 0x80000000
1365 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP 0x0000007F
1366 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT1 0x00000001
1367 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT2 0x00000002
1368 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT3 0x00000004
1369 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT4 0x00000008
1370 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT5 0x00000010
1371 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT6 0x00000020
1372 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT7 0x00000040
1373 #define KSZ8567_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_ALL 0x0000007F
1374 
1375 //Switch MAC Control 0 register
1376 #define KSZ8567_SWITCH_MAC_CTRL0_ALT_BACK_OFF_MODE 0x80
1377 #define KSZ8567_SWITCH_MAC_CTRL0_FRAME_LEN_CHECK_EN 0x08
1378 #define KSZ8567_SWITCH_MAC_CTRL0_FLOW_CTRL_PKT_DROP_MODE 0x02
1379 #define KSZ8567_SWITCH_MAC_CTRL0_AGGRESSIVE_BACK_OFF_EN 0x01
1380 
1381 //Switch MAC Control 1 register
1382 #define KSZ8567_SWITCH_MAC_CTRL1_MCAST_STORM_PROTECT_DIS 0x40
1383 #define KSZ8567_SWITCH_MAC_CTRL1_BACK_PRESSURE_MODE 0x20
1384 #define KSZ8567_SWITCH_MAC_CTRL1_FLOW_CTRL_FAIR_MODE 0x10
1385 #define KSZ8567_SWITCH_MAC_CTRL1_NO_EXCESSIVE_COL_DROP 0x08
1386 #define KSZ8567_SWITCH_MAC_CTRL1_JUMBO_PKT_SUPPORT 0x04
1387 #define KSZ8567_SWITCH_MAC_CTRL1_MAX_PKT_SIZE_CHECK_DIS 0x02
1388 #define KSZ8567_SWITCH_MAC_CTRL1_PASS_SHORT_PKT 0x01
1389 
1390 //Switch MAC Control 2 register
1391 #define KSZ8567_SWITCH_MAC_CTRL2_NULL_VID_REPLACEMENT 0x08
1392 #define KSZ8567_SWITCH_MAC_CTRL2_BCAST_STORM_PROTECT_RATE_MSB 0x07
1393 
1394 //Switch MAC Control 3 register
1395 #define KSZ8567_SWITCH_MAC_CTRL3_BCAST_STORM_PROTECT_RATE_LSB 0xFF
1396 
1397 //Switch MAC Control 4 register
1398 #define KSZ8567_SWITCH_MAC_CTRL4_PASS_FLOW_CTRL_PKT 0x01
1399 
1400 //Switch MAC Control 5 register
1401 #define KSZ8567_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD 0x30
1402 #define KSZ8567_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_16MS 0x00
1403 #define KSZ8567_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_64MS 0x10
1404 #define KSZ8567_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_256MS 0x20
1405 #define KSZ8567_SWITCH_MAC_CTRL5_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
1406 
1407 //Switch MIB Control register
1408 #define KSZ8567_SWITCH_MIB_CTRL_FLUSH 0x80
1409 #define KSZ8567_SWITCH_MIB_CTRL_FREEZE 0x40
1410 
1411 //Global Port Mirroring and Snooping Control register
1412 #define KSZ8567_GLOBAL_PORT_MIRROR_SNOOP_CTRL_IGMP_SNOOP_EN 0x40
1413 #define KSZ8567_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_OPT 0x08
1414 #define KSZ8567_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_EN 0x04
1415 #define KSZ8567_GLOBAL_PORT_MIRROR_SNOOP_CTRL_SNIFF_MODE_SEL 0x01
1416 
1417 //WRED DiffServ Color Mapping register
1418 #define KSZ8567_WRED_DIFFSERV_COLOR_MAPPING_RED 0x30
1419 #define KSZ8567_WRED_DIFFSERV_COLOR_MAPPING_YELLOW 0x0C
1420 #define KSZ8567_WRED_DIFFSERV_COLOR_MAPPING_GREEN 0x03
1421 
1422 //PTP Event Message Priority register
1423 #define KSZ8567_PTP_EVENT_MSG_PRIO_OVERRIDE 0x80
1424 #define KSZ8567_PTP_EVENT_MSG_PRIO_PRIORITY 0x0F
1425 
1426 //PTP Non-Event Message Priority register
1427 #define KSZ8567_PTP_NON_EVENT_MSG_PRIO_OVERRIDE 0x80
1428 #define KSZ8567_PTP_NON_EVENT_MSG_PRIO_PRIORITY 0x0F
1429 
1430 //Queue Management Control 0 register
1431 #define KSZ8567_QUEUE_MGMT_CTRL0_PRIORITY_2Q 0x000000C0
1432 #define KSZ8567_QUEUE_MGMT_CTRL0_UNICAST_PORT_VLAN_DISCARD 0x00000002
1433 
1434 //VLAN Table Entry 0 register
1435 #define KSZ8567_VLAN_TABLE_ENTRY0_VALID 0x80000000
1436 #define KSZ8567_VLAN_TABLE_ENTRY0_FORWARD_OPTION 0x08000000
1437 #define KSZ8567_VLAN_TABLE_ENTRY0_PRIORITY 0x07000000
1438 #define KSZ8567_VLAN_TABLE_ENTRY0_MSTP_INDEX 0x00007000
1439 #define KSZ8567_VLAN_TABLE_ENTRY0_FID 0x0000007F
1440 
1441 //VLAN Table Entry 1 register
1442 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT_UNTAG 0x0000007F
1443 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT7_UNTAG 0x00000040
1444 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT6_UNTAG 0x00000020
1445 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT5_UNTAG 0x00000010
1446 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT4_UNTAG 0x00000008
1447 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT3_UNTAG 0x00000004
1448 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT2_UNTAG 0x00000002
1449 #define KSZ8567_VLAN_TABLE_ENTRY1_PORT1_UNTAG 0x00000001
1450 
1451 //VLAN Table Entry 2 register
1452 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1453 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1454 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1455 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1456 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1457 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1458 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1459 #define KSZ8567_VLAN_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1460 
1461 //VLAN Table Index register
1462 #define KSZ8567_VLAN_TABLE_INDEX_VLAN_INDEX 0x0FFF
1463 
1464 //VLAN Table Access Control register
1465 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_START_FINISH 0x80
1466 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_ACTION 0x03
1467 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_ACTION_NOP 0x00
1468 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_ACTION_WRITE 0x01
1469 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_ACTION_READ 0x02
1470 #define KSZ8567_VLAN_TABLE_ACCESS_CTRL_ACTION_CLEAR 0x03
1471 
1472 //ALU Table Index 0 register
1473 #define KSZ8567_ALU_TABLE_INDEX0_FID_INDEX 0x007F0000
1474 #define KSZ8567_ALU_TABLE_INDEX0_MAC_INDEX_MSB 0x0000FFFF
1475 
1476 //ALU Table Index 1 register
1477 #define KSZ8567_ALU_TABLE_INDEX1_MAC_INDEX_LSB 0xFFFFFFFF
1478 
1479 //ALU Table Access Control register
1480 #define KSZ8567_ALU_TABLE_CTRL_VALID_COUNT 0x3FFF0000
1481 #define KSZ8567_ALU_TABLE_CTRL_START_FINISH 0x00000080
1482 #define KSZ8567_ALU_TABLE_CTRL_VALID 0x00000040
1483 #define KSZ8567_ALU_TABLE_CTRL_VALID_ENTRY_OR_SEARCH_END 0x00000020
1484 #define KSZ8567_ALU_TABLE_CTRL_DIRECT 0x00000004
1485 #define KSZ8567_ALU_TABLE_CTRL_ACTION 0x00000003
1486 #define KSZ8567_ALU_TABLE_CTRL_ACTION_NOP 0x00000000
1487 #define KSZ8567_ALU_TABLE_CTRL_ACTION_WRITE 0x00000001
1488 #define KSZ8567_ALU_TABLE_CTRL_ACTION_READ 0x00000002
1489 #define KSZ8567_ALU_TABLE_CTRL_ACTION_SEARCH 0x00000003
1490 
1491 //Static Address and Reserved Multicast Table Control register
1492 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_TABLE_INDEX 0x003F0000
1493 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_START_FINISH 0x00000080
1494 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_TABLE_SELECT 0x00000002
1495 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_ACTION 0x00000001
1496 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_ACTION_READ 0x00000000
1497 #define KSZ8567_STATIC_MCAST_TABLE_CTRL_ACTION_WRITE 0x00000001
1498 
1499 //ALU Table Entry 1 register
1500 #define KSZ8567_ALU_TABLE_ENTRY1_STATIC 0x80000000
1501 #define KSZ8567_ALU_TABLE_ENTRY1_SRC_FILTER 0x40000000
1502 #define KSZ8567_ALU_TABLE_ENTRY1_DES_FILTER 0x20000000
1503 #define KSZ8567_ALU_TABLE_ENTRY1_PRIORITY 0x1C000000
1504 #define KSZ8567_ALU_TABLE_ENTRY1_AGE_COUNT 0x1C000000
1505 #define KSZ8567_ALU_TABLE_ENTRY1_MSTP 0x00000007
1506 
1507 //ALU Table Entry 2 register
1508 #define KSZ8567_ALU_TABLE_ENTRY2_OVERRIDE 0x80000000
1509 #define KSZ8567_ALU_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1510 #define KSZ8567_ALU_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1511 #define KSZ8567_ALU_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1512 #define KSZ8567_ALU_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1513 #define KSZ8567_ALU_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1514 #define KSZ8567_ALU_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1515 #define KSZ8567_ALU_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1516 #define KSZ8567_ALU_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1517 
1518 //ALU Table Entry 3 register
1519 #define KSZ8567_ALU_TABLE_ENTRY3_FID 0x007F0000
1520 #define KSZ8567_ALU_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1521 
1522 //ALU Table Entry 4 register
1523 #define KSZ8567_ALU_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1524 
1525 //Static Address Table Entry 1 register
1526 #define KSZ8567_STATIC_TABLE_ENTRY1_VALID 0x80000000
1527 #define KSZ8567_STATIC_TABLE_ENTRY1_SRC_FILTER 0x40000000
1528 #define KSZ8567_STATIC_TABLE_ENTRY1_DES_FILTER 0x20000000
1529 #define KSZ8567_STATIC_TABLE_ENTRY1_PRIORITY 0x1C000000
1530 #define KSZ8567_STATIC_TABLE_ENTRY1_MSTP 0x00000007
1531 
1532 //Static Address Table Entry 2 register
1533 #define KSZ8567_STATIC_TABLE_ENTRY2_OVERRIDE 0x80000000
1534 #define KSZ8567_STATIC_TABLE_ENTRY2_USE_FID 0x40000000
1535 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1536 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1537 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1538 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1539 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1540 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1541 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1542 #define KSZ8567_STATIC_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1543 
1544 //Static Address Table Entry 3 register
1545 #define KSZ8567_STATIC_TABLE_ENTRY3_FID 0x007F0000
1546 #define KSZ8567_STATIC_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1547 
1548 //Static Address Table Entry 4 register
1549 #define KSZ8567_STATIC_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1550 
1551 //Reserved Multicast Table Entry 2 register
1552 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1553 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1554 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1555 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1556 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1557 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1558 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1559 #define KSZ8567_RES_MCAST_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1560 
1561 //Global PTP Clock Control register
1562 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_SW_FREQ_ADJ_DIS 0x8000
1563 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_STEP_ADJ 0x0040
1564 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_STEP_DIR 0x0020
1565 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_READ 0x0010
1566 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_LOAD 0x0008
1567 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_CONTINUOUS_ADJ 0x0004
1568 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_EN 0x0002
1569 #define KSZ8567_GLOBAL_PTP_CLK_CTRL_PTP_CLK_RESET 0x0001
1570 
1571 //Global PTP RTC Clock Phase register
1572 #define KSZ8567_GLOBAL_PTP_RTC_CLK_PHASE_PTP_RTC_8NS_PHASE 0x0007
1573 
1574 //Global PTP Clock Sub-Nanosecond Rate High Word register
1575 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RATE_DIR 0x8000
1576 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_TEMP_ADJ_MODE 0x4000
1577 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RTC_SUB_NS_29_16 0x3FFF
1578 
1579 //Global PTP Clock Sub-Nanosecond Rate Low Word register
1580 #define KSZ8567_GLOBAL_PTP_CLK_SUB_NS_RATE_L_PTP_RTC_SUB_NS_15_0 0xFFFF
1581 
1582 //Global PTP Message Config 1 register
1583 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_IEEE_802_1AS_MODE 0x0080
1584 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_IEEE_1588_PTP_MODE 0x0040
1585 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_ETH_PTP_DETECT 0x0020
1586 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_IPV4_UDP_PTP_DETECT 0x0010
1587 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_IPV6_UDP_PTP_DETECT 0x0008
1588 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_E2E_CLK_MODE 0x0000
1589 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_P2P_CLK_MODE 0x0004
1590 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_SLAVE_OC_CLK_MODE 0x0000
1591 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_MASTER_OC_CLK_MODE 0x0002
1592 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_TWO_STEP_CLK_MODE 0x0000
1593 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG1_ONE_STEP_CLK_MODE 0x0001
1594 
1595 //Global PTP Message Config 2 register
1596 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_UNICAST_PTP_EN 0x1000
1597 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_ALT_MASTER_EN 0x0800
1598 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_PTP_MSG_PRIO_TX_QUEUE 0x0400
1599 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_CHECK_SYNC_FOLLOW_UP 0x0200
1600 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_CHECK_DELAY_REQ_RESP 0x0100
1601 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_CHECK_PDELAY_REQ_RESP 0x0080
1602 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_DROP_SYNC_FOLLOW_UP_DELAY_REQ 0x0020
1603 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_CHECK_DOMAIN 0x0010
1604 #define KSZ8567_GLOBAL_PTP_MSG_CONFIG2_IPV4_UDP_CHECKSUM_EN 0x0004
1605 
1606 //Global PTP Domain and Version register
1607 #define KSZ8567_GLOBAL_PTP_DOMAIN_VERSION_PTP_VERSION 0x0F00
1608 #define KSZ8567_GLOBAL_PTP_DOMAIN_VERSION_PTP_DOMAIN 0x00FF
1609 
1610 //Global PTP Unit Index register
1611 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX 0x00000100
1612 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT0 0x00000000
1613 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT1 0x00000100
1614 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX 0x00000003
1615 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT0 0x00000000
1616 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT1 0x00000001
1617 #define KSZ8567_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT2 0x00000002
1618 
1619 //GPIO Status Monitor 0 register
1620 #define KSZ8567_GPIO_STATUS_MONITOR0_TRIGGER_ERROR 0x00070000
1621 #define KSZ8567_GPIO_STATUS_MONITOR0_TRIGGER_DONE 0x00000007
1622 
1623 //GPIO Status Monitor 1 register
1624 #define KSZ8567_GPIO_STATUS_MONITOR1_TRIGGER_INT_STATUS 0x00070000
1625 #define KSZ8567_GPIO_STATUS_MONITOR1_TS_INT_STATUS 0x00000003
1626 
1627 //Timestamp Control and Status register
1628 #define KSZ8567_TS_CTRL_STAT_GPIO_OUT_SEL 0x00000100
1629 #define KSZ8567_TS_CTRL_STAT_GPIO_IN 0x00000080
1630 #define KSZ8567_TS_CTRL_STAT_GPIO_OEN 0x00000040
1631 #define KSZ8567_TS_CTRL_STAT_TS_INT_ENB 0x00000020
1632 #define KSZ8567_TS_CTRL_STAT_TRIGGER_ACTIVE 0x00000010
1633 #define KSZ8567_TS_CTRL_STAT_TRIGGER_EN 0x00000008
1634 #define KSZ8567_TS_CTRL_STAT_TRIGGER_SW_RESET 0x00000004
1635 #define KSZ8567_TS_CTRL_STAT_TS_ENB 0x00000002
1636 #define KSZ8567_TS_CTRL_STAT_TS_SW_RESET 0x00000001
1637 
1638 //Trigger Output Unit Target Time Nanosecond register
1639 #define KSZ8567_TOU_TARGET_TIME_NS_TRIGGER_TARGET_TIME_NS 0x3FFFFFFF
1640 
1641 //Trigger Output Unit Target Time Second register
1642 #define KSZ8567_TOU_TARGET_TIME_S_TRIGGER_TARGET_TIME_S 0xFFFFFFFF
1643 
1644 //Trigger Output Unit Control 1 register
1645 #define KSZ8567_TOU_CTRL1_CASCADE_MODE_ENB 0x80000000
1646 #define KSZ8567_TOU_CTRL1_CASCADE_MODE_TAIL 0x40000000
1647 #define KSZ8567_TOU_CTRL1_CASCADE_MODE_DONE 0x0C000000
1648 #define KSZ8567_TOU_CTRL1_TRIGGER_NOW 0x02000000
1649 #define KSZ8567_TOU_CTRL1_TRIGGER_NOTIFY 0x01000000
1650 #define KSZ8567_TOU_CTRL1_TRIGGER_EDGE 0x00800000
1651 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN 0x00700000
1652 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_NEG_EDGE 0x00000000
1653 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_POS_EDGE 0x00100000
1654 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_NEG_PULSE 0x00200000
1655 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_POS_PULSE 0x00300000
1656 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_NEG_CYCLE 0x00400000
1657 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_POS_CYCLE 0x00500000
1658 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_REG_OUTPUT 0x00600000
1659 #define KSZ8567_TOU_CTRL1_TRIGGER_PATTERN_ITERATION 0x0000FFFF
1660 
1661 //Trigger Output Unit Control 2 register
1662 #define KSZ8567_TOU_CTRL2_TRIGGER_CYCLE_WIDTH 0xFFFFFFFF
1663 
1664 //Trigger Output Unit Control 3 register
1665 #define KSZ8567_TOU_CTRL3_TRIGGER_CYCLE 0xFFFF0000
1666 #define KSZ8567_TOU_CTRL3_TRIGGER_BIT_PATTERN 0x0000FFFF
1667 
1668 //Trigger Output Unit Control 4 register
1669 #define KSZ8567_TOU_CTRL4_CASCADE_INTERATION_CYCLE_TIME 0xFFFFFFFF
1670 
1671 //Trigger Output Unit Control 5 register
1672 #define KSZ8567_TOU_CTRL5_PPS_PULSE_WIDTH 0x00FF0000
1673 #define KSZ8567_TOU_CTRL5_TRIGGER_PULSE_WIDTH 0x0000FFFF
1674 
1675 //Timestamp Status and Control register
1676 #define KSZ8567_TS_STAT_CTRL_TS_EVENT_DET_CNT 0x001E0000
1677 #define KSZ8567_TS_STAT_CTRL_TS_DET_EVENT_CNT_OVERFLOW 0x00010000
1678 #define KSZ8567_TS_STAT_CTRL_TS_RISING_EDGE_ENB 0x00000080
1679 #define KSZ8567_TS_STAT_CTRL_TS_FALLING_EDGE_ENB 0x00000040
1680 #define KSZ8567_TS_STAT_CTRL_TS_CASCADE_MODE_TAIL 0x00000020
1681 #define KSZ8567_TS_STAT_CTRL_TS_UPSTREAM_CASCADE_MODE_SEL 0x00000002
1682 #define KSZ8567_TS_STAT_CTRL_TS_CASCADE_MODE_ENB 0x00000001
1683 
1684 //Timestamp 1st Sample Time Nanoseconds register
1685 #define KSZ8567_TS_SAMPLE1_TIME_NS_TS_SAMPLE_EDGE_1ST 0x40000000
1686 #define KSZ8567_TS_SAMPLE1_TIME_NS_TS_SAMPLE_TIME_NS_1ST 0x3FFFFFFF
1687 
1688 //Timestamp 1st Sample Time Seconds register
1689 #define KSZ8567_TS_SAMPLE1_TIME_S_TS_SAMPLE_TIME_S_1ST 0xFFFFFFFF
1690 
1691 //Timestamp 1st Sample Time Phase register
1692 #define KSZ8567_TS_SAMPLE1_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_1ST 0x00000007
1693 
1694 //Timestamp 2nd Sample Time Nanoseconds register
1695 #define KSZ8567_TS_SAMPLE2_TIME_NS_TS_SAMPLE_EDGE_2ND 0x40000000
1696 #define KSZ8567_TS_SAMPLE2_TIME_NS_TS_SAMPLE_TIME_NS_2ND 0x3FFFFFFF
1697 
1698 //Timestamp 2nd Sample Time Seconds register
1699 #define KSZ8567_TS_SAMPLE2_TIME_S_TS_SAMPLE_TIME_S_2ND 0xFFFFFFFF
1700 
1701 //Timestamp 2nd Sample Time Phase register
1702 #define KSZ8567_TS_SAMPLE2_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_2ND 0x00000007
1703 
1704 //Timestamp 3rd Sample Time Nanoseconds register
1705 #define KSZ8567_TS_SAMPLE3_TIME_NS_TS_SAMPLE_EDGE_3RD 0x40000000
1706 #define KSZ8567_TS_SAMPLE3_TIME_NS_TS_SAMPLE_TIME_NS_3RD 0x3FFFFFFF
1707 
1708 //Timestamp 3rd Sample Time Seconds register
1709 #define KSZ8567_TS_SAMPLE3_TIME_S_TS_SAMPLE_TIME_S_3RD 0xFFFFFFFF
1710 
1711 //Timestamp 3rd Sample Time Phase register
1712 #define KSZ8567_TS_SAMPLE3_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_3RD 0x00000007
1713 
1714 //Timestamp 4th Sample Time Nanoseconds register
1715 #define KSZ8567_TS_SAMPLE4_TIME_NS_TS_SAMPLE_EDGE_4TH 0x40000000
1716 #define KSZ8567_TS_SAMPLE4_TIME_NS_TS_SAMPLE_TIME_NS_4TH 0x3FFFFFFF
1717 
1718 //Timestamp 4th Sample Time Seconds register
1719 #define KSZ8567_TS_SAMPLE4_TIME_S_TS_SAMPLE_TIME_S_4TH 0xFFFFFFFF
1720 
1721 //Timestamp 4th Sample Time Phase register
1722 #define KSZ8567_TS_SAMPLE4_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_4TH 0x00000007
1723 
1724 //Timestamp 5th Sample Time Nanoseconds register
1725 #define KSZ8567_TS_SAMPLE5_TIME_NS_TS_SAMPLE_EDGE_5TH 0x40000000
1726 #define KSZ8567_TS_SAMPLE5_TIME_NS_TS_SAMPLE_TIME_NS_5TH 0x3FFFFFFF
1727 
1728 //Timestamp 5th Sample Time Seconds register
1729 #define KSZ8567_TS_SAMPLE5_TIME_S_TS_SAMPLE_TIME_S_5TH 0xFFFFFFFF
1730 
1731 //Timestamp 5th Sample Time Phase register
1732 #define KSZ8567_TS_SAMPLE5_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_5TH 0x00000007
1733 
1734 //Timestamp 6th Sample Time Nanoseconds register
1735 #define KSZ8567_TS_SAMPLE6_TIME_NS_TS_SAMPLE_EDGE_6TH 0x40000000
1736 #define KSZ8567_TS_SAMPLE6_TIME_NS_TS_SAMPLE_TIME_NS_6TH 0x3FFFFFFF
1737 
1738 //Timestamp 6th Sample Time Seconds register
1739 #define KSZ8567_TS_SAMPLE6_TIME_S_TS_SAMPLE_TIME_S_6TH 0xFFFFFFFF
1740 
1741 //Timestamp 6th Sample Time Phase register
1742 #define KSZ8567_TS_SAMPLE6_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_6TH 0x00000007
1743 
1744 //Timestamp 7th Sample Time Nanoseconds register
1745 #define KSZ8567_TS_SAMPLE7_TIME_NS_TS_SAMPLE_EDGE_7TH 0x40000000
1746 #define KSZ8567_TS_SAMPLE7_TIME_NS_TS_SAMPLE_TIME_NS_7TH 0x3FFFFFFF
1747 
1748 //Timestamp 7th Sample Time Seconds register
1749 #define KSZ8567_TS_SAMPLE7_TIME_S_TS_SAMPLE_TIME_S_7TH 0xFFFFFFFF
1750 
1751 //Timestamp 7th Sample Time Phase register
1752 #define KSZ8567_TS_SAMPLE7_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_7TH 0x00000007
1753 
1754 //Timestamp 8th Sample Time Nanoseconds register
1755 #define KSZ8567_TS_SAMPLE8_TIME_NS_TS_SAMPLE_EDGE_8TH 0x40000000
1756 #define KSZ8567_TS_SAMPLE8_TIME_NS_TS_SAMPLE_TIME_NS_8TH 0x3FFFFFFF
1757 
1758 //Timestamp 8th Sample Time Seconds register
1759 #define KSZ8567_TS_SAMPLE8_TIME_S_TS_SAMPLE_TIME_S_8TH 0xFFFFFFFF
1760 
1761 //Timestamp 8th Sample Time Phase register
1762 #define KSZ8567_TS_SAMPLE8_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_8TH 0x00000007
1763 
1764 //Port N Default Tag 0 register
1765 #define KSZ8567_PORTn_DEFAULT_TAG0_PCP 0xE0
1766 #define KSZ8567_PORTn_DEFAULT_TAG0_DEI 0x10
1767 #define KSZ8567_PORTn_DEFAULT_TAG0_VID_MSB 0x0F
1768 
1769 //Port N Default Tag 1 register
1770 #define KSZ8567_PORTn_DEFAULT_TAG1_VID_LSB 0xFF
1771 
1772 //Port N Interrupt Status register
1773 #define KSZ8567_PORTn_INT_STATUS_SGMII_AN_DONE 0x08
1774 #define KSZ8567_PORTn_INT_STATUS_PTP 0x04
1775 #define KSZ8567_PORTn_INT_STATUS_PHY 0x02
1776 #define KSZ8567_PORTn_INT_STATUS_ACL 0x01
1777 
1778 //Port N Interrupt Mask register
1779 #define KSZ8567_PORTn_INT_MASK_SGMII_AN_DONE 0x08
1780 #define KSZ8567_PORTn_INT_MASK_PTP 0x04
1781 #define KSZ8567_PORTn_INT_MASK_PHY 0x02
1782 #define KSZ8567_PORTn_INT_MASK_ACL 0x01
1783 
1784 //Port N Operation Control 0 register
1785 #define KSZ8567_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
1786 #define KSZ8567_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
1787 #define KSZ8567_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
1788 #define KSZ8567_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
1789 
1790 //Port N Status register
1791 #define KSZ8567_PORTn_STATUS_SPEED 0x18
1792 #define KSZ8567_PORTn_STATUS_SPEED_10MBPS 0x00
1793 #define KSZ8567_PORTn_STATUS_SPEED_100MBPS 0x08
1794 #define KSZ8567_PORTn_STATUS_DUPLEX 0x04
1795 #define KSZ8567_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
1796 #define KSZ8567_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
1797 
1798 //XMII Port N Control 0 register
1799 #define KSZ8567_PORTn_XMII_CTRL0_DUPLEX 0x40
1800 #define KSZ8567_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
1801 #define KSZ8567_PORTn_XMII_CTRL0_SPEED_10_100 0x10
1802 #define KSZ8567_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
1803 
1804 //XMII Port N Control 1 register
1805 #define KSZ8567_PORTn_XMII_CTRL1_SPEED_1000 0x40
1806 #define KSZ8567_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
1807 #define KSZ8567_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
1808 #define KSZ8567_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
1809 #define KSZ8567_PORTn_XMII_CTRL1_IF_TYPE 0x03
1810 #define KSZ8567_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x00
1811 #define KSZ8567_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
1812 #define KSZ8567_PORTn_XMII_CTRL1_IF_TYPE_MII 0x03
1813 
1814 //Port N MAC Control 0 register
1815 #define KSZ8567_PORTn_MAC_CTRL0_BCAST_STORM_PROTECT_EN 0x02
1816 
1817 //Port N MAC Control 1 register
1818 #define KSZ8567_PORTn_MAC_CTRL1_BACK_PRESSURE_EN 0x08
1819 #define KSZ8567_PORTn_MAC_CTRL1_PASS_ALL_FRAMES 0x01
1820 
1821 //Port N MIB Control and Status register
1822 #define KSZ8567_PORTn_MIB_CTRL_STAT_MIB_COUNTER_OVERFLOW 0x80000000
1823 #define KSZ8567_PORTn_MIB_CTRL_STAT_MIB_READ 0x02000000
1824 #define KSZ8567_PORTn_MIB_CTRL_STAT_MIB_FLUSH_FREEZE 0x01000000
1825 #define KSZ8567_PORTn_MIB_CTRL_STAT_MIB_INDEX 0x00FF0000
1826 #define KSZ8567_PORTn_MIB_CTRL_STAT_MIB_COUNTER_VALUE_35_32 0x0000000F
1827 
1828 //Port N MIB Data register
1829 #define KSZ8567_PORTn_MIB_DATA_MIB_COUNTER_VALUE_31_0 0xFFFFFFFF
1830 
1831 //Port N ACL Access Control 0 register
1832 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0_WRITE_STATUS 0x40
1833 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0_READ_STATUS 0x20
1834 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0_READ 0x00
1835 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0_WRITE 0x10
1836 #define KSZ8567_PORTn_ACL_ACCESS_CTRL0_ACL_INDEX 0x0F
1837 
1838 //Port N Port Mirroring Control register
1839 #define KSZ8567_PORTn_MIRRORING_CTRL_RECEIVE_SNIFF 0x40
1840 #define KSZ8567_PORTn_MIRRORING_CTRL_TRANSMIT_SNIFF 0x20
1841 #define KSZ8567_PORTn_MIRRORING_CTRL_SNIFFER_PORT 0x02
1842 
1843 //Port N Authentication Control register
1844 #define KSZ8567_PORTn_AUTH_CTRL_ACL_EN 0x04
1845 #define KSZ8567_PORTn_AUTH_CTRL_AUTH_MODE 0x03
1846 #define KSZ8567_PORTn_AUTH_CTRL_AUTH_MODE_PASS 0x00
1847 #define KSZ8567_PORTn_AUTH_CTRL_AUTH_MODE_BLOCK 0x01
1848 #define KSZ8567_PORTn_AUTH_CTRL_AUTH_MODE_TRAP 0x02
1849 
1850 //Port N Pointer register
1851 #define KSZ8567_PORTn_PTR_PORT_INDEX 0x00070000
1852 #define KSZ8567_PORTn_PTR_QUEUE_PTR 0x00000003
1853 
1854 //Port N Control 1 register
1855 #define KSZ8567_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x0000007F
1856 #define KSZ8567_PORTn_CTRL1_PORT7_VLAN_MEMBERSHIP 0x00000040
1857 #define KSZ8567_PORTn_CTRL1_PORT6_VLAN_MEMBERSHIP 0x00000020
1858 #define KSZ8567_PORTn_CTRL1_PORT5_VLAN_MEMBERSHIP 0x00000010
1859 #define KSZ8567_PORTn_CTRL1_PORT4_VLAN_MEMBERSHIP 0x00000008
1860 #define KSZ8567_PORTn_CTRL1_PORT3_VLAN_MEMBERSHIP 0x00000004
1861 #define KSZ8567_PORTn_CTRL1_PORT2_VLAN_MEMBERSHIP 0x00000002
1862 #define KSZ8567_PORTn_CTRL1_PORT1_VLAN_MEMBERSHIP 0x00000001
1863 
1864 //Port N Control 2 register
1865 #define KSZ8567_PORTn_CTRL2_NULL_VID_LOOKUP_EN 0x80
1866 #define KSZ8567_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
1867 #define KSZ8567_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
1868 #define KSZ8567_PORTn_CTRL2_802_1X_EN 0x10
1869 #define KSZ8567_PORTn_CTRL2_SELF_ADDR_FILT 0x08
1870 
1871 //Port N MSTP Pointer register
1872 #define KSZ8567_PORTn_MSTP_PTR_MSTP_PTR 0x07
1873 
1874 //Port N MSTP State register
1875 #define KSZ8567_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
1876 #define KSZ8567_PORTn_MSTP_STATE_RECEIVE_EN 0x02
1877 #define KSZ8567_PORTn_MSTP_STATE_LEARNING_DIS 0x01
1878 
1879 //Port N PTP Asymmetry Correction register
1880 #define KSZ8567_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR_SIGN 0x8000
1881 #define KSZ8567_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR 0x7FFF
1882 
1883 //Port N PTP Timestamp Interrupt Status register
1884 #define KSZ8567_PORTn_PTP_TS_INT_STAT_TS_SYNC_INT_STATUS 0x8000
1885 #define KSZ8567_PORTn_PTP_TS_INT_STAT_TS_PDLY_REQ_INT_STATUS 0x4000
1886 #define KSZ8567_PORTn_PTP_TS_INT_STAT_TS_PDLY_RESP_INT_STATUS 0x2000
1887 
1888 //Port N PTP Timestamp Interrupt Enable register
1889 #define KSZ8567_PORTn_PTP_TS_INT_EN_TS_SYNC_INT_ENB 0x8000
1890 #define KSZ8567_PORTn_PTP_TS_INT_EN_TS_PDLY_REQ_INT_ENB 0x4000
1891 #define KSZ8567_PORTn_PTP_TS_INT_EN_TS_PDLY_RESP_INT_ENB 0x2000
1892 
1893 //C++ guard
1894 #ifdef __cplusplus
1895 extern "C" {
1896 #endif
1897 
1898 //KSZ8567 Ethernet switch driver
1899 extern const SwitchDriver ksz8567SwitchDriver;
1900 
1901 //KSZ8567 related functions
1902 error_t ksz8567Init(NetInterface *interface);
1903 void ksz8567InitHook(NetInterface *interface);
1904 
1905 void ksz8567Tick(NetInterface *interface);
1906 
1907 void ksz8567EnableIrq(NetInterface *interface);
1908 void ksz8567DisableIrq(NetInterface *interface);
1909 
1910 void ksz8567EventHandler(NetInterface *interface);
1911 
1912 error_t ksz8567TagFrame(NetInterface *interface, NetBuffer *buffer,
1913  size_t *offset, NetTxAncillary *ancillary);
1914 
1915 error_t ksz8567UntagFrame(NetInterface *interface, uint8_t **frame,
1916  size_t *length, NetRxAncillary *ancillary);
1917 
1918 bool_t ksz8567GetLinkState(NetInterface *interface, uint8_t port);
1919 uint32_t ksz8567GetLinkSpeed(NetInterface *interface, uint8_t port);
1921 
1922 void ksz8567SetPortState(NetInterface *interface, uint8_t port,
1923  SwitchPortState state);
1924 
1926 
1927 void ksz8567SetAgingTime(NetInterface *interface, uint32_t agingTime);
1928 
1929 void ksz8567EnableIgmpSnooping(NetInterface *interface, bool_t enable);
1930 void ksz8567EnableMldSnooping(NetInterface *interface, bool_t enable);
1931 void ksz8567EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
1932 
1934  const SwitchFdbEntry *entry);
1935 
1937  const SwitchFdbEntry *entry);
1938 
1940  SwitchFdbEntry *entry);
1941 
1942 void ksz8567FlushStaticFdbTable(NetInterface *interface);
1943 
1945  SwitchFdbEntry *entry);
1946 
1947 void ksz8567FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
1948 
1950  bool_t enable, uint32_t forwardPorts);
1951 
1952 void ksz8567WritePhyReg(NetInterface *interface, uint8_t port,
1953  uint8_t address, uint16_t data);
1954 
1955 uint16_t ksz8567ReadPhyReg(NetInterface *interface, uint8_t port,
1956  uint8_t address);
1957 
1958 void ksz8567DumpPhyReg(NetInterface *interface, uint8_t port);
1959 
1960 void ksz8567WriteMmdReg(NetInterface *interface, uint8_t port,
1961  uint8_t devAddr, uint16_t regAddr, uint16_t data);
1962 
1963 uint16_t ksz8567ReadMmdReg(NetInterface *interface, uint8_t port,
1964  uint8_t devAddr, uint16_t regAddr);
1965 
1966 void ksz8567WriteSwitchReg8(NetInterface *interface, uint16_t address,
1967  uint8_t data);
1968 
1969 uint8_t ksz8567ReadSwitchReg8(NetInterface *interface, uint16_t address);
1970 
1971 void ksz8567WriteSwitchReg16(NetInterface *interface, uint16_t address,
1972  uint16_t data);
1973 
1974 uint16_t ksz8567ReadSwitchReg16(NetInterface *interface, uint16_t address);
1975 
1976 void ksz8567WriteSwitchReg32(NetInterface *interface, uint16_t address,
1977  uint32_t data);
1978 
1979 uint32_t ksz8567ReadSwitchReg32(NetInterface *interface, uint16_t address);
1980 
1981 //C++ guard
1982 #ifdef __cplusplus
1983 }
1984 #endif
1985 
1986 #endif
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
uint16_t port
Definition: dns_common.h:267
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
error_t ksz8567GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
const SwitchDriver ksz8567SwitchDriver
KSZ8567 Ethernet switch driver.
void ksz8567WriteMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
void ksz8567SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
uint8_t ksz8567ReadSwitchReg8(NetInterface *interface, uint16_t address)
Read switch register (8 bits)
uint16_t ksz8567ReadSwitchReg16(NetInterface *interface, uint16_t address)
Read switch register (16 bits)
void ksz8567WriteSwitchReg16(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register (16 bits)
void ksz8567DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz8567EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
error_t ksz8567DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
void ksz8567SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
SwitchPortState ksz8567GetPortState(NetInterface *interface, uint8_t port)
Get port state.
error_t ksz8567UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
bool_t ksz8567GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint16_t ksz8567ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
void ksz8567EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8567Tick(NetInterface *interface)
KSZ8567 timer handler.
error_t ksz8567AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
void ksz8567EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
uint16_t ksz8567ReadMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
void ksz8567FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
error_t ksz8567TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
void ksz8567DisableIrq(NetInterface *interface)
Disable interrupts.
void ksz8567EventHandler(NetInterface *interface)
KSZ8567 event handler.
void ksz8567InitHook(NetInterface *interface)
KSZ8567 custom configuration.
NicDuplexMode ksz8567GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
uint32_t ksz8567ReadSwitchReg32(NetInterface *interface, uint16_t address)
Read switch register (32 bits)
error_t ksz8567Init(NetInterface *interface)
KSZ8567 Ethernet switch initialization.
uint32_t ksz8567GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
void ksz8567EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
void ksz8567FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
void ksz8567WriteSwitchReg8(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register (8 bits)
void ksz8567SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
void ksz8567WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz8567WriteSwitchReg32(NetInterface *interface, uint16_t address, uint32_t data)
Write switch register (32 bits)
error_t ksz8567GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
NicDuplexMode
Duplex mode.
Definition: nic.h:122
SwitchPortState
Switch port state.
Definition: nic.h:134
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
Ethernet switch driver.
Definition: nic.h:322
Forwarding database entry.
Definition: nic.h:149
uint8_t length
Definition: tcp.h:368