ksz9477_driver.h
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1 /**
2  * @file ksz9477_driver.h
3  * @brief KSZ9477 7-port Gigabit Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _KSZ9477_DRIVER_H
32 #define _KSZ9477_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ9477_PORT1 1
39 #define KSZ9477_PORT2 2
40 #define KSZ9477_PORT3 3
41 #define KSZ9477_PORT4 4
42 #define KSZ9477_PORT5 5
43 #define KSZ9477_PORT6 6
44 #define KSZ9477_PORT7 7
45 
46 //Port masks
47 #define KSZ9477_PORT_MASK 0x7F
48 #define KSZ9477_PORT1_MASK 0x01
49 #define KSZ9477_PORT2_MASK 0x02
50 #define KSZ9477_PORT3_MASK 0x04
51 #define KSZ9477_PORT4_MASK 0x08
52 #define KSZ9477_PORT5_MASK 0x10
53 #define KSZ9477_PORT6_MASK 0x20
54 #define KSZ9477_PORT7_MASK 0x40
55 
56 //SPI command byte
57 #define KSZ9477_SPI_CMD_WRITE 0x40000000
58 #define KSZ9477_SPI_CMD_READ 0x60000000
59 #define KSZ9477_SPI_CMD_ADDR 0x001FFFE0
60 
61 //Size of static and dynamic MAC tables
62 #define KSZ9477_STATIC_MAC_TABLE_SIZE 16
63 #define KSZ9477_DYNAMIC_MAC_TABLE_SIZE 4096
64 
65 //Tail tag rules (host to KSZ9477)
66 #define KSZ9477_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x0400
67 #define KSZ9477_TAIL_TAG_PORT_BLOCKING_OVERRIDE 0x0200
68 #define KSZ9477_TAIL_TAG_PRIORITY 0x0180
69 #define KSZ9477_TAIL_TAG_DEST_PORT7 0x0040
70 #define KSZ9477_TAIL_TAG_DEST_PORT6 0x0020
71 #define KSZ9477_TAIL_TAG_DEST_PORT5 0x0010
72 #define KSZ9477_TAIL_TAG_DEST_PORT4 0x0008
73 #define KSZ9477_TAIL_TAG_DEST_PORT3 0x0004
74 #define KSZ9477_TAIL_TAG_DEST_PORT2 0x0002
75 #define KSZ9477_TAIL_TAG_DEST_PORT1 0x0001
76 
77 //Tail tag rules (KSZ9477 to host)
78 #define KSZ9477_TAIL_TAG_PTP_MSG 0x80
79 #define KSZ9477_TAIL_TAG_SRC_PORT 0x07
80 
81 //KSZ9477 PHY registers
82 #define KSZ9477_BMCR 0x00
83 #define KSZ9477_BMSR 0x01
84 #define KSZ9477_PHYID1 0x02
85 #define KSZ9477_PHYID2 0x03
86 #define KSZ9477_ANAR 0x04
87 #define KSZ9477_ANLPAR 0x05
88 #define KSZ9477_ANER 0x06
89 #define KSZ9477_ANNPR 0x07
90 #define KSZ9477_ANLPNPR 0x08
91 #define KSZ9477_GBCR 0x09
92 #define KSZ9477_GBSR 0x0A
93 #define KSZ9477_MMDACR 0x0D
94 #define KSZ9477_MMDAADR 0x0E
95 #define KSZ9477_GBESR 0x0F
96 #define KSZ9477_RLB 0x11
97 #define KSZ9477_LINKMD 0x12
98 #define KSZ9477_DPMAPCSS 0x13
99 #define KSZ9477_RXERCTR 0x15
100 #define KSZ9477_ICSR 0x1B
101 #define KSZ9477_AUTOMDI 0x1C
102 #define KSZ9477_PHYCON 0x1F
103 
104 //KSZ9477 MMD registers
105 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_A 0x01, 0xAC
106 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_B 0x01, 0xAD
107 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_C 0x01, 0xAE
108 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_D 0x01, 0xAF
109 #define KSZ9477_MMD_LED_MODE 0x02, 0x00
110 #define KSZ9477_MMD_EEE_ADV 0x07, 0x3C
111 #define KSZ9477_MMD_QUIET_WIRE_CONFIG0 0x1C, 0x25
112 #define KSZ9477_MMD_QUIET_WIRE_CONFIG1 0x1C, 0x26
113 #define KSZ9477_MMD_QUIET_WIRE_CONFIG2 0x1C, 0x27
114 #define KSZ9477_MMD_QUIET_WIRE_CONFIG3 0x1C, 0x28
115 #define KSZ9477_MMD_QUIET_WIRE_CONFIG4 0x1C, 0x29
116 #define KSZ9477_MMD_QUIET_WIRE_CONFIG5 0x1C, 0x2A
117 #define KSZ9477_MMD_QUIET_WIRE_CONFIG6 0x1C, 0x2B
118 #define KSZ9477_MMD_QUIET_WIRE_CONFIG7 0x1C, 0x2C
119 #define KSZ9477_MMD_QUIET_WIRE_CONFIG8 0x1C, 0x2D
120 #define KSZ9477_MMD_QUIET_WIRE_CONFIG9 0x1C, 0x2E
121 #define KSZ9477_MMD_QUIET_WIRE_CONFIG10 0x1C, 0x2F
122 #define KSZ9477_MMD_QUIET_WIRE_CONFIG11 0x1C, 0x30
123 #define KSZ9477_MMD_QUIET_WIRE_CONFIG12 0x1C, 0x31
124 #define KSZ9477_MMD_QUIET_WIRE_CONFIG13 0x1C, 0x32
125 #define KSZ9477_MMD_QUIET_WIRE_CONFIG14 0x1C, 0x33
126 #define KSZ9477_MMD_QUIET_WIRE_CONFIG15 0x1C, 0x34
127 
128 //KSZ9477 Switch registers
129 #define KSZ9477_CHIP_ID0 0x0000
130 #define KSZ9477_CHIP_ID1 0x0001
131 #define KSZ9477_CHIP_ID2 0x0002
132 #define KSZ9477_CHIP_ID3 0x0003
133 #define KSZ9477_PME_PIN_CTRL 0x0006
134 #define KSZ9477_GLOBAL_INT_STAT 0x0010
135 #define KSZ9477_GLOBAL_INT_MASK 0x0014
136 #define KSZ9477_GLOBAL_PORT_INT_STAT 0x0018
137 #define KSZ9477_GLOBAL_PORT_INT_MASK 0x001C
138 #define KSZ9477_SERIAL_IO_CTRL 0x0100
139 #define KSZ9477_OUT_CLK_CTRL 0x0103
140 #define KSZ9477_IBA_CTRL 0x0104
141 #define KSZ9477_IO_DRIVE_STRENGTH 0x010D
142 #define KSZ9477_IBA_OP_STAT1 0x0110
143 #define KSZ9477_LED_OVERRIDE 0x0120
144 #define KSZ9477_LED_OUTPUT 0x0124
145 #define KSZ9477_LED2_0_LED2_1_SRC 0x0128
146 #define KSZ9477_PWR_DOWN_CTRL0 0x0201
147 #define KSZ9477_LED_STRAP_IN 0x0210
148 #define KSZ9477_SWITCH_OP 0x0300
149 #define KSZ9477_SWITCH_MAC_ADDR0 0x0302
150 #define KSZ9477_SWITCH_MAC_ADDR1 0x0303
151 #define KSZ9477_SWITCH_MAC_ADDR2 0x0304
152 #define KSZ9477_SWITCH_MAC_ADDR3 0x0305
153 #define KSZ9477_SWITCH_MAC_ADDR4 0x0306
154 #define KSZ9477_SWITCH_MAC_ADDR5 0x0307
155 #define KSZ9477_SWITCH_MTU 0x0308
156 #define KSZ9477_SWITCH_ISP_TPID 0x030A
157 #define KSZ9477_SWITCH_HSR_TPID 0x030C
158 #define KSZ9477_AVB_CBS_STRATEGY 0x030E
159 #define KSZ9477_SWITCH_LUE_CTRL0 0x0310
160 #define KSZ9477_SWITCH_LUE_CTRL1 0x0311
161 #define KSZ9477_SWITCH_LUE_CTRL2 0x0312
162 #define KSZ9477_SWITCH_LUE_CTRL3 0x0313
163 #define KSZ9477_ALU_TABLE_INT 0x0314
164 #define KSZ9477_ALU_TABLE_MASK 0x0315
165 #define KSZ9477_ALU_TABLE_ENTRY_INDEX0 0x0316
166 #define KSZ9477_ALU_TABLE_ENTRY_INDEX1 0x0318
167 #define KSZ9477_ALU_TABLE_ENTRY_INDEX2 0x031A
168 #define KSZ9477_UNKNOWN_UNICAST_CTRL 0x0320
169 #define KSZ9477_UNKONWN_MULTICAST_CTRL 0x0324
170 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL 0x0328
171 #define KSZ9477_SWITCH_MAC_CTRL0 0x0330
172 #define KSZ9477_SWITCH_MAC_CTRL1 0x0331
173 #define KSZ9477_SWITCH_MAC_CTRL2 0x0332
174 #define KSZ9477_SWITCH_MAC_CTRL3 0x0333
175 #define KSZ9477_SWITCH_MAC_CTRL4 0x0334
176 #define KSZ9477_SWITCH_MAC_CTRL5 0x0335
177 #define KSZ9477_SWITCH_MIB_CTRL 0x0336
178 #define KSZ9477_802_1P_PRIO_MAPPING0 0x0338
179 #define KSZ9477_802_1P_PRIO_MAPPING1 0x0339
180 #define KSZ9477_802_1P_PRIO_MAPPING2 0x033A
181 #define KSZ9477_802_1P_PRIO_MAPPING3 0x033B
182 #define KSZ9477_IP_DIFFSERV_PRIO_EN 0x033E
183 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING0 0x0340
184 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING1 0x0341
185 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING2 0x0342
186 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING3 0x0343
187 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING4 0x0344
188 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING5 0x0345
189 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING6 0x0346
190 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING7 0x0347
191 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING8 0x0348
192 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING9 0x0349
193 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING10 0x034A
194 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING11 0x034B
195 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING12 0x034C
196 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING13 0x034D
197 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING14 0x034E
198 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING15 0x034F
199 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING16 0x0350
200 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING17 0x0351
201 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING18 0x0352
202 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING19 0x0353
203 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING20 0x0354
204 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING21 0x0355
205 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING22 0x0356
206 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING23 0x0357
207 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING24 0x0358
208 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING25 0x0359
209 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING26 0x035A
210 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING27 0x035B
211 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING28 0x035C
212 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING29 0x035D
213 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING30 0x035E
214 #define KSZ9477_IP_DIFFSERV_PRIO_MAPPING31 0x035F
215 #define KSZ9477_GLOBAL_PORT_MIRROR_SNOOP_CTRL 0x0370
216 #define KSZ9477_WRED_DIFFSERV_COLOR_MAPPING 0x0378
217 #define KSZ9477_PTP_EVENT_MSG_PRIO 0x037C
218 #define KSZ9477_PTP_NON_EVENT_MSG_PRIO 0x037D
219 #define KSZ9477_QUEUE_MGMT_CTRL0 0x0390
220 #define KSZ9477_VLAN_TABLE_ENTRY0 0x0400
221 #define KSZ9477_VLAN_TABLE_ENTRY1 0x0404
222 #define KSZ9477_VLAN_TABLE_ENTRY2 0x0408
223 #define KSZ9477_VLAN_TABLE_INDEX 0x040C
224 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL 0x040E
225 #define KSZ9477_ALU_TABLE_INDEX0 0x0410
226 #define KSZ9477_ALU_TABLE_INDEX1 0x0414
227 #define KSZ9477_ALU_TABLE_CTRL 0x0418
228 #define KSZ9477_STATIC_MCAST_TABLE_CTRL 0x041C
229 #define KSZ9477_ALU_TABLE_ENTRY1 0x0420
230 #define KSZ9477_STATIC_TABLE_ENTRY1 0x0420
231 #define KSZ9477_ALU_TABLE_ENTRY2 0x0424
232 #define KSZ9477_STATIC_TABLE_ENTRY2 0x0424
233 #define KSZ9477_RES_MCAST_TABLE_ENTRY2 0x0424
234 #define KSZ9477_ALU_TABLE_ENTRY3 0x0428
235 #define KSZ9477_STATIC_TABLE_ENTRY3 0x0428
236 #define KSZ9477_ALU_TABLE_ENTRY4 0x042C
237 #define KSZ9477_STATIC_TABLE_ENTRY4 0x042C
238 #define KSZ9477_GLOBAL_HSR_ALU_INDEX1 0x0444
239 #define KSZ9477_GLOBAL_HSR_ALU_INDEX2 0x0448
240 #define KSZ9477_GLOBAL_HSR_ALU_ACCESS_CTRL 0x0450
241 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_A 0x0454
242 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_B 0x0458
243 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_C 0x045C
244 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_D 0x0460
245 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_E 0x0464
246 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_F 0x0468
247 #define KSZ9477_GLOBAL_HSR_ALU_VALUE_G 0x046C
248 #define KSZ9477_GLOBAL_PTP_CLK_CTRL 0x0500
249 #define KSZ9477_GLOBAL_PTP_RTC_CLK_PHASE 0x0502
250 #define KSZ9477_GLOBAL_PTP_RTC_CLK_NS_H 0x0504
251 #define KSZ9477_GLOBAL_PTP_RTC_CLK_NS_L 0x0506
252 #define KSZ9477_GLOBAL_PTP_RTC_CLK_S_H 0x0508
253 #define KSZ9477_GLOBAL_PTP_RTC_CLK_S_L 0x050A
254 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_H 0x050C
255 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_L 0x050E
256 #define KSZ9477_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_H 0x0510
257 #define KSZ9477_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_L 0x0512
258 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1 0x0514
259 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2 0x0516
260 #define KSZ9477_GLOBAL_PTP_DOMAIN_VERSION 0x0518
261 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX 0x0520
262 #define KSZ9477_GPIO_STATUS_MONITOR0 0x0524
263 #define KSZ9477_GPIO_STATUS_MONITOR1 0x0528
264 #define KSZ9477_TS_CTRL_STAT 0x052C
265 #define KSZ9477_TOU_TARGET_TIME_NS 0x0530
266 #define KSZ9477_TOU_TARGET_TIME_S 0x0534
267 #define KSZ9477_TOU_CTRL1 0x0538
268 #define KSZ9477_TOU_CTRL2 0x053C
269 #define KSZ9477_TOU_CTRL3 0x0540
270 #define KSZ9477_TOU_CTRL4 0x0544
271 #define KSZ9477_TOU_CTRL5 0x0548
272 #define KSZ9477_TS_STAT_CTRL 0x0550
273 #define KSZ9477_TS_SAMPLE1_TIME_NS 0x0554
274 #define KSZ9477_TS_SAMPLE1_TIME_S 0x0558
275 #define KSZ9477_TS_SAMPLE1_TIME_PHASE 0x055C
276 #define KSZ9477_TS_SAMPLE2_TIME_NS 0x0560
277 #define KSZ9477_TS_SAMPLE2_TIME_S 0x0564
278 #define KSZ9477_TS_SAMPLE2_TIME_PHASE 0x0568
279 #define KSZ9477_TS_SAMPLE3_TIME_NS 0x056C
280 #define KSZ9477_TS_SAMPLE3_TIME_S 0x0570
281 #define KSZ9477_TS_SAMPLE3_TIME_PHASE 0x0574
282 #define KSZ9477_TS_SAMPLE4_TIME_NS 0x0578
283 #define KSZ9477_TS_SAMPLE4_TIME_S 0x057C
284 #define KSZ9477_TS_SAMPLE4_TIME_PHASE 0x0580
285 #define KSZ9477_TS_SAMPLE5_TIME_NS 0x0584
286 #define KSZ9477_TS_SAMPLE5_TIME_S 0x0588
287 #define KSZ9477_TS_SAMPLE5_TIME_PHASE 0x058C
288 #define KSZ9477_TS_SAMPLE6_TIME_NS 0x0590
289 #define KSZ9477_TS_SAMPLE6_TIME_S 0x0594
290 #define KSZ9477_TS_SAMPLE6_TIME_PHASE 0x0598
291 #define KSZ9477_TS_SAMPLE7_TIME_NS 0x059C
292 #define KSZ9477_TS_SAMPLE7_TIME_S 0x05A0
293 #define KSZ9477_TS_SAMPLE7_TIME_PHASE 0x05A4
294 #define KSZ9477_TS_SAMPLE8_TIME_NS 0x05A8
295 #define KSZ9477_TS_SAMPLE8_TIME_S 0x05AC
296 #define KSZ9477_TS_SAMPLE8_TIME_PHASE 0x05B0
297 #define KSZ9477_GLOBAL_DLR_SRC_PORT 0x0604
298 #define KSZ9477_GLOBAL_DLR_SRC_IP_ADDR 0x0608
299 #define KSZ9477_GLOBAL_DLR_CTRL 0x0610
300 #define KSZ9477_GLOBAL_DLR_STATE 0x0611
301 #define KSZ9477_GLOBAL_DLR_SUPERVISOR_PRECEDENT 0x0612
302 #define KSZ9477_GLOBAL_DLR_BEACON_INTERVAL 0x0614
303 #define KSZ9477_GLOBAL_DLR_BEACON_TIMEOUT 0x0618
304 #define KSZ9477_GLOBAL_DLR_BEACON_TIMEOUT_WINDOW 0x061C
305 #define KSZ9477_GLOBAL_DLR_VLAN 0x0620
306 #define KSZ9477_GLOBAL_DLR_DEST_ADDR 0x0622
307 #define KSZ9477_GLOBAL_DLR_PORT_MAP 0x0628
308 #define KSZ9477_GLOBAL_DLR_CLASS 0x062C
309 #define KSZ9477_GLOBAL_HSR_PORT_MAP 0x0640
310 #define KSZ9477_GLOBAL_HSR_AME_CTRL0 0x0644
311 #define KSZ9477_GLOBAL_HSR_AME_CTRL1 0x0645
312 #define KSZ9477_GLOBAL_HSR_AME_AGE_PERIOD 0x0648
313 #define KSZ9477_GLOBAL_HSR_AME_INT 0x064C
314 #define KSZ9477_GLOBAL_HSR_AME_INT_MASK 0x064D
315 #define KSZ9477_PORT1_DEFAULT_TAG0 0x1000
316 #define KSZ9477_PORT1_DEFAULT_TAG1 0x1001
317 #define KSZ9477_PORT1_PME_WOL_EVENT 0x1013
318 #define KSZ9477_PORT1_PME_WOL_EN 0x1017
319 #define KSZ9477_PORT1_INT_STATUS 0x101B
320 #define KSZ9477_PORT1_INT_MASK 0x101F
321 #define KSZ9477_PORT1_OP_CTRL0 0x1020
322 #define KSZ9477_PORT1_STATUS 0x1030
323 #define KSZ9477_PORT1_MAC_CTRL0 0x1400
324 #define KSZ9477_PORT1_MAC_CTRL1 0x1401
325 #define KSZ9477_PORT1_IG_RATE_LIMIT_CTRL 0x1403
326 #define KSZ9477_PORT1_PRIO0_IG_LIMIT_CTRL 0x1410
327 #define KSZ9477_PORT1_PRIO1_IG_LIMIT_CTRL 0x1411
328 #define KSZ9477_PORT1_PRIO2_IG_LIMIT_CTRL 0x1412
329 #define KSZ9477_PORT1_PRIO3_IG_LIMIT_CTRL 0x1413
330 #define KSZ9477_PORT1_PRIO4_IG_LIMIT_CTRL 0x1414
331 #define KSZ9477_PORT1_PRIO5_IG_LIMIT_CTRL 0x1415
332 #define KSZ9477_PORT1_PRIO6_IG_LIMIT_CTRL 0x1416
333 #define KSZ9477_PORT1_PRIO7_IG_LIMIT_CTRL 0x1417
334 #define KSZ9477_PORT1_QUEUE0_EG_LIMIT_CTRL 0x1420
335 #define KSZ9477_PORT1_QUEUE1_EG_LIMIT_CTRL 0x1421
336 #define KSZ9477_PORT1_QUEUE2_EG_LIMIT_CTRL 0x1422
337 #define KSZ9477_PORT1_QUEUE3_EG_LIMIT_CTRL 0x1423
338 #define KSZ9477_PORT1_MIB_CTRL_STAT 0x1500
339 #define KSZ9477_PORT1_MIB_DATA 0x1504
340 #define KSZ9477_PORT1_ACL_ACCESS0 0x1600
341 #define KSZ9477_PORT1_ACL_ACCESS1 0x1601
342 #define KSZ9477_PORT1_ACL_ACCESS2 0x1602
343 #define KSZ9477_PORT1_ACL_ACCESS3 0x1603
344 #define KSZ9477_PORT1_ACL_ACCESS4 0x1604
345 #define KSZ9477_PORT1_ACL_ACCESS5 0x1605
346 #define KSZ9477_PORT1_ACL_ACCESS6 0x1606
347 #define KSZ9477_PORT1_ACL_ACCESS7 0x1607
348 #define KSZ9477_PORT1_ACL_ACCESS8 0x1608
349 #define KSZ9477_PORT1_ACL_ACCESS9 0x1609
350 #define KSZ9477_PORT1_ACL_ACCESS10 0x160A
351 #define KSZ9477_PORT1_ACL_ACCESS11 0x160B
352 #define KSZ9477_PORT1_ACL_ACCESS12 0x160C
353 #define KSZ9477_PORT1_ACL_ACCESS13 0x160D
354 #define KSZ9477_PORT1_ACL_ACCESS14 0x160E
355 #define KSZ9477_PORT1_ACL_ACCESS15 0x160F
356 #define KSZ9477_PORT1_ACL_BYTE_EN_MSB 0x1610
357 #define KSZ9477_PORT1_ACL_BYTE_EN_LSB 0x1611
358 #define KSZ9477_PORT1_ACL_ACCESS_CTRL0 0x1612
359 #define KSZ9477_PORT1_ACL_ACCESS_CTRL1 0x1613
360 #define KSZ9477_PORT1_MIRRORING_CTRL 0x1800
361 #define KSZ9477_PORT1_PRIO_CTRL 0x1801
362 #define KSZ9477_PORT1_IG_MAC_CTRL 0x1802
363 #define KSZ9477_PORT1_AUTH_CTRL 0x1803
364 #define KSZ9477_PORT1_PTR 0x1804
365 #define KSZ9477_PORT1_PRIO_TO_QUEUE_MAPPING 0x1808
366 #define KSZ9477_PORT1_POLICE_CTRL 0x180C
367 #define KSZ9477_PORT1_POLICE_QUEUE_RATE 0x1820
368 #define KSZ9477_PORT1_POLICE_QUEUE_BURST_SIZE 0x1824
369 #define KSZ9477_PORT1_WRED_PKT_MEM_CTRL0 0x1830
370 #define KSZ9477_PORT1_WRED_PKT_MEM_CTRL1 0x1834
371 #define KSZ9477_PORT1_WRED_QUEUE_CTRL0 0x1840
372 #define KSZ9477_PORT1_WRED_QUEUE_CTRL1 0x1844
373 #define KSZ9477_PORT1_WRED_QUEUE_PERF_MON_CTRL 0x1848
374 #define KSZ9477_PORT1_TX_QUEUE_INDEX 0x1900
375 #define KSZ9477_PORT1_TX_QUEUE_PVID 0x1904
376 #define KSZ9477_PORT1_TX_QUEUE_CTRL0 0x1914
377 #define KSZ9477_PORT1_TX_QUEUE_CTRL1 0x1915
378 #define KSZ9477_PORT1_TX_CREDIT_SHAPER_CTRL0 0x1916
379 #define KSZ9477_PORT1_TX_CREDIT_SHAPER_CTRL1 0x1918
380 #define KSZ9477_PORT1_TX_CREDIT_SHAPER_CTRL2 0x191A
381 #define KSZ9477_PORT1_TAS_CTRL 0x1920
382 #define KSZ9477_PORT1_TAS_EVENT_INDEX 0x1923
383 #define KSZ9477_PORT1_TAS_EVENT 0x1924
384 #define KSZ9477_PORT1_CTRL0 0x1A00
385 #define KSZ9477_PORT1_CTRL1 0x1A04
386 #define KSZ9477_PORT1_CTRL2 0x1B00
387 #define KSZ9477_PORT1_MSTP_PTR 0x1B01
388 #define KSZ9477_PORT1_MSTP_STATE 0x1B04
389 #define KSZ9477_PORT1_PTP_RX_LATENCY 0x1C00
390 #define KSZ9477_PORT1_PTP_TX_LATENCY 0x1C02
391 #define KSZ9477_PORT1_PTP_ASYM_CORRECTION 0x1C04
392 #define KSZ9477_PORT1_PTP_XDLY_REQ_TSH 0x1C08
393 #define KSZ9477_PORT1_PTP_XDLY_REQ_TSL 0x1C0A
394 #define KSZ9477_PORT1_PTP_SYNC_TSH 0x1C0C
395 #define KSZ9477_PORT1_PTP_SYNC_TSL 0x1C0E
396 #define KSZ9477_PORT1_PTP_PDLY_RESP_TSH 0x1C10
397 #define KSZ9477_PORT1_PTP_PDLY_RESP_TSL 0x1C12
398 #define KSZ9477_PORT1_PTP_TS_INT_STAT 0x1C14
399 #define KSZ9477_PORT1_PTP_TS_INT_EN 0x1C16
400 #define KSZ9477_PORT1_PTP_LINK_DELAY 0x1C18
401 #define KSZ9477_PORT2_DEFAULT_TAG0 0x2000
402 #define KSZ9477_PORT2_DEFAULT_TAG1 0x2001
403 #define KSZ9477_PORT2_PME_WOL_EVENT 0x2013
404 #define KSZ9477_PORT2_PME_WOL_EN 0x2017
405 #define KSZ9477_PORT2_INT_STATUS 0x201B
406 #define KSZ9477_PORT2_INT_MASK 0x201F
407 #define KSZ9477_PORT2_OP_CTRL0 0x2020
408 #define KSZ9477_PORT2_STATUS 0x2030
409 #define KSZ9477_PORT2_MAC_CTRL0 0x2400
410 #define KSZ9477_PORT2_MAC_CTRL1 0x2401
411 #define KSZ9477_PORT2_IG_RATE_LIMIT_CTRL 0x2403
412 #define KSZ9477_PORT2_PRIO0_IG_LIMIT_CTRL 0x2410
413 #define KSZ9477_PORT2_PRIO1_IG_LIMIT_CTRL 0x2411
414 #define KSZ9477_PORT2_PRIO2_IG_LIMIT_CTRL 0x2412
415 #define KSZ9477_PORT2_PRIO3_IG_LIMIT_CTRL 0x2413
416 #define KSZ9477_PORT2_PRIO4_IG_LIMIT_CTRL 0x2414
417 #define KSZ9477_PORT2_PRIO5_IG_LIMIT_CTRL 0x2415
418 #define KSZ9477_PORT2_PRIO6_IG_LIMIT_CTRL 0x2416
419 #define KSZ9477_PORT2_PRIO7_IG_LIMIT_CTRL 0x2417
420 #define KSZ9477_PORT2_QUEUE0_EG_LIMIT_CTRL 0x2420
421 #define KSZ9477_PORT2_QUEUE1_EG_LIMIT_CTRL 0x2421
422 #define KSZ9477_PORT2_QUEUE2_EG_LIMIT_CTRL 0x2422
423 #define KSZ9477_PORT2_QUEUE3_EG_LIMIT_CTRL 0x2423
424 #define KSZ9477_PORT2_MIB_CTRL_STAT 0x2500
425 #define KSZ9477_PORT2_MIB_DATA 0x2504
426 #define KSZ9477_PORT2_ACL_ACCESS0 0x2600
427 #define KSZ9477_PORT2_ACL_ACCESS1 0x2601
428 #define KSZ9477_PORT2_ACL_ACCESS2 0x2602
429 #define KSZ9477_PORT2_ACL_ACCESS3 0x2603
430 #define KSZ9477_PORT2_ACL_ACCESS4 0x2604
431 #define KSZ9477_PORT2_ACL_ACCESS5 0x2605
432 #define KSZ9477_PORT2_ACL_ACCESS6 0x2606
433 #define KSZ9477_PORT2_ACL_ACCESS7 0x2607
434 #define KSZ9477_PORT2_ACL_ACCESS8 0x2608
435 #define KSZ9477_PORT2_ACL_ACCESS9 0x2609
436 #define KSZ9477_PORT2_ACL_ACCESS10 0x260A
437 #define KSZ9477_PORT2_ACL_ACCESS11 0x260B
438 #define KSZ9477_PORT2_ACL_ACCESS12 0x260C
439 #define KSZ9477_PORT2_ACL_ACCESS13 0x260D
440 #define KSZ9477_PORT2_ACL_ACCESS14 0x260E
441 #define KSZ9477_PORT2_ACL_ACCESS15 0x260F
442 #define KSZ9477_PORT2_ACL_BYTE_EN_MSB 0x2610
443 #define KSZ9477_PORT2_ACL_BYTE_EN_LSB 0x2611
444 #define KSZ9477_PORT2_ACL_ACCESS_CTRL0 0x2612
445 #define KSZ9477_PORT2_ACL_ACCESS_CTRL1 0x2613
446 #define KSZ9477_PORT2_MIRRORING_CTRL 0x2800
447 #define KSZ9477_PORT2_PRIO_CTRL 0x2801
448 #define KSZ9477_PORT2_IG_MAC_CTRL 0x2802
449 #define KSZ9477_PORT2_AUTH_CTRL 0x2803
450 #define KSZ9477_PORT2_PTR 0x2804
451 #define KSZ9477_PORT2_PRIO_TO_QUEUE_MAPPING 0x2808
452 #define KSZ9477_PORT2_POLICE_CTRL 0x280C
453 #define KSZ9477_PORT2_POLICE_QUEUE_RATE 0x2820
454 #define KSZ9477_PORT2_POLICE_QUEUE_BURST_SIZE 0x2824
455 #define KSZ9477_PORT2_WRED_PKT_MEM_CTRL0 0x2830
456 #define KSZ9477_PORT2_WRED_PKT_MEM_CTRL1 0x2834
457 #define KSZ9477_PORT2_WRED_QUEUE_CTRL0 0x2840
458 #define KSZ9477_PORT2_WRED_QUEUE_CTRL1 0x2844
459 #define KSZ9477_PORT2_WRED_QUEUE_PERF_MON_CTRL 0x2848
460 #define KSZ9477_PORT2_TX_QUEUE_INDEX 0x2900
461 #define KSZ9477_PORT2_TX_QUEUE_PVID 0x2904
462 #define KSZ9477_PORT2_TX_QUEUE_CTRL0 0x2914
463 #define KSZ9477_PORT2_TX_QUEUE_CTRL1 0x2915
464 #define KSZ9477_PORT2_TX_CREDIT_SHAPER_CTRL0 0x2916
465 #define KSZ9477_PORT2_TX_CREDIT_SHAPER_CTRL1 0x2918
466 #define KSZ9477_PORT2_TX_CREDIT_SHAPER_CTRL2 0x291A
467 #define KSZ9477_PORT2_TAS_CTRL 0x2920
468 #define KSZ9477_PORT2_TAS_EVENT_INDEX 0x2923
469 #define KSZ9477_PORT2_TAS_EVENT 0x2924
470 #define KSZ9477_PORT2_CTRL0 0x2A00
471 #define KSZ9477_PORT2_CTRL1 0x2A04
472 #define KSZ9477_PORT2_CTRL2 0x2B00
473 #define KSZ9477_PORT2_MSTP_PTR 0x2B01
474 #define KSZ9477_PORT2_MSTP_STATE 0x2B04
475 #define KSZ9477_PORT2_PTP_RX_LATENCY 0x2C00
476 #define KSZ9477_PORT2_PTP_TX_LATENCY 0x2C02
477 #define KSZ9477_PORT2_PTP_ASYM_CORRECTION 0x2C04
478 #define KSZ9477_PORT2_PTP_XDLY_REQ_TSH 0x2C08
479 #define KSZ9477_PORT2_PTP_XDLY_REQ_TSL 0x2C0A
480 #define KSZ9477_PORT2_PTP_SYNC_TSH 0x2C0C
481 #define KSZ9477_PORT2_PTP_SYNC_TSL 0x2C0E
482 #define KSZ9477_PORT2_PTP_PDLY_RESP_TSH 0x2C10
483 #define KSZ9477_PORT2_PTP_PDLY_RESP_TSL 0x2C12
484 #define KSZ9477_PORT2_PTP_TS_INT_STAT 0x2C14
485 #define KSZ9477_PORT2_PTP_TS_INT_EN 0x2C16
486 #define KSZ9477_PORT2_PTP_LINK_DELAY 0x2C18
487 #define KSZ9477_PORT3_DEFAULT_TAG0 0x3000
488 #define KSZ9477_PORT3_DEFAULT_TAG1 0x3001
489 #define KSZ9477_PORT3_PME_WOL_EVENT 0x3013
490 #define KSZ9477_PORT3_PME_WOL_EN 0x3017
491 #define KSZ9477_PORT3_INT_STATUS 0x301B
492 #define KSZ9477_PORT3_INT_MASK 0x301F
493 #define KSZ9477_PORT3_OP_CTRL0 0x3020
494 #define KSZ9477_PORT3_STATUS 0x3030
495 #define KSZ9477_PORT3_MAC_CTRL0 0x3400
496 #define KSZ9477_PORT3_MAC_CTRL1 0x3401
497 #define KSZ9477_PORT3_IG_RATE_LIMIT_CTRL 0x3403
498 #define KSZ9477_PORT3_PRIO0_IG_LIMIT_CTRL 0x3410
499 #define KSZ9477_PORT3_PRIO1_IG_LIMIT_CTRL 0x3411
500 #define KSZ9477_PORT3_PRIO2_IG_LIMIT_CTRL 0x3412
501 #define KSZ9477_PORT3_PRIO3_IG_LIMIT_CTRL 0x3413
502 #define KSZ9477_PORT3_PRIO4_IG_LIMIT_CTRL 0x3414
503 #define KSZ9477_PORT3_PRIO5_IG_LIMIT_CTRL 0x3415
504 #define KSZ9477_PORT3_PRIO6_IG_LIMIT_CTRL 0x3416
505 #define KSZ9477_PORT3_PRIO7_IG_LIMIT_CTRL 0x3417
506 #define KSZ9477_PORT3_QUEUE0_EG_LIMIT_CTRL 0x3420
507 #define KSZ9477_PORT3_QUEUE1_EG_LIMIT_CTRL 0x3421
508 #define KSZ9477_PORT3_QUEUE2_EG_LIMIT_CTRL 0x3422
509 #define KSZ9477_PORT3_QUEUE3_EG_LIMIT_CTRL 0x3423
510 #define KSZ9477_PORT3_MIB_CTRL_STAT 0x3500
511 #define KSZ9477_PORT3_MIB_DATA 0x3504
512 #define KSZ9477_PORT3_ACL_ACCESS0 0x3600
513 #define KSZ9477_PORT3_ACL_ACCESS1 0x3601
514 #define KSZ9477_PORT3_ACL_ACCESS2 0x3602
515 #define KSZ9477_PORT3_ACL_ACCESS3 0x3603
516 #define KSZ9477_PORT3_ACL_ACCESS4 0x3604
517 #define KSZ9477_PORT3_ACL_ACCESS5 0x3605
518 #define KSZ9477_PORT3_ACL_ACCESS6 0x3606
519 #define KSZ9477_PORT3_ACL_ACCESS7 0x3607
520 #define KSZ9477_PORT3_ACL_ACCESS8 0x3608
521 #define KSZ9477_PORT3_ACL_ACCESS9 0x3609
522 #define KSZ9477_PORT3_ACL_ACCESS10 0x360A
523 #define KSZ9477_PORT3_ACL_ACCESS11 0x360B
524 #define KSZ9477_PORT3_ACL_ACCESS12 0x360C
525 #define KSZ9477_PORT3_ACL_ACCESS13 0x360D
526 #define KSZ9477_PORT3_ACL_ACCESS14 0x360E
527 #define KSZ9477_PORT3_ACL_ACCESS15 0x360F
528 #define KSZ9477_PORT3_ACL_BYTE_EN_MSB 0x3610
529 #define KSZ9477_PORT3_ACL_BYTE_EN_LSB 0x3611
530 #define KSZ9477_PORT3_ACL_ACCESS_CTRL0 0x3612
531 #define KSZ9477_PORT3_ACL_ACCESS_CTRL1 0x3613
532 #define KSZ9477_PORT3_MIRRORING_CTRL 0x3800
533 #define KSZ9477_PORT3_PRIO_CTRL 0x3801
534 #define KSZ9477_PORT3_IG_MAC_CTRL 0x3802
535 #define KSZ9477_PORT3_AUTH_CTRL 0x3803
536 #define KSZ9477_PORT3_PTR 0x3804
537 #define KSZ9477_PORT3_PRIO_TO_QUEUE_MAPPING 0x3808
538 #define KSZ9477_PORT3_POLICE_CTRL 0x380C
539 #define KSZ9477_PORT3_POLICE_QUEUE_RATE 0x3820
540 #define KSZ9477_PORT3_POLICE_QUEUE_BURST_SIZE 0x3824
541 #define KSZ9477_PORT3_WRED_PKT_MEM_CTRL0 0x3830
542 #define KSZ9477_PORT3_WRED_PKT_MEM_CTRL1 0x3834
543 #define KSZ9477_PORT3_WRED_QUEUE_CTRL0 0x3840
544 #define KSZ9477_PORT3_WRED_QUEUE_CTRL1 0x3844
545 #define KSZ9477_PORT3_WRED_QUEUE_PERF_MON_CTRL 0x3848
546 #define KSZ9477_PORT3_TX_QUEUE_INDEX 0x3900
547 #define KSZ9477_PORT3_TX_QUEUE_PVID 0x3904
548 #define KSZ9477_PORT3_TX_QUEUE_CTRL0 0x3914
549 #define KSZ9477_PORT3_TX_QUEUE_CTRL1 0x3915
550 #define KSZ9477_PORT3_TX_CREDIT_SHAPER_CTRL0 0x3916
551 #define KSZ9477_PORT3_TX_CREDIT_SHAPER_CTRL1 0x3918
552 #define KSZ9477_PORT3_TX_CREDIT_SHAPER_CTRL2 0x391A
553 #define KSZ9477_PORT3_TAS_CTRL 0x3920
554 #define KSZ9477_PORT3_TAS_EVENT_INDEX 0x3923
555 #define KSZ9477_PORT3_TAS_EVENT 0x3924
556 #define KSZ9477_PORT3_CTRL0 0x3A00
557 #define KSZ9477_PORT3_CTRL1 0x3A04
558 #define KSZ9477_PORT3_CTRL2 0x3B00
559 #define KSZ9477_PORT3_MSTP_PTR 0x3B01
560 #define KSZ9477_PORT3_MSTP_STATE 0x3B04
561 #define KSZ9477_PORT3_PTP_RX_LATENCY 0x3C00
562 #define KSZ9477_PORT3_PTP_TX_LATENCY 0x3C02
563 #define KSZ9477_PORT3_PTP_ASYM_CORRECTION 0x3C04
564 #define KSZ9477_PORT3_PTP_XDLY_REQ_TSH 0x3C08
565 #define KSZ9477_PORT3_PTP_XDLY_REQ_TSL 0x3C0A
566 #define KSZ9477_PORT3_PTP_SYNC_TSH 0x3C0C
567 #define KSZ9477_PORT3_PTP_SYNC_TSL 0x3C0E
568 #define KSZ9477_PORT3_PTP_PDLY_RESP_TSH 0x3C10
569 #define KSZ9477_PORT3_PTP_PDLY_RESP_TSL 0x3C12
570 #define KSZ9477_PORT3_PTP_TS_INT_STAT 0x3C14
571 #define KSZ9477_PORT3_PTP_TS_INT_EN 0x3C16
572 #define KSZ9477_PORT3_PTP_LINK_DELAY 0x3C18
573 #define KSZ9477_PORT4_DEFAULT_TAG0 0x4000
574 #define KSZ9477_PORT4_DEFAULT_TAG1 0x4001
575 #define KSZ9477_PORT4_PME_WOL_EVENT 0x4013
576 #define KSZ9477_PORT4_PME_WOL_EN 0x4017
577 #define KSZ9477_PORT4_INT_STATUS 0x401B
578 #define KSZ9477_PORT4_INT_MASK 0x401F
579 #define KSZ9477_PORT4_OP_CTRL0 0x4020
580 #define KSZ9477_PORT4_STATUS 0x4030
581 #define KSZ9477_PORT4_MAC_CTRL0 0x4400
582 #define KSZ9477_PORT4_MAC_CTRL1 0x4401
583 #define KSZ9477_PORT4_IG_RATE_LIMIT_CTRL 0x4403
584 #define KSZ9477_PORT4_PRIO0_IG_LIMIT_CTRL 0x4410
585 #define KSZ9477_PORT4_PRIO1_IG_LIMIT_CTRL 0x4411
586 #define KSZ9477_PORT4_PRIO2_IG_LIMIT_CTRL 0x4412
587 #define KSZ9477_PORT4_PRIO3_IG_LIMIT_CTRL 0x4413
588 #define KSZ9477_PORT4_PRIO4_IG_LIMIT_CTRL 0x4414
589 #define KSZ9477_PORT4_PRIO5_IG_LIMIT_CTRL 0x4415
590 #define KSZ9477_PORT4_PRIO6_IG_LIMIT_CTRL 0x4416
591 #define KSZ9477_PORT4_PRIO7_IG_LIMIT_CTRL 0x4417
592 #define KSZ9477_PORT4_QUEUE0_EG_LIMIT_CTRL 0x4420
593 #define KSZ9477_PORT4_QUEUE1_EG_LIMIT_CTRL 0x4421
594 #define KSZ9477_PORT4_QUEUE2_EG_LIMIT_CTRL 0x4422
595 #define KSZ9477_PORT4_QUEUE3_EG_LIMIT_CTRL 0x4423
596 #define KSZ9477_PORT4_MIB_CTRL_STAT 0x4500
597 #define KSZ9477_PORT4_MIB_DATA 0x4504
598 #define KSZ9477_PORT4_ACL_ACCESS0 0x4600
599 #define KSZ9477_PORT4_ACL_ACCESS1 0x4601
600 #define KSZ9477_PORT4_ACL_ACCESS2 0x4602
601 #define KSZ9477_PORT4_ACL_ACCESS3 0x4603
602 #define KSZ9477_PORT4_ACL_ACCESS4 0x4604
603 #define KSZ9477_PORT4_ACL_ACCESS5 0x4605
604 #define KSZ9477_PORT4_ACL_ACCESS6 0x4606
605 #define KSZ9477_PORT4_ACL_ACCESS7 0x4607
606 #define KSZ9477_PORT4_ACL_ACCESS8 0x4608
607 #define KSZ9477_PORT4_ACL_ACCESS9 0x4609
608 #define KSZ9477_PORT4_ACL_ACCESS10 0x460A
609 #define KSZ9477_PORT4_ACL_ACCESS11 0x460B
610 #define KSZ9477_PORT4_ACL_ACCESS12 0x460C
611 #define KSZ9477_PORT4_ACL_ACCESS13 0x460D
612 #define KSZ9477_PORT4_ACL_ACCESS14 0x460E
613 #define KSZ9477_PORT4_ACL_ACCESS15 0x460F
614 #define KSZ9477_PORT4_ACL_BYTE_EN_MSB 0x4610
615 #define KSZ9477_PORT4_ACL_BYTE_EN_LSB 0x4611
616 #define KSZ9477_PORT4_ACL_ACCESS_CTRL0 0x4612
617 #define KSZ9477_PORT4_ACL_ACCESS_CTRL1 0x4613
618 #define KSZ9477_PORT4_MIRRORING_CTRL 0x4800
619 #define KSZ9477_PORT4_PRIO_CTRL 0x4801
620 #define KSZ9477_PORT4_IG_MAC_CTRL 0x4802
621 #define KSZ9477_PORT4_AUTH_CTRL 0x4803
622 #define KSZ9477_PORT4_PTR 0x4804
623 #define KSZ9477_PORT4_PRIO_TO_QUEUE_MAPPING 0x4808
624 #define KSZ9477_PORT4_POLICE_CTRL 0x480C
625 #define KSZ9477_PORT4_POLICE_QUEUE_RATE 0x4820
626 #define KSZ9477_PORT4_POLICE_QUEUE_BURST_SIZE 0x4824
627 #define KSZ9477_PORT4_WRED_PKT_MEM_CTRL0 0x4830
628 #define KSZ9477_PORT4_WRED_PKT_MEM_CTRL1 0x4834
629 #define KSZ9477_PORT4_WRED_QUEUE_CTRL0 0x4840
630 #define KSZ9477_PORT4_WRED_QUEUE_CTRL1 0x4844
631 #define KSZ9477_PORT4_WRED_QUEUE_PERF_MON_CTRL 0x4848
632 #define KSZ9477_PORT4_TX_QUEUE_INDEX 0x4900
633 #define KSZ9477_PORT4_TX_QUEUE_PVID 0x4904
634 #define KSZ9477_PORT4_TX_QUEUE_CTRL0 0x4914
635 #define KSZ9477_PORT4_TX_QUEUE_CTRL1 0x4915
636 #define KSZ9477_PORT4_TX_CREDIT_SHAPER_CTRL0 0x4916
637 #define KSZ9477_PORT4_TX_CREDIT_SHAPER_CTRL1 0x4918
638 #define KSZ9477_PORT4_TX_CREDIT_SHAPER_CTRL2 0x491A
639 #define KSZ9477_PORT4_TAS_CTRL 0x4920
640 #define KSZ9477_PORT4_TAS_EVENT_INDEX 0x4923
641 #define KSZ9477_PORT4_TAS_EVENT 0x4924
642 #define KSZ9477_PORT4_CTRL0 0x4A00
643 #define KSZ9477_PORT4_CTRL1 0x4A04
644 #define KSZ9477_PORT4_CTRL2 0x4B00
645 #define KSZ9477_PORT4_MSTP_PTR 0x4B01
646 #define KSZ9477_PORT4_MSTP_STATE 0x4B04
647 #define KSZ9477_PORT4_PTP_RX_LATENCY 0x4C00
648 #define KSZ9477_PORT4_PTP_TX_LATENCY 0x4C02
649 #define KSZ9477_PORT4_PTP_ASYM_CORRECTION 0x4C04
650 #define KSZ9477_PORT4_PTP_XDLY_REQ_TSH 0x4C08
651 #define KSZ9477_PORT4_PTP_XDLY_REQ_TSL 0x4C0A
652 #define KSZ9477_PORT4_PTP_SYNC_TSH 0x4C0C
653 #define KSZ9477_PORT4_PTP_SYNC_TSL 0x4C0E
654 #define KSZ9477_PORT4_PTP_PDLY_RESP_TSH 0x4C10
655 #define KSZ9477_PORT4_PTP_PDLY_RESP_TSL 0x4C12
656 #define KSZ9477_PORT4_PTP_TS_INT_STAT 0x4C14
657 #define KSZ9477_PORT4_PTP_TS_INT_EN 0x4C16
658 #define KSZ9477_PORT4_PTP_LINK_DELAY 0x4C18
659 #define KSZ9477_PORT5_DEFAULT_TAG0 0x5000
660 #define KSZ9477_PORT5_DEFAULT_TAG1 0x5001
661 #define KSZ9477_PORT5_PME_WOL_EVENT 0x5013
662 #define KSZ9477_PORT5_PME_WOL_EN 0x5017
663 #define KSZ9477_PORT5_INT_STATUS 0x501B
664 #define KSZ9477_PORT5_INT_MASK 0x501F
665 #define KSZ9477_PORT5_OP_CTRL0 0x5020
666 #define KSZ9477_PORT5_STATUS 0x5030
667 #define KSZ9477_PORT5_MAC_CTRL0 0x5400
668 #define KSZ9477_PORT5_MAC_CTRL1 0x5401
669 #define KSZ9477_PORT5_IG_RATE_LIMIT_CTRL 0x5403
670 #define KSZ9477_PORT5_PRIO0_IG_LIMIT_CTRL 0x5410
671 #define KSZ9477_PORT5_PRIO1_IG_LIMIT_CTRL 0x5411
672 #define KSZ9477_PORT5_PRIO2_IG_LIMIT_CTRL 0x5412
673 #define KSZ9477_PORT5_PRIO3_IG_LIMIT_CTRL 0x5413
674 #define KSZ9477_PORT5_PRIO4_IG_LIMIT_CTRL 0x5414
675 #define KSZ9477_PORT5_PRIO5_IG_LIMIT_CTRL 0x5415
676 #define KSZ9477_PORT5_PRIO6_IG_LIMIT_CTRL 0x5416
677 #define KSZ9477_PORT5_PRIO7_IG_LIMIT_CTRL 0x5417
678 #define KSZ9477_PORT5_QUEUE0_EG_LIMIT_CTRL 0x5420
679 #define KSZ9477_PORT5_QUEUE1_EG_LIMIT_CTRL 0x5421
680 #define KSZ9477_PORT5_QUEUE2_EG_LIMIT_CTRL 0x5422
681 #define KSZ9477_PORT5_QUEUE3_EG_LIMIT_CTRL 0x5423
682 #define KSZ9477_PORT5_MIB_CTRL_STAT 0x5500
683 #define KSZ9477_PORT5_MIB_DATA 0x5504
684 #define KSZ9477_PORT5_ACL_ACCESS0 0x5600
685 #define KSZ9477_PORT5_ACL_ACCESS1 0x5601
686 #define KSZ9477_PORT5_ACL_ACCESS2 0x5602
687 #define KSZ9477_PORT5_ACL_ACCESS3 0x5603
688 #define KSZ9477_PORT5_ACL_ACCESS4 0x5604
689 #define KSZ9477_PORT5_ACL_ACCESS5 0x5605
690 #define KSZ9477_PORT5_ACL_ACCESS6 0x5606
691 #define KSZ9477_PORT5_ACL_ACCESS7 0x5607
692 #define KSZ9477_PORT5_ACL_ACCESS8 0x5608
693 #define KSZ9477_PORT5_ACL_ACCESS9 0x5609
694 #define KSZ9477_PORT5_ACL_ACCESS10 0x560A
695 #define KSZ9477_PORT5_ACL_ACCESS11 0x560B
696 #define KSZ9477_PORT5_ACL_ACCESS12 0x560C
697 #define KSZ9477_PORT5_ACL_ACCESS13 0x560D
698 #define KSZ9477_PORT5_ACL_ACCESS14 0x560E
699 #define KSZ9477_PORT5_ACL_ACCESS15 0x560F
700 #define KSZ9477_PORT5_ACL_BYTE_EN_MSB 0x5610
701 #define KSZ9477_PORT5_ACL_BYTE_EN_LSB 0x5611
702 #define KSZ9477_PORT5_ACL_ACCESS_CTRL0 0x5612
703 #define KSZ9477_PORT5_ACL_ACCESS_CTRL1 0x5613
704 #define KSZ9477_PORT5_MIRRORING_CTRL 0x5800
705 #define KSZ9477_PORT5_PRIO_CTRL 0x5801
706 #define KSZ9477_PORT5_IG_MAC_CTRL 0x5802
707 #define KSZ9477_PORT5_AUTH_CTRL 0x5803
708 #define KSZ9477_PORT5_PTR 0x5804
709 #define KSZ9477_PORT5_PRIO_TO_QUEUE_MAPPING 0x5808
710 #define KSZ9477_PORT5_POLICE_CTRL 0x580C
711 #define KSZ9477_PORT5_POLICE_QUEUE_RATE 0x5820
712 #define KSZ9477_PORT5_POLICE_QUEUE_BURST_SIZE 0x5824
713 #define KSZ9477_PORT5_WRED_PKT_MEM_CTRL0 0x5830
714 #define KSZ9477_PORT5_WRED_PKT_MEM_CTRL1 0x5834
715 #define KSZ9477_PORT5_WRED_QUEUE_CTRL0 0x5840
716 #define KSZ9477_PORT5_WRED_QUEUE_CTRL1 0x5844
717 #define KSZ9477_PORT5_WRED_QUEUE_PERF_MON_CTRL 0x5848
718 #define KSZ9477_PORT5_TX_QUEUE_INDEX 0x5900
719 #define KSZ9477_PORT5_TX_QUEUE_PVID 0x5904
720 #define KSZ9477_PORT5_TX_QUEUE_CTRL0 0x5914
721 #define KSZ9477_PORT5_TX_QUEUE_CTRL1 0x5915
722 #define KSZ9477_PORT5_TX_CREDIT_SHAPER_CTRL0 0x5916
723 #define KSZ9477_PORT5_TX_CREDIT_SHAPER_CTRL1 0x5918
724 #define KSZ9477_PORT5_TX_CREDIT_SHAPER_CTRL2 0x591A
725 #define KSZ9477_PORT5_TAS_CTRL 0x5920
726 #define KSZ9477_PORT5_TAS_EVENT_INDEX 0x5923
727 #define KSZ9477_PORT5_TAS_EVENT 0x5924
728 #define KSZ9477_PORT5_CTRL0 0x5A00
729 #define KSZ9477_PORT5_CTRL1 0x5A04
730 #define KSZ9477_PORT5_CTRL2 0x5B00
731 #define KSZ9477_PORT5_MSTP_PTR 0x5B01
732 #define KSZ9477_PORT5_MSTP_STATE 0x5B04
733 #define KSZ9477_PORT5_PTP_RX_LATENCY 0x5C00
734 #define KSZ9477_PORT5_PTP_TX_LATENCY 0x5C02
735 #define KSZ9477_PORT5_PTP_ASYM_CORRECTION 0x5C04
736 #define KSZ9477_PORT5_PTP_XDLY_REQ_TSH 0x5C08
737 #define KSZ9477_PORT5_PTP_XDLY_REQ_TSL 0x5C0A
738 #define KSZ9477_PORT5_PTP_SYNC_TSH 0x5C0C
739 #define KSZ9477_PORT5_PTP_SYNC_TSL 0x5C0E
740 #define KSZ9477_PORT5_PTP_PDLY_RESP_TSH 0x5C10
741 #define KSZ9477_PORT5_PTP_PDLY_RESP_TSL 0x5C12
742 #define KSZ9477_PORT5_PTP_TS_INT_STAT 0x5C14
743 #define KSZ9477_PORT5_PTP_TS_INT_EN 0x5C16
744 #define KSZ9477_PORT5_PTP_LINK_DELAY 0x5C18
745 #define KSZ9477_PORT6_DEFAULT_TAG0 0x6000
746 #define KSZ9477_PORT6_DEFAULT_TAG1 0x6001
747 #define KSZ9477_PORT6_PME_WOL_EVENT 0x6013
748 #define KSZ9477_PORT6_PME_WOL_EN 0x6017
749 #define KSZ9477_PORT6_INT_STATUS 0x601B
750 #define KSZ9477_PORT6_INT_MASK 0x601F
751 #define KSZ9477_PORT6_OP_CTRL0 0x6020
752 #define KSZ9477_PORT6_STATUS 0x6030
753 #define KSZ9477_PORT6_XMII_CTRL0 0x6300
754 #define KSZ9477_PORT6_XMII_CTRL1 0x6301
755 #define KSZ9477_PORT6_MAC_CTRL0 0x6400
756 #define KSZ9477_PORT6_MAC_CTRL1 0x6401
757 #define KSZ9477_PORT6_IG_RATE_LIMIT_CTRL 0x6403
758 #define KSZ9477_PORT6_PRIO0_IG_LIMIT_CTRL 0x6410
759 #define KSZ9477_PORT6_PRIO1_IG_LIMIT_CTRL 0x6411
760 #define KSZ9477_PORT6_PRIO2_IG_LIMIT_CTRL 0x6412
761 #define KSZ9477_PORT6_PRIO3_IG_LIMIT_CTRL 0x6413
762 #define KSZ9477_PORT6_PRIO4_IG_LIMIT_CTRL 0x6414
763 #define KSZ9477_PORT6_PRIO5_IG_LIMIT_CTRL 0x6415
764 #define KSZ9477_PORT6_PRIO6_IG_LIMIT_CTRL 0x6416
765 #define KSZ9477_PORT6_PRIO7_IG_LIMIT_CTRL 0x6417
766 #define KSZ9477_PORT6_QUEUE0_EG_LIMIT_CTRL 0x6420
767 #define KSZ9477_PORT6_QUEUE1_EG_LIMIT_CTRL 0x6421
768 #define KSZ9477_PORT6_QUEUE2_EG_LIMIT_CTRL 0x6422
769 #define KSZ9477_PORT6_QUEUE3_EG_LIMIT_CTRL 0x6423
770 #define KSZ9477_PORT6_MIB_CTRL_STAT 0x6500
771 #define KSZ9477_PORT6_MIB_DATA 0x6504
772 #define KSZ9477_PORT6_ACL_ACCESS0 0x6600
773 #define KSZ9477_PORT6_ACL_ACCESS1 0x6601
774 #define KSZ9477_PORT6_ACL_ACCESS2 0x6602
775 #define KSZ9477_PORT6_ACL_ACCESS3 0x6603
776 #define KSZ9477_PORT6_ACL_ACCESS4 0x6604
777 #define KSZ9477_PORT6_ACL_ACCESS5 0x6605
778 #define KSZ9477_PORT6_ACL_ACCESS6 0x6606
779 #define KSZ9477_PORT6_ACL_ACCESS7 0x6607
780 #define KSZ9477_PORT6_ACL_ACCESS8 0x6608
781 #define KSZ9477_PORT6_ACL_ACCESS9 0x6609
782 #define KSZ9477_PORT6_ACL_ACCESS10 0x660A
783 #define KSZ9477_PORT6_ACL_ACCESS11 0x660B
784 #define KSZ9477_PORT6_ACL_ACCESS12 0x660C
785 #define KSZ9477_PORT6_ACL_ACCESS13 0x660D
786 #define KSZ9477_PORT6_ACL_ACCESS14 0x660E
787 #define KSZ9477_PORT6_ACL_ACCESS15 0x660F
788 #define KSZ9477_PORT6_ACL_BYTE_EN_MSB 0x6610
789 #define KSZ9477_PORT6_ACL_BYTE_EN_LSB 0x6611
790 #define KSZ9477_PORT6_ACL_ACCESS_CTRL0 0x6612
791 #define KSZ9477_PORT6_ACL_ACCESS_CTRL1 0x6613
792 #define KSZ9477_PORT6_MIRRORING_CTRL 0x6800
793 #define KSZ9477_PORT6_PRIO_CTRL 0x6801
794 #define KSZ9477_PORT6_IG_MAC_CTRL 0x6802
795 #define KSZ9477_PORT6_AUTH_CTRL 0x6803
796 #define KSZ9477_PORT6_PTR 0x6804
797 #define KSZ9477_PORT6_PRIO_TO_QUEUE_MAPPING 0x6808
798 #define KSZ9477_PORT6_POLICE_CTRL 0x680C
799 #define KSZ9477_PORT6_POLICE_QUEUE_RATE 0x6820
800 #define KSZ9477_PORT6_POLICE_QUEUE_BURST_SIZE 0x6824
801 #define KSZ9477_PORT6_WRED_PKT_MEM_CTRL0 0x6830
802 #define KSZ9477_PORT6_WRED_PKT_MEM_CTRL1 0x6834
803 #define KSZ9477_PORT6_WRED_QUEUE_CTRL0 0x6840
804 #define KSZ9477_PORT6_WRED_QUEUE_CTRL1 0x6844
805 #define KSZ9477_PORT6_WRED_QUEUE_PERF_MON_CTRL 0x6848
806 #define KSZ9477_PORT6_TX_QUEUE_INDEX 0x6900
807 #define KSZ9477_PORT6_TX_QUEUE_PVID 0x6904
808 #define KSZ9477_PORT6_TX_QUEUE_CTRL0 0x6914
809 #define KSZ9477_PORT6_TX_QUEUE_CTRL1 0x6915
810 #define KSZ9477_PORT6_TX_CREDIT_SHAPER_CTRL0 0x6916
811 #define KSZ9477_PORT6_TX_CREDIT_SHAPER_CTRL1 0x6918
812 #define KSZ9477_PORT6_TX_CREDIT_SHAPER_CTRL2 0x691A
813 #define KSZ9477_PORT6_TAS_CTRL 0x6920
814 #define KSZ9477_PORT6_TAS_EVENT_INDEX 0x6923
815 #define KSZ9477_PORT6_TAS_EVENT 0x6924
816 #define KSZ9477_PORT6_CTRL0 0x6A00
817 #define KSZ9477_PORT6_CTRL1 0x6A04
818 #define KSZ9477_PORT6_CTRL2 0x6B00
819 #define KSZ9477_PORT6_MSTP_PTR 0x6B01
820 #define KSZ9477_PORT6_MSTP_STATE 0x6B04
821 #define KSZ9477_PORT6_PTP_RX_LATENCY 0x6C00
822 #define KSZ9477_PORT6_PTP_TX_LATENCY 0x6C02
823 #define KSZ9477_PORT6_PTP_ASYM_CORRECTION 0x6C04
824 #define KSZ9477_PORT6_PTP_XDLY_REQ_TSH 0x6C08
825 #define KSZ9477_PORT6_PTP_XDLY_REQ_TSL 0x6C0A
826 #define KSZ9477_PORT6_PTP_SYNC_TSH 0x6C0C
827 #define KSZ9477_PORT6_PTP_SYNC_TSL 0x6C0E
828 #define KSZ9477_PORT6_PTP_PDLY_RESP_TSH 0x6C10
829 #define KSZ9477_PORT6_PTP_PDLY_RESP_TSL 0x6C12
830 #define KSZ9477_PORT6_PTP_TS_INT_STAT 0x6C14
831 #define KSZ9477_PORT6_PTP_TS_INT_EN 0x6C16
832 #define KSZ9477_PORT6_PTP_LINK_DELAY 0x6C18
833 #define KSZ9477_PORT7_DEFAULT_TAG0 0x7000
834 #define KSZ9477_PORT7_DEFAULT_TAG1 0x7001
835 #define KSZ9477_PORT7_PME_WOL_EVENT 0x7013
836 #define KSZ9477_PORT7_PME_WOL_EN 0x7017
837 #define KSZ9477_PORT7_INT_STATUS 0x701B
838 #define KSZ9477_PORT7_INT_MASK 0x701F
839 #define KSZ9477_PORT7_OP_CTRL0 0x7020
840 #define KSZ9477_PORT7_STATUS 0x7030
841 #define KSZ9477_PORT7_SGMII_ADDR 0x7200
842 #define KSZ9477_PORT7_SGMII_DATA 0x7206
843 #define KSZ9477_PORT7_XMII_CTRL0 0x7300
844 #define KSZ9477_PORT7_XMII_CTRL1 0x7301
845 #define KSZ9477_PORT7_MAC_CTRL0 0x7400
846 #define KSZ9477_PORT7_MAC_CTRL1 0x7401
847 #define KSZ9477_PORT7_IG_RATE_LIMIT_CTRL 0x7403
848 #define KSZ9477_PORT7_PRIO0_IG_LIMIT_CTRL 0x7410
849 #define KSZ9477_PORT7_PRIO1_IG_LIMIT_CTRL 0x7411
850 #define KSZ9477_PORT7_PRIO2_IG_LIMIT_CTRL 0x7412
851 #define KSZ9477_PORT7_PRIO3_IG_LIMIT_CTRL 0x7413
852 #define KSZ9477_PORT7_PRIO4_IG_LIMIT_CTRL 0x7414
853 #define KSZ9477_PORT7_PRIO5_IG_LIMIT_CTRL 0x7415
854 #define KSZ9477_PORT7_PRIO6_IG_LIMIT_CTRL 0x7416
855 #define KSZ9477_PORT7_PRIO7_IG_LIMIT_CTRL 0x7417
856 #define KSZ9477_PORT7_QUEUE0_EG_LIMIT_CTRL 0x7420
857 #define KSZ9477_PORT7_QUEUE1_EG_LIMIT_CTRL 0x7421
858 #define KSZ9477_PORT7_QUEUE2_EG_LIMIT_CTRL 0x7422
859 #define KSZ9477_PORT7_QUEUE3_EG_LIMIT_CTRL 0x7423
860 #define KSZ9477_PORT7_MIB_CTRL_STAT 0x7500
861 #define KSZ9477_PORT7_MIB_DATA 0x7504
862 #define KSZ9477_PORT7_ACL_ACCESS0 0x7600
863 #define KSZ9477_PORT7_ACL_ACCESS1 0x7601
864 #define KSZ9477_PORT7_ACL_ACCESS2 0x7602
865 #define KSZ9477_PORT7_ACL_ACCESS3 0x7603
866 #define KSZ9477_PORT7_ACL_ACCESS4 0x7604
867 #define KSZ9477_PORT7_ACL_ACCESS5 0x7605
868 #define KSZ9477_PORT7_ACL_ACCESS6 0x7606
869 #define KSZ9477_PORT7_ACL_ACCESS7 0x7607
870 #define KSZ9477_PORT7_ACL_ACCESS8 0x7608
871 #define KSZ9477_PORT7_ACL_ACCESS9 0x7609
872 #define KSZ9477_PORT7_ACL_ACCESS10 0x760A
873 #define KSZ9477_PORT7_ACL_ACCESS11 0x760B
874 #define KSZ9477_PORT7_ACL_ACCESS12 0x760C
875 #define KSZ9477_PORT7_ACL_ACCESS13 0x760D
876 #define KSZ9477_PORT7_ACL_ACCESS14 0x760E
877 #define KSZ9477_PORT7_ACL_ACCESS15 0x760F
878 #define KSZ9477_PORT7_ACL_BYTE_EN_MSB 0x7610
879 #define KSZ9477_PORT7_ACL_BYTE_EN_LSB 0x7611
880 #define KSZ9477_PORT7_ACL_ACCESS_CTRL0 0x7612
881 #define KSZ9477_PORT7_ACL_ACCESS_CTRL1 0x7613
882 #define KSZ9477_PORT7_MIRRORING_CTRL 0x7800
883 #define KSZ9477_PORT7_PRIO_CTRL 0x7801
884 #define KSZ9477_PORT7_IG_MAC_CTRL 0x7802
885 #define KSZ9477_PORT7_AUTH_CTRL 0x7803
886 #define KSZ9477_PORT7_PTR 0x7804
887 #define KSZ9477_PORT7_PRIO_TO_QUEUE_MAPPING 0x7808
888 #define KSZ9477_PORT7_POLICE_CTRL 0x780C
889 #define KSZ9477_PORT7_POLICE_QUEUE_RATE 0x7820
890 #define KSZ9477_PORT7_POLICE_QUEUE_BURST_SIZE 0x7824
891 #define KSZ9477_PORT7_WRED_PKT_MEM_CTRL0 0x7830
892 #define KSZ9477_PORT7_WRED_PKT_MEM_CTRL1 0x7834
893 #define KSZ9477_PORT7_WRED_QUEUE_CTRL0 0x7840
894 #define KSZ9477_PORT7_WRED_QUEUE_CTRL1 0x7844
895 #define KSZ9477_PORT7_WRED_QUEUE_PERF_MON_CTRL 0x7848
896 #define KSZ9477_PORT7_TX_QUEUE_INDEX 0x7900
897 #define KSZ9477_PORT7_TX_QUEUE_PVID 0x7904
898 #define KSZ9477_PORT7_TX_QUEUE_CTRL0 0x7914
899 #define KSZ9477_PORT7_TX_QUEUE_CTRL1 0x7915
900 #define KSZ9477_PORT7_TX_CREDIT_SHAPER_CTRL0 0x7916
901 #define KSZ9477_PORT7_TX_CREDIT_SHAPER_CTRL1 0x7918
902 #define KSZ9477_PORT7_TX_CREDIT_SHAPER_CTRL2 0x791A
903 #define KSZ9477_PORT7_TAS_CTRL 0x7920
904 #define KSZ9477_PORT7_TAS_EVENT_INDEX 0x7923
905 #define KSZ9477_PORT7_TAS_EVENT 0x7924
906 #define KSZ9477_PORT7_CTRL0 0x7A00
907 #define KSZ9477_PORT7_CTRL1 0x7A04
908 #define KSZ9477_PORT7_CTRL2 0x7B00
909 #define KSZ9477_PORT7_MSTP_PTR 0x7B01
910 #define KSZ9477_PORT7_MSTP_STATE 0x7B04
911 #define KSZ9477_PORT7_PTP_RX_LATENCY 0x7C00
912 #define KSZ9477_PORT7_PTP_TX_LATENCY 0x7C02
913 #define KSZ9477_PORT7_PTP_ASYM_CORRECTION 0x7C04
914 #define KSZ9477_PORT7_PTP_XDLY_REQ_TSH 0x7C08
915 #define KSZ9477_PORT7_PTP_XDLY_REQ_TSL 0x7C0A
916 #define KSZ9477_PORT7_PTP_SYNC_TSH 0x7C0C
917 #define KSZ9477_PORT7_PTP_SYNC_TSL 0x7C0E
918 #define KSZ9477_PORT7_PTP_PDLY_RESP_TSH 0x7C10
919 #define KSZ9477_PORT7_PTP_PDLY_RESP_TSL 0x7C12
920 #define KSZ9477_PORT7_PTP_TS_INT_STAT 0x7C14
921 #define KSZ9477_PORT7_PTP_TS_INT_EN 0x7C16
922 #define KSZ9477_PORT7_PTP_LINK_DELAY 0x7C18
923 
924 //KSZ9477 Switch register access macros
925 #define KSZ9477_PORTn_DEFAULT_TAG0(port) (0x0000 + ((port) * 0x1000))
926 #define KSZ9477_PORTn_DEFAULT_TAG1(port) (0x0001 + ((port) * 0x1000))
927 #define KSZ9477_PORTn_PME_WOL_EVENT(port) (0x0013 + ((port) * 0x1000))
928 #define KSZ9477_PORTn_PME_WOL_EN(port) (0x0017 + ((port) * 0x1000))
929 #define KSZ9477_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
930 #define KSZ9477_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
931 #define KSZ9477_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
932 #define KSZ9477_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
933 #define KSZ9477_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
934 #define KSZ9477_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
935 #define KSZ9477_PORTn_MAC_CTRL0(port) (0x0400 + ((port) * 0x1000))
936 #define KSZ9477_PORTn_MAC_CTRL1(port) (0x0401 + ((port) * 0x1000))
937 #define KSZ9477_PORTn_IG_RATE_LIMIT_CTRL(port) (0x0403 + ((port) * 0x1000))
938 #define KSZ9477_PORTn_PRIO0_IG_LIMIT_CTRL(port) (0x0410 + ((port) * 0x1000))
939 #define KSZ9477_PORTn_PRIO1_IG_LIMIT_CTRL(port) (0x0411 + ((port) * 0x1000))
940 #define KSZ9477_PORTn_PRIO2_IG_LIMIT_CTRL(port) (0x0412 + ((port) * 0x1000))
941 #define KSZ9477_PORTn_PRIO3_IG_LIMIT_CTRL(port) (0x0413 + ((port) * 0x1000))
942 #define KSZ9477_PORTn_PRIO4_IG_LIMIT_CTRL(port) (0x0414 + ((port) * 0x1000))
943 #define KSZ9477_PORTn_PRIO5_IG_LIMIT_CTRL(port) (0x0415 + ((port) * 0x1000))
944 #define KSZ9477_PORTn_PRIO6_IG_LIMIT_CTRL(port) (0x0416 + ((port) * 0x1000))
945 #define KSZ9477_PORTn_PRIO7_IG_LIMIT_CTRL(port) (0x0417 + ((port) * 0x1000))
946 #define KSZ9477_PORTn_QUEUE0_EG_LIMIT_CTRL(port) (0x0420 + ((port) * 0x1000))
947 #define KSZ9477_PORTn_QUEUE1_EG_LIMIT_CTRL(port) (0x0421 + ((port) * 0x1000))
948 #define KSZ9477_PORTn_QUEUE2_EG_LIMIT_CTRL(port) (0x0422 + ((port) * 0x1000))
949 #define KSZ9477_PORTn_QUEUE3_EG_LIMIT_CTRL(port) (0x0423 + ((port) * 0x1000))
950 #define KSZ9477_PORTn_MIB_CTRL_STAT(port) (0x0500 + ((port) * 0x1000))
951 #define KSZ9477_PORTn_MIB_DATA(port) (0x0504 + ((port) * 0x1000))
952 #define KSZ9477_PORTn_ACL_ACCESS0(port) (0x0600 + ((port) * 0x1000))
953 #define KSZ9477_PORTn_ACL_ACCESS1(port) (0x0601 + ((port) * 0x1000))
954 #define KSZ9477_PORTn_ACL_ACCESS2(port) (0x0602 + ((port) * 0x1000))
955 #define KSZ9477_PORTn_ACL_ACCESS3(port) (0x0603 + ((port) * 0x1000))
956 #define KSZ9477_PORTn_ACL_ACCESS4(port) (0x0604 + ((port) * 0x1000))
957 #define KSZ9477_PORTn_ACL_ACCESS5(port) (0x0605 + ((port) * 0x1000))
958 #define KSZ9477_PORTn_ACL_ACCESS6(port) (0x0606 + ((port) * 0x1000))
959 #define KSZ9477_PORTn_ACL_ACCESS7(port) (0x0607 + ((port) * 0x1000))
960 #define KSZ9477_PORTn_ACL_ACCESS8(port) (0x0608 + ((port) * 0x1000))
961 #define KSZ9477_PORTn_ACL_ACCESS9(port) (0x0609 + ((port) * 0x1000))
962 #define KSZ9477_PORTn_ACL_ACCESS10(port) (0x060A + ((port) * 0x1000))
963 #define KSZ9477_PORTn_ACL_ACCESS11(port) (0x060B + ((port) * 0x1000))
964 #define KSZ9477_PORTn_ACL_ACCESS12(port) (0x060C + ((port) * 0x1000))
965 #define KSZ9477_PORTn_ACL_ACCESS13(port) (0x060D + ((port) * 0x1000))
966 #define KSZ9477_PORTn_ACL_ACCESS14(port) (0x060E + ((port) * 0x1000))
967 #define KSZ9477_PORTn_ACL_ACCESS15(port) (0x060F + ((port) * 0x1000))
968 #define KSZ9477_PORTn_ACL_BYTE_EN_MSB(port) (0x0610 + ((port) * 0x1000))
969 #define KSZ9477_PORTn_ACL_BYTE_EN_LSB(port) (0x0611 + ((port) * 0x1000))
970 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0(port) (0x0612 + ((port) * 0x1000))
971 #define KSZ9477_PORTn_ACL_ACCESS_CTRL1(port) (0x0613 + ((port) * 0x1000))
972 #define KSZ9477_PORTn_MIRRORING_CTRL(port) (0x0800 + ((port) * 0x1000))
973 #define KSZ9477_PORTn_PRIO_CTRL(port) (0x0801 + ((port) * 0x1000))
974 #define KSZ9477_PORTn_IG_MAC_CTRL(port) (0x0802 + ((port) * 0x1000))
975 #define KSZ9477_PORTn_AUTH_CTRL(port) (0x0803 + ((port) * 0x1000))
976 #define KSZ9477_PORTn_PTR(port) (0x0804 + ((port) * 0x1000))
977 #define KSZ9477_PORTn_PRIO_TO_QUEUE_MAPPING(port) (0x0808 + ((port) * 0x1000))
978 #define KSZ9477_PORTn_POLICE_CTRL(port) (0x080C + ((port) * 0x1000))
979 #define KSZ9477_PORTn_POLICE_QUEUE_RATE(port) (0x0820 + ((port) * 0x1000))
980 #define KSZ9477_PORTn_POLICE_QUEUE_BURST_SIZE(port) (0x0824 + ((port) * 0x1000))
981 #define KSZ9477_PORTn_WRED_PKT_MEM_CTRL0(port) (0x0830 + ((port) * 0x1000))
982 #define KSZ9477_PORTn_WRED_PKT_MEM_CTRL1(port) (0x0834 + ((port) * 0x1000))
983 #define KSZ9477_PORTn_WRED_QUEUE_CTRL0(port) (0x0840 + ((port) * 0x1000))
984 #define KSZ9477_PORTn_WRED_QUEUE_CTRL1(port) (0x0844 + ((port) * 0x1000))
985 #define KSZ9477_PORTn_WRED_QUEUE_PERF_MON_CTRL(port) (0x0848 + ((port) * 0x1000))
986 #define KSZ9477_PORTn_TX_QUEUE_INDEX(port) (0x0900 + ((port) * 0x1000))
987 #define KSZ9477_PORTn_TX_QUEUE_PVID(port) (0x0904 + ((port) * 0x1000))
988 #define KSZ9477_PORTn_TX_QUEUE_CTRL0(port) (0x0914 + ((port) * 0x1000))
989 #define KSZ9477_PORTn_TX_QUEUE_CTRL1(port) (0x0915 + ((port) * 0x1000))
990 #define KSZ9477_PORTn_TX_CREDIT_SHAPER_CTRL0(port) (0x0916 + ((port) * 0x1000))
991 #define KSZ9477_PORTn_TX_CREDIT_SHAPER_CTRL1(port) (0x0918 + ((port) * 0x1000))
992 #define KSZ9477_PORTn_TX_CREDIT_SHAPER_CTRL2(port) (0x091A + ((port) * 0x1000))
993 #define KSZ9477_PORTn_TAS_CTRL(port) (0x0920 + ((port) * 0x1000))
994 #define KSZ9477_PORTn_TAS_EVENT_INDEX(port) (0x0923 + ((port) * 0x1000))
995 #define KSZ9477_PORTn_TAS_EVENT(port) (0x0924 + ((port) * 0x1000))
996 #define KSZ9477_PORTn_CTRL0(port) (0x0A00 + ((port) * 0x1000))
997 #define KSZ9477_PORTn_CTRL1(port) (0x0A04 + ((port) * 0x1000))
998 #define KSZ9477_PORTn_CTRL2(port) (0x0B00 + ((port) * 0x1000))
999 #define KSZ9477_PORTn_MSTP_PTR(port) (0x0B01 + ((port) * 0x1000))
1000 #define KSZ9477_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
1001 #define KSZ9477_PORTn_PTP_RX_LATENCY(port) (0x0C00 + ((port) * 0x1000))
1002 #define KSZ9477_PORTn_PTP_TX_LATENCY(port) (0x0C02 + ((port) * 0x1000))
1003 #define KSZ9477_PORTn_PTP_ASYM_CORRECTION(port) (0x0C04 + ((port) * 0x1000))
1004 #define KSZ9477_PORTn_PTP_XDLY_REQ_TSH(port) (0x0C08 + ((port) * 0x1000))
1005 #define KSZ9477_PORTn_PTP_XDLY_REQ_TSL(port) (0x0C0A + ((port) * 0x1000))
1006 #define KSZ9477_PORTn_PTP_SYNC_TSH(port) (0x0C0C + ((port) * 0x1000))
1007 #define KSZ9477_PORTn_PTP_SYNC_TSL(port) (0x0C0E + ((port) * 0x1000))
1008 #define KSZ9477_PORTn_PTP_PDLY_RESP_TSH(port) (0x0C10 + ((port) * 0x1000))
1009 #define KSZ9477_PORTn_PTP_PDLY_RESP_TSL(port) (0x0C12 + ((port) * 0x1000))
1010 #define KSZ9477_PORTn_PTP_TS_INT_STAT(port) (0x0C14 + ((port) * 0x1000))
1011 #define KSZ9477_PORTn_PTP_TS_INT_EN(port) (0x0C16 + ((port) * 0x1000))
1012 #define KSZ9477_PORTn_PTP_LINK_DELAY(port) (0x0C18 + ((port) * 0x1000))
1013 #define KSZ9477_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
1014 
1015 //PHY Basic Control register
1016 #define KSZ9477_BMCR_RESET 0x8000
1017 #define KSZ9477_BMCR_LOOPBACK 0x4000
1018 #define KSZ9477_BMCR_SPEED_SEL_LSB 0x2000
1019 #define KSZ9477_BMCR_AN_EN 0x1000
1020 #define KSZ9477_BMCR_POWER_DOWN 0x0800
1021 #define KSZ9477_BMCR_ISOLATE 0x0400
1022 #define KSZ9477_BMCR_RESTART_AN 0x0200
1023 #define KSZ9477_BMCR_DUPLEX_MODE 0x0100
1024 #define KSZ9477_BMCR_COL_TEST 0x0080
1025 #define KSZ9477_BMCR_SPEED_SEL_MSB 0x0040
1026 
1027 //PHY Basic Status register
1028 #define KSZ9477_BMSR_100BT4 0x8000
1029 #define KSZ9477_BMSR_100BTX_FD 0x4000
1030 #define KSZ9477_BMSR_100BTX_HD 0x2000
1031 #define KSZ9477_BMSR_10BT_FD 0x1000
1032 #define KSZ9477_BMSR_10BT_HD 0x0800
1033 #define KSZ9477_BMSR_EXTENDED_STATUS 0x0100
1034 #define KSZ9477_BMSR_MF_PREAMBLE_SUPPR 0x0040
1035 #define KSZ9477_BMSR_AN_COMPLETE 0x0020
1036 #define KSZ9477_BMSR_REMOTE_FAULT 0x0010
1037 #define KSZ9477_BMSR_AN_CAPABLE 0x0008
1038 #define KSZ9477_BMSR_LINK_STATUS 0x0004
1039 #define KSZ9477_BMSR_JABBER_DETECT 0x0002
1040 #define KSZ9477_BMSR_EXTENDED_CAPABLE 0x0001
1041 
1042 //PHY ID High register
1043 #define KSZ9477_PHYID1_DEFAULT 0x0022
1044 
1045 //PHY ID Low register
1046 #define KSZ9477_PHYID2_DEFAULT 0x1631
1047 
1048 //PHY Auto-Negotiation Advertisement register
1049 #define KSZ9477_ANAR_NEXT_PAGE 0x8000
1050 #define KSZ9477_ANAR_REMOTE_FAULT 0x2000
1051 #define KSZ9477_ANAR_PAUSE 0x0C00
1052 #define KSZ9477_ANAR_100BT4 0x0200
1053 #define KSZ9477_ANAR_100BTX_FD 0x0100
1054 #define KSZ9477_ANAR_100BTX_HD 0x0080
1055 #define KSZ9477_ANAR_10BT_FD 0x0040
1056 #define KSZ9477_ANAR_10BT_HD 0x0020
1057 #define KSZ9477_ANAR_SELECTOR 0x001F
1058 #define KSZ9477_ANAR_SELECTOR_DEFAULT 0x0001
1059 
1060 //PHY Auto-Negotiation Link Partner Ability register
1061 #define KSZ9477_ANLPAR_NEXT_PAGE 0x8000
1062 #define KSZ9477_ANLPAR_ACK 0x4000
1063 #define KSZ9477_ANLPAR_REMOTE_FAULT 0x2000
1064 #define KSZ9477_ANLPAR_PAUSE 0x0C00
1065 #define KSZ9477_ANLPAR_100BT4 0x0200
1066 #define KSZ9477_ANLPAR_100BTX_FD 0x0100
1067 #define KSZ9477_ANLPAR_100BTX_HD 0x0080
1068 #define KSZ9477_ANLPAR_10BT_FD 0x0040
1069 #define KSZ9477_ANLPAR_10BT_HD 0x0020
1070 #define KSZ9477_ANLPAR_SELECTOR 0x001F
1071 #define KSZ9477_ANLPAR_SELECTOR_DEFAULT 0x0001
1072 
1073 //PHY Auto-Negotiation Expansion Status register
1074 #define KSZ9477_ANER_PAR_DETECT_FAULT 0x0010
1075 #define KSZ9477_ANER_LP_NEXT_PAGE_ABLE 0x0008
1076 #define KSZ9477_ANER_NEXT_PAGE_ABLE 0x0004
1077 #define KSZ9477_ANER_PAGE_RECEIVED 0x0002
1078 #define KSZ9477_ANER_LP_AN_ABLE 0x0001
1079 
1080 //PHY Auto-Negotiation Next Page register
1081 #define KSZ9477_ANNPR_NEXT_PAGE 0x8000
1082 #define KSZ9477_ANNPR_MSG_PAGE 0x2000
1083 #define KSZ9477_ANNPR_ACK2 0x1000
1084 #define KSZ9477_ANNPR_TOGGLE 0x0800
1085 #define KSZ9477_ANNPR_MESSAGE 0x07FF
1086 
1087 //PHY Auto-Negotiation Link Partner Next Page Ability register
1088 #define KSZ9477_ANLPNPR_NEXT_PAGE 0x8000
1089 #define KSZ9477_ANLPNPR_ACK 0x4000
1090 #define KSZ9477_ANLPNPR_MSG_PAGE 0x2000
1091 #define KSZ9477_ANLPNPR_ACK2 0x1000
1092 #define KSZ9477_ANLPNPR_TOGGLE 0x0800
1093 #define KSZ9477_ANLPNPR_MESSAGE 0x07FF
1094 
1095 //PHY 1000BASE-T Control register
1096 #define KSZ9477_GBCR_TEST_MODE 0xE000
1097 #define KSZ9477_GBCR_MS_MAN_CONF_EN 0x1000
1098 #define KSZ9477_GBCR_MS_MAN_CONF_VAL 0x0800
1099 #define KSZ9477_GBCR_PORT_TYPE 0x0400
1100 #define KSZ9477_GBCR_1000BT_FD 0x0200
1101 #define KSZ9477_GBCR_1000BT_HD 0x0100
1102 
1103 //PHY 1000BASE-T Status register
1104 #define KSZ9477_GBSR_MS_CONF_FAULT 0x8000
1105 #define KSZ9477_GBSR_MS_CONF_RES 0x4000
1106 #define KSZ9477_GBSR_LOCAL_RECEIVER_STATUS 0x2000
1107 #define KSZ9477_GBSR_REMOTE_RECEIVER_STATUS 0x1000
1108 #define KSZ9477_GBSR_LP_1000BT_FD 0x0800
1109 #define KSZ9477_GBSR_LP_1000BT_HD 0x0400
1110 #define KSZ9477_GBSR_IDLE_ERR_COUNT 0x00FF
1111 
1112 //PHY MMD Setup register
1113 #define KSZ9477_MMDACR_FUNC 0xC000
1114 #define KSZ9477_MMDACR_FUNC_ADDR 0x0000
1115 #define KSZ9477_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
1116 #define KSZ9477_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
1117 #define KSZ9477_MMDACR_FUNC_DATA_POST_INC_W 0xC000
1118 #define KSZ9477_MMDACR_DEVAD 0x001F
1119 
1120 //PHY Extended Status register
1121 #define KSZ9477_GBESR_1000BX_FD 0x8000
1122 #define KSZ9477_GBESR_1000BX_HD 0x4000
1123 #define KSZ9477_GBESR_1000BT_FD 0x2000
1124 #define KSZ9477_GBESR_1000BT_HD 0x1000
1125 
1126 //PHY Remote Loopback register
1127 #define KSZ9477_RLB_REMOTE_LOOPBACK 0x0100
1128 
1129 //PHY LinkMD register
1130 #define KSZ9477_LINKMD_TEST_EN 0x8000
1131 #define KSZ9477_LINKMD_PAIR 0x3000
1132 #define KSZ9477_LINKMD_PAIR_A 0x0000
1133 #define KSZ9477_LINKMD_PAIR_B 0x1000
1134 #define KSZ9477_LINKMD_PAIR_C 0x2000
1135 #define KSZ9477_LINKMD_PAIR_D 0x3000
1136 #define KSZ9477_LINKMD_STATUS 0x0300
1137 #define KSZ9477_LINKMD_STATUS_NORMAL 0x0000
1138 #define KSZ9477_LINKMD_STATUS_OPEN 0x0100
1139 #define KSZ9477_LINKMD_STATUS_SHORT 0x0200
1140 #define KSZ9477_LINKMD_RESULT 0x00FF
1141 
1142 //PHY Digital PMA/PCS Status register
1143 #define KSZ9477_DPMAPCSS_1000BT_LINK_STATUS 0x0002
1144 #define KSZ9477_DPMAPCSS_100BTX_LINK_STATUS 0x0001
1145 
1146 //Port Interrupt Control/Status register
1147 #define KSZ9477_ICSR_JABBER_IE 0x8000
1148 #define KSZ9477_ICSR_RECEIVE_ERROR_IE 0x4000
1149 #define KSZ9477_ICSR_PAGE_RECEIVED_IE 0x2000
1150 #define KSZ9477_ICSR_PAR_DETECT_FAULT_IE 0x1000
1151 #define KSZ9477_ICSR_LP_ACK_IE 0x0800
1152 #define KSZ9477_ICSR_LINK_DOWN_IE 0x0400
1153 #define KSZ9477_ICSR_REMOTE_FAULT_IE 0x0200
1154 #define KSZ9477_ICSR_LINK_UP_IE 0x0100
1155 #define KSZ9477_ICSR_JABBER_IF 0x0080
1156 #define KSZ9477_ICSR_RECEIVE_ERROR_IF 0x0040
1157 #define KSZ9477_ICSR_PAGE_RECEIVED_IF 0x0020
1158 #define KSZ9477_ICSR_PAR_DETECT_FAULT_IF 0x0010
1159 #define KSZ9477_ICSR_LP_ACK_IF 0x0008
1160 #define KSZ9477_ICSR_LINK_DOWN_IF 0x0004
1161 #define KSZ9477_ICSR_REMOTE_FAULT_IF 0x0002
1162 #define KSZ9477_ICSR_LINK_UP_IF 0x0001
1163 
1164 //PHY Auto MDI/MDI-X register
1165 #define KSZ9477_AUTOMDI_MDI_SET 0x0080
1166 #define KSZ9477_AUTOMDI_SWAP_OFF 0x0040
1167 
1168 //PHY Control register
1169 #define KSZ9477_PHYCON_JABBER_EN 0x0200
1170 #define KSZ9477_PHYCON_SPEED_1000BT 0x0040
1171 #define KSZ9477_PHYCON_SPEED_100BTX 0x0020
1172 #define KSZ9477_PHYCON_SPEED_10BT 0x0010
1173 #define KSZ9477_PHYCON_DUPLEX_STATUS 0x0008
1174 #define KSZ9477_PHYCON_1000BT_MS_STATUS 0x0004
1175 
1176 //MMD Signal Quality Channel A register
1177 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_A_QUALITY_INDICATOR 0x7F00
1178 
1179 //MMD Signal Quality Channel B register
1180 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_B_QUALITY_INDICATOR 0x7F00
1181 
1182 //MMD Signal Quality Channel C register
1183 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_C_QUALITY_INDICATOR 0x7F00
1184 
1185 //MMD Signal Quality Channel D register
1186 #define KSZ9477_MMD_SIGNAL_QUALITY_CH_D_QUALITY_INDICATOR 0x7F00
1187 
1188 //MMD LED Mode register
1189 #define KSZ9477_MMD_LED_MODE_LED_MODE 0x0010
1190 #define KSZ9477_MMD_LED_MODE_LED_MODE_TRI_COLOR_DUAL 0x0000
1191 #define KSZ9477_MMD_LED_MODE_LED_MODE_SINGLE 0x0010
1192 #define KSZ9477_MMD_LED_MODE_RESERVED 0x000F
1193 #define KSZ9477_MMD_LED_MODE_RESERVED_DEFAULT 0x0001
1194 
1195 //MMD EEE Advertisement register
1196 #define KSZ9477_MMD_EEE_ADV_1000BT_EEE_EN 0x0004
1197 #define KSZ9477_MMD_EEE_ADV_100BT_EEE_EN 0x0002
1198 
1199 //Global Chip ID 0 register
1200 #define KSZ9477_CHIP_ID0_DEFAULT 0x00
1201 
1202 //Global Chip ID 1 register
1203 #define KSZ9477_CHIP_ID1_DEFAULT 0x94
1204 
1205 //Global Chip ID 2 register
1206 #define KSZ9477_CHIP_ID2_DEFAULT 0x77
1207 
1208 //Global Chip ID 3 register
1209 #define KSZ9477_CHIP_ID3_REVISION_ID 0xF0
1210 #define KSZ9477_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
1211 
1212 //PME Pin Control register
1213 #define KSZ9477_PME_PIN_CTRL_PME_PIN_OUT_EN 0x02
1214 #define KSZ9477_PME_PIN_CTRL_PME_PIN_OUT_POL 0x01
1215 
1216 //Global Interrupt Status register
1217 #define KSZ9477_GLOBAL_INT_STAT_LUE 0x80000000
1218 #define KSZ9477_GLOBAL_INT_STAT_GPIO_TRIG_TS_UNIT 0x40000000
1219 
1220 //Global Interrupt Mask register
1221 #define KSZ9477_GLOBAL_INT_MASK_LUE 0x80000000
1222 #define KSZ9477_GLOBAL_INT_MASK_GPIO_TRIG_TS_UNIT 0x40000000
1223 
1224 //Global Port Interrupt Status register
1225 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT7 0x00000040
1226 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT6 0x00000020
1227 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT5 0x00000010
1228 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT4 0x00000008
1229 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT3 0x00000004
1230 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT2 0x00000002
1231 #define KSZ9477_GLOBAL_PORT_INT_STAT_PORT1 0x00000001
1232 
1233 //Global Port Interrupt Mask register
1234 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT7 0x00000040
1235 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT6 0x00000020
1236 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT5 0x00000010
1237 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT4 0x00000008
1238 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT3 0x00000004
1239 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT2 0x00000002
1240 #define KSZ9477_GLOBAL_PORT_INT_MASK_PORT1 0x00000001
1241 
1242 //Serial I/O Control register
1243 #define KSZ9477_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPR 0x04
1244 #define KSZ9477_SERIAL_IO_CTRL_AUTO_SPI_DATA_OUT_EDGE_SEL 0x02
1245 #define KSZ9477_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL 0x01
1246 #define KSZ9477_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_FALLING 0x00
1247 #define KSZ9477_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_RISING 0x01
1248 
1249 //Output Clock Control register
1250 #define KSZ9477_OUT_CLK_CTRL_REC_CLK_RDY 0x80
1251 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC 0x1C
1252 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_XI 0x00
1253 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_PORT1 0x04
1254 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_PORT2 0x08
1255 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_PORT3 0x0C
1256 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_PORT4 0x10
1257 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_SRC_PORT5 0x14
1258 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_EN 0x02
1259 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_FREQ 0x01
1260 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_FREQ_25MHZ 0x00
1261 #define KSZ9477_OUT_CLK_CTRL_SYNCLKO_FREQ_125MHZ 0x01
1262 
1263 //In-Band Management Control register
1264 #define KSZ9477_IBA_CTRL_IBA_EN 0x80000000
1265 #define KSZ9477_IBA_CTRL_DEST_MAC_ADDR_MATCH_EN 0x40000000
1266 #define KSZ9477_IBA_CTRL_IBA_RESET 0x20000000
1267 #define KSZ9477_IBA_CTRL_RESP_PRIO_QUEUE 0x00C00000
1268 #define KSZ9477_IBA_CTRL_RESP_PRIO_QUEUE_DEFAULT 0x00400000
1269 #define KSZ9477_IBA_CTRL_IBA_COMM 0x00070000
1270 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT1 0x00000000
1271 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT2 0x00010000
1272 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT3 0x00020000
1273 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT4 0x00030000
1274 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT5 0x00040000
1275 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT6 0x00050000
1276 #define KSZ9477_IBA_CTRL_IBA_COMM_PORT7 0x00060000
1277 #define KSZ9477_IBA_CTRL_TPID 0x0000FFFF
1278 #define KSZ9477_IBA_CTRL_TPID_DEFAULT 0x000040FE
1279 
1280 //I/O Drive Strength register
1281 #define KSZ9477_IO_DRIVE_STRENGTH_HIGH_SPEED_DRIVE_STRENGTH 0x70
1282 #define KSZ9477_IO_DRIVE_STRENGTH_LOW_SPEED_DRIVE_STRENGTH 0x07
1283 
1284 //In-Band Management Operation Status 1 register
1285 #define KSZ9477_IBA_OP_STAT1_GOOD_PKT_DETECT 0x80000000
1286 #define KSZ9477_IBA_OP_STAT1_RESP_PKT_TX_DONE 0x40000000
1287 #define KSZ9477_IBA_OP_STAT1_EXEC_DONE 0x20000000
1288 #define KSZ9477_IBA_OP_STAT1_MAC_ADDR_MISMATCH_ERR 0x00004000
1289 #define KSZ9477_IBA_OP_STAT1_ACCESS_FORMAT_ERR 0x00002000
1290 #define KSZ9477_IBA_OP_STAT1_ACCESS_CODE_ERR 0x00001000
1291 #define KSZ9477_IBA_OP_STAT1_ACCESS_CMD_ERR 0x00000800
1292 #define KSZ9477_IBA_OP_STAT1_OVERSIZE_PKT_ERR 0x00000400
1293 #define KSZ9477_IBA_OP_STAT1_ACCESS_CODE_ERR_LOC 0x0000007F
1294 
1295 //LED Override register
1296 #define KSZ9477_LED_OVERRIDE_OVERRIDE 0x000003FF
1297 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED1_0 0x00000001
1298 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED1_1 0x00000002
1299 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED2_0 0x00000004
1300 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED2_1 0x00000008
1301 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED3_0 0x00000010
1302 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED3_1 0x00000020
1303 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED4_0 0x00000040
1304 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED4_1 0x00000080
1305 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED5_0 0x00000100
1306 #define KSZ9477_LED_OVERRIDE_OVERRIDE_LED5_1 0x00000200
1307 
1308 //LED Output register
1309 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL 0x000003FF
1310 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED1_0 0x00000001
1311 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED1_1 0x00000002
1312 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED2_0 0x00000004
1313 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED2_1 0x00000008
1314 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED3_0 0x00000010
1315 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED3_1 0x00000020
1316 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED4_0 0x00000040
1317 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED4_1 0x00000080
1318 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED5_0 0x00000100
1319 #define KSZ9477_LED_OUTPUT_GPIO_OUT_CTRL_LED5_1 0x00000200
1320 
1321 //LED2_0/LED2_1 Source register
1322 #define KSZ9477_LED2_0_LED2_1_SRC_LED2_1_SRC 0x00000008
1323 #define KSZ9477_LED2_0_LED2_1_SRC_LED2_0_SRC 0x00000004
1324 
1325 //Power Down Control 0 register
1326 #define KSZ9477_PWR_DOWN_CTRL0_PLL_PWR_DOWN 0x20
1327 #define KSZ9477_PWR_DOWN_CTRL0_PWR_MGMT_MODE 0x18
1328 #define KSZ9477_PWR_DOWN_CTRL0_PWR_MGMT_MODE_NORMAL 0x00
1329 #define KSZ9477_PWR_DOWN_CTRL0_PWR_MGMT_MODE_EDPD 0x08
1330 #define KSZ9477_PWR_DOWN_CTRL0_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
1331 
1332 //LED Strap-In register
1333 #define KSZ9477_LED_STRAP_IN_STRAP_IN 0x000003FF
1334 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED1_0 0x00000001
1335 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED1_1 0x00000002
1336 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED2_0 0x00000004
1337 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED2_1 0x00000008
1338 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED3_0 0x00000010
1339 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED3_1 0x00000020
1340 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED4_0 0x00000040
1341 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED4_1 0x00000080
1342 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED5_0 0x00000100
1343 #define KSZ9477_LED_STRAP_IN_STRAP_IN_LED5_1 0x00000200
1344 
1345 //Switch Operation register
1346 #define KSZ9477_SWITCH_OP_DOUBLE_TAG_EN 0x80
1347 #define KSZ9477_SWITCH_OP_SOFT_HARD_RESET 0x02
1348 #define KSZ9477_SWITCH_OP_START_SWITCH 0x01
1349 
1350 //Switch Maximum Transmit Unit register
1351 #define KSZ9477_SWITCH_MTU_MTU 0x3FFF
1352 #define KSZ9477_SWITCH_MTU_MTU_DEFAULT 0x07D0
1353 
1354 //Switch ISP TPID register
1355 #define KSZ9477_SWITCH_ISP_TPID_ISP_TAG_TPID 0xFFFF
1356 
1357 //AVB Credit Based Shaper Strategy register
1358 #define KSZ9477_AVB_CBS_STRATEGY_SHAPING_CREDIT_ACCOUNTING 0x0002
1359 #define KSZ9477_AVB_CBS_STRATEGY_POLICING_CREDIT_ACCOUNTING 0x0001
1360 
1361 //Switch Lookup Engine Control 0 register
1362 #define KSZ9477_SWITCH_LUE_CTRL0_VLAN_EN 0x80
1363 #define KSZ9477_SWITCH_LUE_CTRL0_DROP_INVALID_VID 0x40
1364 #define KSZ9477_SWITCH_LUE_CTRL0_AGE_COUNT 0x38
1365 #define KSZ9477_SWITCH_LUE_CTRL0_AGE_COUNT_DEFAULT 0x20
1366 #define KSZ9477_SWITCH_LUE_CTRL0_RESERVED_MCAST_LOOKUP_EN 0x04
1367 #define KSZ9477_SWITCH_LUE_CTRL0_HASH_OPTION 0x03
1368 #define KSZ9477_SWITCH_LUE_CTRL0_HASH_OPTION_NONE 0x00
1369 #define KSZ9477_SWITCH_LUE_CTRL0_HASH_OPTION_CRC 0x01
1370 #define KSZ9477_SWITCH_LUE_CTRL0_HASH_OPTION_XOR 0x02
1371 
1372 //Switch Lookup Engine Control 1 register
1373 #define KSZ9477_SWITCH_LUE_CTRL1_UNICAST_LEARNING_DIS 0x80
1374 #define KSZ9477_SWITCH_LUE_CTRL1_SELF_ADDR_FILT 0x40
1375 #define KSZ9477_SWITCH_LUE_CTRL1_FLUSH_ALU_TABLE 0x20
1376 #define KSZ9477_SWITCH_LUE_CTRL1_FLUSH_MSTP_ENTRIES 0x10
1377 #define KSZ9477_SWITCH_LUE_CTRL1_MCAST_SRC_ADDR_FILT 0x08
1378 #define KSZ9477_SWITCH_LUE_CTRL1_AGING_EN 0x04
1379 #define KSZ9477_SWITCH_LUE_CTRL1_FAST_AGING 0x02
1380 #define KSZ9477_SWITCH_LUE_CTRL1_LINK_DOWN_FLUSH 0x01
1381 
1382 //Switch Lookup Engine Control 2 register
1383 #define KSZ9477_SWITCH_LUE_CTRL2_DOUBLE_TAG_MCAST_TRAP 0x40
1384 #define KSZ9477_SWITCH_LUE_CTRL2_DYNAMIC_ENTRY_EG_VLAN_FILT 0x20
1385 #define KSZ9477_SWITCH_LUE_CTRL2_STATIC_ENTRY_EG_VLAN_FILT 0x10
1386 #define KSZ9477_SWITCH_LUE_CTRL2_FLUSH_OPTION 0x0C
1387 #define KSZ9477_SWITCH_LUE_CTRL2_FLUSH_OPTION_NONE 0x00
1388 #define KSZ9477_SWITCH_LUE_CTRL2_FLUSH_OPTION_DYNAMIC 0x04
1389 #define KSZ9477_SWITCH_LUE_CTRL2_FLUSH_OPTION_STATIC 0x08
1390 #define KSZ9477_SWITCH_LUE_CTRL2_FLUSH_OPTION_BOTH 0x0C
1391 #define KSZ9477_SWITCH_LUE_CTRL2_MAC_ADDR_PRIORITY 0x03
1392 
1393 //Switch Lookup Engine Control 3 register
1394 #define KSZ9477_SWITCH_LUE_CTRL3_AGE_PERIOD 0xFF
1395 #define KSZ9477_SWITCH_LUE_CTRL3_AGE_PERIOD_DEFAULT 0x4B
1396 
1397 //Address Lookup Table Interrupt register
1398 #define KSZ9477_ALU_TABLE_INT_LEARN_FAIL 0x04
1399 #define KSZ9477_ALU_TABLE_INT_ALMOST_FULL 0x02
1400 #define KSZ9477_ALU_TABLE_INT_WRITE_FAIL 0x01
1401 
1402 //Address Lookup Table Mask register
1403 #define KSZ9477_ALU_TABLE_MASK_LEARN_FAIL 0x04
1404 #define KSZ9477_ALU_TABLE_MASK_ALMOST_FULL 0x02
1405 #define KSZ9477_ALU_TABLE_MASK_WRITE_FAIL 0x01
1406 
1407 //Address Lookup Table Entry Index 0 register
1408 #define KSZ9477_ALU_TABLE_ENTRY_INDEX0_ALMOST_FULL_ENTRY_INDEX 0x0FFF
1409 #define KSZ9477_ALU_TABLE_ENTRY_INDEX0_FAIL_WRITE_INDEX 0x03FF
1410 
1411 //Address Lookup Table Entry Index 1 register
1412 #define KSZ9477_ALU_TABLE_ENTRY_INDEX1_FAIL_LEARN_INDEX 0x03FF
1413 
1414 //Address Lookup Table Entry Index 2 register
1415 #define KSZ9477_ALU_TABLE_ENTRY_INDEX2_CPU_ACCESS_INDEX 0x03FF
1416 
1417 //Unknown Unicast Control register
1418 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD 0x80000000
1419 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP 0x0000007F
1420 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT1 0x00000001
1421 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT2 0x00000002
1422 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT3 0x00000004
1423 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT4 0x00000008
1424 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT5 0x00000010
1425 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT6 0x00000020
1426 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT7 0x00000040
1427 #define KSZ9477_UNKNOWN_UNICAST_CTRL_FWD_MAP_ALL 0x0000007F
1428 
1429 //Unknown Multicast Control register
1430 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD 0x80000000
1431 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP 0x0000007F
1432 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT1 0x00000001
1433 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT2 0x00000002
1434 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT3 0x00000004
1435 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT4 0x00000008
1436 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT5 0x00000010
1437 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT6 0x00000020
1438 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT7 0x00000040
1439 #define KSZ9477_UNKONWN_MULTICAST_CTRL_FWD_MAP_ALL 0x0000007F
1440 
1441 //Unknown VLAN ID Control register
1442 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD 0x80000000
1443 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP 0x0000007F
1444 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT1 0x00000001
1445 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT2 0x00000002
1446 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT3 0x00000004
1447 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT4 0x00000008
1448 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT5 0x00000010
1449 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT6 0x00000020
1450 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT7 0x00000040
1451 #define KSZ9477_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_ALL 0x0000007F
1452 
1453 //Switch MAC Control 0 register
1454 #define KSZ9477_SWITCH_MAC_CTRL0_ALT_BACK_OFF_MODE 0x80
1455 #define KSZ9477_SWITCH_MAC_CTRL0_FRAME_LEN_CHECK_EN 0x08
1456 #define KSZ9477_SWITCH_MAC_CTRL0_FLOW_CTRL_PKT_DROP_MODE 0x02
1457 #define KSZ9477_SWITCH_MAC_CTRL0_AGGRESSIVE_BACK_OFF_EN 0x01
1458 
1459 //Switch MAC Control 1 register
1460 #define KSZ9477_SWITCH_MAC_CTRL1_MCAST_STORM_PROTECT_DIS 0x40
1461 #define KSZ9477_SWITCH_MAC_CTRL1_BACK_PRESSURE_MODE 0x20
1462 #define KSZ9477_SWITCH_MAC_CTRL1_FLOW_CTRL_FAIR_MODE 0x10
1463 #define KSZ9477_SWITCH_MAC_CTRL1_NO_EXCESSIVE_COL_DROP 0x08
1464 #define KSZ9477_SWITCH_MAC_CTRL1_JUMBO_PKT_SUPPORT 0x04
1465 #define KSZ9477_SWITCH_MAC_CTRL1_MAX_PKT_SIZE_CHECK_DIS 0x02
1466 #define KSZ9477_SWITCH_MAC_CTRL1_PASS_SHORT_PKT 0x01
1467 
1468 //Switch MAC Control 2 register
1469 #define KSZ9477_SWITCH_MAC_CTRL2_NULL_VID_REPLACEMENT 0x08
1470 #define KSZ9477_SWITCH_MAC_CTRL2_BCAST_STORM_PROTECT_RATE_MSB 0x07
1471 
1472 //Switch MAC Control 3 register
1473 #define KSZ9477_SWITCH_MAC_CTRL3_BCAST_STORM_PROTECT_RATE_LSB 0xFF
1474 
1475 //Switch MAC Control 4 register
1476 #define KSZ9477_SWITCH_MAC_CTRL4_PASS_FLOW_CTRL_PKT 0x01
1477 
1478 //Switch MAC Control 5 register
1479 #define KSZ9477_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD 0x30
1480 #define KSZ9477_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_16MS 0x00
1481 #define KSZ9477_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_64MS 0x10
1482 #define KSZ9477_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_256MS 0x20
1483 #define KSZ9477_SWITCH_MAC_CTRL5_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
1484 
1485 //Switch MIB Control register
1486 #define KSZ9477_SWITCH_MIB_CTRL_FLUSH 0x80
1487 #define KSZ9477_SWITCH_MIB_CTRL_FREEZE 0x40
1488 
1489 //Global Port Mirroring and Snooping Control register
1490 #define KSZ9477_GLOBAL_PORT_MIRROR_SNOOP_CTRL_IGMP_SNOOP_EN 0x40
1491 #define KSZ9477_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_OPT 0x08
1492 #define KSZ9477_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_EN 0x04
1493 #define KSZ9477_GLOBAL_PORT_MIRROR_SNOOP_CTRL_SNIFF_MODE_SEL 0x01
1494 
1495 //WRED DiffServ Color Mapping register
1496 #define KSZ9477_WRED_DIFFSERV_COLOR_MAPPING_RED 0x30
1497 #define KSZ9477_WRED_DIFFSERV_COLOR_MAPPING_YELLOW 0x0C
1498 #define KSZ9477_WRED_DIFFSERV_COLOR_MAPPING_GREEN 0x03
1499 
1500 //PTP Event Message Priority register
1501 #define KSZ9477_PTP_EVENT_MSG_PRIO_OVERRIDE 0x80
1502 #define KSZ9477_PTP_EVENT_MSG_PRIO_PRIORITY 0x0F
1503 
1504 //PTP Non-Event Message Priority register
1505 #define KSZ9477_PTP_NON_EVENT_MSG_PRIO_OVERRIDE 0x80
1506 #define KSZ9477_PTP_NON_EVENT_MSG_PRIO_PRIORITY 0x0F
1507 
1508 //Queue Management Control 0 register
1509 #define KSZ9477_QUEUE_MGMT_CTRL0_PRIORITY_2Q 0x000000C0
1510 #define KSZ9477_QUEUE_MGMT_CTRL0_UNICAST_PORT_VLAN_DISCARD 0x00000002
1511 
1512 //VLAN Table Entry 0 register
1513 #define KSZ9477_VLAN_TABLE_ENTRY0_VALID 0x80000000
1514 #define KSZ9477_VLAN_TABLE_ENTRY0_FORWARD_OPTION 0x08000000
1515 #define KSZ9477_VLAN_TABLE_ENTRY0_PRIORITY 0x07000000
1516 #define KSZ9477_VLAN_TABLE_ENTRY0_MSTP_INDEX 0x00007000
1517 #define KSZ9477_VLAN_TABLE_ENTRY0_FID 0x0000007F
1518 
1519 //VLAN Table Entry 1 register
1520 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT_UNTAG 0x0000007F
1521 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT7_UNTAG 0x00000040
1522 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT6_UNTAG 0x00000020
1523 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT5_UNTAG 0x00000010
1524 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT4_UNTAG 0x00000008
1525 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT3_UNTAG 0x00000004
1526 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT2_UNTAG 0x00000002
1527 #define KSZ9477_VLAN_TABLE_ENTRY1_PORT1_UNTAG 0x00000001
1528 
1529 //VLAN Table Entry 2 register
1530 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1531 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1532 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1533 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1534 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1535 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1536 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1537 #define KSZ9477_VLAN_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1538 
1539 //VLAN Table Index register
1540 #define KSZ9477_VLAN_TABLE_INDEX_VLAN_INDEX 0x0FFF
1541 
1542 //VLAN Table Access Control register
1543 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_START_FINISH 0x80
1544 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_ACTION 0x03
1545 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_ACTION_NOP 0x00
1546 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_ACTION_WRITE 0x01
1547 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_ACTION_READ 0x02
1548 #define KSZ9477_VLAN_TABLE_ACCESS_CTRL_ACTION_CLEAR 0x03
1549 
1550 //ALU Table Index 0 register
1551 #define KSZ9477_ALU_TABLE_INDEX0_FID_INDEX 0x007F0000
1552 #define KSZ9477_ALU_TABLE_INDEX0_MAC_INDEX_MSB 0x0000FFFF
1553 
1554 //ALU Table Index 1 register
1555 #define KSZ9477_ALU_TABLE_INDEX1_MAC_INDEX_LSB 0xFFFFFFFF
1556 
1557 //ALU Table Access Control register
1558 #define KSZ9477_ALU_TABLE_CTRL_VALID_COUNT 0x3FFF0000
1559 #define KSZ9477_ALU_TABLE_CTRL_START_FINISH 0x00000080
1560 #define KSZ9477_ALU_TABLE_CTRL_VALID 0x00000040
1561 #define KSZ9477_ALU_TABLE_CTRL_VALID_ENTRY_OR_SEARCH_END 0x00000020
1562 #define KSZ9477_ALU_TABLE_CTRL_DIRECT 0x00000004
1563 #define KSZ9477_ALU_TABLE_CTRL_ACTION 0x00000003
1564 #define KSZ9477_ALU_TABLE_CTRL_ACTION_NOP 0x00000000
1565 #define KSZ9477_ALU_TABLE_CTRL_ACTION_WRITE 0x00000001
1566 #define KSZ9477_ALU_TABLE_CTRL_ACTION_READ 0x00000002
1567 #define KSZ9477_ALU_TABLE_CTRL_ACTION_SEARCH 0x00000003
1568 
1569 //Static Address and Reserved Multicast Table Control register
1570 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_TABLE_INDEX 0x003F0000
1571 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_START_FINISH 0x00000080
1572 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_TABLE_SELECT 0x00000002
1573 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_ACTION 0x00000001
1574 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_ACTION_READ 0x00000000
1575 #define KSZ9477_STATIC_MCAST_TABLE_CTRL_ACTION_WRITE 0x00000001
1576 
1577 //ALU Table Entry 1 register
1578 #define KSZ9477_ALU_TABLE_ENTRY1_STATIC 0x80000000
1579 #define KSZ9477_ALU_TABLE_ENTRY1_SRC_FILTER 0x40000000
1580 #define KSZ9477_ALU_TABLE_ENTRY1_DES_FILTER 0x20000000
1581 #define KSZ9477_ALU_TABLE_ENTRY1_PRIORITY 0x1C000000
1582 #define KSZ9477_ALU_TABLE_ENTRY1_AGE_COUNT 0x1C000000
1583 #define KSZ9477_ALU_TABLE_ENTRY1_MSTP 0x00000007
1584 
1585 //ALU Table Entry 2 register
1586 #define KSZ9477_ALU_TABLE_ENTRY2_OVERRIDE 0x80000000
1587 #define KSZ9477_ALU_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1588 #define KSZ9477_ALU_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1589 #define KSZ9477_ALU_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1590 #define KSZ9477_ALU_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1591 #define KSZ9477_ALU_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1592 #define KSZ9477_ALU_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1593 #define KSZ9477_ALU_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1594 #define KSZ9477_ALU_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1595 
1596 //ALU Table Entry 3 register
1597 #define KSZ9477_ALU_TABLE_ENTRY3_FID 0x007F0000
1598 #define KSZ9477_ALU_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1599 
1600 //ALU Table Entry 4 register
1601 #define KSZ9477_ALU_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1602 
1603 //Static Address Table Entry 1 register
1604 #define KSZ9477_STATIC_TABLE_ENTRY1_VALID 0x80000000
1605 #define KSZ9477_STATIC_TABLE_ENTRY1_SRC_FILTER 0x40000000
1606 #define KSZ9477_STATIC_TABLE_ENTRY1_DES_FILTER 0x20000000
1607 #define KSZ9477_STATIC_TABLE_ENTRY1_PRIORITY 0x1C000000
1608 #define KSZ9477_STATIC_TABLE_ENTRY1_MSTP 0x00000007
1609 
1610 //Static Address Table Entry 2 register
1611 #define KSZ9477_STATIC_TABLE_ENTRY2_OVERRIDE 0x80000000
1612 #define KSZ9477_STATIC_TABLE_ENTRY2_USE_FID 0x40000000
1613 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1614 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1615 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1616 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1617 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1618 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1619 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1620 #define KSZ9477_STATIC_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1621 
1622 //Static Address Table Entry 3 register
1623 #define KSZ9477_STATIC_TABLE_ENTRY3_FID 0x007F0000
1624 #define KSZ9477_STATIC_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1625 
1626 //Static Address Table Entry 4 register
1627 #define KSZ9477_STATIC_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1628 
1629 //Reserved Multicast Table Entry 2 register
1630 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1631 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1632 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1633 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1634 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1635 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1636 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1637 #define KSZ9477_RES_MCAST_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1638 
1639 //Global PTP Clock Control register
1640 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_SW_FREQ_ADJ_DIS 0x8000
1641 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_STEP_ADJ 0x0040
1642 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_STEP_DIR 0x0020
1643 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_READ 0x0010
1644 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_LOAD 0x0008
1645 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_CONTINUOUS_ADJ 0x0004
1646 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_EN 0x0002
1647 #define KSZ9477_GLOBAL_PTP_CLK_CTRL_PTP_CLK_RESET 0x0001
1648 
1649 //Global PTP RTC Clock Phase register
1650 #define KSZ9477_GLOBAL_PTP_RTC_CLK_PHASE_PTP_RTC_8NS_PHASE 0x0007
1651 
1652 //Global PTP Clock Sub-Nanosecond Rate High Word register
1653 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RATE_DIR 0x8000
1654 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_TEMP_ADJ_MODE 0x4000
1655 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RTC_SUB_NS_29_16 0x3FFF
1656 
1657 //Global PTP Clock Sub-Nanosecond Rate Low Word register
1658 #define KSZ9477_GLOBAL_PTP_CLK_SUB_NS_RATE_L_PTP_RTC_SUB_NS_15_0 0xFFFF
1659 
1660 //Global PTP Message Config 1 register
1661 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_IEEE_802_1AS_MODE 0x0080
1662 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_IEEE_1588_PTP_MODE 0x0040
1663 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_ETH_PTP_DETECT 0x0020
1664 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_IPV4_UDP_PTP_DETECT 0x0010
1665 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_IPV6_UDP_PTP_DETECT 0x0008
1666 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_E2E_CLK_MODE 0x0000
1667 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_P2P_CLK_MODE 0x0004
1668 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_SLAVE_OC_CLK_MODE 0x0000
1669 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_MASTER_OC_CLK_MODE 0x0002
1670 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_TWO_STEP_CLK_MODE 0x0000
1671 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG1_ONE_STEP_CLK_MODE 0x0001
1672 
1673 //Global PTP Message Config 2 register
1674 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_UNICAST_PTP_EN 0x1000
1675 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_ALT_MASTER_EN 0x0800
1676 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_PTP_MSG_PRIO_TX_QUEUE 0x0400
1677 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_CHECK_SYNC_FOLLOW_UP 0x0200
1678 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_CHECK_DELAY_REQ_RESP 0x0100
1679 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_CHECK_PDELAY_REQ_RESP 0x0080
1680 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_DROP_SYNC_FOLLOW_UP_DELAY_REQ 0x0020
1681 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_CHECK_DOMAIN 0x0010
1682 #define KSZ9477_GLOBAL_PTP_MSG_CONFIG2_IPV4_UDP_CHECKSUM_EN 0x0004
1683 
1684 //Global PTP Domain and Version register
1685 #define KSZ9477_GLOBAL_PTP_DOMAIN_VERSION_PTP_VERSION 0x0F00
1686 #define KSZ9477_GLOBAL_PTP_DOMAIN_VERSION_PTP_DOMAIN 0x00FF
1687 
1688 //Global PTP Unit Index register
1689 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX 0x00000100
1690 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT0 0x00000000
1691 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT1 0x00000100
1692 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX 0x00000003
1693 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT0 0x00000000
1694 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT1 0x00000001
1695 #define KSZ9477_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT2 0x00000002
1696 
1697 //GPIO Status Monitor 0 register
1698 #define KSZ9477_GPIO_STATUS_MONITOR0_TRIGGER_ERROR 0x00070000
1699 #define KSZ9477_GPIO_STATUS_MONITOR0_TRIGGER_DONE 0x00000007
1700 
1701 //GPIO Status Monitor 1 register
1702 #define KSZ9477_GPIO_STATUS_MONITOR1_TRIGGER_INT_STATUS 0x00070000
1703 #define KSZ9477_GPIO_STATUS_MONITOR1_TS_INT_STATUS 0x00000003
1704 
1705 //Timestamp Control and Status register
1706 #define KSZ9477_TS_CTRL_STAT_GPIO_OUT_SEL 0x00000100
1707 #define KSZ9477_TS_CTRL_STAT_GPIO_IN 0x00000080
1708 #define KSZ9477_TS_CTRL_STAT_GPIO_OEN 0x00000040
1709 #define KSZ9477_TS_CTRL_STAT_TS_INT_ENB 0x00000020
1710 #define KSZ9477_TS_CTRL_STAT_TRIGGER_ACTIVE 0x00000010
1711 #define KSZ9477_TS_CTRL_STAT_TRIGGER_EN 0x00000008
1712 #define KSZ9477_TS_CTRL_STAT_TRIGGER_SW_RESET 0x00000004
1713 #define KSZ9477_TS_CTRL_STAT_TS_ENB 0x00000002
1714 #define KSZ9477_TS_CTRL_STAT_TS_SW_RESET 0x00000001
1715 
1716 //Trigger Output Unit Target Time Nanosecond register
1717 #define KSZ9477_TOU_TARGET_TIME_NS_TRIGGER_TARGET_TIME_NS 0x3FFFFFFF
1718 
1719 //Trigger Output Unit Target Time Second register
1720 #define KSZ9477_TOU_TARGET_TIME_S_TRIGGER_TARGET_TIME_S 0xFFFFFFFF
1721 
1722 //Trigger Output Unit Control 1 register
1723 #define KSZ9477_TOU_CTRL1_CASCADE_MODE_ENB 0x80000000
1724 #define KSZ9477_TOU_CTRL1_CASCADE_MODE_TAIL 0x40000000
1725 #define KSZ9477_TOU_CTRL1_CASCADE_MODE_DONE 0x0C000000
1726 #define KSZ9477_TOU_CTRL1_TRIGGER_NOW 0x02000000
1727 #define KSZ9477_TOU_CTRL1_TRIGGER_NOTIFY 0x01000000
1728 #define KSZ9477_TOU_CTRL1_TRIGGER_EDGE 0x00800000
1729 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN 0x00700000
1730 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_NEG_EDGE 0x00000000
1731 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_POS_EDGE 0x00100000
1732 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_NEG_PULSE 0x00200000
1733 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_POS_PULSE 0x00300000
1734 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_NEG_CYCLE 0x00400000
1735 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_POS_CYCLE 0x00500000
1736 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_REG_OUTPUT 0x00600000
1737 #define KSZ9477_TOU_CTRL1_TRIGGER_PATTERN_ITERATION 0x0000FFFF
1738 
1739 //Trigger Output Unit Control 2 register
1740 #define KSZ9477_TOU_CTRL2_TRIGGER_CYCLE_WIDTH 0xFFFFFFFF
1741 
1742 //Trigger Output Unit Control 3 register
1743 #define KSZ9477_TOU_CTRL3_TRIGGER_CYCLE 0xFFFF0000
1744 #define KSZ9477_TOU_CTRL3_TRIGGER_BIT_PATTERN 0x0000FFFF
1745 
1746 //Trigger Output Unit Control 4 register
1747 #define KSZ9477_TOU_CTRL4_CASCADE_INTERATION_CYCLE_TIME 0xFFFFFFFF
1748 
1749 //Trigger Output Unit Control 5 register
1750 #define KSZ9477_TOU_CTRL5_PPS_PULSE_WIDTH 0x00FF0000
1751 #define KSZ9477_TOU_CTRL5_TRIGGER_PULSE_WIDTH 0x0000FFFF
1752 
1753 //Timestamp Status and Control register
1754 #define KSZ9477_TS_STAT_CTRL_TS_EVENT_DET_CNT 0x001E0000
1755 #define KSZ9477_TS_STAT_CTRL_TS_DET_EVENT_CNT_OVERFLOW 0x00010000
1756 #define KSZ9477_TS_STAT_CTRL_TS_RISING_EDGE_ENB 0x00000080
1757 #define KSZ9477_TS_STAT_CTRL_TS_FALLING_EDGE_ENB 0x00000040
1758 #define KSZ9477_TS_STAT_CTRL_TS_CASCADE_MODE_TAIL 0x00000020
1759 #define KSZ9477_TS_STAT_CTRL_TS_UPSTREAM_CASCADE_MODE_SEL 0x00000002
1760 #define KSZ9477_TS_STAT_CTRL_TS_CASCADE_MODE_ENB 0x00000001
1761 
1762 //Timestamp 1st Sample Time Nanoseconds register
1763 #define KSZ9477_TS_SAMPLE1_TIME_NS_TS_SAMPLE_EDGE_1ST 0x40000000
1764 #define KSZ9477_TS_SAMPLE1_TIME_NS_TS_SAMPLE_TIME_NS_1ST 0x3FFFFFFF
1765 
1766 //Timestamp 1st Sample Time Seconds register
1767 #define KSZ9477_TS_SAMPLE1_TIME_S_TS_SAMPLE_TIME_S_1ST 0xFFFFFFFF
1768 
1769 //Timestamp 1st Sample Time Phase register
1770 #define KSZ9477_TS_SAMPLE1_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_1ST 0x00000007
1771 
1772 //Timestamp 2nd Sample Time Nanoseconds register
1773 #define KSZ9477_TS_SAMPLE2_TIME_NS_TS_SAMPLE_EDGE_2ND 0x40000000
1774 #define KSZ9477_TS_SAMPLE2_TIME_NS_TS_SAMPLE_TIME_NS_2ND 0x3FFFFFFF
1775 
1776 //Timestamp 2nd Sample Time Seconds register
1777 #define KSZ9477_TS_SAMPLE2_TIME_S_TS_SAMPLE_TIME_S_2ND 0xFFFFFFFF
1778 
1779 //Timestamp 2nd Sample Time Phase register
1780 #define KSZ9477_TS_SAMPLE2_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_2ND 0x00000007
1781 
1782 //Timestamp 3rd Sample Time Nanoseconds register
1783 #define KSZ9477_TS_SAMPLE3_TIME_NS_TS_SAMPLE_EDGE_3RD 0x40000000
1784 #define KSZ9477_TS_SAMPLE3_TIME_NS_TS_SAMPLE_TIME_NS_3RD 0x3FFFFFFF
1785 
1786 //Timestamp 3rd Sample Time Seconds register
1787 #define KSZ9477_TS_SAMPLE3_TIME_S_TS_SAMPLE_TIME_S_3RD 0xFFFFFFFF
1788 
1789 //Timestamp 3rd Sample Time Phase register
1790 #define KSZ9477_TS_SAMPLE3_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_3RD 0x00000007
1791 
1792 //Timestamp 4th Sample Time Nanoseconds register
1793 #define KSZ9477_TS_SAMPLE4_TIME_NS_TS_SAMPLE_EDGE_4TH 0x40000000
1794 #define KSZ9477_TS_SAMPLE4_TIME_NS_TS_SAMPLE_TIME_NS_4TH 0x3FFFFFFF
1795 
1796 //Timestamp 4th Sample Time Seconds register
1797 #define KSZ9477_TS_SAMPLE4_TIME_S_TS_SAMPLE_TIME_S_4TH 0xFFFFFFFF
1798 
1799 //Timestamp 4th Sample Time Phase register
1800 #define KSZ9477_TS_SAMPLE4_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_4TH 0x00000007
1801 
1802 //Timestamp 5th Sample Time Nanoseconds register
1803 #define KSZ9477_TS_SAMPLE5_TIME_NS_TS_SAMPLE_EDGE_5TH 0x40000000
1804 #define KSZ9477_TS_SAMPLE5_TIME_NS_TS_SAMPLE_TIME_NS_5TH 0x3FFFFFFF
1805 
1806 //Timestamp 5th Sample Time Seconds register
1807 #define KSZ9477_TS_SAMPLE5_TIME_S_TS_SAMPLE_TIME_S_5TH 0xFFFFFFFF
1808 
1809 //Timestamp 5th Sample Time Phase register
1810 #define KSZ9477_TS_SAMPLE5_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_5TH 0x00000007
1811 
1812 //Timestamp 6th Sample Time Nanoseconds register
1813 #define KSZ9477_TS_SAMPLE6_TIME_NS_TS_SAMPLE_EDGE_6TH 0x40000000
1814 #define KSZ9477_TS_SAMPLE6_TIME_NS_TS_SAMPLE_TIME_NS_6TH 0x3FFFFFFF
1815 
1816 //Timestamp 6th Sample Time Seconds register
1817 #define KSZ9477_TS_SAMPLE6_TIME_S_TS_SAMPLE_TIME_S_6TH 0xFFFFFFFF
1818 
1819 //Timestamp 6th Sample Time Phase register
1820 #define KSZ9477_TS_SAMPLE6_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_6TH 0x00000007
1821 
1822 //Timestamp 7th Sample Time Nanoseconds register
1823 #define KSZ9477_TS_SAMPLE7_TIME_NS_TS_SAMPLE_EDGE_7TH 0x40000000
1824 #define KSZ9477_TS_SAMPLE7_TIME_NS_TS_SAMPLE_TIME_NS_7TH 0x3FFFFFFF
1825 
1826 //Timestamp 7th Sample Time Seconds register
1827 #define KSZ9477_TS_SAMPLE7_TIME_S_TS_SAMPLE_TIME_S_7TH 0xFFFFFFFF
1828 
1829 //Timestamp 7th Sample Time Phase register
1830 #define KSZ9477_TS_SAMPLE7_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_7TH 0x00000007
1831 
1832 //Timestamp 8th Sample Time Nanoseconds register
1833 #define KSZ9477_TS_SAMPLE8_TIME_NS_TS_SAMPLE_EDGE_8TH 0x40000000
1834 #define KSZ9477_TS_SAMPLE8_TIME_NS_TS_SAMPLE_TIME_NS_8TH 0x3FFFFFFF
1835 
1836 //Timestamp 8th Sample Time Seconds register
1837 #define KSZ9477_TS_SAMPLE8_TIME_S_TS_SAMPLE_TIME_S_8TH 0xFFFFFFFF
1838 
1839 //Timestamp 8th Sample Time Phase register
1840 #define KSZ9477_TS_SAMPLE8_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_8TH 0x00000007
1841 
1842 //Port N Default Tag 0 register
1843 #define KSZ9477_PORTn_DEFAULT_TAG0_PCP 0xE0
1844 #define KSZ9477_PORTn_DEFAULT_TAG0_DEI 0x10
1845 #define KSZ9477_PORTn_DEFAULT_TAG0_VID_MSB 0x0F
1846 
1847 //Port N Default Tag 1 register
1848 #define KSZ9477_PORTn_DEFAULT_TAG1_VID_LSB 0xFF
1849 
1850 //Port N Interrupt Status register
1851 #define KSZ9477_PORTn_INT_STATUS_SGMII_AN_DONE 0x08
1852 #define KSZ9477_PORTn_INT_STATUS_PTP 0x04
1853 #define KSZ9477_PORTn_INT_STATUS_PHY 0x02
1854 #define KSZ9477_PORTn_INT_STATUS_ACL 0x01
1855 
1856 //Port N Interrupt Mask register
1857 #define KSZ9477_PORTn_INT_MASK_SGMII_AN_DONE 0x08
1858 #define KSZ9477_PORTn_INT_MASK_PTP 0x04
1859 #define KSZ9477_PORTn_INT_MASK_PHY 0x02
1860 #define KSZ9477_PORTn_INT_MASK_ACL 0x01
1861 
1862 //Port N Operation Control 0 register
1863 #define KSZ9477_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
1864 #define KSZ9477_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
1865 #define KSZ9477_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
1866 #define KSZ9477_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
1867 
1868 //Port N Status register
1869 #define KSZ9477_PORTn_STATUS_SPEED 0x18
1870 #define KSZ9477_PORTn_STATUS_SPEED_10MBPS 0x00
1871 #define KSZ9477_PORTn_STATUS_SPEED_100MBPS 0x08
1872 #define KSZ9477_PORTn_STATUS_SPEED_1000MBPS 0x10
1873 #define KSZ9477_PORTn_STATUS_DUPLEX 0x04
1874 #define KSZ9477_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
1875 #define KSZ9477_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
1876 
1877 //XMII Port N Control 0 register
1878 #define KSZ9477_PORTn_XMII_CTRL0_DUPLEX 0x40
1879 #define KSZ9477_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
1880 #define KSZ9477_PORTn_XMII_CTRL0_SPEED_10_100 0x10
1881 #define KSZ9477_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
1882 
1883 //XMII Port N Control 1 register
1884 #define KSZ9477_PORTn_XMII_CTRL1_SPEED_1000 0x40
1885 #define KSZ9477_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
1886 #define KSZ9477_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
1887 #define KSZ9477_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
1888 #define KSZ9477_PORTn_XMII_CTRL1_IF_TYPE 0x03
1889 #define KSZ9477_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x00
1890 #define KSZ9477_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
1891 #define KSZ9477_PORTn_XMII_CTRL1_IF_TYPE_MII 0x03
1892 
1893 //Port N MAC Control 0 register
1894 #define KSZ9477_PORTn_MAC_CTRL0_BCAST_STORM_PROTECT_EN 0x02
1895 
1896 //Port N MAC Control 1 register
1897 #define KSZ9477_PORTn_MAC_CTRL1_BACK_PRESSURE_EN 0x08
1898 #define KSZ9477_PORTn_MAC_CTRL1_PASS_ALL_FRAMES 0x01
1899 
1900 //Port N MIB Control and Status register
1901 #define KSZ9477_PORTn_MIB_CTRL_STAT_MIB_COUNTER_OVERFLOW 0x80000000
1902 #define KSZ9477_PORTn_MIB_CTRL_STAT_MIB_READ 0x02000000
1903 #define KSZ9477_PORTn_MIB_CTRL_STAT_MIB_FLUSH_FREEZE 0x01000000
1904 #define KSZ9477_PORTn_MIB_CTRL_STAT_MIB_INDEX 0x00FF0000
1905 #define KSZ9477_PORTn_MIB_CTRL_STAT_MIB_COUNTER_VALUE_35_32 0x0000000F
1906 
1907 //Port N MIB Data register
1908 #define KSZ9477_PORTn_MIB_DATA_MIB_COUNTER_VALUE_31_0 0xFFFFFFFF
1909 
1910 //Port N ACL Access Control 0 register
1911 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0_WRITE_STATUS 0x40
1912 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0_READ_STATUS 0x20
1913 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0_READ 0x00
1914 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0_WRITE 0x10
1915 #define KSZ9477_PORTn_ACL_ACCESS_CTRL0_ACL_INDEX 0x0F
1916 
1917 //Port N ACL Access Control 1 register
1918 #define KSZ9477_PORTn_ACL_ACCESS_CTRL1_FORCE_DLR_MISS 0x01
1919 
1920 //Port N Port Mirroring Control register
1921 #define KSZ9477_PORTn_MIRRORING_CTRL_RECEIVE_SNIFF 0x40
1922 #define KSZ9477_PORTn_MIRRORING_CTRL_TRANSMIT_SNIFF 0x20
1923 #define KSZ9477_PORTn_MIRRORING_CTRL_SNIFFER_PORT 0x02
1924 
1925 //Port N Authentication Control register
1926 #define KSZ9477_PORTn_AUTH_CTRL_ACL_EN 0x04
1927 #define KSZ9477_PORTn_AUTH_CTRL_AUTH_MODE 0x03
1928 #define KSZ9477_PORTn_AUTH_CTRL_AUTH_MODE_PASS 0x00
1929 #define KSZ9477_PORTn_AUTH_CTRL_AUTH_MODE_BLOCK 0x01
1930 #define KSZ9477_PORTn_AUTH_CTRL_AUTH_MODE_TRAP 0x02
1931 
1932 //Port N Pointer register
1933 #define KSZ9477_PORTn_PTR_PORT_INDEX 0x00070000
1934 #define KSZ9477_PORTn_PTR_QUEUE_PTR 0x00000003
1935 
1936 //Port N Control 1 register
1937 #define KSZ9477_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x0000007F
1938 #define KSZ9477_PORTn_CTRL1_PORT7_VLAN_MEMBERSHIP 0x00000040
1939 #define KSZ9477_PORTn_CTRL1_PORT6_VLAN_MEMBERSHIP 0x00000020
1940 #define KSZ9477_PORTn_CTRL1_PORT5_VLAN_MEMBERSHIP 0x00000010
1941 #define KSZ9477_PORTn_CTRL1_PORT4_VLAN_MEMBERSHIP 0x00000008
1942 #define KSZ9477_PORTn_CTRL1_PORT3_VLAN_MEMBERSHIP 0x00000004
1943 #define KSZ9477_PORTn_CTRL1_PORT2_VLAN_MEMBERSHIP 0x00000002
1944 #define KSZ9477_PORTn_CTRL1_PORT1_VLAN_MEMBERSHIP 0x00000001
1945 
1946 //Port N Control 2 register
1947 #define KSZ9477_PORTn_CTRL2_NULL_VID_LOOKUP_EN 0x80
1948 #define KSZ9477_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
1949 #define KSZ9477_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
1950 #define KSZ9477_PORTn_CTRL2_802_1X_EN 0x10
1951 #define KSZ9477_PORTn_CTRL2_SELF_ADDR_FILT 0x08
1952 
1953 //Port N MSTP Pointer register
1954 #define KSZ9477_PORTn_MSTP_PTR_MSTP_PTR 0x07
1955 
1956 //Port N MSTP State register
1957 #define KSZ9477_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
1958 #define KSZ9477_PORTn_MSTP_STATE_RECEIVE_EN 0x02
1959 #define KSZ9477_PORTn_MSTP_STATE_LEARNING_DIS 0x01
1960 
1961 //Port N PTP Asymmetry Correction register
1962 #define KSZ9477_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR_SIGN 0x8000
1963 #define KSZ9477_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR 0x7FFF
1964 
1965 //Port N PTP Timestamp Interrupt Status register
1966 #define KSZ9477_PORTn_PTP_TS_INT_STAT_TS_SYNC_INT_STATUS 0x8000
1967 #define KSZ9477_PORTn_PTP_TS_INT_STAT_TS_PDLY_REQ_INT_STATUS 0x4000
1968 #define KSZ9477_PORTn_PTP_TS_INT_STAT_TS_PDLY_RESP_INT_STATUS 0x2000
1969 
1970 //Port N PTP Timestamp Interrupt Enable register
1971 #define KSZ9477_PORTn_PTP_TS_INT_EN_TS_SYNC_INT_ENB 0x8000
1972 #define KSZ9477_PORTn_PTP_TS_INT_EN_TS_PDLY_REQ_INT_ENB 0x4000
1973 #define KSZ9477_PORTn_PTP_TS_INT_EN_TS_PDLY_RESP_INT_ENB 0x2000
1974 
1975 //C++ guard
1976 #ifdef __cplusplus
1977 extern "C" {
1978 #endif
1979 
1980 //KSZ9477 Ethernet switch driver
1981 extern const SwitchDriver ksz9477SwitchDriver;
1982 
1983 //KSZ9477 related functions
1984 error_t ksz9477Init(NetInterface *interface);
1985 void ksz9477InitHook(NetInterface *interface);
1986 
1987 void ksz9477Tick(NetInterface *interface);
1988 
1989 void ksz9477EnableIrq(NetInterface *interface);
1990 void ksz9477DisableIrq(NetInterface *interface);
1991 
1992 void ksz9477EventHandler(NetInterface *interface);
1993 
1994 error_t ksz9477TagFrame(NetInterface *interface, NetBuffer *buffer,
1995  size_t *offset, NetTxAncillary *ancillary);
1996 
1997 error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame,
1998  size_t *length, NetRxAncillary *ancillary);
1999 
2000 bool_t ksz9477GetLinkState(NetInterface *interface, uint8_t port);
2001 uint32_t ksz9477GetLinkSpeed(NetInterface *interface, uint8_t port);
2003 
2004 void ksz9477SetPortState(NetInterface *interface, uint8_t port,
2005  SwitchPortState state);
2006 
2008 
2009 void ksz9477SetAgingTime(NetInterface *interface, uint32_t agingTime);
2010 
2011 void ksz9477EnableIgmpSnooping(NetInterface *interface, bool_t enable);
2012 void ksz9477EnableMldSnooping(NetInterface *interface, bool_t enable);
2013 void ksz9477EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
2014 
2016  const SwitchFdbEntry *entry);
2017 
2019  const SwitchFdbEntry *entry);
2020 
2022  SwitchFdbEntry *entry);
2023 
2024 void ksz9477FlushStaticFdbTable(NetInterface *interface);
2025 
2027  SwitchFdbEntry *entry);
2028 
2029 void ksz9477FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
2030 
2032  bool_t enable, uint32_t forwardPorts);
2033 
2034 void ksz9477WritePhyReg(NetInterface *interface, uint8_t port,
2035  uint8_t address, uint16_t data);
2036 
2037 uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port,
2038  uint8_t address);
2039 
2040 void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port);
2041 
2042 void ksz9477WriteMmdReg(NetInterface *interface, uint8_t port,
2043  uint8_t devAddr, uint16_t regAddr, uint16_t data);
2044 
2045 uint16_t ksz9477ReadMmdReg(NetInterface *interface, uint8_t port,
2046  uint8_t devAddr, uint16_t regAddr);
2047 
2048 void ksz9477WriteSwitchReg8(NetInterface *interface, uint16_t address,
2049  uint8_t data);
2050 
2051 uint8_t ksz9477ReadSwitchReg8(NetInterface *interface, uint16_t address);
2052 
2053 void ksz9477WriteSwitchReg16(NetInterface *interface, uint16_t address,
2054  uint16_t data);
2055 
2056 uint16_t ksz9477ReadSwitchReg16(NetInterface *interface, uint16_t address);
2057 
2058 void ksz9477WriteSwitchReg32(NetInterface *interface, uint16_t address,
2059  uint32_t data);
2060 
2061 uint32_t ksz9477ReadSwitchReg32(NetInterface *interface, uint16_t address);
2062 
2063 //C++ guard
2064 #ifdef __cplusplus
2065 }
2066 #endif
2067 
2068 #endif
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
uint16_t port
Definition: dns_common.h:267
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
error_t ksz9477GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
void ksz9477FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
SwitchPortState ksz9477GetPortState(NetInterface *interface, uint8_t port)
Get port state.
void ksz9477WriteSwitchReg16(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register (16 bits)
void ksz9477DisableIrq(NetInterface *interface)
Disable interrupts.
bool_t ksz9477GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz9477EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
error_t ksz9477TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
error_t ksz9477GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
uint16_t ksz9477ReadMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
void ksz9477WriteSwitchReg32(NetInterface *interface, uint16_t address, uint32_t data)
Write switch register (32 bits)
uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
void ksz9477EnableIrq(NetInterface *interface)
Enable interrupts.
error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
uint16_t ksz9477ReadSwitchReg16(NetInterface *interface, uint16_t address)
Read switch register (16 bits)
void ksz9477EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
uint32_t ksz9477GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
NicDuplexMode ksz9477GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
void ksz9477EventHandler(NetInterface *interface)
KSZ9477 event handler.
void ksz9477EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
void ksz9477InitHook(NetInterface *interface)
KSZ9477 custom configuration.
void ksz9477FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
uint8_t ksz9477ReadSwitchReg8(NetInterface *interface, uint16_t address)
Read switch register (8 bits)
void ksz9477SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
void ksz9477WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz9477SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
error_t ksz9477Init(NetInterface *interface)
KSZ9477 Ethernet switch initialization.
void ksz9477SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
error_t ksz9477AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
error_t ksz9477DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
void ksz9477WriteMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
uint32_t ksz9477ReadSwitchReg32(NetInterface *interface, uint16_t address)
Read switch register (32 bits)
void ksz9477Tick(NetInterface *interface)
KSZ9477 timer handler.
void ksz9477WriteSwitchReg8(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register (8 bits)
void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
const SwitchDriver ksz9477SwitchDriver
KSZ9477 Ethernet switch driver.
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
NicDuplexMode
Duplex mode.
Definition: nic.h:122
SwitchPortState
Switch port state.
Definition: nic.h:134
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
Ethernet switch driver.
Definition: nic.h:322
Forwarding database entry.
Definition: nic.h:149
uint8_t length
Definition: tcp.h:368