ksz9897_driver.h
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1 /**
2  * @file ksz9897_driver.h
3  * @brief KSZ9897 7-port Gigabit Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2026 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.6.0
29  **/
30 
31 #ifndef _KSZ9897_DRIVER_H
32 #define _KSZ9897_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ9897_PORT1 1
39 #define KSZ9897_PORT2 2
40 #define KSZ9897_PORT3 3
41 #define KSZ9897_PORT4 4
42 #define KSZ9897_PORT5 5
43 #define KSZ9897_PORT6 6
44 #define KSZ9897_PORT7 7
45 
46 //Port masks
47 #define KSZ9897_PORT_MASK 0x7F
48 #define KSZ9897_PORT1_MASK 0x01
49 #define KSZ9897_PORT2_MASK 0x02
50 #define KSZ9897_PORT3_MASK 0x04
51 #define KSZ9897_PORT4_MASK 0x08
52 #define KSZ9897_PORT5_MASK 0x10
53 #define KSZ9897_PORT6_MASK 0x20
54 #define KSZ9897_PORT7_MASK 0x40
55 
56 //SPI command byte
57 #define KSZ9897_SPI_CMD_WRITE 0x40000000
58 #define KSZ9897_SPI_CMD_READ 0x60000000
59 #define KSZ9897_SPI_CMD_ADDR 0x001FFFE0
60 
61 //Size of static and dynamic MAC tables
62 #define KSZ9897_STATIC_MAC_TABLE_SIZE 16
63 #define KSZ9897_DYNAMIC_MAC_TABLE_SIZE 4096
64 
65 //Tail tag rules (host to KSZ9897)
66 #define KSZ9897_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x0400
67 #define KSZ9897_TAIL_TAG_PORT_BLOCKING_OVERRIDE 0x0200
68 #define KSZ9897_TAIL_TAG_PRIORITY 0x0180
69 #define KSZ9897_TAIL_TAG_DEST_PORT7 0x0040
70 #define KSZ9897_TAIL_TAG_DEST_PORT6 0x0020
71 #define KSZ9897_TAIL_TAG_DEST_PORT5 0x0010
72 #define KSZ9897_TAIL_TAG_DEST_PORT4 0x0008
73 #define KSZ9897_TAIL_TAG_DEST_PORT3 0x0004
74 #define KSZ9897_TAIL_TAG_DEST_PORT2 0x0002
75 #define KSZ9897_TAIL_TAG_DEST_PORT1 0x0001
76 
77 //Tail tag rules (KSZ9897 to host)
78 #define KSZ9897_TAIL_TAG_PTP_MSG 0x80
79 #define KSZ9897_TAIL_TAG_SRC_PORT 0x07
80 
81 //KSZ9897 PHY registers
82 #define KSZ9897_BMCR 0x00
83 #define KSZ9897_BMSR 0x01
84 #define KSZ9897_PHYID1 0x02
85 #define KSZ9897_PHYID2 0x03
86 #define KSZ9897_ANAR 0x04
87 #define KSZ9897_ANLPAR 0x05
88 #define KSZ9897_ANER 0x06
89 #define KSZ9897_ANNPR 0x07
90 #define KSZ9897_ANLPNPR 0x08
91 #define KSZ9897_GBCR 0x09
92 #define KSZ9897_GBSR 0x0A
93 #define KSZ9897_MMDACR 0x0D
94 #define KSZ9897_MMDAADR 0x0E
95 #define KSZ9897_GBESR 0x0F
96 #define KSZ9897_RLB 0x11
97 #define KSZ9897_LINKMD 0x12
98 #define KSZ9897_DPMAPCSS 0x13
99 #define KSZ9897_RXERCTR 0x15
100 #define KSZ9897_ICSR 0x1B
101 #define KSZ9897_AUTOMDI 0x1C
102 #define KSZ9897_PHYCON 0x1F
103 
104 //KSZ9897 MMD registers
105 #define KSZ9897_MMD_LED_MODE 0x02, 0x00
106 #define KSZ9897_MMD_EEE_ADV 0x07, 0x3C
107 
108 //KSZ9897 SGMII registers
109 #define KSZ9897_SGMII_CTRL 0x1F0000
110 #define KSZ9897_SGMII_STATUS 0x1F0001
111 #define KSZ9897_SGMII_PHYID1 0x1F0002
112 #define KSZ9897_SGMII_PHYID2 0x1F0003
113 #define KSZ9897_SGMII_ANAR 0x1F0004
114 #define KSZ9897_SGMII_ANLPAR 0x1F0005
115 #define KSZ9897_SGMII_ANER 0x1F0006
116 #define KSZ9897_SGMII_DIGITAL_CTRL 0x1F8000
117 #define KSZ9897_SGMII_AN_CTRL 0x1F8001
118 #define KSZ9897_SGMII_AN_STATUS 0x1F8002
119 
120 //KSZ9897 Switch registers
121 #define KSZ9897_CHIP_ID0 0x0000
122 #define KSZ9897_CHIP_ID1 0x0001
123 #define KSZ9897_CHIP_ID2 0x0002
124 #define KSZ9897_CHIP_ID3 0x0003
125 #define KSZ9897_PME_PIN_CTRL 0x0006
126 #define KSZ9897_GLOBAL_INT_STAT 0x0010
127 #define KSZ9897_GLOBAL_INT_MASK 0x0014
128 #define KSZ9897_GLOBAL_PORT_INT_STAT 0x0018
129 #define KSZ9897_GLOBAL_PORT_INT_MASK 0x001C
130 #define KSZ9897_SERIAL_IO_CTRL 0x0100
131 #define KSZ9897_OUT_CLK_CTRL 0x0103
132 #define KSZ9897_IBA_CTRL 0x0104
133 #define KSZ9897_IO_DRIVE_STRENGTH 0x010D
134 #define KSZ9897_IBA_OP_STAT1 0x0110
135 #define KSZ9897_LED_OVERRIDE 0x0120
136 #define KSZ9897_LED_OUTPUT 0x0124
137 #define KSZ9897_PWR_DOWN_CTRL0 0x0201
138 #define KSZ9897_LED_STRAP_IN 0x0210
139 #define KSZ9897_SWITCH_OP 0x0300
140 #define KSZ9897_SWITCH_MAC_ADDR0 0x0302
141 #define KSZ9897_SWITCH_MAC_ADDR1 0x0303
142 #define KSZ9897_SWITCH_MAC_ADDR2 0x0304
143 #define KSZ9897_SWITCH_MAC_ADDR3 0x0305
144 #define KSZ9897_SWITCH_MAC_ADDR4 0x0306
145 #define KSZ9897_SWITCH_MAC_ADDR5 0x0307
146 #define KSZ9897_SWITCH_MTU 0x0308
147 #define KSZ9897_SWITCH_ISP_TPID 0x030A
148 #define KSZ9897_SWITCH_LUE_CTRL0 0x0310
149 #define KSZ9897_SWITCH_LUE_CTRL1 0x0311
150 #define KSZ9897_SWITCH_LUE_CTRL2 0x0312
151 #define KSZ9897_SWITCH_LUE_CTRL3 0x0313
152 #define KSZ9897_ALU_TABLE_INT 0x0314
153 #define KSZ9897_ALU_TABLE_MASK 0x0315
154 #define KSZ9897_ALU_TABLE_ENTRY_INDEX0 0x0316
155 #define KSZ9897_ALU_TABLE_ENTRY_INDEX1 0x0318
156 #define KSZ9897_ALU_TABLE_ENTRY_INDEX2 0x031A
157 #define KSZ9897_UNKNOWN_UNICAST_CTRL 0x0320
158 #define KSZ9897_UNKONWN_MULTICAST_CTRL 0x0324
159 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL 0x0328
160 #define KSZ9897_SWITCH_MAC_CTRL0 0x0330
161 #define KSZ9897_SWITCH_MAC_CTRL1 0x0331
162 #define KSZ9897_SWITCH_MAC_CTRL2 0x0332
163 #define KSZ9897_SWITCH_MAC_CTRL3 0x0333
164 #define KSZ9897_SWITCH_MAC_CTRL4 0x0334
165 #define KSZ9897_SWITCH_MAC_CTRL5 0x0335
166 #define KSZ9897_SWITCH_MIB_CTRL 0x0336
167 #define KSZ9897_802_1P_PRIO_MAPPING0 0x0338
168 #define KSZ9897_802_1P_PRIO_MAPPING1 0x0339
169 #define KSZ9897_802_1P_PRIO_MAPPING2 0x033A
170 #define KSZ9897_802_1P_PRIO_MAPPING3 0x033B
171 #define KSZ9897_IP_DIFFSERV_PRIO_EN 0x033E
172 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING0 0x0340
173 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING1 0x0341
174 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING2 0x0342
175 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING3 0x0343
176 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING4 0x0344
177 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING5 0x0345
178 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING6 0x0346
179 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING7 0x0347
180 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING8 0x0348
181 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING9 0x0349
182 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING10 0x034A
183 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING11 0x034B
184 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING12 0x034C
185 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING13 0x034D
186 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING14 0x034E
187 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING15 0x034F
188 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING16 0x0350
189 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING17 0x0351
190 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING18 0x0352
191 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING19 0x0353
192 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING20 0x0354
193 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING21 0x0355
194 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING22 0x0356
195 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING23 0x0357
196 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING24 0x0358
197 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING25 0x0359
198 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING26 0x035A
199 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING27 0x035B
200 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING28 0x035C
201 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING29 0x035D
202 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING30 0x035E
203 #define KSZ9897_IP_DIFFSERV_PRIO_MAPPING31 0x035F
204 #define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL 0x0370
205 #define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING 0x0378
206 #define KSZ9897_QUEUE_MGMT_CTRL0 0x0390
207 #define KSZ9897_VLAN_TABLE_ENTRY0 0x0400
208 #define KSZ9897_VLAN_TABLE_ENTRY1 0x0404
209 #define KSZ9897_VLAN_TABLE_ENTRY2 0x0408
210 #define KSZ9897_VLAN_TABLE_INDEX 0x040C
211 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL 0x040E
212 #define KSZ9897_ALU_TABLE_INDEX0 0x0410
213 #define KSZ9897_ALU_TABLE_INDEX1 0x0414
214 #define KSZ9897_ALU_TABLE_CTRL 0x0418
215 #define KSZ9897_STATIC_MCAST_TABLE_CTRL 0x041C
216 #define KSZ9897_ALU_TABLE_ENTRY1 0x0420
217 #define KSZ9897_STATIC_TABLE_ENTRY1 0x0420
218 #define KSZ9897_ALU_TABLE_ENTRY2 0x0424
219 #define KSZ9897_STATIC_TABLE_ENTRY2 0x0424
220 #define KSZ9897_RES_MCAST_TABLE_ENTRY2 0x0424
221 #define KSZ9897_ALU_TABLE_ENTRY3 0x0428
222 #define KSZ9897_STATIC_TABLE_ENTRY3 0x0428
223 #define KSZ9897_ALU_TABLE_ENTRY4 0x042C
224 #define KSZ9897_STATIC_TABLE_ENTRY4 0x042C
225 #define KSZ9897_PORT1_DEFAULT_TAG0 0x1000
226 #define KSZ9897_PORT1_DEFAULT_TAG1 0x1001
227 #define KSZ9897_PORT1_PME_WOL_EVENT 0x1013
228 #define KSZ9897_PORT1_PME_WOL_EN 0x1017
229 #define KSZ9897_PORT1_INT_STATUS 0x101B
230 #define KSZ9897_PORT1_INT_MASK 0x101F
231 #define KSZ9897_PORT1_OP_CTRL0 0x1020
232 #define KSZ9897_PORT1_STATUS 0x1030
233 #define KSZ9897_PORT1_MAC_CTRL0 0x1400
234 #define KSZ9897_PORT1_MAC_CTRL1 0x1401
235 #define KSZ9897_PORT1_IG_RATE_LIMIT_CTRL 0x1403
236 #define KSZ9897_PORT1_PRIO0_IG_LIMIT_CTRL 0x1410
237 #define KSZ9897_PORT1_PRIO1_IG_LIMIT_CTRL 0x1411
238 #define KSZ9897_PORT1_PRIO2_IG_LIMIT_CTRL 0x1412
239 #define KSZ9897_PORT1_PRIO3_IG_LIMIT_CTRL 0x1413
240 #define KSZ9897_PORT1_PRIO4_IG_LIMIT_CTRL 0x1414
241 #define KSZ9897_PORT1_PRIO5_IG_LIMIT_CTRL 0x1415
242 #define KSZ9897_PORT1_PRIO6_IG_LIMIT_CTRL 0x1416
243 #define KSZ9897_PORT1_PRIO7_IG_LIMIT_CTRL 0x1417
244 #define KSZ9897_PORT1_QUEUE0_EG_LIMIT_CTRL 0x1420
245 #define KSZ9897_PORT1_QUEUE1_EG_LIMIT_CTRL 0x1421
246 #define KSZ9897_PORT1_QUEUE2_EG_LIMIT_CTRL 0x1422
247 #define KSZ9897_PORT1_QUEUE3_EG_LIMIT_CTRL 0x1423
248 #define KSZ9897_PORT1_MIB_CTRL_STAT 0x1500
249 #define KSZ9897_PORT1_MIB_DATA 0x1504
250 #define KSZ9897_PORT1_ACL_ACCESS0 0x1600
251 #define KSZ9897_PORT1_ACL_ACCESS1 0x1601
252 #define KSZ9897_PORT1_ACL_ACCESS2 0x1602
253 #define KSZ9897_PORT1_ACL_ACCESS3 0x1603
254 #define KSZ9897_PORT1_ACL_ACCESS4 0x1604
255 #define KSZ9897_PORT1_ACL_ACCESS5 0x1605
256 #define KSZ9897_PORT1_ACL_ACCESS6 0x1606
257 #define KSZ9897_PORT1_ACL_ACCESS7 0x1607
258 #define KSZ9897_PORT1_ACL_ACCESS8 0x1608
259 #define KSZ9897_PORT1_ACL_ACCESS9 0x1609
260 #define KSZ9897_PORT1_ACL_ACCESS10 0x160A
261 #define KSZ9897_PORT1_ACL_ACCESS11 0x160B
262 #define KSZ9897_PORT1_ACL_ACCESS12 0x160C
263 #define KSZ9897_PORT1_ACL_ACCESS13 0x160D
264 #define KSZ9897_PORT1_ACL_ACCESS14 0x160E
265 #define KSZ9897_PORT1_ACL_ACCESS15 0x160F
266 #define KSZ9897_PORT1_ACL_BYTE_EN_MSB 0x1610
267 #define KSZ9897_PORT1_ACL_BYTE_EN_LSB 0x1611
268 #define KSZ9897_PORT1_ACL_ACCESS_CTRL0 0x1612
269 #define KSZ9897_PORT1_MIRRORING_CTRL 0x1800
270 #define KSZ9897_PORT1_PRIO_CTRL 0x1801
271 #define KSZ9897_PORT1_IG_MAC_CTRL 0x1802
272 #define KSZ9897_PORT1_AUTH_CTRL 0x1803
273 #define KSZ9897_PORT1_PTR 0x1804
274 #define KSZ9897_PORT1_PRIO_TO_QUEUE_MAPPING 0x1808
275 #define KSZ9897_PORT1_POLICE_CTRL 0x180C
276 #define KSZ9897_PORT1_POLICE_QUEUE_RATE 0x1820
277 #define KSZ9897_PORT1_POLICE_QUEUE_BURST_SIZE 0x1824
278 #define KSZ9897_PORT1_WRED_PKT_MEM_CTRL0 0x1830
279 #define KSZ9897_PORT1_WRED_PKT_MEM_CTRL1 0x1834
280 #define KSZ9897_PORT1_WRED_QUEUE_CTRL0 0x1840
281 #define KSZ9897_PORT1_WRED_QUEUE_CTRL1 0x1844
282 #define KSZ9897_PORT1_WRED_QUEUE_PERF_MON_CTRL 0x1848
283 #define KSZ9897_PORT1_TX_QUEUE_INDEX 0x1900
284 #define KSZ9897_PORT1_TX_QUEUE_PVID 0x1904
285 #define KSZ9897_PORT1_TX_QUEUE_CTRL0 0x1914
286 #define KSZ9897_PORT1_TX_QUEUE_CTRL1 0x1915
287 #define KSZ9897_PORT1_CTRL0 0x1A00
288 #define KSZ9897_PORT1_CTRL1 0x1A04
289 #define KSZ9897_PORT1_CTRL2 0x1B00
290 #define KSZ9897_PORT1_MSTP_PTR 0x1B01
291 #define KSZ9897_PORT1_MSTP_STATE 0x1B04
292 #define KSZ9897_PORT2_DEFAULT_TAG0 0x2000
293 #define KSZ9897_PORT2_DEFAULT_TAG1 0x2001
294 #define KSZ9897_PORT2_PME_WOL_EVENT 0x2013
295 #define KSZ9897_PORT2_PME_WOL_EN 0x2017
296 #define KSZ9897_PORT2_INT_STATUS 0x201B
297 #define KSZ9897_PORT2_INT_MASK 0x201F
298 #define KSZ9897_PORT2_OP_CTRL0 0x2020
299 #define KSZ9897_PORT2_STATUS 0x2030
300 #define KSZ9897_PORT2_MAC_CTRL0 0x2400
301 #define KSZ9897_PORT2_MAC_CTRL1 0x2401
302 #define KSZ9897_PORT2_IG_RATE_LIMIT_CTRL 0x2403
303 #define KSZ9897_PORT2_PRIO0_IG_LIMIT_CTRL 0x2410
304 #define KSZ9897_PORT2_PRIO1_IG_LIMIT_CTRL 0x2411
305 #define KSZ9897_PORT2_PRIO2_IG_LIMIT_CTRL 0x2412
306 #define KSZ9897_PORT2_PRIO3_IG_LIMIT_CTRL 0x2413
307 #define KSZ9897_PORT2_PRIO4_IG_LIMIT_CTRL 0x2414
308 #define KSZ9897_PORT2_PRIO5_IG_LIMIT_CTRL 0x2415
309 #define KSZ9897_PORT2_PRIO6_IG_LIMIT_CTRL 0x2416
310 #define KSZ9897_PORT2_PRIO7_IG_LIMIT_CTRL 0x2417
311 #define KSZ9897_PORT2_QUEUE0_EG_LIMIT_CTRL 0x2420
312 #define KSZ9897_PORT2_QUEUE1_EG_LIMIT_CTRL 0x2421
313 #define KSZ9897_PORT2_QUEUE2_EG_LIMIT_CTRL 0x2422
314 #define KSZ9897_PORT2_QUEUE3_EG_LIMIT_CTRL 0x2423
315 #define KSZ9897_PORT2_MIB_CTRL_STAT 0x2500
316 #define KSZ9897_PORT2_MIB_DATA 0x2504
317 #define KSZ9897_PORT2_ACL_ACCESS0 0x2600
318 #define KSZ9897_PORT2_ACL_ACCESS1 0x2601
319 #define KSZ9897_PORT2_ACL_ACCESS2 0x2602
320 #define KSZ9897_PORT2_ACL_ACCESS3 0x2603
321 #define KSZ9897_PORT2_ACL_ACCESS4 0x2604
322 #define KSZ9897_PORT2_ACL_ACCESS5 0x2605
323 #define KSZ9897_PORT2_ACL_ACCESS6 0x2606
324 #define KSZ9897_PORT2_ACL_ACCESS7 0x2607
325 #define KSZ9897_PORT2_ACL_ACCESS8 0x2608
326 #define KSZ9897_PORT2_ACL_ACCESS9 0x2609
327 #define KSZ9897_PORT2_ACL_ACCESS10 0x260A
328 #define KSZ9897_PORT2_ACL_ACCESS11 0x260B
329 #define KSZ9897_PORT2_ACL_ACCESS12 0x260C
330 #define KSZ9897_PORT2_ACL_ACCESS13 0x260D
331 #define KSZ9897_PORT2_ACL_ACCESS14 0x260E
332 #define KSZ9897_PORT2_ACL_ACCESS15 0x260F
333 #define KSZ9897_PORT2_ACL_BYTE_EN_MSB 0x2610
334 #define KSZ9897_PORT2_ACL_BYTE_EN_LSB 0x2611
335 #define KSZ9897_PORT2_ACL_ACCESS_CTRL0 0x2612
336 #define KSZ9897_PORT2_MIRRORING_CTRL 0x2800
337 #define KSZ9897_PORT2_PRIO_CTRL 0x2801
338 #define KSZ9897_PORT2_IG_MAC_CTRL 0x2802
339 #define KSZ9897_PORT2_AUTH_CTRL 0x2803
340 #define KSZ9897_PORT2_PTR 0x2804
341 #define KSZ9897_PORT2_PRIO_TO_QUEUE_MAPPING 0x2808
342 #define KSZ9897_PORT2_POLICE_CTRL 0x280C
343 #define KSZ9897_PORT2_POLICE_QUEUE_RATE 0x2820
344 #define KSZ9897_PORT2_POLICE_QUEUE_BURST_SIZE 0x2824
345 #define KSZ9897_PORT2_WRED_PKT_MEM_CTRL0 0x2830
346 #define KSZ9897_PORT2_WRED_PKT_MEM_CTRL1 0x2834
347 #define KSZ9897_PORT2_WRED_QUEUE_CTRL0 0x2840
348 #define KSZ9897_PORT2_WRED_QUEUE_CTRL1 0x2844
349 #define KSZ9897_PORT2_WRED_QUEUE_PERF_MON_CTRL 0x2848
350 #define KSZ9897_PORT2_TX_QUEUE_INDEX 0x2900
351 #define KSZ9897_PORT2_TX_QUEUE_PVID 0x2904
352 #define KSZ9897_PORT2_TX_QUEUE_CTRL0 0x2914
353 #define KSZ9897_PORT2_TX_QUEUE_CTRL1 0x2915
354 #define KSZ9897_PORT2_CTRL0 0x2A00
355 #define KSZ9897_PORT2_CTRL1 0x2A04
356 #define KSZ9897_PORT2_CTRL2 0x2B00
357 #define KSZ9897_PORT2_MSTP_PTR 0x2B01
358 #define KSZ9897_PORT2_MSTP_STATE 0x2B04
359 #define KSZ9897_PORT3_DEFAULT_TAG0 0x3000
360 #define KSZ9897_PORT3_DEFAULT_TAG1 0x3001
361 #define KSZ9897_PORT3_PME_WOL_EVENT 0x3013
362 #define KSZ9897_PORT3_PME_WOL_EN 0x3017
363 #define KSZ9897_PORT3_INT_STATUS 0x301B
364 #define KSZ9897_PORT3_INT_MASK 0x301F
365 #define KSZ9897_PORT3_OP_CTRL0 0x3020
366 #define KSZ9897_PORT3_STATUS 0x3030
367 #define KSZ9897_PORT3_MAC_CTRL0 0x3400
368 #define KSZ9897_PORT3_MAC_CTRL1 0x3401
369 #define KSZ9897_PORT3_IG_RATE_LIMIT_CTRL 0x3403
370 #define KSZ9897_PORT3_PRIO0_IG_LIMIT_CTRL 0x3410
371 #define KSZ9897_PORT3_PRIO1_IG_LIMIT_CTRL 0x3411
372 #define KSZ9897_PORT3_PRIO2_IG_LIMIT_CTRL 0x3412
373 #define KSZ9897_PORT3_PRIO3_IG_LIMIT_CTRL 0x3413
374 #define KSZ9897_PORT3_PRIO4_IG_LIMIT_CTRL 0x3414
375 #define KSZ9897_PORT3_PRIO5_IG_LIMIT_CTRL 0x3415
376 #define KSZ9897_PORT3_PRIO6_IG_LIMIT_CTRL 0x3416
377 #define KSZ9897_PORT3_PRIO7_IG_LIMIT_CTRL 0x3417
378 #define KSZ9897_PORT3_QUEUE0_EG_LIMIT_CTRL 0x3420
379 #define KSZ9897_PORT3_QUEUE1_EG_LIMIT_CTRL 0x3421
380 #define KSZ9897_PORT3_QUEUE2_EG_LIMIT_CTRL 0x3422
381 #define KSZ9897_PORT3_QUEUE3_EG_LIMIT_CTRL 0x3423
382 #define KSZ9897_PORT3_MIB_CTRL_STAT 0x3500
383 #define KSZ9897_PORT3_MIB_DATA 0x3504
384 #define KSZ9897_PORT3_ACL_ACCESS0 0x3600
385 #define KSZ9897_PORT3_ACL_ACCESS1 0x3601
386 #define KSZ9897_PORT3_ACL_ACCESS2 0x3602
387 #define KSZ9897_PORT3_ACL_ACCESS3 0x3603
388 #define KSZ9897_PORT3_ACL_ACCESS4 0x3604
389 #define KSZ9897_PORT3_ACL_ACCESS5 0x3605
390 #define KSZ9897_PORT3_ACL_ACCESS6 0x3606
391 #define KSZ9897_PORT3_ACL_ACCESS7 0x3607
392 #define KSZ9897_PORT3_ACL_ACCESS8 0x3608
393 #define KSZ9897_PORT3_ACL_ACCESS9 0x3609
394 #define KSZ9897_PORT3_ACL_ACCESS10 0x360A
395 #define KSZ9897_PORT3_ACL_ACCESS11 0x360B
396 #define KSZ9897_PORT3_ACL_ACCESS12 0x360C
397 #define KSZ9897_PORT3_ACL_ACCESS13 0x360D
398 #define KSZ9897_PORT3_ACL_ACCESS14 0x360E
399 #define KSZ9897_PORT3_ACL_ACCESS15 0x360F
400 #define KSZ9897_PORT3_ACL_BYTE_EN_MSB 0x3610
401 #define KSZ9897_PORT3_ACL_BYTE_EN_LSB 0x3611
402 #define KSZ9897_PORT3_ACL_ACCESS_CTRL0 0x3612
403 #define KSZ9897_PORT3_MIRRORING_CTRL 0x3800
404 #define KSZ9897_PORT3_PRIO_CTRL 0x3801
405 #define KSZ9897_PORT3_IG_MAC_CTRL 0x3802
406 #define KSZ9897_PORT3_AUTH_CTRL 0x3803
407 #define KSZ9897_PORT3_PTR 0x3804
408 #define KSZ9897_PORT3_PRIO_TO_QUEUE_MAPPING 0x3808
409 #define KSZ9897_PORT3_POLICE_CTRL 0x380C
410 #define KSZ9897_PORT3_POLICE_QUEUE_RATE 0x3820
411 #define KSZ9897_PORT3_POLICE_QUEUE_BURST_SIZE 0x3824
412 #define KSZ9897_PORT3_WRED_PKT_MEM_CTRL0 0x3830
413 #define KSZ9897_PORT3_WRED_PKT_MEM_CTRL1 0x3834
414 #define KSZ9897_PORT3_WRED_QUEUE_CTRL0 0x3840
415 #define KSZ9897_PORT3_WRED_QUEUE_CTRL1 0x3844
416 #define KSZ9897_PORT3_WRED_QUEUE_PERF_MON_CTRL 0x3848
417 #define KSZ9897_PORT3_TX_QUEUE_INDEX 0x3900
418 #define KSZ9897_PORT3_TX_QUEUE_PVID 0x3904
419 #define KSZ9897_PORT3_TX_QUEUE_CTRL0 0x3914
420 #define KSZ9897_PORT3_TX_QUEUE_CTRL1 0x3915
421 #define KSZ9897_PORT3_CTRL0 0x3A00
422 #define KSZ9897_PORT3_CTRL1 0x3A04
423 #define KSZ9897_PORT3_CTRL2 0x3B00
424 #define KSZ9897_PORT3_MSTP_PTR 0x3B01
425 #define KSZ9897_PORT3_MSTP_STATE 0x3B04
426 #define KSZ9897_PORT4_DEFAULT_TAG0 0x4000
427 #define KSZ9897_PORT4_DEFAULT_TAG1 0x4001
428 #define KSZ9897_PORT4_PME_WOL_EVENT 0x4013
429 #define KSZ9897_PORT4_PME_WOL_EN 0x4017
430 #define KSZ9897_PORT4_INT_STATUS 0x401B
431 #define KSZ9897_PORT4_INT_MASK 0x401F
432 #define KSZ9897_PORT4_OP_CTRL0 0x4020
433 #define KSZ9897_PORT4_STATUS 0x4030
434 #define KSZ9897_PORT4_MAC_CTRL0 0x4400
435 #define KSZ9897_PORT4_MAC_CTRL1 0x4401
436 #define KSZ9897_PORT4_IG_RATE_LIMIT_CTRL 0x4403
437 #define KSZ9897_PORT4_PRIO0_IG_LIMIT_CTRL 0x4410
438 #define KSZ9897_PORT4_PRIO1_IG_LIMIT_CTRL 0x4411
439 #define KSZ9897_PORT4_PRIO2_IG_LIMIT_CTRL 0x4412
440 #define KSZ9897_PORT4_PRIO3_IG_LIMIT_CTRL 0x4413
441 #define KSZ9897_PORT4_PRIO4_IG_LIMIT_CTRL 0x4414
442 #define KSZ9897_PORT4_PRIO5_IG_LIMIT_CTRL 0x4415
443 #define KSZ9897_PORT4_PRIO6_IG_LIMIT_CTRL 0x4416
444 #define KSZ9897_PORT4_PRIO7_IG_LIMIT_CTRL 0x4417
445 #define KSZ9897_PORT4_QUEUE0_EG_LIMIT_CTRL 0x4420
446 #define KSZ9897_PORT4_QUEUE1_EG_LIMIT_CTRL 0x4421
447 #define KSZ9897_PORT4_QUEUE2_EG_LIMIT_CTRL 0x4422
448 #define KSZ9897_PORT4_QUEUE3_EG_LIMIT_CTRL 0x4423
449 #define KSZ9897_PORT4_MIB_CTRL_STAT 0x4500
450 #define KSZ9897_PORT4_MIB_DATA 0x4504
451 #define KSZ9897_PORT4_ACL_ACCESS0 0x4600
452 #define KSZ9897_PORT4_ACL_ACCESS1 0x4601
453 #define KSZ9897_PORT4_ACL_ACCESS2 0x4602
454 #define KSZ9897_PORT4_ACL_ACCESS3 0x4603
455 #define KSZ9897_PORT4_ACL_ACCESS4 0x4604
456 #define KSZ9897_PORT4_ACL_ACCESS5 0x4605
457 #define KSZ9897_PORT4_ACL_ACCESS6 0x4606
458 #define KSZ9897_PORT4_ACL_ACCESS7 0x4607
459 #define KSZ9897_PORT4_ACL_ACCESS8 0x4608
460 #define KSZ9897_PORT4_ACL_ACCESS9 0x4609
461 #define KSZ9897_PORT4_ACL_ACCESS10 0x460A
462 #define KSZ9897_PORT4_ACL_ACCESS11 0x460B
463 #define KSZ9897_PORT4_ACL_ACCESS12 0x460C
464 #define KSZ9897_PORT4_ACL_ACCESS13 0x460D
465 #define KSZ9897_PORT4_ACL_ACCESS14 0x460E
466 #define KSZ9897_PORT4_ACL_ACCESS15 0x460F
467 #define KSZ9897_PORT4_ACL_BYTE_EN_MSB 0x4610
468 #define KSZ9897_PORT4_ACL_BYTE_EN_LSB 0x4611
469 #define KSZ9897_PORT4_ACL_ACCESS_CTRL0 0x4612
470 #define KSZ9897_PORT4_MIRRORING_CTRL 0x4800
471 #define KSZ9897_PORT4_PRIO_CTRL 0x4801
472 #define KSZ9897_PORT4_IG_MAC_CTRL 0x4802
473 #define KSZ9897_PORT4_AUTH_CTRL 0x4803
474 #define KSZ9897_PORT4_PTR 0x4804
475 #define KSZ9897_PORT4_PRIO_TO_QUEUE_MAPPING 0x4808
476 #define KSZ9897_PORT4_POLICE_CTRL 0x480C
477 #define KSZ9897_PORT4_POLICE_QUEUE_RATE 0x4820
478 #define KSZ9897_PORT4_POLICE_QUEUE_BURST_SIZE 0x4824
479 #define KSZ9897_PORT4_WRED_PKT_MEM_CTRL0 0x4830
480 #define KSZ9897_PORT4_WRED_PKT_MEM_CTRL1 0x4834
481 #define KSZ9897_PORT4_WRED_QUEUE_CTRL0 0x4840
482 #define KSZ9897_PORT4_WRED_QUEUE_CTRL1 0x4844
483 #define KSZ9897_PORT4_WRED_QUEUE_PERF_MON_CTRL 0x4848
484 #define KSZ9897_PORT4_TX_QUEUE_INDEX 0x4900
485 #define KSZ9897_PORT4_TX_QUEUE_PVID 0x4904
486 #define KSZ9897_PORT4_TX_QUEUE_CTRL0 0x4914
487 #define KSZ9897_PORT4_TX_QUEUE_CTRL1 0x4915
488 #define KSZ9897_PORT4_CTRL0 0x4A00
489 #define KSZ9897_PORT4_CTRL1 0x4A04
490 #define KSZ9897_PORT4_CTRL2 0x4B00
491 #define KSZ9897_PORT4_MSTP_PTR 0x4B01
492 #define KSZ9897_PORT4_MSTP_STATE 0x4B04
493 #define KSZ9897_PORT5_DEFAULT_TAG0 0x5000
494 #define KSZ9897_PORT5_DEFAULT_TAG1 0x5001
495 #define KSZ9897_PORT5_PME_WOL_EVENT 0x5013
496 #define KSZ9897_PORT5_PME_WOL_EN 0x5017
497 #define KSZ9897_PORT5_INT_STATUS 0x501B
498 #define KSZ9897_PORT5_INT_MASK 0x501F
499 #define KSZ9897_PORT5_OP_CTRL0 0x5020
500 #define KSZ9897_PORT5_STATUS 0x5030
501 #define KSZ9897_PORT5_MAC_CTRL0 0x5400
502 #define KSZ9897_PORT5_MAC_CTRL1 0x5401
503 #define KSZ9897_PORT5_IG_RATE_LIMIT_CTRL 0x5403
504 #define KSZ9897_PORT5_PRIO0_IG_LIMIT_CTRL 0x5410
505 #define KSZ9897_PORT5_PRIO1_IG_LIMIT_CTRL 0x5411
506 #define KSZ9897_PORT5_PRIO2_IG_LIMIT_CTRL 0x5412
507 #define KSZ9897_PORT5_PRIO3_IG_LIMIT_CTRL 0x5413
508 #define KSZ9897_PORT5_PRIO4_IG_LIMIT_CTRL 0x5414
509 #define KSZ9897_PORT5_PRIO5_IG_LIMIT_CTRL 0x5415
510 #define KSZ9897_PORT5_PRIO6_IG_LIMIT_CTRL 0x5416
511 #define KSZ9897_PORT5_PRIO7_IG_LIMIT_CTRL 0x5417
512 #define KSZ9897_PORT5_QUEUE0_EG_LIMIT_CTRL 0x5420
513 #define KSZ9897_PORT5_QUEUE1_EG_LIMIT_CTRL 0x5421
514 #define KSZ9897_PORT5_QUEUE2_EG_LIMIT_CTRL 0x5422
515 #define KSZ9897_PORT5_QUEUE3_EG_LIMIT_CTRL 0x5423
516 #define KSZ9897_PORT5_MIB_CTRL_STAT 0x5500
517 #define KSZ9897_PORT5_MIB_DATA 0x5504
518 #define KSZ9897_PORT5_ACL_ACCESS0 0x5600
519 #define KSZ9897_PORT5_ACL_ACCESS1 0x5601
520 #define KSZ9897_PORT5_ACL_ACCESS2 0x5602
521 #define KSZ9897_PORT5_ACL_ACCESS3 0x5603
522 #define KSZ9897_PORT5_ACL_ACCESS4 0x5604
523 #define KSZ9897_PORT5_ACL_ACCESS5 0x5605
524 #define KSZ9897_PORT5_ACL_ACCESS6 0x5606
525 #define KSZ9897_PORT5_ACL_ACCESS7 0x5607
526 #define KSZ9897_PORT5_ACL_ACCESS8 0x5608
527 #define KSZ9897_PORT5_ACL_ACCESS9 0x5609
528 #define KSZ9897_PORT5_ACL_ACCESS10 0x560A
529 #define KSZ9897_PORT5_ACL_ACCESS11 0x560B
530 #define KSZ9897_PORT5_ACL_ACCESS12 0x560C
531 #define KSZ9897_PORT5_ACL_ACCESS13 0x560D
532 #define KSZ9897_PORT5_ACL_ACCESS14 0x560E
533 #define KSZ9897_PORT5_ACL_ACCESS15 0x560F
534 #define KSZ9897_PORT5_ACL_BYTE_EN_MSB 0x5610
535 #define KSZ9897_PORT5_ACL_BYTE_EN_LSB 0x5611
536 #define KSZ9897_PORT5_ACL_ACCESS_CTRL0 0x5612
537 #define KSZ9897_PORT5_MIRRORING_CTRL 0x5800
538 #define KSZ9897_PORT5_PRIO_CTRL 0x5801
539 #define KSZ9897_PORT5_IG_MAC_CTRL 0x5802
540 #define KSZ9897_PORT5_AUTH_CTRL 0x5803
541 #define KSZ9897_PORT5_PTR 0x5804
542 #define KSZ9897_PORT5_PRIO_TO_QUEUE_MAPPING 0x5808
543 #define KSZ9897_PORT5_POLICE_CTRL 0x580C
544 #define KSZ9897_PORT5_POLICE_QUEUE_RATE 0x5820
545 #define KSZ9897_PORT5_POLICE_QUEUE_BURST_SIZE 0x5824
546 #define KSZ9897_PORT5_WRED_PKT_MEM_CTRL0 0x5830
547 #define KSZ9897_PORT5_WRED_PKT_MEM_CTRL1 0x5834
548 #define KSZ9897_PORT5_WRED_QUEUE_CTRL0 0x5840
549 #define KSZ9897_PORT5_WRED_QUEUE_CTRL1 0x5844
550 #define KSZ9897_PORT5_WRED_QUEUE_PERF_MON_CTRL 0x5848
551 #define KSZ9897_PORT5_TX_QUEUE_INDEX 0x5900
552 #define KSZ9897_PORT5_TX_QUEUE_PVID 0x5904
553 #define KSZ9897_PORT5_TX_QUEUE_CTRL0 0x5914
554 #define KSZ9897_PORT5_TX_QUEUE_CTRL1 0x5915
555 #define KSZ9897_PORT5_CTRL0 0x5A00
556 #define KSZ9897_PORT5_CTRL1 0x5A04
557 #define KSZ9897_PORT5_CTRL2 0x5B00
558 #define KSZ9897_PORT5_MSTP_PTR 0x5B01
559 #define KSZ9897_PORT5_MSTP_STATE 0x5B04
560 #define KSZ9897_PORT6_DEFAULT_TAG0 0x6000
561 #define KSZ9897_PORT6_DEFAULT_TAG1 0x6001
562 #define KSZ9897_PORT6_PME_WOL_EVENT 0x6013
563 #define KSZ9897_PORT6_PME_WOL_EN 0x6017
564 #define KSZ9897_PORT6_INT_STATUS 0x601B
565 #define KSZ9897_PORT6_INT_MASK 0x601F
566 #define KSZ9897_PORT6_OP_CTRL0 0x6020
567 #define KSZ9897_PORT6_STATUS 0x6030
568 #define KSZ9897_PORT6_XMII_CTRL0 0x6300
569 #define KSZ9897_PORT6_XMII_CTRL1 0x6301
570 #define KSZ9897_PORT6_MAC_CTRL0 0x6400
571 #define KSZ9897_PORT6_MAC_CTRL1 0x6401
572 #define KSZ9897_PORT6_IG_RATE_LIMIT_CTRL 0x6403
573 #define KSZ9897_PORT6_PRIO0_IG_LIMIT_CTRL 0x6410
574 #define KSZ9897_PORT6_PRIO1_IG_LIMIT_CTRL 0x6411
575 #define KSZ9897_PORT6_PRIO2_IG_LIMIT_CTRL 0x6412
576 #define KSZ9897_PORT6_PRIO3_IG_LIMIT_CTRL 0x6413
577 #define KSZ9897_PORT6_PRIO4_IG_LIMIT_CTRL 0x6414
578 #define KSZ9897_PORT6_PRIO5_IG_LIMIT_CTRL 0x6415
579 #define KSZ9897_PORT6_PRIO6_IG_LIMIT_CTRL 0x6416
580 #define KSZ9897_PORT6_PRIO7_IG_LIMIT_CTRL 0x6417
581 #define KSZ9897_PORT6_QUEUE0_EG_LIMIT_CTRL 0x6420
582 #define KSZ9897_PORT6_QUEUE1_EG_LIMIT_CTRL 0x6421
583 #define KSZ9897_PORT6_QUEUE2_EG_LIMIT_CTRL 0x6422
584 #define KSZ9897_PORT6_QUEUE3_EG_LIMIT_CTRL 0x6423
585 #define KSZ9897_PORT6_MIB_CTRL_STAT 0x6500
586 #define KSZ9897_PORT6_MIB_DATA 0x6504
587 #define KSZ9897_PORT6_ACL_ACCESS0 0x6600
588 #define KSZ9897_PORT6_ACL_ACCESS1 0x6601
589 #define KSZ9897_PORT6_ACL_ACCESS2 0x6602
590 #define KSZ9897_PORT6_ACL_ACCESS3 0x6603
591 #define KSZ9897_PORT6_ACL_ACCESS4 0x6604
592 #define KSZ9897_PORT6_ACL_ACCESS5 0x6605
593 #define KSZ9897_PORT6_ACL_ACCESS6 0x6606
594 #define KSZ9897_PORT6_ACL_ACCESS7 0x6607
595 #define KSZ9897_PORT6_ACL_ACCESS8 0x6608
596 #define KSZ9897_PORT6_ACL_ACCESS9 0x6609
597 #define KSZ9897_PORT6_ACL_ACCESS10 0x660A
598 #define KSZ9897_PORT6_ACL_ACCESS11 0x660B
599 #define KSZ9897_PORT6_ACL_ACCESS12 0x660C
600 #define KSZ9897_PORT6_ACL_ACCESS13 0x660D
601 #define KSZ9897_PORT6_ACL_ACCESS14 0x660E
602 #define KSZ9897_PORT6_ACL_ACCESS15 0x660F
603 #define KSZ9897_PORT6_ACL_BYTE_EN_MSB 0x6610
604 #define KSZ9897_PORT6_ACL_BYTE_EN_LSB 0x6611
605 #define KSZ9897_PORT6_ACL_ACCESS_CTRL0 0x6612
606 #define KSZ9897_PORT6_MIRRORING_CTRL 0x6800
607 #define KSZ9897_PORT6_PRIO_CTRL 0x6801
608 #define KSZ9897_PORT6_IG_MAC_CTRL 0x6802
609 #define KSZ9897_PORT6_AUTH_CTRL 0x6803
610 #define KSZ9897_PORT6_PTR 0x6804
611 #define KSZ9897_PORT6_PRIO_TO_QUEUE_MAPPING 0x6808
612 #define KSZ9897_PORT6_POLICE_CTRL 0x680C
613 #define KSZ9897_PORT6_POLICE_QUEUE_RATE 0x6820
614 #define KSZ9897_PORT6_POLICE_QUEUE_BURST_SIZE 0x6824
615 #define KSZ9897_PORT6_WRED_PKT_MEM_CTRL0 0x6830
616 #define KSZ9897_PORT6_WRED_PKT_MEM_CTRL1 0x6834
617 #define KSZ9897_PORT6_WRED_QUEUE_CTRL0 0x6840
618 #define KSZ9897_PORT6_WRED_QUEUE_CTRL1 0x6844
619 #define KSZ9897_PORT6_WRED_QUEUE_PERF_MON_CTRL 0x6848
620 #define KSZ9897_PORT6_TX_QUEUE_INDEX 0x6900
621 #define KSZ9897_PORT6_TX_QUEUE_PVID 0x6904
622 #define KSZ9897_PORT6_TX_QUEUE_CTRL0 0x6914
623 #define KSZ9897_PORT6_TX_QUEUE_CTRL1 0x6915
624 #define KSZ9897_PORT6_CTRL0 0x6A00
625 #define KSZ9897_PORT6_CTRL1 0x6A04
626 #define KSZ9897_PORT6_CTRL2 0x6B00
627 #define KSZ9897_PORT6_MSTP_PTR 0x6B01
628 #define KSZ9897_PORT6_MSTP_STATE 0x6B04
629 #define KSZ9897_PORT7_DEFAULT_TAG0 0x7000
630 #define KSZ9897_PORT7_DEFAULT_TAG1 0x7001
631 #define KSZ9897_PORT7_PME_WOL_EVENT 0x7013
632 #define KSZ9897_PORT7_PME_WOL_EN 0x7017
633 #define KSZ9897_PORT7_INT_STATUS 0x701B
634 #define KSZ9897_PORT7_INT_MASK 0x701F
635 #define KSZ9897_PORT7_OP_CTRL0 0x7020
636 #define KSZ9897_PORT7_STATUS 0x7030
637 #define KSZ9897_PORT7_SGMII_ADDR 0x7200
638 #define KSZ9897_PORT7_SGMII_DATA 0x7206
639 #define KSZ9897_PORT7_XMII_CTRL0 0x7300
640 #define KSZ9897_PORT7_XMII_CTRL1 0x7301
641 #define KSZ9897_PORT7_MAC_CTRL0 0x7400
642 #define KSZ9897_PORT7_MAC_CTRL1 0x7401
643 #define KSZ9897_PORT7_IG_RATE_LIMIT_CTRL 0x7403
644 #define KSZ9897_PORT7_PRIO0_IG_LIMIT_CTRL 0x7410
645 #define KSZ9897_PORT7_PRIO1_IG_LIMIT_CTRL 0x7411
646 #define KSZ9897_PORT7_PRIO2_IG_LIMIT_CTRL 0x7412
647 #define KSZ9897_PORT7_PRIO3_IG_LIMIT_CTRL 0x7413
648 #define KSZ9897_PORT7_PRIO4_IG_LIMIT_CTRL 0x7414
649 #define KSZ9897_PORT7_PRIO5_IG_LIMIT_CTRL 0x7415
650 #define KSZ9897_PORT7_PRIO6_IG_LIMIT_CTRL 0x7416
651 #define KSZ9897_PORT7_PRIO7_IG_LIMIT_CTRL 0x7417
652 #define KSZ9897_PORT7_QUEUE0_EG_LIMIT_CTRL 0x7420
653 #define KSZ9897_PORT7_QUEUE1_EG_LIMIT_CTRL 0x7421
654 #define KSZ9897_PORT7_QUEUE2_EG_LIMIT_CTRL 0x7422
655 #define KSZ9897_PORT7_QUEUE3_EG_LIMIT_CTRL 0x7423
656 #define KSZ9897_PORT7_MIB_CTRL_STAT 0x7500
657 #define KSZ9897_PORT7_MIB_DATA 0x7504
658 #define KSZ9897_PORT7_ACL_ACCESS0 0x7600
659 #define KSZ9897_PORT7_ACL_ACCESS1 0x7601
660 #define KSZ9897_PORT7_ACL_ACCESS2 0x7602
661 #define KSZ9897_PORT7_ACL_ACCESS3 0x7603
662 #define KSZ9897_PORT7_ACL_ACCESS4 0x7604
663 #define KSZ9897_PORT7_ACL_ACCESS5 0x7605
664 #define KSZ9897_PORT7_ACL_ACCESS6 0x7606
665 #define KSZ9897_PORT7_ACL_ACCESS7 0x7607
666 #define KSZ9897_PORT7_ACL_ACCESS8 0x7608
667 #define KSZ9897_PORT7_ACL_ACCESS9 0x7609
668 #define KSZ9897_PORT7_ACL_ACCESS10 0x760A
669 #define KSZ9897_PORT7_ACL_ACCESS11 0x760B
670 #define KSZ9897_PORT7_ACL_ACCESS12 0x760C
671 #define KSZ9897_PORT7_ACL_ACCESS13 0x760D
672 #define KSZ9897_PORT7_ACL_ACCESS14 0x760E
673 #define KSZ9897_PORT7_ACL_ACCESS15 0x760F
674 #define KSZ9897_PORT7_ACL_BYTE_EN_MSB 0x7610
675 #define KSZ9897_PORT7_ACL_BYTE_EN_LSB 0x7611
676 #define KSZ9897_PORT7_ACL_ACCESS_CTRL0 0x7612
677 #define KSZ9897_PORT7_MIRRORING_CTRL 0x7800
678 #define KSZ9897_PORT7_PRIO_CTRL 0x7801
679 #define KSZ9897_PORT7_IG_MAC_CTRL 0x7802
680 #define KSZ9897_PORT7_AUTH_CTRL 0x7803
681 #define KSZ9897_PORT7_PTR 0x7804
682 #define KSZ9897_PORT7_PRIO_TO_QUEUE_MAPPING 0x7808
683 #define KSZ9897_PORT7_POLICE_CTRL 0x780C
684 #define KSZ9897_PORT7_POLICE_QUEUE_RATE 0x7820
685 #define KSZ9897_PORT7_POLICE_QUEUE_BURST_SIZE 0x7824
686 #define KSZ9897_PORT7_WRED_PKT_MEM_CTRL0 0x7830
687 #define KSZ9897_PORT7_WRED_PKT_MEM_CTRL1 0x7834
688 #define KSZ9897_PORT7_WRED_QUEUE_CTRL0 0x7840
689 #define KSZ9897_PORT7_WRED_QUEUE_CTRL1 0x7844
690 #define KSZ9897_PORT7_WRED_QUEUE_PERF_MON_CTRL 0x7848
691 #define KSZ9897_PORT7_TX_QUEUE_INDEX 0x7900
692 #define KSZ9897_PORT7_TX_QUEUE_PVID 0x7904
693 #define KSZ9897_PORT7_TX_QUEUE_CTRL0 0x7914
694 #define KSZ9897_PORT7_TX_QUEUE_CTRL1 0x7915
695 #define KSZ9897_PORT7_CTRL0 0x7A00
696 #define KSZ9897_PORT7_CTRL1 0x7A04
697 #define KSZ9897_PORT7_CTRL2 0x7B00
698 #define KSZ9897_PORT7_MSTP_PTR 0x7B01
699 #define KSZ9897_PORT7_MSTP_STATE 0x7B04
700 
701 //KSZ9897 Switch register access macros
702 #define KSZ9897_PORTn_DEFAULT_TAG0(port) (0x0000 + ((port) * 0x1000))
703 #define KSZ9897_PORTn_DEFAULT_TAG1(port) (0x0001 + ((port) * 0x1000))
704 #define KSZ9897_PORTn_PME_WOL_EVENT(port) (0x0013 + ((port) * 0x1000))
705 #define KSZ9897_PORTn_PME_WOL_EN(port) (0x0017 + ((port) * 0x1000))
706 #define KSZ9897_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
707 #define KSZ9897_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
708 #define KSZ9897_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
709 #define KSZ9897_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
710 #define KSZ9897_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
711 #define KSZ9897_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
712 #define KSZ9897_PORTn_MAC_CTRL0(port) (0x0400 + ((port) * 0x1000))
713 #define KSZ9897_PORTn_MAC_CTRL1(port) (0x0401 + ((port) * 0x1000))
714 #define KSZ9897_PORTn_IG_RATE_LIMIT_CTRL(port) (0x0403 + ((port) * 0x1000))
715 #define KSZ9897_PORTn_PRIO0_IG_LIMIT_CTRL(port) (0x0410 + ((port) * 0x1000))
716 #define KSZ9897_PORTn_PRIO1_IG_LIMIT_CTRL(port) (0x0411 + ((port) * 0x1000))
717 #define KSZ9897_PORTn_PRIO2_IG_LIMIT_CTRL(port) (0x0412 + ((port) * 0x1000))
718 #define KSZ9897_PORTn_PRIO3_IG_LIMIT_CTRL(port) (0x0413 + ((port) * 0x1000))
719 #define KSZ9897_PORTn_PRIO4_IG_LIMIT_CTRL(port) (0x0414 + ((port) * 0x1000))
720 #define KSZ9897_PORTn_PRIO5_IG_LIMIT_CTRL(port) (0x0415 + ((port) * 0x1000))
721 #define KSZ9897_PORTn_PRIO6_IG_LIMIT_CTRL(port) (0x0416 + ((port) * 0x1000))
722 #define KSZ9897_PORTn_PRIO7_IG_LIMIT_CTRL(port) (0x0417 + ((port) * 0x1000))
723 #define KSZ9897_PORTn_QUEUE0_EG_LIMIT_CTRL(port) (0x0420 + ((port) * 0x1000))
724 #define KSZ9897_PORTn_QUEUE1_EG_LIMIT_CTRL(port) (0x0421 + ((port) * 0x1000))
725 #define KSZ9897_PORTn_QUEUE2_EG_LIMIT_CTRL(port) (0x0422 + ((port) * 0x1000))
726 #define KSZ9897_PORTn_QUEUE3_EG_LIMIT_CTRL(port) (0x0423 + ((port) * 0x1000))
727 #define KSZ9897_PORTn_MIB_CTRL_STAT(port) (0x0500 + ((port) * 0x1000))
728 #define KSZ9897_PORTn_MIB_DATA(port) (0x0504 + ((port) * 0x1000))
729 #define KSZ9897_PORTn_ACL_ACCESS0(port) (0x0600 + ((port) * 0x1000))
730 #define KSZ9897_PORTn_ACL_ACCESS1(port) (0x0601 + ((port) * 0x1000))
731 #define KSZ9897_PORTn_ACL_ACCESS2(port) (0x0602 + ((port) * 0x1000))
732 #define KSZ9897_PORTn_ACL_ACCESS3(port) (0x0603 + ((port) * 0x1000))
733 #define KSZ9897_PORTn_ACL_ACCESS4(port) (0x0604 + ((port) * 0x1000))
734 #define KSZ9897_PORTn_ACL_ACCESS5(port) (0x0605 + ((port) * 0x1000))
735 #define KSZ9897_PORTn_ACL_ACCESS6(port) (0x0606 + ((port) * 0x1000))
736 #define KSZ9897_PORTn_ACL_ACCESS7(port) (0x0607 + ((port) * 0x1000))
737 #define KSZ9897_PORTn_ACL_ACCESS8(port) (0x0608 + ((port) * 0x1000))
738 #define KSZ9897_PORTn_ACL_ACCESS9(port) (0x0609 + ((port) * 0x1000))
739 #define KSZ9897_PORTn_ACL_ACCESS10(port) (0x060A + ((port) * 0x1000))
740 #define KSZ9897_PORTn_ACL_ACCESS11(port) (0x060B + ((port) * 0x1000))
741 #define KSZ9897_PORTn_ACL_ACCESS12(port) (0x060C + ((port) * 0x1000))
742 #define KSZ9897_PORTn_ACL_ACCESS13(port) (0x060D + ((port) * 0x1000))
743 #define KSZ9897_PORTn_ACL_ACCESS14(port) (0x060E + ((port) * 0x1000))
744 #define KSZ9897_PORTn_ACL_ACCESS15(port) (0x060F + ((port) * 0x1000))
745 #define KSZ9897_PORTn_ACL_BYTE_EN_MSB(port) (0x0610 + ((port) * 0x1000))
746 #define KSZ9897_PORTn_ACL_BYTE_EN_LSB(port) (0x0611 + ((port) * 0x1000))
747 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0(port) (0x0612 + ((port) * 0x1000))
748 #define KSZ9897_PORTn_MIRRORING_CTRL(port) (0x0800 + ((port) * 0x1000))
749 #define KSZ9897_PORTn_PRIO_CTRL(port) (0x0801 + ((port) * 0x1000))
750 #define KSZ9897_PORTn_IG_MAC_CTRL(port) (0x0802 + ((port) * 0x1000))
751 #define KSZ9897_PORTn_AUTH_CTRL(port) (0x0803 + ((port) * 0x1000))
752 #define KSZ9897_PORTn_PTR(port) (0x0804 + ((port) * 0x1000))
753 #define KSZ9897_PORTn_PRIO_TO_QUEUE_MAPPING(port) (0x0808 + ((port) * 0x1000))
754 #define KSZ9897_PORTn_POLICE_CTRL(port) (0x080C + ((port) * 0x1000))
755 #define KSZ9897_PORTn_POLICE_QUEUE_RATE(port) (0x0820 + ((port) * 0x1000))
756 #define KSZ9897_PORTn_POLICE_QUEUE_BURST_SIZE(port) (0x0824 + ((port) * 0x1000))
757 #define KSZ9897_PORTn_WRED_PKT_MEM_CTRL0(port) (0x0830 + ((port) * 0x1000))
758 #define KSZ9897_PORTn_WRED_PKT_MEM_CTRL1(port) (0x0834 + ((port) * 0x1000))
759 #define KSZ9897_PORTn_WRED_QUEUE_CTRL0(port) (0x0840 + ((port) * 0x1000))
760 #define KSZ9897_PORTn_WRED_QUEUE_CTRL1(port) (0x0844 + ((port) * 0x1000))
761 #define KSZ9897_PORTn_WRED_QUEUE_PERF_MON_CTRL(port) (0x0848 + ((port) * 0x1000))
762 #define KSZ9897_PORTn_TX_QUEUE_INDEX(port) (0x0900 + ((port) * 0x1000))
763 #define KSZ9897_PORTn_TX_QUEUE_PVID(port) (0x0904 + ((port) * 0x1000))
764 #define KSZ9897_PORTn_TX_QUEUE_CTRL0(port) (0x0914 + ((port) * 0x1000))
765 #define KSZ9897_PORTn_TX_QUEUE_CTRL1(port) (0x0915 + ((port) * 0x1000))
766 #define KSZ9897_PORTn_CTRL0(port) (0x0A00 + ((port) * 0x1000))
767 #define KSZ9897_PORTn_CTRL1(port) (0x0A04 + ((port) * 0x1000))
768 #define KSZ9897_PORTn_CTRL2(port) (0x0B00 + ((port) * 0x1000))
769 #define KSZ9897_PORTn_MSTP_PTR(port) (0x0B01 + ((port) * 0x1000))
770 #define KSZ9897_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
771 #define KSZ9897_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
772 
773 //PHY Basic Control register
774 #define KSZ9897_BMCR_RESET 0x8000
775 #define KSZ9897_BMCR_LOOPBACK 0x4000
776 #define KSZ9897_BMCR_SPEED_SEL_LSB 0x2000
777 #define KSZ9897_BMCR_AN_EN 0x1000
778 #define KSZ9897_BMCR_POWER_DOWN 0x0800
779 #define KSZ9897_BMCR_ISOLATE 0x0400
780 #define KSZ9897_BMCR_RESTART_AN 0x0200
781 #define KSZ9897_BMCR_DUPLEX_MODE 0x0100
782 #define KSZ9897_BMCR_COL_TEST 0x0080
783 #define KSZ9897_BMCR_SPEED_SEL_MSB 0x0040
784 
785 //PHY Basic Status register
786 #define KSZ9897_BMSR_100BT4 0x8000
787 #define KSZ9897_BMSR_100BTX_FD 0x4000
788 #define KSZ9897_BMSR_100BTX_HD 0x2000
789 #define KSZ9897_BMSR_10BT_FD 0x1000
790 #define KSZ9897_BMSR_10BT_HD 0x0800
791 #define KSZ9897_BMSR_EXTENDED_STATUS 0x0100
792 #define KSZ9897_BMSR_MF_PREAMBLE_SUPPR 0x0040
793 #define KSZ9897_BMSR_AN_COMPLETE 0x0020
794 #define KSZ9897_BMSR_REMOTE_FAULT 0x0010
795 #define KSZ9897_BMSR_AN_CAPABLE 0x0008
796 #define KSZ9897_BMSR_LINK_STATUS 0x0004
797 #define KSZ9897_BMSR_JABBER_DETECT 0x0002
798 #define KSZ9897_BMSR_EXTENDED_CAPABLE 0x0001
799 
800 //PHY ID High register
801 #define KSZ9897_PHYID1_DEFAULT 0x0022
802 
803 //PHY ID Low register
804 #define KSZ9897_PHYID2_DEFAULT 0x1631
805 
806 //PHY Auto-Negotiation Advertisement register
807 #define KSZ9897_ANAR_NEXT_PAGE 0x8000
808 #define KSZ9897_ANAR_REMOTE_FAULT 0x2000
809 #define KSZ9897_ANAR_PAUSE 0x0C00
810 #define KSZ9897_ANAR_100BT4 0x0200
811 #define KSZ9897_ANAR_100BTX_FD 0x0100
812 #define KSZ9897_ANAR_100BTX_HD 0x0080
813 #define KSZ9897_ANAR_10BT_FD 0x0040
814 #define KSZ9897_ANAR_10BT_HD 0x0020
815 #define KSZ9897_ANAR_SELECTOR 0x001F
816 #define KSZ9897_ANAR_SELECTOR_DEFAULT 0x0001
817 
818 //PHY Auto-Negotiation Link Partner Ability register
819 #define KSZ9897_ANLPAR_NEXT_PAGE 0x8000
820 #define KSZ9897_ANLPAR_ACK 0x4000
821 #define KSZ9897_ANLPAR_REMOTE_FAULT 0x2000
822 #define KSZ9897_ANLPAR_PAUSE 0x0C00
823 #define KSZ9897_ANLPAR_100BT4 0x0200
824 #define KSZ9897_ANLPAR_100BTX_FD 0x0100
825 #define KSZ9897_ANLPAR_100BTX_HD 0x0080
826 #define KSZ9897_ANLPAR_10BT_FD 0x0040
827 #define KSZ9897_ANLPAR_10BT_HD 0x0020
828 #define KSZ9897_ANLPAR_SELECTOR 0x001F
829 #define KSZ9897_ANLPAR_SELECTOR_DEFAULT 0x0001
830 
831 //PHY Auto-Negotiation Expansion Status register
832 #define KSZ9897_ANER_PAR_DETECT_FAULT 0x0010
833 #define KSZ9897_ANER_LP_NEXT_PAGE_ABLE 0x0008
834 #define KSZ9897_ANER_NEXT_PAGE_ABLE 0x0004
835 #define KSZ9897_ANER_PAGE_RECEIVED 0x0002
836 #define KSZ9897_ANER_LP_AN_ABLE 0x0001
837 
838 //PHY Auto-Negotiation Next Page register
839 #define KSZ9897_ANNPR_NEXT_PAGE 0x8000
840 #define KSZ9897_ANNPR_MSG_PAGE 0x2000
841 #define KSZ9897_ANNPR_ACK2 0x1000
842 #define KSZ9897_ANNPR_TOGGLE 0x0800
843 #define KSZ9897_ANNPR_MESSAGE 0x07FF
844 
845 //PHY Auto-Negotiation Link Partner Next Page Ability register
846 #define KSZ9897_ANLPNPR_NEXT_PAGE 0x8000
847 #define KSZ9897_ANLPNPR_ACK 0x4000
848 #define KSZ9897_ANLPNPR_MSG_PAGE 0x2000
849 #define KSZ9897_ANLPNPR_ACK2 0x1000
850 #define KSZ9897_ANLPNPR_TOGGLE 0x0800
851 #define KSZ9897_ANLPNPR_MESSAGE 0x07FF
852 
853 //PHY 1000BASE-T Control register
854 #define KSZ9897_GBCR_TEST_MODE 0xE000
855 #define KSZ9897_GBCR_MS_MAN_CONF_EN 0x1000
856 #define KSZ9897_GBCR_MS_MAN_CONF_VAL 0x0800
857 #define KSZ9897_GBCR_PORT_TYPE 0x0400
858 #define KSZ9897_GBCR_1000BT_FD 0x0200
859 #define KSZ9897_GBCR_1000BT_HD 0x0100
860 
861 //PHY 1000BASE-T Status register
862 #define KSZ9897_GBSR_MS_CONF_FAULT 0x8000
863 #define KSZ9897_GBSR_MS_CONF_RES 0x4000
864 #define KSZ9897_GBSR_LOCAL_RECEIVER_STATUS 0x2000
865 #define KSZ9897_GBSR_REMOTE_RECEIVER_STATUS 0x1000
866 #define KSZ9897_GBSR_LP_1000BT_FD 0x0800
867 #define KSZ9897_GBSR_LP_1000BT_HD 0x0400
868 #define KSZ9897_GBSR_IDLE_ERR_COUNT 0x00FF
869 
870 //PHY MMD Setup register
871 #define KSZ9897_MMDACR_FUNC 0xC000
872 #define KSZ9897_MMDACR_FUNC_ADDR 0x0000
873 #define KSZ9897_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
874 #define KSZ9897_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
875 #define KSZ9897_MMDACR_FUNC_DATA_POST_INC_W 0xC000
876 #define KSZ9897_MMDACR_DEVAD 0x001F
877 
878 //PHY Extended Status register
879 #define KSZ9897_GBESR_1000BX_FD 0x8000
880 #define KSZ9897_GBESR_1000BX_HD 0x4000
881 #define KSZ9897_GBESR_1000BT_FD 0x2000
882 #define KSZ9897_GBESR_1000BT_HD 0x1000
883 
884 //PHY Remote Loopback register
885 #define KSZ9897_RLB_REMOTE_LOOPBACK 0x0100
886 
887 //PHY LinkMD register
888 #define KSZ9897_LINKMD_TEST_EN 0x8000
889 #define KSZ9897_LINKMD_PAIR 0x3000
890 #define KSZ9897_LINKMD_PAIR_A 0x0000
891 #define KSZ9897_LINKMD_PAIR_B 0x1000
892 #define KSZ9897_LINKMD_PAIR_C 0x2000
893 #define KSZ9897_LINKMD_PAIR_D 0x3000
894 #define KSZ9897_LINKMD_STATUS 0x0300
895 #define KSZ9897_LINKMD_STATUS_NORMAL 0x0000
896 #define KSZ9897_LINKMD_STATUS_OPEN 0x0100
897 #define KSZ9897_LINKMD_STATUS_SHORT 0x0200
898 #define KSZ9897_LINKMD_RESULT 0x00FF
899 
900 //PHY Digital PMA/PCS Status register
901 #define KSZ9897_DPMAPCSS_1000BT_LINK_STATUS 0x0002
902 #define KSZ9897_DPMAPCSS_100BTX_LINK_STATUS 0x0001
903 
904 //Port Interrupt Control/Status register
905 #define KSZ9897_ICSR_JABBER_IE 0x8000
906 #define KSZ9897_ICSR_RECEIVE_ERROR_IE 0x4000
907 #define KSZ9897_ICSR_PAGE_RECEIVED_IE 0x2000
908 #define KSZ9897_ICSR_PAR_DETECT_FAULT_IE 0x1000
909 #define KSZ9897_ICSR_LP_ACK_IE 0x0800
910 #define KSZ9897_ICSR_LINK_DOWN_IE 0x0400
911 #define KSZ9897_ICSR_REMOTE_FAULT_IE 0x0200
912 #define KSZ9897_ICSR_LINK_UP_IE 0x0100
913 #define KSZ9897_ICSR_JABBER_IF 0x0080
914 #define KSZ9897_ICSR_RECEIVE_ERROR_IF 0x0040
915 #define KSZ9897_ICSR_PAGE_RECEIVED_IF 0x0020
916 #define KSZ9897_ICSR_PAR_DETECT_FAULT_IF 0x0010
917 #define KSZ9897_ICSR_LP_ACK_IF 0x0008
918 #define KSZ9897_ICSR_LINK_DOWN_IF 0x0004
919 #define KSZ9897_ICSR_REMOTE_FAULT_IF 0x0002
920 #define KSZ9897_ICSR_LINK_UP_IF 0x0001
921 
922 //PHY Auto MDI/MDI-X register
923 #define KSZ9897_AUTOMDI_MDI_SET 0x0080
924 #define KSZ9897_AUTOMDI_SWAP_OFF 0x0040
925 
926 //PHY Control register
927 #define KSZ9897_PHYCON_JABBER_EN 0x0200
928 #define KSZ9897_PHYCON_SPEED_1000BT 0x0040
929 #define KSZ9897_PHYCON_SPEED_100BTX 0x0020
930 #define KSZ9897_PHYCON_SPEED_10BT 0x0010
931 #define KSZ9897_PHYCON_DUPLEX_STATUS 0x0008
932 #define KSZ9897_PHYCON_1000BT_MS_STATUS 0x0004
933 
934 //MMD LED Mode register
935 #define KSZ9897_MMD_LED_MODE_LED_MODE 0x0010
936 #define KSZ9897_MMD_LED_MODE_LED_MODE_TRI_COLOR_DUAL 0x0000
937 #define KSZ9897_MMD_LED_MODE_LED_MODE_SINGLE 0x0010
938 #define KSZ9897_MMD_LED_MODE_RESERVED 0x000F
939 #define KSZ9897_MMD_LED_MODE_RESERVED_DEFAULT 0x0001
940 
941 //MMD EEE Advertisement register
942 #define KSZ9897_MMD_EEE_ADV_1000BT_EEE_EN 0x0004
943 #define KSZ9897_MMD_EEE_ADV_100BT_EEE_EN 0x0002
944 
945 //SGMII Control register
946 #define KSZ9897_SGMII_CTRL_SOFT_RESET 0x8000
947 #define KSZ9897_SGMII_CTRL_LOCAL_LOOPBACK 0x4000
948 #define KSZ9897_SGMII_CTRL_SPEED_SEL_LSB 0x2000
949 #define KSZ9897_SGMII_CTRL_AN_EN 0x1000
950 #define KSZ9897_SGMII_CTRL_POWER_DOWN 0x0800
951 #define KSZ9897_SGMII_CTRL_RESTART_AN 0x0200
952 #define KSZ9897_SGMII_CTRL_DUPLEX_MODE 0x0100
953 #define KSZ9897_SGMII_CTRL_SPEED_SEL_MSB 0x0040
954 
955 //SGMII Status register
956 #define KSZ9897_SGMII_STATUS_AN_COMPLETE 0x0020
957 #define KSZ9897_SGMII_STATUS_REMOTE_FAULT 0x0010
958 #define KSZ9897_SGMII_STATUS_LINK_STATUS 0x0004
959 
960 //SGMII PHY ID 1 register
961 #define KSZ9897_SGMII_PHYID1_DEFAULT 0x7996
962 
963 //SGMII PHY ID 2 register
964 #define KSZ9897_SGMII_PHYID2_DEFAULT 0xCED0
965 
966 //SGMII Auto-Negotiation Advertisement register
967 #define KSZ9897_SGMII_ANAR_NEXT_PAGE 0x8000
968 #define KSZ9897_SGMII_ANAR_REMOTE_FAULT 0x3000
969 #define KSZ9897_SGMII_ANAR_REMOTE_FAULT_NO_ERROR 0x0000
970 #define KSZ9897_SGMII_ANAR_REMOTE_FAULT_OFFINE 0x1000
971 #define KSZ9897_SGMII_ANAR_REMOTE_FAULT_LINK_FAILURE 0x2000
972 #define KSZ9897_SGMII_ANAR_REMOTE_FAULT_AN_ERROR 0x3000
973 #define KSZ9897_SGMII_ANAR_PAUSE 0x0180
974 #define KSZ9897_SGMII_ANAR_HALF_DUPLEX 0x0040
975 #define KSZ9897_SGMII_ANAR_FULL_DUPLEX 0x0020
976 
977 //SGMII Auto-Negotiation Link Partner Base Ability register
978 #define KSZ9897_SGMII_ANLPAR_NEXT_PAGE 0x8000
979 #define KSZ9897_SGMII_ANLPAR_ACK 0x4000
980 #define KSZ9897_SGMII_ANLPAR_REMOTE_FAULT 0x3000
981 #define KSZ9897_SGMII_ANLPAR_REMOTE_FAULT_NO_ERROR 0x0000
982 #define KSZ9897_SGMII_ANLPAR_REMOTE_FAULT_OFFINE 0x1000
983 #define KSZ9897_SGMII_ANLPAR_REMOTE_FAULT_LINK_FAILURE 0x2000
984 #define KSZ9897_SGMII_ANLPAR_REMOTE_FAULT_AN_ERROR 0x3000
985 #define KSZ9897_SGMII_ANLPAR_PAUSE 0x0180
986 #define KSZ9897_SGMII_ANLPAR_HALF_DUPLEX 0x0040
987 #define KSZ9897_SGMII_ANLPAR_FULL_DUPLEX 0x0020
988 
989 //SGMII Auto-Negotiation Expansion register
990 #define KSZ9897_SGMII_ANER_PAGE_RECEIVED 0x0002
991 
992 //SGMII Digital Control register
993 #define KSZ9897_SGMII_DIGITAL_CTRL_REMOTE_LOOPBACK 0x4000
994 #define KSZ9897_SGMII_DIGITAL_CTRL_POWER_SAVE 0x0800
995 
996 //SGMII Auto-Negotiation Control register
997 #define KSZ9897_SGMII_AN_CTRL_LINK_STATUS 0x0010
998 #define KSZ9897_SGMII_AN_CTRL_TX_CONFIG_MASTER 0x0008
999 #define KSZ9897_SGMII_AN_CTRL_PCS_MODE 0x0006
1000 #define KSZ9897_SGMII_AN_CTRL_PCS_MODE_SERDES 0x0000
1001 #define KSZ9897_SGMII_AN_CTRL_PCS_MODE_SGMII 0x0004
1002 #define KSZ9897_SGMII_AN_CTRL_AN_COMPLETE_INT_EN 0x0001
1003 
1004 //SGMII Auto-Negotiation Status register
1005 #define KSZ9897_SGMII_AN_STATUS_LINK_STATUS 0x0010
1006 #define KSZ9897_SGMII_AN_STATUS_LINK_SPEED 0x000C
1007 #define KSZ9897_SGMII_AN_STATUS_LINK_SPEED_10MBPS 0x0000
1008 #define KSZ9897_SGMII_AN_STATUS_LINK_SPEED_100MBPS 0x0004
1009 #define KSZ9897_SGMII_AN_STATUS_LINK_SPEED_1000MBPS 0x0008
1010 #define KSZ9897_SGMII_AN_STATUS_FULL_DUPLEX 0x0002
1011 #define KSZ9897_SGMII_AN_STATUS_AN_COMPLETE_INT 0x0001
1012 
1013 //Global Chip ID 0 register
1014 #define KSZ9897_CHIP_ID0_DEFAULT 0x00
1015 
1016 //Global Chip ID 1 register
1017 #define KSZ9897_CHIP_ID1_DEFAULT 0x98
1018 
1019 //Global Chip ID 2 register
1020 #define KSZ9897_CHIP_ID2_DEFAULT 0x97
1021 
1022 //Global Chip ID 3 register
1023 #define KSZ9897_CHIP_ID3_REVISION_ID 0xF0
1024 #define KSZ9897_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
1025 
1026 //PME Pin Control register
1027 #define KSZ9897_PME_PIN_CTRL_PME_PIN_OUT_EN 0x02
1028 #define KSZ9897_PME_PIN_CTRL_PME_PIN_OUT_POL 0x01
1029 
1030 //Global Interrupt Status register
1031 #define KSZ9897_GLOBAL_INT_STAT_LUE 0x80000000
1032 
1033 //Global Interrupt Mask register
1034 #define KSZ9897_GLOBAL_INT_MASK_LUE 0x80000000
1035 
1036 //Global Port Interrupt Status register
1037 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT7 0x00000040
1038 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT6 0x00000020
1039 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT5 0x00000010
1040 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT4 0x00000008
1041 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT3 0x00000004
1042 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT2 0x00000002
1043 #define KSZ9897_GLOBAL_PORT_INT_STAT_PORT1 0x00000001
1044 
1045 //Global Port Interrupt Mask register
1046 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT7 0x00000040
1047 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT6 0x00000020
1048 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT5 0x00000010
1049 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT4 0x00000008
1050 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT3 0x00000004
1051 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT2 0x00000002
1052 #define KSZ9897_GLOBAL_PORT_INT_MASK_PORT1 0x00000001
1053 
1054 //Serial I/O Control register
1055 #define KSZ9897_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPR 0x04
1056 #define KSZ9897_SERIAL_IO_CTRL_AUTO_SPI_DATA_OUT_EDGE_SEL 0x02
1057 #define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL 0x01
1058 #define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_FALLING 0x00
1059 #define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_RISING 0x01
1060 
1061 //Output Clock Control register
1062 #define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_EN 0x02
1063 #define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ 0x01
1064 #define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ_25MHZ 0x00
1065 #define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ_125MHZ 0x01
1066 
1067 //In-Band Management Control register
1068 #define KSZ9897_IBA_CTRL_IBA_EN 0x80000000
1069 #define KSZ9897_IBA_CTRL_DEST_MAC_ADDR_MATCH_EN 0x40000000
1070 #define KSZ9897_IBA_CTRL_IBA_RESET 0x20000000
1071 #define KSZ9897_IBA_CTRL_RESP_PRIO_QUEUE 0x00C00000
1072 #define KSZ9897_IBA_CTRL_RESP_PRIO_QUEUE_DEFAULT 0x00400000
1073 #define KSZ9897_IBA_CTRL_IBA_COMM 0x00070000
1074 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT1 0x00000000
1075 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT2 0x00010000
1076 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT3 0x00020000
1077 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT4 0x00030000
1078 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT5 0x00040000
1079 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT6 0x00050000
1080 #define KSZ9897_IBA_CTRL_IBA_COMM_PORT7 0x00060000
1081 #define KSZ9897_IBA_CTRL_TPID 0x0000FFFF
1082 #define KSZ9897_IBA_CTRL_TPID_DEFAULT 0x000040FE
1083 
1084 //I/O Drive Strength register
1085 #define KSZ9897_IO_DRIVE_STRENGTH_HIGH_SPEED_DRIVE_STRENGTH 0x70
1086 #define KSZ9897_IO_DRIVE_STRENGTH_LOW_SPEED_DRIVE_STRENGTH 0x07
1087 
1088 //In-Band Management Operation Status 1 register
1089 #define KSZ9897_IBA_OP_STAT1_GOOD_PKT_DETECT 0x80000000
1090 #define KSZ9897_IBA_OP_STAT1_RESP_PKT_TX_DONE 0x40000000
1091 #define KSZ9897_IBA_OP_STAT1_EXEC_DONE 0x20000000
1092 #define KSZ9897_IBA_OP_STAT1_MAC_ADDR_MISMATCH_ERR 0x00004000
1093 #define KSZ9897_IBA_OP_STAT1_ACCESS_FORMAT_ERR 0x00002000
1094 #define KSZ9897_IBA_OP_STAT1_ACCESS_CODE_ERR 0x00001000
1095 #define KSZ9897_IBA_OP_STAT1_ACCESS_CMD_ERR 0x00000800
1096 #define KSZ9897_IBA_OP_STAT1_OVERSIZE_PKT_ERR 0x00000400
1097 #define KSZ9897_IBA_OP_STAT1_ACCESS_CODE_ERR_LOC 0x0000007F
1098 
1099 //LED Override register
1100 #define KSZ9897_LED_OVERRIDE_OVERRIDE 0x000003FF
1101 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED1_0 0x00000001
1102 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED1_1 0x00000002
1103 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED2_0 0x00000004
1104 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED2_1 0x00000008
1105 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED3_0 0x00000010
1106 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED3_1 0x00000020
1107 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED4_0 0x00000040
1108 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED4_1 0x00000080
1109 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED5_0 0x00000100
1110 #define KSZ9897_LED_OVERRIDE_OVERRIDE_LED5_1 0x00000200
1111 
1112 //LED Output register
1113 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL 0x000003FF
1114 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED1_0 0x00000001
1115 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED1_1 0x00000002
1116 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED2_0 0x00000004
1117 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED2_1 0x00000008
1118 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED3_0 0x00000010
1119 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED3_1 0x00000020
1120 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED4_0 0x00000040
1121 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED4_1 0x00000080
1122 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED5_0 0x00000100
1123 #define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED5_1 0x00000200
1124 
1125 //Power Down Control 0 register
1126 #define KSZ9897_PWR_DOWN_CTRL0_PLL_PWR_DOWN 0x20
1127 #define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE 0x18
1128 #define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_NORMAL 0x00
1129 #define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_EDPD 0x08
1130 #define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
1131 
1132 //LED Strap-In register
1133 #define KSZ9897_LED_STRAP_IN_STRAP_IN 0x000003FF
1134 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED1_0 0x00000001
1135 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED1_1 0x00000002
1136 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED2_0 0x00000004
1137 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED2_1 0x00000008
1138 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED3_0 0x00000010
1139 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED3_1 0x00000020
1140 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED4_0 0x00000040
1141 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED4_1 0x00000080
1142 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED5_0 0x00000100
1143 #define KSZ9897_LED_STRAP_IN_STRAP_IN_LED5_1 0x00000200
1144 
1145 //Switch Operation register
1146 #define KSZ9897_SWITCH_OP_DOUBLE_TAG_EN 0x80
1147 #define KSZ9897_SWITCH_OP_SOFT_HARD_RESET 0x02
1148 #define KSZ9897_SWITCH_OP_START_SWITCH 0x01
1149 
1150 //Switch Maximum Transmit Unit register
1151 #define KSZ9897_SWITCH_MTU_MTU 0x3FFF
1152 #define KSZ9897_SWITCH_MTU_MTU_DEFAULT 0x07D0
1153 
1154 //Switch Lookup Engine Control 0 register
1155 #define KSZ9897_SWITCH_LUE_CTRL0_VLAN_EN 0x80
1156 #define KSZ9897_SWITCH_LUE_CTRL0_DROP_INVALID_VID 0x40
1157 #define KSZ9897_SWITCH_LUE_CTRL0_AGE_COUNT 0x38
1158 #define KSZ9897_SWITCH_LUE_CTRL0_AGE_COUNT_DEFAULT 0x20
1159 #define KSZ9897_SWITCH_LUE_CTRL0_RESERVED_MCAST_LOOKUP_EN 0x04
1160 #define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION 0x03
1161 #define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_NONE 0x00
1162 #define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_CRC 0x01
1163 #define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_XOR 0x02
1164 
1165 //Switch Lookup Engine Control 1 register
1166 #define KSZ9897_SWITCH_LUE_CTRL1_UNICAST_LEARNING_DIS 0x80
1167 #define KSZ9897_SWITCH_LUE_CTRL1_SELF_ADDR_FILT 0x40
1168 #define KSZ9897_SWITCH_LUE_CTRL1_FLUSH_ALU_TABLE 0x20
1169 #define KSZ9897_SWITCH_LUE_CTRL1_FLUSH_MSTP_ENTRIES 0x10
1170 #define KSZ9897_SWITCH_LUE_CTRL1_MCAST_SRC_ADDR_FILT 0x08
1171 #define KSZ9897_SWITCH_LUE_CTRL1_AGING_EN 0x04
1172 #define KSZ9897_SWITCH_LUE_CTRL1_FAST_AGING 0x02
1173 #define KSZ9897_SWITCH_LUE_CTRL1_LINK_DOWN_FLUSH 0x01
1174 
1175 //Switch Lookup Engine Control 2 register
1176 #define KSZ9897_SWITCH_LUE_CTRL2_DOUBLE_TAG_MCAST_TRAP 0x40
1177 #define KSZ9897_SWITCH_LUE_CTRL2_DYNAMIC_ENTRY_EG_VLAN_FILT 0x20
1178 #define KSZ9897_SWITCH_LUE_CTRL2_STATIC_ENTRY_EG_VLAN_FILT 0x10
1179 #define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION 0x0C
1180 #define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_NONE 0x00
1181 #define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_DYNAMIC 0x04
1182 #define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_STATIC 0x08
1183 #define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_BOTH 0x0C
1184 #define KSZ9897_SWITCH_LUE_CTRL2_MAC_ADDR_PRIORITY 0x03
1185 
1186 //Switch Lookup Engine Control 3 register
1187 #define KSZ9897_SWITCH_LUE_CTRL3_AGE_PERIOD 0xFF
1188 #define KSZ9897_SWITCH_LUE_CTRL3_AGE_PERIOD_DEFAULT 0x4B
1189 
1190 //Address Lookup Table Interrupt register
1191 #define KSZ9897_ALU_TABLE_INT_LEARN_FAIL 0x04
1192 #define KSZ9897_ALU_TABLE_INT_ALMOST_FULL 0x02
1193 #define KSZ9897_ALU_TABLE_INT_WRITE_FAIL 0x01
1194 
1195 //Address Lookup Table Mask register
1196 #define KSZ9897_ALU_TABLE_MASK_LEARN_FAIL 0x04
1197 #define KSZ9897_ALU_TABLE_MASK_ALMOST_FULL 0x02
1198 #define KSZ9897_ALU_TABLE_MASK_WRITE_FAIL 0x01
1199 
1200 //Address Lookup Table Entry Index 0 register
1201 #define KSZ9897_ALU_TABLE_ENTRY_INDEX0_ALMOST_FULL_ENTRY_INDEX 0x0FFF
1202 #define KSZ9897_ALU_TABLE_ENTRY_INDEX0_FAIL_WRITE_INDEX 0x03FF
1203 
1204 //Address Lookup Table Entry Index 1 register
1205 #define KSZ9897_ALU_TABLE_ENTRY_INDEX1_FAIL_LEARN_INDEX 0x03FF
1206 
1207 //Address Lookup Table Entry Index 2 register
1208 #define KSZ9897_ALU_TABLE_ENTRY_INDEX2_CPU_ACCESS_INDEX 0x03FF
1209 
1210 //Unknown Unicast Control register
1211 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD 0x80000000
1212 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP 0x0000007F
1213 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT1 0x00000001
1214 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT2 0x00000002
1215 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT3 0x00000004
1216 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT4 0x00000008
1217 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT5 0x00000010
1218 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT6 0x00000020
1219 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT7 0x00000040
1220 #define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_ALL 0x0000007F
1221 
1222 //Unknown Multicast Control register
1223 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD 0x80000000
1224 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP 0x0000007F
1225 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT1 0x00000001
1226 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT2 0x00000002
1227 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT3 0x00000004
1228 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT4 0x00000008
1229 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT5 0x00000010
1230 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT6 0x00000020
1231 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT7 0x00000040
1232 #define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_ALL 0x0000007F
1233 
1234 //Unknown VLAN ID Control register
1235 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD 0x80000000
1236 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP 0x0000007F
1237 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT1 0x00000001
1238 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT2 0x00000002
1239 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT3 0x00000004
1240 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT4 0x00000008
1241 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT5 0x00000010
1242 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT6 0x00000020
1243 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT7 0x00000040
1244 #define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_ALL 0x0000007F
1245 
1246 //Switch MAC Control 0 register
1247 #define KSZ9897_SWITCH_MAC_CTRL0_ALT_BACK_OFF_MODE 0x80
1248 #define KSZ9897_SWITCH_MAC_CTRL0_FRAME_LEN_CHECK_EN 0x08
1249 #define KSZ9897_SWITCH_MAC_CTRL0_FLOW_CTRL_PKT_DROP_MODE 0x02
1250 #define KSZ9897_SWITCH_MAC_CTRL0_AGGRESSIVE_BACK_OFF_EN 0x01
1251 
1252 //Switch MAC Control 1 register
1253 #define KSZ9897_SWITCH_MAC_CTRL1_MCAST_STORM_PROTECT_DIS 0x40
1254 #define KSZ9897_SWITCH_MAC_CTRL1_BACK_PRESSURE_MODE 0x20
1255 #define KSZ9897_SWITCH_MAC_CTRL1_FLOW_CTRL_FAIR_MODE 0x10
1256 #define KSZ9897_SWITCH_MAC_CTRL1_NO_EXCESSIVE_COL_DROP 0x08
1257 #define KSZ9897_SWITCH_MAC_CTRL1_JUMBO_PKT_SUPPORT 0x04
1258 #define KSZ9897_SWITCH_MAC_CTRL1_MAX_PKT_SIZE_CHECK_DIS 0x02
1259 #define KSZ9897_SWITCH_MAC_CTRL1_PASS_SHORT_PKT 0x01
1260 
1261 //Switch MAC Control 2 register
1262 #define KSZ9897_SWITCH_MAC_CTRL2_NULL_VID_REPLACEMENT 0x08
1263 #define KSZ9897_SWITCH_MAC_CTRL2_BCAST_STORM_PROTECT_RATE_MSB 0x07
1264 
1265 //Switch MAC Control 3 register
1266 #define KSZ9897_SWITCH_MAC_CTRL3_BCAST_STORM_PROTECT_RATE_LSB 0xFF
1267 
1268 //Switch MAC Control 4 register
1269 #define KSZ9897_SWITCH_MAC_CTRL4_PASS_FLOW_CTRL_PKT 0x01
1270 
1271 //Switch MAC Control 5 register
1272 #define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD 0x30
1273 #define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_16MS 0x00
1274 #define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_64MS 0x10
1275 #define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_256MS 0x20
1276 #define KSZ9897_SWITCH_MAC_CTRL5_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
1277 
1278 //Switch MIB Control register
1279 #define KSZ9897_SWITCH_MIB_CTRL_FLUSH 0x80
1280 #define KSZ9897_SWITCH_MIB_CTRL_FREEZE 0x40
1281 
1282 //Global Port Mirroring and Snooping Control register
1283 #define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_IGMP_SNOOP_EN 0x40
1284 #define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_OPT 0x08
1285 #define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_EN 0x04
1286 #define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_SNIFF_MODE_SEL 0x01
1287 
1288 //WRED DiffServ Color Mapping register
1289 #define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_RED 0x30
1290 #define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_YELLOW 0x0C
1291 #define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_GREEN 0x03
1292 
1293 //Queue Management Control 0 register
1294 #define KSZ9897_QUEUE_MGMT_CTRL0_PRIORITY_2Q 0x000000C0
1295 #define KSZ9897_QUEUE_MGMT_CTRL0_UNICAST_PORT_VLAN_DISCARD 0x00000002
1296 
1297 //VLAN Table Entry 0 register
1298 #define KSZ9897_VLAN_TABLE_ENTRY0_VALID 0x80000000
1299 #define KSZ9897_VLAN_TABLE_ENTRY0_FORWARD_OPTION 0x08000000
1300 #define KSZ9897_VLAN_TABLE_ENTRY0_PRIORITY 0x07000000
1301 #define KSZ9897_VLAN_TABLE_ENTRY0_MSTP_INDEX 0x00007000
1302 #define KSZ9897_VLAN_TABLE_ENTRY0_FID 0x0000007F
1303 
1304 //VLAN Table Entry 1 register
1305 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT_UNTAG 0x0000007F
1306 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT7_UNTAG 0x00000040
1307 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT6_UNTAG 0x00000020
1308 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT5_UNTAG 0x00000010
1309 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT4_UNTAG 0x00000008
1310 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT3_UNTAG 0x00000004
1311 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT2_UNTAG 0x00000002
1312 #define KSZ9897_VLAN_TABLE_ENTRY1_PORT1_UNTAG 0x00000001
1313 
1314 //VLAN Table Entry 2 register
1315 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1316 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1317 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1318 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1319 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1320 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1321 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1322 #define KSZ9897_VLAN_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1323 
1324 //VLAN Table Index register
1325 #define KSZ9897_VLAN_TABLE_INDEX_VLAN_INDEX 0x0FFF
1326 
1327 //VLAN Table Access Control register
1328 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_START_FINISH 0x80
1329 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION 0x03
1330 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_NOP 0x00
1331 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_WRITE 0x01
1332 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_READ 0x02
1333 #define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_CLEAR 0x03
1334 
1335 //ALU Table Index 0 register
1336 #define KSZ9897_ALU_TABLE_INDEX0_FID_INDEX 0x007F0000
1337 #define KSZ9897_ALU_TABLE_INDEX0_MAC_INDEX_MSB 0x0000FFFF
1338 
1339 //ALU Table Index 1 register
1340 #define KSZ9897_ALU_TABLE_INDEX1_MAC_INDEX_LSB 0xFFFFFFFF
1341 
1342 //ALU Table Access Control register
1343 #define KSZ9897_ALU_TABLE_CTRL_VALID_COUNT 0x3FFF0000
1344 #define KSZ9897_ALU_TABLE_CTRL_START_FINISH 0x00000080
1345 #define KSZ9897_ALU_TABLE_CTRL_VALID 0x00000040
1346 #define KSZ9897_ALU_TABLE_CTRL_VALID_ENTRY_OR_SEARCH_END 0x00000020
1347 #define KSZ9897_ALU_TABLE_CTRL_DIRECT 0x00000004
1348 #define KSZ9897_ALU_TABLE_CTRL_ACTION 0x00000003
1349 #define KSZ9897_ALU_TABLE_CTRL_ACTION_NOP 0x00000000
1350 #define KSZ9897_ALU_TABLE_CTRL_ACTION_WRITE 0x00000001
1351 #define KSZ9897_ALU_TABLE_CTRL_ACTION_READ 0x00000002
1352 #define KSZ9897_ALU_TABLE_CTRL_ACTION_SEARCH 0x00000003
1353 
1354 //Static Address and Reserved Multicast Table Control register
1355 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_TABLE_INDEX 0x003F0000
1356 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_START_FINISH 0x00000080
1357 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_TABLE_SELECT 0x00000002
1358 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_ACTION 0x00000001
1359 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_ACTION_READ 0x00000000
1360 #define KSZ9897_STATIC_MCAST_TABLE_CTRL_ACTION_WRITE 0x00000001
1361 
1362 //ALU Table Entry 1 register
1363 #define KSZ9897_ALU_TABLE_ENTRY1_STATIC 0x80000000
1364 #define KSZ9897_ALU_TABLE_ENTRY1_SRC_FILTER 0x40000000
1365 #define KSZ9897_ALU_TABLE_ENTRY1_DES_FILTER 0x20000000
1366 #define KSZ9897_ALU_TABLE_ENTRY1_PRIORITY 0x1C000000
1367 #define KSZ9897_ALU_TABLE_ENTRY1_AGE_COUNT 0x1C000000
1368 #define KSZ9897_ALU_TABLE_ENTRY1_MSTP 0x00000007
1369 
1370 //ALU Table Entry 2 register
1371 #define KSZ9897_ALU_TABLE_ENTRY2_OVERRIDE 0x80000000
1372 #define KSZ9897_ALU_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1373 #define KSZ9897_ALU_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1374 #define KSZ9897_ALU_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1375 #define KSZ9897_ALU_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1376 #define KSZ9897_ALU_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1377 #define KSZ9897_ALU_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1378 #define KSZ9897_ALU_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1379 #define KSZ9897_ALU_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1380 
1381 //ALU Table Entry 3 register
1382 #define KSZ9897_ALU_TABLE_ENTRY3_FID 0x007F0000
1383 #define KSZ9897_ALU_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1384 
1385 //ALU Table Entry 4 register
1386 #define KSZ9897_ALU_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1387 
1388 //Static Address Table Entry 1 register
1389 #define KSZ9897_STATIC_TABLE_ENTRY1_VALID 0x80000000
1390 #define KSZ9897_STATIC_TABLE_ENTRY1_SRC_FILTER 0x40000000
1391 #define KSZ9897_STATIC_TABLE_ENTRY1_DES_FILTER 0x20000000
1392 #define KSZ9897_STATIC_TABLE_ENTRY1_PRIORITY 0x1C000000
1393 #define KSZ9897_STATIC_TABLE_ENTRY1_MSTP 0x00000007
1394 
1395 //Static Address Table Entry 2 register
1396 #define KSZ9897_STATIC_TABLE_ENTRY2_OVERRIDE 0x80000000
1397 #define KSZ9897_STATIC_TABLE_ENTRY2_USE_FID 0x40000000
1398 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1399 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1400 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1401 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1402 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1403 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1404 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1405 #define KSZ9897_STATIC_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1406 
1407 //Static Address Table Entry 3 register
1408 #define KSZ9897_STATIC_TABLE_ENTRY3_FID 0x007F0000
1409 #define KSZ9897_STATIC_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1410 
1411 //Static Address Table Entry 4 register
1412 #define KSZ9897_STATIC_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1413 
1414 //Reserved Multicast Table Entry 2 register
1415 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1416 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1417 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1418 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1419 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1420 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1421 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1422 #define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1423 
1424 //Port N Default Tag 0 register
1425 #define KSZ9897_PORTn_DEFAULT_TAG0_PCP 0xE0
1426 #define KSZ9897_PORTn_DEFAULT_TAG0_DEI 0x10
1427 #define KSZ9897_PORTn_DEFAULT_TAG0_VID_MSB 0x0F
1428 
1429 //Port N Default Tag 1 register
1430 #define KSZ9897_PORTn_DEFAULT_TAG1_VID_LSB 0xFF
1431 
1432 //Port N Interrupt Status register
1433 #define KSZ9897_PORTn_INT_STATUS_SGMII_AN_DONE 0x08
1434 #define KSZ9897_PORTn_INT_STATUS_PHY 0x02
1435 #define KSZ9897_PORTn_INT_STATUS_ACL 0x01
1436 
1437 //Port N Interrupt Mask register
1438 #define KSZ9897_PORTn_INT_MASK_SGMII_AN_DONE 0x08
1439 #define KSZ9897_PORTn_INT_MASK_PHY 0x02
1440 #define KSZ9897_PORTn_INT_MASK_ACL 0x01
1441 
1442 //Port N Operation Control 0 register
1443 #define KSZ9897_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
1444 #define KSZ9897_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
1445 #define KSZ9897_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
1446 #define KSZ9897_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
1447 
1448 //Port N Status register
1449 #define KSZ9897_PORTn_STATUS_SPEED 0x18
1450 #define KSZ9897_PORTn_STATUS_SPEED_10MBPS 0x00
1451 #define KSZ9897_PORTn_STATUS_SPEED_100MBPS 0x08
1452 #define KSZ9897_PORTn_STATUS_SPEED_1000MBPS 0x10
1453 #define KSZ9897_PORTn_STATUS_DUPLEX 0x04
1454 #define KSZ9897_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
1455 #define KSZ9897_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
1456 
1457 //Port 7 SGMII Address register
1458 #define KSZ9897_PORT7_SGMII_ADDR_AUTO_INC_ENB 0x00800000
1459 #define KSZ9897_PORT7_SGMII_ADDR_SGMII_ADDR 0x001FFFFF
1460 
1461 //Port 7 SGMII Data register
1462 #define KSZ9897_PORT7_SGMII_DATA_SGMII_DATA 0xFFFF
1463 
1464 //XMII Port N Control 0 register
1465 #define KSZ9897_PORTn_XMII_CTRL0_DUPLEX 0x40
1466 #define KSZ9897_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
1467 #define KSZ9897_PORTn_XMII_CTRL0_SPEED_10_100 0x10
1468 #define KSZ9897_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
1469 
1470 //XMII Port N Control 1 register
1471 #define KSZ9897_PORTn_XMII_CTRL1_SPEED_1000 0x40
1472 #define KSZ9897_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
1473 #define KSZ9897_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
1474 #define KSZ9897_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
1475 #define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE 0x03
1476 #define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x00
1477 #define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
1478 #define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_MII 0x03
1479 
1480 //Port N MAC Control 0 register
1481 #define KSZ9897_PORTn_MAC_CTRL0_BCAST_STORM_PROTECT_EN 0x02
1482 
1483 //Port N MAC Control 1 register
1484 #define KSZ9897_PORTn_MAC_CTRL1_BACK_PRESSURE_EN 0x08
1485 #define KSZ9897_PORTn_MAC_CTRL1_PASS_ALL_FRAMES 0x01
1486 
1487 //Port N MIB Control and Status register
1488 #define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_COUNTER_OVERFLOW 0x80000000
1489 #define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_READ 0x02000000
1490 #define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_FLUSH_FREEZE 0x01000000
1491 #define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_INDEX 0x00FF0000
1492 #define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_COUNTER_VALUE_35_32 0x0000000F
1493 
1494 //Port N MIB Data register
1495 #define KSZ9897_PORTn_MIB_DATA_MIB_COUNTER_VALUE_31_0 0xFFFFFFFF
1496 
1497 //Port N ACL Access Control 0 register
1498 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0_WRITE_STATUS 0x40
1499 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0_READ_STATUS 0x20
1500 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0_READ 0x00
1501 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0_WRITE 0x10
1502 #define KSZ9897_PORTn_ACL_ACCESS_CTRL0_ACL_INDEX 0x0F
1503 
1504 //Port N Port Mirroring Control register
1505 #define KSZ9897_PORTn_MIRRORING_CTRL_RECEIVE_SNIFF 0x40
1506 #define KSZ9897_PORTn_MIRRORING_CTRL_TRANSMIT_SNIFF 0x20
1507 #define KSZ9897_PORTn_MIRRORING_CTRL_SNIFFER_PORT 0x02
1508 
1509 //Port N Authentication Control register
1510 #define KSZ9897_PORTn_AUTH_CTRL_ACL_EN 0x04
1511 #define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE 0x03
1512 #define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_PASS 0x00
1513 #define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_BLOCK 0x01
1514 #define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_TRAP 0x02
1515 
1516 //Port N Pointer register
1517 #define KSZ9897_PORTn_PTR_PORT_INDEX 0x00070000
1518 #define KSZ9897_PORTn_PTR_QUEUE_PTR 0x00000003
1519 
1520 //Port N Control 1 register
1521 #define KSZ9897_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x0000007F
1522 #define KSZ9897_PORTn_CTRL1_PORT7_VLAN_MEMBERSHIP 0x00000040
1523 #define KSZ9897_PORTn_CTRL1_PORT6_VLAN_MEMBERSHIP 0x00000020
1524 #define KSZ9897_PORTn_CTRL1_PORT5_VLAN_MEMBERSHIP 0x00000010
1525 #define KSZ9897_PORTn_CTRL1_PORT4_VLAN_MEMBERSHIP 0x00000008
1526 #define KSZ9897_PORTn_CTRL1_PORT3_VLAN_MEMBERSHIP 0x00000004
1527 #define KSZ9897_PORTn_CTRL1_PORT2_VLAN_MEMBERSHIP 0x00000002
1528 #define KSZ9897_PORTn_CTRL1_PORT1_VLAN_MEMBERSHIP 0x00000001
1529 
1530 //Port N Control 2 register
1531 #define KSZ9897_PORTn_CTRL2_NULL_VID_LOOKUP_EN 0x80
1532 #define KSZ9897_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
1533 #define KSZ9897_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
1534 #define KSZ9897_PORTn_CTRL2_802_1X_EN 0x10
1535 #define KSZ9897_PORTn_CTRL2_SELF_ADDR_FILT 0x08
1536 
1537 //Port N MSTP Pointer register
1538 #define KSZ9897_PORTn_MSTP_PTR_MSTP_PTR 0x07
1539 
1540 //Port N MSTP State register
1541 #define KSZ9897_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
1542 #define KSZ9897_PORTn_MSTP_STATE_RECEIVE_EN 0x02
1543 #define KSZ9897_PORTn_MSTP_STATE_LEARNING_DIS 0x01
1544 
1545 //C++ guard
1546 #ifdef __cplusplus
1547 extern "C" {
1548 #endif
1549 
1550 //KSZ9897 Ethernet switch driver
1551 extern const SwitchDriver ksz9897SwitchDriver;
1552 
1553 //KSZ9897 related functions
1554 error_t ksz9897Init(NetInterface *interface);
1555 void ksz9897InitHook(NetInterface *interface);
1556 
1557 void ksz9897Tick(NetInterface *interface);
1558 
1559 void ksz9897EnableIrq(NetInterface *interface);
1560 void ksz9897DisableIrq(NetInterface *interface);
1561 
1562 void ksz9897EventHandler(NetInterface *interface);
1563 
1564 error_t ksz9897TagFrame(NetInterface *interface, NetBuffer *buffer,
1565  size_t *offset, NetTxAncillary *ancillary);
1566 
1567 error_t ksz9897UntagFrame(NetInterface *interface, uint8_t **frame,
1568  size_t *length, NetRxAncillary *ancillary);
1569 
1570 bool_t ksz9897GetLinkState(NetInterface *interface, uint8_t port);
1571 uint32_t ksz9897GetLinkSpeed(NetInterface *interface, uint8_t port);
1573 
1575 uint32_t ksz9897GetPort7LinkSpeed(NetInterface *interface);
1577 
1578 void ksz9897SetPortState(NetInterface *interface, uint8_t port,
1579  SwitchPortState state);
1580 
1582 
1583 void ksz9897SetAgingTime(NetInterface *interface, uint32_t agingTime);
1584 
1585 void ksz9897EnableIgmpSnooping(NetInterface *interface, bool_t enable);
1586 void ksz9897EnableMldSnooping(NetInterface *interface, bool_t enable);
1587 void ksz9897EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
1588 
1590  const SwitchFdbEntry *entry);
1591 
1593  const SwitchFdbEntry *entry);
1594 
1596  SwitchFdbEntry *entry);
1597 
1598 void ksz9897FlushStaticFdbTable(NetInterface *interface);
1599 
1601  SwitchFdbEntry *entry);
1602 
1603 void ksz9897FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
1604 
1606  bool_t enable, uint32_t forwardPorts);
1607 
1608 void ksz9897WritePhyReg(NetInterface *interface, uint8_t port,
1609  uint8_t address, uint16_t data);
1610 
1611 uint16_t ksz9897ReadPhyReg(NetInterface *interface, uint8_t port,
1612  uint8_t address);
1613 
1614 void ksz9897DumpPhyReg(NetInterface *interface, uint8_t port);
1615 
1616 void ksz9897WriteMmdReg(NetInterface *interface, uint8_t port,
1617  uint8_t devAddr, uint16_t regAddr, uint16_t data);
1618 
1619 uint16_t ksz9897ReadMmdReg(NetInterface *interface, uint8_t port,
1620  uint8_t devAddr, uint16_t regAddr);
1621 
1622 void ksz9897WriteSgmiiReg(NetInterface *interface, uint32_t address,
1623  uint16_t data);
1624 
1625 uint16_t ksz9897ReadSgmiiReg(NetInterface *interface, uint32_t address);
1626 
1627 void ksz9897WriteSwitchReg8(NetInterface *interface, uint16_t address,
1628  uint8_t data);
1629 
1630 uint8_t ksz9897ReadSwitchReg8(NetInterface *interface, uint16_t address);
1631 
1632 void ksz9897WriteSwitchReg16(NetInterface *interface, uint16_t address,
1633  uint16_t data);
1634 
1635 uint16_t ksz9897ReadSwitchReg16(NetInterface *interface, uint16_t address);
1636 
1637 void ksz9897WriteSwitchReg32(NetInterface *interface, uint16_t address,
1638  uint32_t data);
1639 
1640 uint32_t ksz9897ReadSwitchReg32(NetInterface *interface, uint16_t address);
1641 
1642 //C++ guard
1643 #ifdef __cplusplus
1644 }
1645 #endif
1646 
1647 #endif
SwitchPortState ksz9897GetPortState(NetInterface *interface, uint8_t port)
Get port state.
void ksz9897WriteSgmiiReg(NetInterface *interface, uint32_t address, uint16_t data)
Write SGMII register.
void ksz9897EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
int bool_t
Definition: compiler_port.h:63
void ksz9897WriteSwitchReg8(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register (8 bits)
bool_t ksz9897GetPort7LinkState(NetInterface *interface)
Get port 7 link state.
error_t ksz9897UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
void ksz9897FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
void ksz9897DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz9897Tick(NetInterface *interface)
KSZ9897 timer handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint8_t data[]
Definition: ethernet.h:224
void ksz9897SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
error_t ksz9897GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
void ksz9897EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz9897FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
void ksz9897WriteSwitchReg16(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register (16 bits)
void ksz9897WriteSwitchReg32(NetInterface *interface, uint16_t address, uint32_t data)
Write switch register (32 bits)
uint32_t ksz9897GetPort7LinkSpeed(NetInterface *interface)
Get port 7 link speed.
uint32_t ksz9897GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
uint8_t ksz9897ReadSwitchReg8(NetInterface *interface, uint16_t address)
Read switch register (8 bits)
void ksz9897SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
const SwitchDriver ksz9897SwitchDriver
KSZ9897 Ethernet switch driver.
void ksz9897EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
error_t
Error codes.
Definition: error.h:43
error_t ksz9897TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
error_t ksz9897DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:40
#define NetTxAncillary
Definition: net_misc.h:36
SwitchPortState
Switch port state.
Definition: nic.h:134
NicDuplexMode ksz9897GetPort7DuplexMode(NetInterface *interface)
Get port 7 duplex mode.
uint8_t length
Definition: tcp.h:375
uint16_t ksz9897ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
error_t ksz9897GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
uint16_t port
Definition: dns_common.h:270
void ksz9897DisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t regAddr
Ethernet switch driver.
Definition: nic.h:325
error_t ksz9897Init(NetInterface *interface)
KSZ9897 Ethernet switch initialization.
Ipv6Addr address[]
Definition: ipv6.h:345
NicDuplexMode
Duplex mode.
Definition: nic.h:122
Network interface controller abstraction layer.
error_t ksz9897AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
bool_t ksz9897GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint16_t ksz9897ReadSwitchReg16(NetInterface *interface, uint16_t address)
Read switch register (16 bits)
uint32_t ksz9897ReadSwitchReg32(NetInterface *interface, uint16_t address)
Read switch register (32 bits)
void ksz9897WriteMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
void ksz9897SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
NicDuplexMode ksz9897GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
void ksz9897InitHook(NetInterface *interface)
KSZ9897 custom configuration.
unsigned int uint_t
Definition: compiler_port.h:57
uint16_t ksz9897ReadSgmiiReg(NetInterface *interface, uint32_t address)
Read SGMII register.
void ksz9897EventHandler(NetInterface *interface)
KSZ9897 event handler.
uint16_t ksz9897ReadMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
Forwarding database entry.
Definition: nic.h:149
void ksz9897WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz9897EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.