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31 #ifndef _MCIMX6UL_ETH1_DRIVER_H
32 #define _MCIMX6UL_ETH1_DRIVER_H
38 #ifndef MCIMX6UL_ETH1_TX_BUFFER_COUNT
39 #define MCIMX6UL_ETH1_TX_BUFFER_COUNT 8
40 #elif (MCIMX6UL_ETH1_TX_BUFFER_COUNT < 1)
41 #error MCIMX6UL_ETH1_TX_BUFFER_COUNT parameter is not valid
45 #ifndef MCIMX6UL_ETH1_TX_BUFFER_SIZE
46 #define MCIMX6UL_ETH1_TX_BUFFER_SIZE 1536
47 #elif (MCIMX6UL_ETH1_TX_BUFFER_SIZE != 1536)
48 #error MCIMX6UL_ETH1_TX_BUFFER_SIZE parameter is not valid
52 #ifndef MCIMX6UL_ETH1_RX_BUFFER_COUNT
53 #define MCIMX6UL_ETH1_RX_BUFFER_COUNT 8
54 #elif (MCIMX6UL_ETH1_RX_BUFFER_COUNT < 1)
55 #error MCIMX6UL_ETH1_RX_BUFFER_COUNT parameter is not valid
59 #ifndef MCIMX6UL_ETH1_RX_BUFFER_SIZE
60 #define MCIMX6UL_ETH1_RX_BUFFER_SIZE 1536
61 #elif (MCIMX6UL_ETH1_RX_BUFFER_SIZE != 1536)
62 #error MCIMX6UL_ETH1_RX_BUFFER_SIZE parameter is not valid
66 #ifndef MCIMX6UL_ETH1_IRQ_PRIORITY
67 #define MCIMX6UL_ETH1_IRQ_PRIORITY 21
68 #elif (MCIMX6UL_ETH1_IRQ_PRIORITY < 0)
69 #error MCIMX6UL_ETH1_IRQ_PRIORITY parameter is not valid
73 #ifndef MCIMX6UL_ETH1_RAM_SECTION
74 #define MCIMX6UL_ETH1_RAM_SECTION "NonCacheable"
78 #define ENET_TBD0_R 0x80000000
79 #define ENET_TBD0_TO1 0x40000000
80 #define ENET_TBD0_W 0x20000000
81 #define ENET_TBD0_TO2 0x10000000
82 #define ENET_TBD0_L 0x08000000
83 #define ENET_TBD0_TC 0x04000000
84 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
85 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
86 #define ENET_TBD2_INT 0x40000000
87 #define ENET_TBD2_TS 0x20000000
88 #define ENET_TBD2_PINS 0x10000000
89 #define ENET_TBD2_IINS 0x08000000
90 #define ENET_TBD2_TXE 0x00008000
91 #define ENET_TBD2_UE 0x00002000
92 #define ENET_TBD2_EE 0x00001000
93 #define ENET_TBD2_FE 0x00000800
94 #define ENET_TBD2_LCE 0x00000400
95 #define ENET_TBD2_OE 0x00000200
96 #define ENET_TBD2_TSE 0x00000100
97 #define ENET_TBD4_BDU 0x80000000
98 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
101 #define ENET_RBD0_E 0x80000000
102 #define ENET_RBD0_RO1 0x40000000
103 #define ENET_RBD0_W 0x20000000
104 #define ENET_RBD0_RO2 0x10000000
105 #define ENET_RBD0_L 0x08000000
106 #define ENET_RBD0_M 0x01000000
107 #define ENET_RBD0_BC 0x00800000
108 #define ENET_RBD0_MC 0x00400000
109 #define ENET_RBD0_LG 0x00200000
110 #define ENET_RBD0_NO 0x00100000
111 #define ENET_RBD0_CR 0x00040000
112 #define ENET_RBD0_OV 0x00020000
113 #define ENET_RBD0_TR 0x00010000
114 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
115 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
116 #define ENET_RBD2_ME 0x80000000
117 #define ENET_RBD2_PE 0x04000000
118 #define ENET_RBD2_CE 0x02000000
119 #define ENET_RBD2_UC 0x01000000
120 #define ENET_RBD2_INT 0x00800000
121 #define ENET_RBD2_VPCP 0x0000E000
122 #define ENET_RBD2_ICE 0x00000020
123 #define ENET_RBD2_PCR 0x00000010
124 #define ENET_RBD2_VLAN 0x00000004
125 #define ENET_RBD2_IPV6 0x00000002
126 #define ENET_RBD2_FRAG 0x00000001
127 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
128 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
129 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
130 #define ENET_RBD4_BDU 0x80000000
131 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
const NicDriver mcimx6ulEth1Driver
i.MX6UL Ethernet MAC driver (ENET1 instance)
void mcimx6ulEth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t mcimx6ulEth1CalcCrc(const void *data, size_t length)
CRC calculation.
void mcimx6ulEth1InitGpio(NetInterface *interface)
GPIO configuration.
Structure describing a buffer that spans multiple chunks.
error_t mcimx6ulEth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mcimx6ulEth1Init(NetInterface *interface)
i.MX6UL Ethernet MAC initialization
error_t mcimx6ulEth1ReceivePacket(NetInterface *interface)
Receive a packet.
error_t mcimx6ulEth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void mcimx6ulEth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void mcimx6ulEth1Tick(NetInterface *interface)
i.MX6UL Ethernet MAC timer handler
void mcimx6ulEth1DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
void mcimx6ulEth1EventHandler(NetInterface *interface)
i.MX6UL Ethernet MAC event handler
error_t mcimx6ulEth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t mcimx6ulEth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mcimx6ulEth1EnableIrq(NetInterface *interface)
Enable interrupts.