mimxrt1060_eth1_driver.h
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1 /**
2  * @file mimxrt1060_eth1_driver.h
3  * @brief NXP i.MX RT1060 Ethernet MAC driver (ENET instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _MIMXRT1060_ETH1_DRIVER_H
32 #define _MIMXRT1060_ETH1_DRIVER_H
33 
34 //Number of TX buffers
35 #ifndef MIMXRT1060_ETH1_TX_BUFFER_COUNT
36  #define MIMXRT1060_ETH1_TX_BUFFER_COUNT 8
37 #elif (MIMXRT1060_ETH1_TX_BUFFER_COUNT < 1)
38  #error MIMXRT1060_ETH1_TX_BUFFER_COUNT parameter is not valid
39 #endif
40 
41 //TX buffer size
42 #ifndef MIMXRT1060_ETH1_TX_BUFFER_SIZE
43  #define MIMXRT1060_ETH1_TX_BUFFER_SIZE 1536
44 #elif (MIMXRT1060_ETH1_TX_BUFFER_SIZE != 1536)
45  #error MIMXRT1060_ETH1_TX_BUFFER_SIZE parameter is not valid
46 #endif
47 
48 //Number of RX buffers
49 #ifndef MIMXRT1060_ETH1_RX_BUFFER_COUNT
50  #define MIMXRT1060_ETH1_RX_BUFFER_COUNT 8
51 #elif (MIMXRT1060_ETH1_RX_BUFFER_COUNT < 1)
52  #error MIMXRT1060_ETH1_RX_BUFFER_COUNT parameter is not valid
53 #endif
54 
55 //RX buffer size
56 #ifndef MIMXRT1060_ETH1_RX_BUFFER_SIZE
57  #define MIMXRT1060_ETH1_RX_BUFFER_SIZE 1536
58 #elif (MIMXRT1060_ETH1_RX_BUFFER_SIZE != 1536)
59  #error MIMXRT1060_ETH1_RX_BUFFER_SIZE parameter is not valid
60 #endif
61 
62 //Interrupt priority grouping
63 #ifndef MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING
64  #define MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING 3
65 #elif (MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING < 0)
66  #error MIMXRT1060_ETH1_IRQ_PRIORITY_GROUPING parameter is not valid
67 #endif
68 
69 //Ethernet interrupt group priority
70 #ifndef MIMXRT1060_ETH1_IRQ_GROUP_PRIORITY
71  #define MIMXRT1060_ETH1_IRQ_GROUP_PRIORITY 12
72 #elif (MIMXRT1060_ETH1_IRQ_GROUP_PRIORITY < 0)
73  #error MIMXRT1060_ETH1_IRQ_GROUP_PRIORITY parameter is not valid
74 #endif
75 
76 //Ethernet interrupt subpriority
77 #ifndef MIMXRT1060_ETH1_IRQ_SUB_PRIORITY
78  #define MIMXRT1060_ETH1_IRQ_SUB_PRIORITY 0
79 #elif (MIMXRT1060_ETH1_IRQ_SUB_PRIORITY < 0)
80  #error MIMXRT1060_ETH1_IRQ_SUB_PRIORITY parameter is not valid
81 #endif
82 
83 //Name of the section where to place DMA buffers
84 #ifndef MIMXRT1060_ETH1_RAM_SECTION
85  #define MIMXRT1060_ETH1_RAM_SECTION ".ram_no_cache"
86 #endif
87 
88 //Enhanced transmit buffer descriptor
89 #define ENET_TBD0_R 0x80000000
90 #define ENET_TBD0_TO1 0x40000000
91 #define ENET_TBD0_W 0x20000000
92 #define ENET_TBD0_TO2 0x10000000
93 #define ENET_TBD0_L 0x08000000
94 #define ENET_TBD0_TC 0x04000000
95 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
96 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
97 #define ENET_TBD2_INT 0x40000000
98 #define ENET_TBD2_TS 0x20000000
99 #define ENET_TBD2_PINS 0x10000000
100 #define ENET_TBD2_IINS 0x08000000
101 #define ENET_TBD2_TXE 0x00008000
102 #define ENET_TBD2_UE 0x00002000
103 #define ENET_TBD2_EE 0x00001000
104 #define ENET_TBD2_FE 0x00000800
105 #define ENET_TBD2_LCE 0x00000400
106 #define ENET_TBD2_OE 0x00000200
107 #define ENET_TBD2_TSE 0x00000100
108 #define ENET_TBD4_BDU 0x80000000
109 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
110 
111 //Enhanced receive buffer descriptor
112 #define ENET_RBD0_E 0x80000000
113 #define ENET_RBD0_RO1 0x40000000
114 #define ENET_RBD0_W 0x20000000
115 #define ENET_RBD0_RO2 0x10000000
116 #define ENET_RBD0_L 0x08000000
117 #define ENET_RBD0_M 0x01000000
118 #define ENET_RBD0_BC 0x00800000
119 #define ENET_RBD0_MC 0x00400000
120 #define ENET_RBD0_LG 0x00200000
121 #define ENET_RBD0_NO 0x00100000
122 #define ENET_RBD0_CR 0x00040000
123 #define ENET_RBD0_OV 0x00020000
124 #define ENET_RBD0_TR 0x00010000
125 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
126 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
127 #define ENET_RBD2_ME 0x80000000
128 #define ENET_RBD2_PE 0x04000000
129 #define ENET_RBD2_CE 0x02000000
130 #define ENET_RBD2_UC 0x01000000
131 #define ENET_RBD2_INT 0x00800000
132 #define ENET_RBD2_VPCP 0x0000E000
133 #define ENET_RBD2_ICE 0x00000020
134 #define ENET_RBD2_PCR 0x00000010
135 #define ENET_RBD2_VLAN 0x00000004
136 #define ENET_RBD2_IPV6 0x00000002
137 #define ENET_RBD2_FRAG 0x00000001
138 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
139 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
140 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
141 #define ENET_RBD4_BDU 0x80000000
142 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
143 
144 //C++ guard
145 #ifdef __cplusplus
146 extern "C" {
147 #endif
148 
149 //i.MX RT1060 Ethernet MAC driver (ENET instance)
150 extern const NicDriver mimxrt1060Eth1Driver;
151 
152 //i.MX RT1060 Ethernet MAC related functions
154 void mimxrt1060Eth1InitGpio(NetInterface *interface);
156 
157 void mimxrt1060Eth1Tick(NetInterface *interface);
158 
159 void mimxrt1060Eth1EnableIrq(NetInterface *interface);
160 void mimxrt1060Eth1DisableIrq(NetInterface *interface);
162 
164  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
165 
167 
170 
171 void mimxrt1060Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
172  uint8_t regAddr, uint16_t data);
173 
174 uint16_t mimxrt1060Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
175  uint8_t regAddr);
176 
177 uint32_t mimxrt1060Eth1CalcCrc(const void *data, size_t length);
178 
179 //C++ guard
180 #ifdef __cplusplus
181 }
182 #endif
183 
184 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
error_t mimxrt1060Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mimxrt1060Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
void mimxrt1060Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t mimxrt1060Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mimxrt1060Eth1Tick(NetInterface *interface)
i.MX RT1060 Ethernet MAC timer handler
void mimxrt1060Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
void mimxrt1060Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
void mimxrt1060Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint32_t mimxrt1060Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1060Eth1EventHandler(NetInterface *interface)
i.MX RT1060 Ethernet MAC event handler
void mimxrt1060Eth1InitGpio(NetInterface *interface)
GPIO configuration.
uint16_t mimxrt1060Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mimxrt1060Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t mimxrt1060Eth1Init(NetInterface *interface)
i.MX RT1060 Ethernet MAC initialization
const NicDriver mimxrt1060Eth1Driver
i.MX RT1060 Ethernet MAC driver (ENET instance)
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368