ncn26010_driver.h
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1 /**
2  * @file ncn26010_driver.h
3  * @brief Onsemi NCN26010 10Base-T1S Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _NCN26010_DRIVER_H
32 #define _NCN26010_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PLCA support
38 #ifndef NCN26010_PLCA_SUPPORT
39  #define NCN26010_PLCA_SUPPORT ENABLED
40 #elif (NCN26010_PLCA_SUPPORT != ENABLED && NCN26010_PLCA_SUPPORT != DISABLED)
41  #error NCN26010_PLCA_SUPPORT parameter is not valid
42 #endif
43 
44 //Node count
45 #ifndef NCN26010_NODE_COUNT
46  #define NCN26010_NODE_COUNT 8
47 #elif (NCN26010_NODE_COUNT < 0 || NCN26010_NODE_COUNT > 255)
48  #error NCN26010_NODE_COUNT parameter is not valid
49 #endif
50 
51 //Local ID
52 #ifndef NCN26010_LOCAL_ID
53  #define NCN26010_LOCAL_ID 1
54 #elif (NCN26010_LOCAL_ID < 0 || NCN26010_LOCAL_ID > 255)
55  #error NCN26010_LOCAL_ID parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef NCN26010_ETH_RX_BUFFER_SIZE
60  #define NCN26010_ETH_RX_BUFFER_SIZE 1536
61 #elif (NCN26010_ETH_RX_BUFFER_SIZE != 1536)
62  #error NCN26010_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Chunk payload size
66 #define NCN26010_CHUNK_PAYLOAD_SIZE 64
67 
68 //Transmit data header
69 #define NCN26010_TX_HEADER_DNC 0x80000000
70 #define NCN26010_TX_HEADER_SEQ 0x40000000
71 #define NCN26010_TX_HEADER_NORX 0x20000000
72 #define NCN26010_TX_HEADER_VS 0x00C00000
73 #define NCN26010_TX_HEADER_DV 0x00200000
74 #define NCN26010_TX_HEADER_SV 0x00100000
75 #define NCN26010_TX_HEADER_SWO 0x000F0000
76 #define NCN26010_TX_HEADER_EV 0x00004000
77 #define NCN26010_TX_HEADER_EBO 0x00003F00
78 #define NCN26010_TX_HEADER_TSC 0x000000C0
79 #define NCN26010_TX_HEADER_P 0x00000001
80 
81 //Receive data footer
82 #define NCN26010_RX_FOOTER_EXST 0x80000000
83 #define NCN26010_RX_FOOTER_HDRB 0x40000000
84 #define NCN26010_RX_FOOTER_SYNC 0x20000000
85 #define NCN26010_RX_FOOTER_RCA 0x1F000000
86 #define NCN26010_RX_FOOTER_VS 0x00C00000
87 #define NCN26010_RX_FOOTER_DV 0x00200000
88 #define NCN26010_RX_FOOTER_SV 0x00100000
89 #define NCN26010_RX_FOOTER_SWO 0x000F0000
90 #define NCN26010_RX_FOOTER_FD 0x00008000
91 #define NCN26010_RX_FOOTER_EV 0x00004000
92 #define NCN26010_RX_FOOTER_EBO 0x00003F00
93 #define NCN26010_RX_FOOTER_RTSA 0x00000080
94 #define NCN26010_RX_FOOTER_RTSP 0x00000040
95 #define NCN26010_RX_FOOTER_TXC 0x0000003E
96 #define NCN26010_RX_FOOTER_P 0x00000001
97 
98 //Control command header
99 #define NCN26010_CTRL_HEADER_DNC 0x80000000
100 #define NCN26010_CTRL_HEADER_HDRB 0x40000000
101 #define NCN26010_CTRL_HEADER_WNR 0x20000000
102 #define NCN26010_CTRL_HEADER_AID 0x10000000
103 #define NCN26010_CTRL_HEADER_MMS 0x0F000000
104 #define NCN26010_CTRL_HEADER_ADDR 0x00FFFF00
105 #define NCN26010_CTRL_HEADER_LEN 0x000000FE
106 #define NCN26010_CTRL_HEADER_P 0x00000001
107 
108 //Memory map selectors
109 #define NCN26010_MMS_STD 0x00
110 #define NCN26010_MMS_MAC 0x01
111 #define NCN26010_MMS_PHY_PCS 0x02
112 #define NCN26010_MMS_PHY_PMA_PMD 0x03
113 #define NCN26010_MMS_PHY_PLCA 0x04
114 #define NCN26010_MMS_PHY_VS 0x0C
115 
116 //NCN26010 Standard Control and Status registers (MMS 0)
117 #define NCN26010_IDVER 0x00, 0x0000
118 #define NCN26010_PHYID 0x00, 0x0001
119 #define NCN26010_STDCAP 0x00, 0x0002
120 #define NCN26010_RESET 0x00, 0x0003
121 #define NCN26010_CONFIG0 0x00, 0x0004
122 #define NCN26010_STATUS0 0x00, 0x0008
123 #define NCN26010_BUFSTS 0x00, 0x000B
124 #define NCN26010_IMSK0 0x00, 0x000C
125 #define NCN26010_PHYCTRL 0x00, 0xFF00
126 #define NCN26010_PHYSTATUS 0x00, 0xFF01
127 #define NCN26010_PHYID0 0x00, 0xFF02
128 #define NCN26010_PHYID1 0x00, 0xFF03
129 
130 //NCN26010 MAC registers (MMS 1)
131 #define NCN26010_MACCTRL0 0x01, 0x0000
132 #define NCN26010_ADDRFILT0L 0x01, 0x0010
133 #define NCN26010_ADDRFILT0H 0x01, 0x0011
134 #define NCN26010_ADDRFILT1L 0x01, 0x0012
135 #define NCN26010_ADDRFILT1H 0x01, 0x0013
136 #define NCN26010_ADDRFILT2L 0x01, 0x0014
137 #define NCN26010_ADDRFILT2H 0x01, 0x0015
138 #define NCN26010_ADDRFILT3L 0x01, 0x0016
139 #define NCN26010_ADDRFILT3H 0x01, 0x0017
140 #define NCN26010_ADDRMASK0L 0x01, 0x0020
141 #define NCN26010_ADDRMASK0H 0x01, 0x0021
142 #define NCN26010_ADDRMASK1L 0x01, 0x0022
143 #define NCN26010_ADDRMASK1H 0x01, 0x0023
144 #define NCN26010_ADDRMASK2L 0x01, 0x0024
145 #define NCN26010_ADDRMASK2H 0x01, 0x0025
146 #define NCN26010_ADDRMASK3L 0x01, 0x0026
147 #define NCN26010_ADDRMASK3H 0x01, 0x0027
148 #define NCN26010_STOCTETSTXL 0x01, 0x0030
149 #define NCN26010_STOCTETSTXH 0x01, 0x0031
150 #define NCN26010_STFRAMESTXOK 0x01, 0x0032
151 #define NCN26010_STBCASTTXOK 0x01, 0x0033
152 #define NCN26010_STMCASTTXOK 0x01, 0x0034
153 #define NCN26010_STFRAMESTX64 0x01, 0x0035
154 #define NCN26010_STFRAMESTX65 0x01, 0x0036
155 #define NCN26010_STFRAMESTX128 0x01, 0x0037
156 #define NCN26010_STFRAMESTX256 0x01, 0x0038
157 #define NCN26010_STFRAMESTX512 0x01, 0x0039
158 #define NCN26010_STFRAMESTX1024 0x01, 0x003A
159 #define NCN26010_STUNDERFLOW 0x01, 0x003B
160 #define NCN26010_STSINGLECOL 0x01, 0x003C
161 #define NCN26010_STMULTICOL 0x01, 0x003D
162 #define NCN26010_STEXCESSCOL 0x01, 0x003E
163 #define NCN26010_STDEFERREDTX 0x01, 0x003F
164 #define NCN26010_STCRSERR 0x01, 0x0040
165 #define NCN26010_STOCTETSRXL 0x01, 0x0041
166 #define NCN26010_STOCTETSRXH 0x01, 0x0042
167 #define NCN26010_STFRAMESRXOK 0x01, 0x0043
168 #define NCN26010_STBCASTRXOK 0x01, 0x0044
169 #define NCN26010_STMCASTRXOK 0x01, 0x0045
170 #define NCN26010_STFRAMESRX64 0x01, 0x0046
171 #define NCN26010_STFRAMESRX65 0x01, 0x0047
172 #define NCN26010_STFRAMESRX128 0x01, 0x0048
173 #define NCN26010_STFRAMESRX256 0x01, 0x0049
174 #define NCN26010_STFRAMESRX512 0x01, 0x004A
175 #define NCN26010_STFRAMESRX1024 0x01, 0x004B
176 #define NCN26010_STRUNTSERR 0x01, 0x004C
177 #define NCN26010_STRXTOOLONG 0x01, 0x004D
178 #define NCN26010_STFCSERRS 0x01, 0x004E
179 #define NCN26010_STSYMBOLERRS 0x01, 0x004F
180 #define NCN26010_STALIGNERRS 0x01, 0x0050
181 #define NCN26010_STRXOVERFLOW 0x01, 0x0051
182 #define NCN26010_STRXDROPPED 0x01, 0x0052
183 
184 //NCN26010 PHY PCS registers (MMS 2)
185 #define NCN26010_PCS_DEVINPKG1 0x02, 0x0005
186 #define NCN26010_PCS_DEVINPKG2 0x02, 0x0006
187 #define NCN26010_T1SPCSCTRL 0x02, 0x08F3
188 #define NCN26010_T1SPCSSTATUS 0x02, 0x08F4
189 #define NCN26010_T1SPCSRMTJAB 0x02, 0x08F5
190 #define NCN26010_T1SPCSPHYCOL 0x02, 0x08F6
191 
192 //NCN26010 PHY PMA/PMD registers (MMS 3)
193 #define NCN26010_PMA_DEVINPKG1 0x03, 0x0005
194 #define NCN26010_PMA_DEVINPKG2 0x03, 0x0006
195 #define NCN26010_BASET1EXTABLTY 0x03, 0x0012
196 #define NCN26010_T1SPMACTRL 0x03, 0x08F9
197 #define NCN26010_T1SPMASTS 0x03, 0x08FA
198 #define NCN26010_T1STMCTL 0x03, 0x08FB
199 
200 //NCN26010 PHY PCLA registers (MMS 4)
201 #define NCN26010_CHIPREV 0x04, 0x8000
202 #define NCN26010_PHYCFG1 0x04, 0x8001
203 #define NCN26010_PLCAEXT 0x04, 0x8002
204 #define NCN26010_PMATUNE0 0x04, 0x8003
205 #define NCN26010_PMATUNE1 0x04, 0x8004
206 #define NCN26010_PLCAREGMAP 0x04, 0xCA00
207 #define NCN26010_PLCACTRL0 0x04, 0xCA01
208 #define NCN26010_PLCACTRL1 0x04, 0xCA02
209 #define NCN26010_PLCASTS 0x04, 0xCA03
210 #define NCN26010_PLCATOTMR 0x04, 0xCA04
211 #define NCN26010_PLCABURST 0x04, 0xCA05
212 
213 //NCN26010 Vendor Specific registers (MMS 12)
214 #define NCN26010_MIIMIRQCTRL 0x0C, 0x0010
215 #define NCN26010_MIIMIRQSTS 0x0C, 0x0011
216 #define NCN26010_DIOCFG 0x0C, 0x0012
217 #define NCN26010_PHYTWEAK 0x0C, 0x1001
218 #define NCN26010_MACID0 0x0C, 0x1002
219 #define NCN26010_MACID1 0x0C, 0x1003
220 #define NCN26010_CHIPINFO 0x0C, 0x1004
221 #define NCN26010_NVMHEALTH 0x0C, 0x1005
222 
223 //SPI Identification register
224 #define NCN26010_IDVER_MAJVER 0x000000F0
225 #define NCN26010_IDVER_MAJVER_DEFAULT 0x00000010
226 #define NCN26010_IDVER_MINVER 0x0000000F
227 #define NCN26010_IDVER_MINVER_DEFAULT 0x00000001
228 
229 //SPI Identification register
230 #define NCN26010_PHYID_OUI 0xFFFFFC00
231 #define NCN26010_PHYID_OUI_DEFAULT 0x180FF400
232 #define NCN26010_PHYID_MODEL 0x000003F0
233 #define NCN26010_PHYID_MODEL_DEFAULT 0x000001A0
234 #define NCN26010_PHYID_REV 0x0000000F
235 #define NCN26010_PHYID_REV_DEFAULT 0x00000001
236 
237 //SPI Capabilities register
238 #define NCN26010_STDCAP_TXFCSVC 0x00000400
239 #define NCN26010_STDCAP_IPRAC 0x00000200
240 #define NCN26010_STDCAP_DPRAC 0x00000100
241 #define NCN26010_STDCAP_CTC 0x00000080
242 #define NCN26010_STDCAP_FTC 0x00000040
243 #define NCN26010_STDCAP_AIDC 0x00000020
244 #define NCN26010_STDCAP_SEQ 0x00000010
245 #define NCN26010_STDCAP_MINCPS 0x00000007
246 
247 //Reset Control And Status register
248 #define NCN26010_RESET_RESET 0x00000001
249 
250 //SPI Protocol Configuration 0 register
251 #define NCN26010_CONFIG0_SYNC 0x00008000
252 #define NCN26010_CONFIG0_TXFCSVE 0x00004000
253 #define NCN26010_CONFIG0_CSARFE 0x00002000
254 #define NCN26010_CONFIG0_ZARFE 0x00001000
255 #define NCN26010_CONFIG0_TXCTHRESH 0x00000C00
256 #define NCN26010_CONFIG0_TXCTHRESH_1_CREDIT 0x00000000
257 #define NCN26010_CONFIG0_TXCTHRESH_4_CREDITS 0x00000400
258 #define NCN26010_CONFIG0_TXCTHRESH_8_CREDITS 0x00000800
259 #define NCN26010_CONFIG0_TXCTHRESH_16_CREDITS 0x00000C00
260 #define NCN26010_CONFIG0_TXCTE 0x00000200
261 #define NCN26010_CONFIG0_RXCTE 0x00000100
262 #define NCN26010_CONFIG0_FTSE 0x00000080
263 #define NCN26010_CONFIG0_FTSS 0x00000040
264 #define NCN26010_CONFIG0_PROTE 0x00000020
265 #define NCN26010_CONFIG0_CPS 0x00000007
266 #define NCN26010_CONFIG0_CPS_8_BYTES 0x00000003
267 #define NCN26010_CONFIG0_CPS_16_BYTES 0x00000004
268 #define NCN26010_CONFIG0_CPS_32_BYTES 0x00000005
269 #define NCN26010_CONFIG0_CPS_64_BYTES 0x00000006
270 
271 //SPI Protocol Status 0 register
272 #define NCN26010_STATUS0_CDPE 0x00001000
273 #define NCN26010_STATUS0_TXFCSE 0x00000800
274 #define NCN26010_STATUS0_TTSCAC 0x00000400
275 #define NCN26010_STATUS0_TTSCAB 0x00000200
276 #define NCN26010_STATUS0_TTSCAA 0x00000100
277 #define NCN26010_STATUS0_PHYINT 0x00000080
278 #define NCN26010_STATUS0_RESETC 0x00000040
279 #define NCN26010_STATUS0_HDRE 0x00000020
280 #define NCN26010_STATUS0_LOFE 0x00000010
281 #define NCN26010_STATUS0_RXBOE 0x00000008
282 #define NCN26010_STATUS0_TXBUE 0x00000004
283 #define NCN26010_STATUS0_TXBOE 0x00000002
284 #define NCN26010_STATUS0_TXPE 0x00000001
285 
286 //Buffer Status register
287 #define NCN26010_BUFSTS_TXC 0x0000FF00
288 #define NCN26010_BUFSTS_RCA 0x000000FF
289 
290 //Interrupt Mask 0 register
291 #define NCN26010_IMSK0_CDPEM 0x00001000
292 #define NCN26010_IMSK0_TXFCSEM 0x00000800
293 #define NCN26010_IMSK0_PHYINTM 0x00000080
294 #define NCN26010_IMSK0_RESETCM 0x00000040
295 #define NCN26010_IMSK0_HDREM 0x00000020
296 #define NCN26010_IMSK0_LOFEM 0x00000010
297 #define NCN26010_IMSK0_RXDOEM 0x00000008
298 #define NCN26010_IMSK0_TXBUEM 0x00000004
299 #define NCN26010_IMSK0_TXBOEM 0x00000002
300 #define NCN26010_IMSK0_TXPEM 0x00000001
301 
302 //PHY Control register
303 #define NCN26010_PHYCTRL_RESET 0x00008000
304 #define NCN26010_PHYCTRL_LOOPBACK 0x00004000
305 #define NCN26010_PHYCTRL_SPEED_LSB 0x00002000
306 #define NCN26010_PHYCTRL_LINK_CONTROL 0x00001000
307 #define NCN26010_PHYCTRL_ISOLATE 0x00000400
308 #define NCN26010_PHYCTRL_LINK_RESET 0x00000200
309 #define NCN26010_PHYCTRL_DUPLEX_MODE 0x00000100
310 #define NCN26010_PHYCTRL_COLLISION_TEST 0x00000080
311 #define NCN26010_PHYCTRL_SPEED_MSB 0x00000040
312 
313 //PHY Status register
314 #define NCN26010_PHYSTATUS_10_HALF_DUPLEX 0x00000800
315 #define NCN26010_PHYSTATUS_UNIDIRECTIONAL_ABILITY 0x00000080
316 #define NCN26010_PHYSTATUS_MF_PREAMBLE_SUPPR 0x00000040
317 #define NCN26010_PHYSTATUS_LINK_NEGOTIATION_COMPLETE 0x00000020
318 #define NCN26010_PHYSTATUS_REMOTE_FAULT 0x00000010
319 #define NCN26010_PHYSTATUS_AUTO_NEGOTIATION_ABILITY 0x00000008
320 #define NCN26010_PHYSTATUS_LINK_STATUS 0x00000004
321 #define NCN26010_PHYSTATUS_JABBER_DETECT 0x00000002
322 #define NCN26010_PHYSTATUS_EXTENDED_CAPABILITY 0x00000001
323 
324 //PHY Identifier 0 register
325 #define NCN26010_PHYID0_OUI_MSB 0x0000FFFF
326 #define NCN26010_PHYID0_OUI_MSB_DEFAULT 0x0000180F
327 
328 //PHY Identifier 1 register
329 #define NCN26010_PHYID1_OUI_LSB 0x0000FC00
330 #define NCN26010_PHYID1_OUI_LSB_DEFAULT 0x0000D400
331 #define NCN26010_PHYID1_MODEL_NUM 0x000003F0
332 #define NCN26010_PHYID1_MODEL_NUM_DEFAULT 0x000001A0
333 #define NCN26010_PHYID1_REV_NUM 0x0000000F
334 #define NCN26010_PHYID1_REV_NUM_DEFAULT 0x00000001
335 
336 //MAC Control 0 register
337 #define NCN26010_MACCTRL0_IPGNF 0x00200000
338 #define NCN26010_MACCTRL0_BKOD 0x00100000
339 #define NCN26010_MACCTRL0_NFCSF 0x00080000
340 #define NCN26010_MACCTRL0_MCSF 0x00040000
341 #define NCN26010_MACCTRL0_BCSF 0x00020000
342 #define NCN26010_MACCTRL0_ADRF 0x00010000
343 #define NCN26010_MACCTRL0_FCSA 0x00000100
344 #define NCN26010_MACCTRL0_TXEN 0x00000002
345 #define NCN26010_MACCTRL0_RXEN 0x00000001
346 
347 //Address Filter Low register
348 #define NCN26010_ADDRFILTnL_ADDRFILT_31_0 0xFFFFFFFF
349 
350 //Address Filter High register
351 #define NCN26010_ADDRFILTnH_EN 0x80000000
352 #define NCN26010_ADDRFILTnH_ADDRFILT_47_32 0x0000FFFF
353 
354 //Address Mask Low register
355 #define NCN26010_ADDRMASKnL_ADDRMASK_31_0 0xFFFFFFFF
356 
357 //Address Mask High register
358 #define NCN26010_ADDRMASKnH_ADDRMASK_47_32 0x00008000
359 
360 //Statistic Sent Bytes Counter Low register
361 #define NCN26010_STOCTETSTXL_STOCTETSTXL_31_0 0xFFFFFFFF
362 
363 //Statistic Sent Bytes Counter High register
364 #define NCN26010_STOCTETSTXH_STOCTETSTXL_47_32 0x0000FFFF
365 
366 //Statistic Aborted Frames Due To Tx-buffer underflow register
367 #define NCN26010_STUNDERFLOW_STUNDERFLOW 0x000003FF
368 
369 //Statistic Frames Transmitted After Single Collision register
370 #define NCN26010_STSINGLECOL_STSINGLECOL 0x0003FFFF
371 
372 //Statistic Frames Transmitted After Multiple Collisions register
373 #define NCN26010_STMULTICOL_STMULTICOL 0x0003FFFF
374 
375 //Statistic Frames Transmitted After Excessive Collisions register
376 #define NCN26010_STEXCESSCOL_STEXCESSCOL 0x000003FF
377 
378 //Statistic Frames Transmitted After Deferral register
379 #define NCN26010_STDEFERREDTX_STDEFERREDTX 0x0003FFFF
380 
381 //Statistic Counter Of Crs De-assertion During Frame Transmission register
382 #define NCN26010_STCRSERR_STCRSERR 0x000003FF
383 
384 //Statistic Received Bytes Counter Low register
385 #define NCN26010_STOCTETSRXL_STOCTETSRX_31_0 0xFFFFFFFF
386 
387 //Statistic Received Bytes Counter High register
388 #define NCN26010_STOCTETSRXH_STOCTETSRX_47_32 0x0000FFFF
389 
390 //Statistic Dropped Too Short Frames register
391 #define NCN26010_STRUNTSERR_STRUNTERR 0x000003FF
392 
393 //Statistic Dropped Too Long Frames register
394 #define NCN26010_STRXTOOLONG_STRXTOOLONG 0x000003FF
395 
396 //Statistic Dropped Fcs Error Frames register
397 #define NCN26010_STFCSERRS_STFCSERRS 0x000003FF
398 
399 //Statistic Symbol Errors During Frame Reception register
400 #define NCN26010_STSYMBOLERRS_STSYMBOLERRS 0x000003FF
401 
402 //Statistic Align Errors During Frame Reception register
403 #define NCN26010_STALIGNERRS_STALIGNERRS 0x000003FF
404 
405 //Statistic RX Buffer Overflow Errors register
406 #define NCN26010_STRXOVERFLOW_STRXOVERFLOW 0x000003FF
407 
408 //Devices In Package 1 register
409 #define NCN26010_PCS_DEVINPKG1_PCS_PRESENT 0x0008
410 #define NCN26010_PCS_DEVINPKG1_PMA_PRESENT 0x0002
411 #define NCN26010_PCS_DEVINPKG1_CLAUSE_22_REGS_PRESENT 0x0001
412 
413 //10BASE-T1S PCS Control register
414 #define NCN26010_T1SPCSCTRL_PCS_RESET 0x8000
415 #define NCN26010_T1SPCSCTRL_LOOPBACK 0x4000
416 
417 //10BASE-T1S PCS Status register
418 #define NCN26010_T1SPCSSTATUS_FAULT 0x0080
419 
420 //10BASE-T1S PCS Diagnostics 1 register
421 #define NCN26010_T1SPCSRMTJAB_PCS_REMOTE_JABBER_COUNT 0xFFFF
422 
423 //10BASE-T1S PCS Diagnostics 2 register
424 #define NCN26010_T1SPCSPHYCOL_PCS_PHY_COL_COUNT 0xFFFF
425 
426 //Devices In Package 1 register
427 #define NCN26010_PMA_DEVINPKG1_PCS_PRESENT 0x0008
428 #define NCN26010_PMA_DEVINPKG1_PMA_PRESENT 0x0002
429 #define NCN26010_PMA_DEVINPKG1_CLAUSE_22_REGS_PRESENT 0x0001
430 
431 //BASE-T1 Extended Ability register
432 #define NCN26010_BASET1EXTABLTY_10BASE_T1S 0x0008
433 
434 //10BASE-T1S PMA Control register
435 #define NCN26010_T1SPMACTRL_PMA_RESET 0x8000
436 #define NCN26010_T1SPMACTRL_TX_DIS 0x4000
437 #define NCN26010_T1SPMACTRL_LOW_POWER_MODE 0x0800
438 #define NCN26010_T1SPMACTRL_MULTI_DROP_EN 0x0400
439 #define NCN26010_T1SPMACTRL_LOOPBACK_MODE 0x0001
440 
441 //10BASE-T1S PMA Status register
442 #define NCN26010_T1SPMASTS_LOOPBACK_ABILITY 0x2000
443 #define NCN26010_T1SPMASTS_LOW_POWER_ABILITY 0x0800
444 #define NCN26010_T1SPMASTS_MULTI_DROP_ABILITY 0x0400
445 #define NCN26010_T1SPMASTS_RECEIVE_FAULT_ABILITY 0x0200
446 #define NCN26010_T1SPMASTS_REMOTE_JABBER 0x0002
447 
448 //10BASE-T1S Test Mode Control register
449 #define NCN26010_T1STMCTL_TEST_MODE 0xE000
450 #define NCN26010_T1STMCTL_TEST_MODE_NORMAL 0x0000
451 #define NCN26010_T1STMCTL_TEST_MODE_TX_OUT_VOLTAGE_TEST 0x2000
452 #define NCN26010_T1STMCTL_TEST_MODE_TX_OUT_DROP_TEST 0x4000
453 #define NCN26010_T1STMCTL_TEST_MODE_TX_PSD_MASK 0x6000
454 #define NCN26010_T1STMCTL_TEST_MODE_TX_HIGH_Z_TEST 0x8000
455 
456 //Chip Revision register
457 #define NCN26010_CHIPREV_MAJOR_REV 0xF000
458 #define NCN26010_CHIPREV_MAJOR_REV_DEFAULT 0x1000
459 #define NCN26010_CHIPREV_MINOR_REV 0x0F00
460 #define NCN26010_CHIPREV_MINOR_REV_DEFAULT 0x0000
461 #define NCN26010_CHIPREV_STAGE 0x00C0
462 #define NCN26010_CHIPREV_STAGE_DEFAULT 0x00C0
463 #define NCN26010_CHIPREV_PATCH 0x003F
464 #define NCN26010_CHIPREV_PATCH_DEFAULT 0x0001
465 
466 //PHY Configuration 1 register
467 #define NCN26010_PHYCFG1_ENHANCED_NOISE_IMMUNITY 0x0080
468 #define NCN26010_PHYCFG1_UNJAB_TIMER_EN 0x0040
469 #define NCN26010_PHYCFG1_SCRAMBLER_DIS 0x0004
470 #define NCN26010_PHYCFG1_NO_COL_MASKING 0x0002
471 #define NCN26010_PHYCFG1_RX_DELAY 0x0001
472 
473 //PLCA Extensions register
474 #define NCN26010_PLCAEXT_PLCA_PRECEDENCE 0x8000
475 #define NCN26010_PLCAEXT_COORDINATOR_MODE 0x0002
476 #define NCN26010_PLCAEXT_COORDINATOR_ROLE 0x0001
477 
478 //PMA Tune 0 register
479 #define NCN26010_PMATUNE0_PLCA_BEACON_DETECT_THRESHOLD 0x3F00
480 #define NCN26010_PMATUNE0_DRIFT_COMPENSATION_WIN_SEL 0x0007
481 
482 //PMA Tune 1 register
483 #define NCN26010_PMATUNE1_PKT_PREAMBLE_DETEC_THRESHOLD 0x3F00
484 #define NCN26010_PMATUNE1_COMMIT_DETECT_THRESHOLD 0x003F
485 
486 //PLCA Register Map And Identification register
487 #define NCN26010_PLCAREGMAP_MAPID 0xFF00
488 #define NCN26010_PLCAREGMAP_MAPVER 0x00FF
489 
490 //PLCA Control 0 register
491 #define NCN26010_PLCACTRL0_PCLA_EN 0x8000
492 #define NCN26010_PLCACTRL0_PLCA_RESET 0x4000
493 
494 //PLCA Control 1 register
495 #define NCN26010_PLCACTRL1_NCNT 0xFF00
496 #define NCN26010_PLCACTRL1_ID 0x00FF
497 
498 //PLCA Status register
499 #define NCN26010_PLCASTS_PST 0x8000
500 
501 //PLCA Transmit Opportunity Timer register
502 #define NCN26010_PLCATOTMR_TOTMR 0x00FF
503 #define NCN26010_PLCATOTMR_TOTMR_DEFAULT 0x0018
504 
505 //PLCA Burst Mode register
506 #define NCN26010_PLCABURST_MAXBC 0xFF00
507 #define NCN26010_PLCABURST_MAXBC_DEFAULT 0x0000
508 #define NCN26010_PLCABURST_BTMR 0x00FF
509 #define NCN26010_PLCABURST_BTMR_DEFAULT 0x0080
510 
511 //MIIM IRQ Control register
512 #define NCN26010_MIIMIRQCTRL_PHY_COL_REPORT 0x0020
513 #define NCN26010_MIIMIRQCTRL_PLCA_RECOVERY_REPORT 0x0010
514 #define NCN26010_MIIMIRQCTRL_REMOTE_JABBER_REPORT 0x0008
515 #define NCN26010_MIIMIRQCTRL_LOCAL_JABBER_REPORT 0x0004
516 #define NCN26010_MIIMIRQCTRL_PLCA_STATUS_CHANGE_REPORT 0x0002
517 #define NCN26010_MIIMIRQCTRL_LINK_STATUS_CHANGE_REPORT 0x0001
518 
519 //MIIM IRQ Status register
520 #define NCN26010_MIIMIRQSTS_RESET_STATUS 0x8000
521 #define NCN26010_MIIMIRQSTS_PHY_COL 0x0020
522 #define NCN26010_MIIMIRQSTS_PLCA_RECOVERY 0x0010
523 #define NCN26010_MIIMIRQSTS_REMOTE_JABBER 0x0008
524 #define NCN26010_MIIMIRQSTS_LOCAL_JABBER 0x0004
525 #define NCN26010_MIIMIRQSTS_PLCA_STATUS_CHANGE 0x0002
526 #define NCN26010_MIIMIRQSTS_LINK_STATUS_CHANGE 0x0001
527 
528 //DIO Configuration register
529 #define NCN26010_DIOCFG_SLEW_RATE_1 0x8000
530 #define NCN26010_DIOCFG_PULL_EN_1 0x4000
531 #define NCN26010_DIOCFG_PULL_TYPE_1 0x2000
532 #define NCN26010_DIOCFG_PULL_TYPE_1_PULL_UP 0x0000
533 #define NCN26010_DIOCFG_PULL_TYPE_1_PULL_DOWN 0x2000
534 #define NCN26010_DIOCFG_FN1 0x1E00
535 #define NCN26010_DIOCFG_FN1_DISABLE 0x0000
536 #define NCN26010_DIOCFG_FN1_GPIO 0x0200
537 #define NCN26010_DIOCFG_FN1_SFD_TX 0x0400
538 #define NCN26010_DIOCFG_FN1_SFD_RX 0x0600
539 #define NCN26010_DIOCFG_FN1_LED_LINK_CTRL 0x0800
540 #define NCN26010_DIOCFG_FN1_LED_PLCA_STATUS 0x0A00
541 #define NCN26010_DIOCFG_FN1_LED_TX 0x0C00
542 #define NCN26010_DIOCFG_FN1_LED_RX 0x0E00
543 #define NCN26010_DIOCFG_FN1_CLK25M 0x1000
544 #define NCN26010_DIOCFG_FN1_SFD_RX_TX 0x1600
545 #define NCN26010_DIOCFG_FN1_LED_TX_RX 0x1E00
546 #define NCN26010_DIOCFG_VAL1 0x0100
547 #define NCN26010_DIOCFG_SLEW_RATE_0 0x0080
548 #define NCN26010_DIOCFG_PULL_EN_0 0x0040
549 #define NCN26010_DIOCFG_PULL_TYPE_0 0x0020
550 #define NCN26010_DIOCFG_PULL_TYPE_0_PULL_UP 0x0000
551 #define NCN26010_DIOCFG_PULL_TYPE_0_PULL_DOWN 0x0020
552 #define NCN26010_DIOCFG_FN0 0x001E
553 #define NCN26010_DIOCFG_FN0_DISABLE 0x0000
554 #define NCN26010_DIOCFG_FN0_GPIO 0x0002
555 #define NCN26010_DIOCFG_FN0_SFD_TX 0x0004
556 #define NCN26010_DIOCFG_FN0_SFD_RX 0x0006
557 #define NCN26010_DIOCFG_FN0_LED_LINK_CTRL 0x0008
558 #define NCN26010_DIOCFG_FN0_LED_PLCA_STATUS 0x000A
559 #define NCN26010_DIOCFG_FN0_LED_TX 0x000C
560 #define NCN26010_DIOCFG_FN0_LED_RX 0x000E
561 #define NCN26010_DIOCFG_FN0_CLK25M 0x0010
562 #define NCN26010_DIOCFG_FN0_SFD_RX_TX 0x0016
563 #define NCN26010_DIOCFG_FN0_LED_TX_RX 0x001E
564 #define NCN26010_DIOCFG_VAL0 0x0001
565 
566 //PHY Tweaks register
567 #define NCN26010_PHYTWEAK_TX_GAIN 0xC000
568 #define NCN26010_PHYTWEAK_TX_GAIN_1000_MVPP 0x0000
569 #define NCN26010_PHYTWEAK_TX_GAIN_1100_MVPP 0x4000
570 #define NCN26010_PHYTWEAK_TX_GAIN_900_MVPP 0x8000
571 #define NCN26010_PHYTWEAK_TX_GAIN_800_MVPP 0xC000
572 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD 0x3C00
573 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_150_MVPP 0x0000
574 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_200_MVPP 0x0400
575 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_250_MVPP 0x0800
576 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_300_MVPP 0x0C00
577 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_350_MVPP 0x1000
578 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_400_MVPP 0x1400
579 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_450_MVPP 0x1800
580 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_500_MVPP 0x1C00
581 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_550_MVPP 0x2000
582 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_600_MVPP 0x2400
583 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_650_MVPP 0x2800
584 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_700_MVPP 0x2C00
585 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_750_MVPP 0x3000
586 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_800_MVPP 0x3400
587 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_850_MVPP 0x3800
588 #define NCN26010_PHYTWEAK_RX_CD_THRESHOLD_900_MVPP 0x3C00
589 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD 0x03C0
590 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_150_MVPP 0x0000
591 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_200_MVPP 0x0040
592 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_250_MVPP 0x0080
593 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_300_MVPP 0x00C0
594 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_350_MVPP 0x0100
595 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_400_MVPP 0x0140
596 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_450_MVPP 0x0180
597 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_500_MVPP 0x01C0
598 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_550_MVPP 0x0200
599 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_600_MVPP 0x0240
600 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_650_MVPP 0x0280
601 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_700_MVPP 0x02C0
602 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_750_MVPP 0x0300
603 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_800_MVPP 0x0340
604 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_850_MVPP 0x0380
605 #define NCN26010_PHYTWEAK_RX_ED_THRESHOLD_900_MVPP 0x03C0
606 #define NCN26010_PHYTWEAK_DIGITAL_SLEW_RATE 0x0020
607 #define NCN26010_PHYTWEAK_DIGITAL_SLEW_RATE_SLOW 0x0000
608 #define NCN26010_PHYTWEAK_DIGITAL_SLEW_RATE_FAST 0x0020
609 #define NCN26010_PHYTWEAK_CMC_COMPENSATION 0x0018
610 #define NCN26010_PHYTWEAK_CMC_COMPENSATION_0_TO_0_5_R 0x0000
611 #define NCN26010_PHYTWEAK_CMC_COMPENSATION_0_5_TO_2_25_R 0x0008
612 #define NCN26010_PHYTWEAK_CMC_COMPENSATION_2_25_TO_3_75_R 0x0010
613 #define NCN26010_PHYTWEAK_CMC_COMPENSATION_3_75_TO_5_R 0x0018
614 #define NCN26010_PHYTWEAK_TX_SLEW 0x0004
615 #define NCN26010_PHYTWEAK_TX_SLEW_SLOW 0x0000
616 #define NCN26010_PHYTWEAK_TX_SLEW_FAST 0x0004
617 #define NCN26010_PHYTWEAK_CLK_OUT_EN 0x0001
618 
619 //MAC Identification 0 register
620 #define NCN26010_MACID0_MACID_15_0 0xFFFF
621 
622 //MAC Identification 1 register
623 #define NCN26010_MACID1_MACID_23_16 0x00FF
624 
625 //Chip Info register
626 #define NCN26010_CHIPINFO_WAFER_Y 0x7F00
627 #define NCN26010_CHIPINFO_WAFER_X 0x007F
628 
629 //NVM Health register
630 #define NCN26010_NVMHEALTH_RED_ZONE_NVM_WARNING 0x8000
631 #define NCN26010_NVMHEALTH_RED_ZONE_NVM_ERROR 0x4000
632 #define NCN26010_NVMHEALTH_YELLOW_ZONE_NVM_WARNING 0x2000
633 #define NCN26010_NVMHEALTH_YELLOW_ZONE_NVM_ERROR 0x1000
634 #define NCN26010_NVMHEALTH_GREEN_ZONE_NVM_WARNING 0x0800
635 #define NCN26010_NVMHEALTH_GREEN_ZONE_NVM_ERROR 0x0400
636 
637 //C++ guard
638 #ifdef __cplusplus
639 extern "C" {
640 #endif
641 
642 //NCN26010 driver
643 extern const NicDriver ncn26010Driver;
644 
645 //NCN26010 related functions
646 error_t ncn26010Init(NetInterface *interface);
647 void ncn26010InitHook(NetInterface *interface);
648 
649 void ncn26010Tick(NetInterface *interface);
650 
651 void ncn26010EnableIrq(NetInterface *interface);
652 void ncn26010DisableIrq(NetInterface *interface);
654 void ncn26010EventHandler(NetInterface *interface);
655 
657  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
658 
660 
662 
663 void ncn26010WriteReg(NetInterface *interface, uint8_t mms, uint16_t address,
664  uint32_t data);
665 
666 uint32_t ncn26010ReadReg(NetInterface *interface, uint8_t mms,
667  uint16_t address);
668 
669 void ncn26010DumpReg(NetInterface *interface, uint8_t mms, uint16_t address,
670  uint_t num);
671 
672 uint32_t ncn26010CalcParity(uint32_t data);
673 
674 //C++ guard
675 #ifdef __cplusplus
676 }
677 #endif
678 
679 #endif
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
const NicDriver ncn26010Driver
NCN26010 driver.
bool_t ncn26010IrqHandler(NetInterface *interface)
NCN26010 interrupt service routine.
uint32_t ncn26010CalcParity(uint32_t data)
Calculate parity bit over a 32-bit data.
void ncn26010DumpReg(NetInterface *interface, uint8_t mms, uint16_t address, uint_t num)
Dump registers for debugging purpose.
void ncn26010DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ncn26010Init(NetInterface *interface)
NCN26010 controller initialization.
error_t ncn26010UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t ncn26010ReceivePacket(NetInterface *interface)
Receive a packet.
void ncn26010EnableIrq(NetInterface *interface)
Enable interrupts.
error_t ncn26010SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void ncn26010EventHandler(NetInterface *interface)
NCN26010 event handler.
void ncn26010InitHook(NetInterface *interface)
NCN26010 custom configuration.
void ncn26010WriteReg(NetInterface *interface, uint8_t mms, uint16_t address, uint32_t data)
Write register.
uint32_t ncn26010ReadReg(NetInterface *interface, uint8_t mms, uint16_t address)
Read register.
void ncn26010Tick(NetInterface *interface)
NCN26010 timer handler.
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283