w5100s_driver.h
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1 /**
2  * @file w5100s_driver.h
3  * @brief WIZnet W5100S Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _W5100S_DRIVER_H
32 #define _W5100S_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //TX buffer size
38 #ifndef W5100S_ETH_TX_BUFFER_SIZE
39  #define W5100S_ETH_TX_BUFFER_SIZE 1536
40 #elif (W5100S_ETH_TX_BUFFER_SIZE != 1536)
41  #error W5100S_ETH_TX_BUFFER_SIZE parameter is not valid
42 #endif
43 
44 //RX buffer size
45 #ifndef W5100S_ETH_RX_BUFFER_SIZE
46  #define W5100S_ETH_RX_BUFFER_SIZE 1536
47 #elif (W5100S_ETH_RX_BUFFER_SIZE != 1536)
48  #error W5100S_ETH_RX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Control byte
52 #define W5100S_CTRL_READ 0x0F
53 #define W5100S_CTRL_WRITE 0xF0
54 
55 //W5100S Common registers
56 #define W5100S_MR 0x00
57 #define W5100S_GAR0 0x01
58 #define W5100S_GAR1 0x02
59 #define W5100S_GAR2 0x03
60 #define W5100S_GAR3 0x04
61 #define W5100S_SUBR0 0x05
62 #define W5100S_SUBR1 0x06
63 #define W5100S_SUBR2 0x07
64 #define W5100S_SUBR3 0x08
65 #define W5100S_SHAR0 0x09
66 #define W5100S_SHAR1 0x0A
67 #define W5100S_SHAR2 0x0B
68 #define W5100S_SHAR3 0x0C
69 #define W5100S_SHAR4 0x0D
70 #define W5100S_SHAR5 0x0E
71 #define W5100S_SIPR0 0x0F
72 #define W5100S_SIPR1 0x10
73 #define W5100S_SIPR2 0x11
74 #define W5100S_SIPR3 0x12
75 #define W5100S_INTPTMR0 0x13
76 #define W5100S_INTPTMR1 0x14
77 #define W5100S_IR 0x15
78 #define W5100S_IMR 0x16
79 #define W5100S_RTR0 0x17
80 #define W5100S_RTR1 0x18
81 #define W5100S_RCR 0x19
82 #define W5100S_RMSR 0x1A
83 #define W5100S_TMSR 0x1B
84 #define W5100S_IR2 0x20
85 #define W5100S_IMR2 0x21
86 #define W5100S_PTIMER 0x28
87 #define W5100S_PMAGIC 0x29
88 #define W5100S_UIPR0 0x2A
89 #define W5100S_UIPR1 0x2B
90 #define W5100S_UIPR2 0x2C
91 #define W5100S_UIPR3 0x2D
92 #define W5100S_UPORTR0 0x2E
93 #define W5100S_UPORTR1 0x2F
94 #define W5100S_MR2 0x30
95 #define W5100S_PHAR0 0x32
96 #define W5100S_PHAR1 0x33
97 #define W5100S_PHAR2 0x34
98 #define W5100S_PHAR3 0x35
99 #define W5100S_PHAR4 0x36
100 #define W5100S_PHAR5 0x37
101 #define W5100S_PSIDR0 0x38
102 #define W5100S_PSIDR1 0x39
103 #define W5100S_PMRUR0 0x3A
104 #define W5100S_PMRUR1 0x3B
105 #define W5100S_PHYSR0 0x3C
106 #define W5100S_PHYSR1 0x3D
107 #define W5100S_PHYAR 0x3E
108 #define W5100S_PHYRAR 0x3F
109 #define W5100S_PHYDIR0 0x40
110 #define W5100S_PHYDIR1 0x41
111 #define W5100S_PHYDOR0 0x42
112 #define W5100S_PHYDOR1 0x43
113 #define W5100S_PHYACR 0x44
114 #define W5100S_PHYDIVR 0x45
115 #define W5100S_PHYCR0 0x46
116 #define W5100S_PHYCR1 0x47
117 #define W5100S_SLCR 0x4C
118 #define W5100S_SLRTR0 0x4D
119 #define W5100S_SLRTR1 0x4E
120 #define W5100S_SLRCR 0x4F
121 #define W5100S_SLPIPR0 0x50
122 #define W5100S_SLPIPR1 0x51
123 #define W5100S_SLPIPR2 0x52
124 #define W5100S_SLPIPR3 0x53
125 #define W5100S_SLPHAR0 0x54
126 #define W5100S_SLPHAR1 0x55
127 #define W5100S_SLPHAR2 0x56
128 #define W5100S_SLPHAR3 0x57
129 #define W5100S_SLPHAR4 0x58
130 #define W5100S_SLPHAR5 0x59
131 #define W5100S_PINGSEQR0 0x5A
132 #define W5100S_PINGSEQR1 0x5B
133 #define W5100S_PINGIDR0 0x5C
134 #define W5100S_PINGIDR1 0x5D
135 #define W5100S_SLIMR 0x5E
136 #define W5100S_SLIR 0x5F
137 #define W5100S_CLKLCKR 0x70
138 #define W5100S_NETLCKR 0x71
139 #define W5100S_PHYLCKR 0x72
140 #define W5100S_VERR 0x80
141 #define W5100S_TCNTR0 0x82
142 #define W5100S_TCNTR1 0x83
143 #define W5100S_TCNTCLR 0x88
144 
145 //W5100S Socket registers
146 #define W5100S_S0_MR 0x0400
147 #define W5100S_S0_CR 0x0401
148 #define W5100S_S0_IR 0x0402
149 #define W5100S_S0_SR 0x0403
150 #define W5100S_S0_PORTR0 0x0404
151 #define W5100S_S0_PORTR1 0x0405
152 #define W5100S_S0_DHAR0 0x0406
153 #define W5100S_S0_DHAR1 0x0407
154 #define W5100S_S0_DHAR2 0x0408
155 #define W5100S_S0_DHAR3 0x0409
156 #define W5100S_S0_DHAR4 0x040A
157 #define W5100S_S0_DHAR5 0x040B
158 #define W5100S_S0_DIPR0 0x040C
159 #define W5100S_S0_DIPR1 0x040D
160 #define W5100S_S0_DIPR2 0x040E
161 #define W5100S_S0_DIPR3 0x040F
162 #define W5100S_S0_DPORTR0 0x0410
163 #define W5100S_S0_DPORTR1 0x0411
164 #define W5100S_S0_MSS0 0x0412
165 #define W5100S_S0_MSS1 0x0413
166 #define W5100S_S0_PROTOR 0x0414
167 #define W5100S_S0_TOS 0x0415
168 #define W5100S_S0_TTL 0x0416
169 #define W5100S_S0_RXBUF_SIZE 0x041E
170 #define W5100S_S0_TXBUF_SIZE 0x041F
171 #define W5100S_S0_TX_FSR0 0x0420
172 #define W5100S_S0_TX_FSR1 0x0421
173 #define W5100S_S0_TX_RD0 0x0422
174 #define W5100S_S0_TX_RD1 0x0423
175 #define W5100S_S0_TX_WR0 0x0424
176 #define W5100S_S0_TX_WR1 0x0425
177 #define W5100S_S0_RX_RSR0 0x0426
178 #define W5100S_S0_RX_RSR1 0x0427
179 #define W5100S_S0_RX_RD0 0x0428
180 #define W5100S_S0_RX_RD1 0x0429
181 #define W5100S_S0_RX_WR0 0x042A
182 #define W5100S_S0_RX_WR1 0x042B
183 #define W5100S_S0_IMR 0x042C
184 #define W5100S_S0_FRAGR0 0x042D
185 #define W5100S_S0_FRAGR1 0x042E
186 #define W5100S_S0_MR2 0x042F
187 #define W5100S_S0_KPALVTR 0x0430
188 #define W5100S_S0_RTR0 0x0432
189 #define W5100S_S0_RTR1 0x0433
190 #define W5100S_S0_RCR 0x0434
191 #define W5100S_S1_MR 0x0500
192 #define W5100S_S1_CR 0x0501
193 #define W5100S_S1_IR 0x0502
194 #define W5100S_S1_SR 0x0503
195 #define W5100S_S1_PORTR0 0x0504
196 #define W5100S_S1_PORTR1 0x0505
197 #define W5100S_S1_DHAR0 0x0506
198 #define W5100S_S1_DHAR1 0x0507
199 #define W5100S_S1_DHAR2 0x0508
200 #define W5100S_S1_DHAR3 0x0509
201 #define W5100S_S1_DHAR4 0x050A
202 #define W5100S_S1_DHAR5 0x050B
203 #define W5100S_S1_DIPR0 0x050C
204 #define W5100S_S1_DIPR1 0x050D
205 #define W5100S_S1_DIPR2 0x050E
206 #define W5100S_S1_DIPR3 0x050F
207 #define W5100S_S1_DPORTR0 0x0510
208 #define W5100S_S1_DPORTR1 0x0511
209 #define W5100S_S1_MSS0 0x0512
210 #define W5100S_S1_MSS1 0x0513
211 #define W5100S_S1_PROTOR 0x0514
212 #define W5100S_S1_TOS 0x0515
213 #define W5100S_S1_TTL 0x0516
214 #define W5100S_S1_RXBUF_SIZE 0x051E
215 #define W5100S_S1_TXBUF_SIZE 0x051F
216 #define W5100S_S1_TX_FSR0 0x0520
217 #define W5100S_S1_TX_FSR1 0x0521
218 #define W5100S_S1_TX_RD0 0x0522
219 #define W5100S_S1_TX_RD1 0x0523
220 #define W5100S_S1_TX_WR0 0x0524
221 #define W5100S_S1_TX_WR1 0x0525
222 #define W5100S_S1_RX_RSR0 0x0526
223 #define W5100S_S1_RX_RSR1 0x0527
224 #define W5100S_S1_RX_RD0 0x0528
225 #define W5100S_S1_RX_RD1 0x0529
226 #define W5100S_S1_RX_WR0 0x052A
227 #define W5100S_S1_RX_WR1 0x052B
228 #define W5100S_S1_IMR 0x052C
229 #define W5100S_S1_FRAGR0 0x052D
230 #define W5100S_S1_FRAGR1 0x052E
231 #define W5100S_S1_MR2 0x052F
232 #define W5100S_S1_KPALVTR 0x0530
233 #define W5100S_S1_RTR0 0x0532
234 #define W5100S_S1_RTR1 0x0533
235 #define W5100S_S1_RCR 0x0534
236 #define W5100S_S2_MR 0x0600
237 #define W5100S_S2_CR 0x0601
238 #define W5100S_S2_IR 0x0602
239 #define W5100S_S2_SR 0x0603
240 #define W5100S_S2_PORTR0 0x0604
241 #define W5100S_S2_PORTR1 0x0605
242 #define W5100S_S2_DHAR0 0x0606
243 #define W5100S_S2_DHAR1 0x0607
244 #define W5100S_S2_DHAR2 0x0608
245 #define W5100S_S2_DHAR3 0x0609
246 #define W5100S_S2_DHAR4 0x060A
247 #define W5100S_S2_DHAR5 0x060B
248 #define W5100S_S2_DIPR0 0x060C
249 #define W5100S_S2_DIPR1 0x060D
250 #define W5100S_S2_DIPR2 0x060E
251 #define W5100S_S2_DIPR3 0x060F
252 #define W5100S_S2_DPORTR0 0x0610
253 #define W5100S_S2_DPORTR1 0x0611
254 #define W5100S_S2_MSS0 0x0612
255 #define W5100S_S2_MSS1 0x0613
256 #define W5100S_S2_PROTOR 0x0614
257 #define W5100S_S2_TOS 0x0615
258 #define W5100S_S2_TTL 0x0616
259 #define W5100S_S2_RXBUF_SIZE 0x061E
260 #define W5100S_S2_TXBUF_SIZE 0x061F
261 #define W5100S_S2_TX_FSR0 0x0620
262 #define W5100S_S2_TX_FSR1 0x0621
263 #define W5100S_S2_TX_RD0 0x0622
264 #define W5100S_S2_TX_RD1 0x0623
265 #define W5100S_S2_TX_WR0 0x0624
266 #define W5100S_S2_TX_WR1 0x0625
267 #define W5100S_S2_RX_RSR0 0x0626
268 #define W5100S_S2_RX_RSR1 0x0627
269 #define W5100S_S2_RX_RD0 0x0628
270 #define W5100S_S2_RX_RD1 0x0629
271 #define W5100S_S2_RX_WR0 0x062A
272 #define W5100S_S2_RX_WR1 0x062B
273 #define W5100S_S2_IMR 0x062C
274 #define W5100S_S2_FRAGR0 0x062D
275 #define W5100S_S2_FRAGR1 0x062E
276 #define W5100S_S2_MR2 0x062F
277 #define W5100S_S2_KPALVTR 0x0630
278 #define W5100S_S2_RTR0 0x0632
279 #define W5100S_S2_RTR1 0x0633
280 #define W5100S_S2_RCR 0x0634
281 #define W5100S_S3_MR 0x0700
282 #define W5100S_S3_CR 0x0701
283 #define W5100S_S3_IR 0x0702
284 #define W5100S_S3_SR 0x0703
285 #define W5100S_S3_PORTR0 0x0704
286 #define W5100S_S3_PORTR1 0x0705
287 #define W5100S_S3_DHAR0 0x0706
288 #define W5100S_S3_DHAR1 0x0707
289 #define W5100S_S3_DHAR2 0x0708
290 #define W5100S_S3_DHAR3 0x0709
291 #define W5100S_S3_DHAR4 0x070A
292 #define W5100S_S3_DHAR5 0x070B
293 #define W5100S_S3_DIPR0 0x070C
294 #define W5100S_S3_DIPR1 0x070D
295 #define W5100S_S3_DIPR2 0x070E
296 #define W5100S_S3_DIPR3 0x070F
297 #define W5100S_S3_DPORTR0 0x0710
298 #define W5100S_S3_DPORTR1 0x0711
299 #define W5100S_S3_MSS0 0x0712
300 #define W5100S_S3_MSS1 0x0713
301 #define W5100S_S3_PROTOR 0x0714
302 #define W5100S_S3_TOS 0x0715
303 #define W5100S_S3_TTL 0x0716
304 #define W5100S_S3_RXBUF_SIZE 0x071E
305 #define W5100S_S3_TXBUF_SIZE 0x071F
306 #define W5100S_S3_TX_FSR0 0x0720
307 #define W5100S_S3_TX_FSR1 0x0721
308 #define W5100S_S3_TX_RD0 0x0722
309 #define W5100S_S3_TX_RD1 0x0723
310 #define W5100S_S3_TX_WR0 0x0724
311 #define W5100S_S3_TX_WR1 0x0725
312 #define W5100S_S3_RX_RSR0 0x0726
313 #define W5100S_S3_RX_RSR1 0x0727
314 #define W5100S_S3_RX_RD0 0x0728
315 #define W5100S_S3_RX_RD1 0x0729
316 #define W5100S_S3_RX_WR0 0x072A
317 #define W5100S_S3_RX_WR1 0x072B
318 #define W5100S_S3_IMR 0x072C
319 #define W5100S_S3_FRAGR0 0x072D
320 #define W5100S_S3_FRAGR1 0x072E
321 #define W5100S_S3_MR2 0x072F
322 #define W5100S_S3_KPALVTR 0x0730
323 #define W5100S_S3_RTR0 0x0732
324 #define W5100S_S3_RTR1 0x0733
325 #define W5100S_S3_RCR 0x0734
326 
327 //W5100S Socket register access macros
328 #define W5100S_Sn_MR(n) (0x0400 + ((n) * 0x0100))
329 #define W5100S_Sn_CR(n) (0x0401 + ((n) * 0x0100))
330 #define W5100S_Sn_IR(n) (0x0402 + ((n) * 0x0100))
331 #define W5100S_Sn_SR(n) (0x0403 + ((n) * 0x0100))
332 #define W5100S_Sn_PORTR0(n) (0x0404 + ((n) * 0x0100))
333 #define W5100S_Sn_PORTR1(n) (0x0405 + ((n) * 0x0100))
334 #define W5100S_Sn_DHAR0(n) (0x0406 + ((n) * 0x0100))
335 #define W5100S_Sn_DHAR1(n) (0x0407 + ((n) * 0x0100))
336 #define W5100S_Sn_DHAR2(n) (0x0408 + ((n) * 0x0100))
337 #define W5100S_Sn_DHAR3(n) (0x0409 + ((n) * 0x0100))
338 #define W5100S_Sn_DHAR4(n) (0x040A + ((n) * 0x0100))
339 #define W5100S_Sn_DHAR5(n) (0x040B + ((n) * 0x0100))
340 #define W5100S_Sn_DIPR0(n) (0x040C + ((n) * 0x0100))
341 #define W5100S_Sn_DIPR1(n) (0x040D + ((n) * 0x0100))
342 #define W5100S_Sn_DIPR2(n) (0x040E + ((n) * 0x0100))
343 #define W5100S_Sn_DIPR3(n) (0x040F + ((n) * 0x0100))
344 #define W5100S_Sn_DPORTR0(n) (0x0410 + ((n) * 0x0100))
345 #define W5100S_Sn_DPORTR1(n) (0x0411 + ((n) * 0x0100))
346 #define W5100S_Sn_MSS0(n) (0x0412 + ((n) * 0x0100))
347 #define W5100S_Sn_MSS1(n) (0x0413 + ((n) * 0x0100))
348 #define W5100S_Sn_PROTOR(n) (0x0414 + ((n) * 0x0100))
349 #define W5100S_Sn_TOS(n) (0x0415 + ((n) * 0x0100))
350 #define W5100S_Sn_TTL(n) (0x0416 + ((n) * 0x0100))
351 #define W5100S_Sn_RXBUF_SIZE(n) (0x041E + ((n) * 0x0100))
352 #define W5100S_Sn_TXBUF_SIZE(n) (0x041F + ((n) * 0x0100))
353 #define W5100S_Sn_TX_FSR0(n) (0x0420 + ((n) * 0x0100))
354 #define W5100S_Sn_TX_FSR1(n) (0x0421 + ((n) * 0x0100))
355 #define W5100S_Sn_TX_RD0(n) (0x0422 + ((n) * 0x0100))
356 #define W5100S_Sn_TX_RD1(n) (0x0423 + ((n) * 0x0100))
357 #define W5100S_Sn_TX_WR0(n) (0x0424 + ((n) * 0x0100))
358 #define W5100S_Sn_TX_WR1(n) (0x0425 + ((n) * 0x0100))
359 #define W5100S_Sn_RX_RSR0(n) (0x0426 + ((n) * 0x0100))
360 #define W5100S_Sn_RX_RSR1(n) (0x0427 + ((n) * 0x0100))
361 #define W5100S_Sn_RX_RD0(n) (0x0428 + ((n) * 0x0100))
362 #define W5100S_Sn_RX_RD1(n) (0x0429 + ((n) * 0x0100))
363 #define W5100S_Sn_RX_WR0(n) (0x042A + ((n) * 0x0100))
364 #define W5100S_Sn_RX_WR1(n) (0x042B + ((n) * 0x0100))
365 #define W5100S_Sn_IMR(n) (0x042C + ((n) * 0x0100))
366 #define W5100S_Sn_FRAGR0(n) (0x042D + ((n) * 0x0100))
367 #define W5100S_Sn_FRAGR1(n) (0x042E + ((n) * 0x0100))
368 #define W5100S_Sn_MR2(n) (0x042F + ((n) * 0x0100))
369 #define W5100S_Sn_KPALVTR(n) (0x0430 + ((n) * 0x0100))
370 #define W5100S_Sn_RTR0(n) (0x0432 + ((n) * 0x0100))
371 #define W5100S_Sn_RTR1(n) (0x0433 + ((n) * 0x0100))
372 #define W5100S_Sn_RCR(n) (0x0434 + ((n) * 0x0100))
373 
374 //TX and RX buffers
375 #define W5100S_TX_BUFFER 0x4000
376 #define W5100S_RX_BUFFER 0x6000
377 
378 //Mode register
379 #define W5100S_MR_RST 0x80
380 #define W5100S_MR_PB 0x10
381 #define W5100S_MR_PPPOE 0x08
382 
383 //Interrupt register
384 #define W5100S_IR_CONFLICT 0x80
385 #define W5100S_IR_UNREACH 0x40
386 #define W5100S_IR_PPPTERM 0x20
387 #define W5100S_IR_S3_INT 0x08
388 #define W5100S_IR_S2_INT 0x04
389 #define W5100S_IR_S1_INT 0x02
390 #define W5100S_IR_S0_INT 0x01
391 
392 //Interrupt Mask register
393 #define W5100S_IMR_CNFT 0x80
394 #define W5100S_IMR_UNREACH 0x40
395 #define W5100S_IMR_PPPTERM 0x20
396 #define W5100S_IMR_S3_INT 0x08
397 #define W5100S_IMR_S2_INT 0x04
398 #define W5100S_IMR_S1_INT 0x02
399 #define W5100S_IMR_S0_INT 0x01
400 
401 //RX Memory Size register
402 #define W5100S_RMSR_SOCKET3 0xC0
403 #define W5100S_RMSR_SOCKET3_1KB 0x00
404 #define W5100S_RMSR_SOCKET3_2KB 0x40
405 #define W5100S_RMSR_SOCKET3_4KB 0x80
406 #define W5100S_RMSR_SOCKET3_8KB 0xC0
407 #define W5100S_RMSR_SOCKET2 0x30
408 #define W5100S_RMSR_SOCKET2_1KB 0x00
409 #define W5100S_RMSR_SOCKET2_2KB 0x10
410 #define W5100S_RMSR_SOCKET2_4KB 0x20
411 #define W5100S_RMSR_SOCKET2_8KB 0x30
412 #define W5100S_RMSR_SOCKET1 0x0C
413 #define W5100S_RMSR_SOCKET1_1KB 0x00
414 #define W5100S_RMSR_SOCKET1_2KB 0x04
415 #define W5100S_RMSR_SOCKET1_4KB 0x08
416 #define W5100S_RMSR_SOCKET1_8KB 0x0C
417 #define W5100S_RMSR_SOCKET0 0x03
418 #define W5100S_RMSR_SOCKET0_1KB 0x00
419 #define W5100S_RMSR_SOCKET0_2KB 0x01
420 #define W5100S_RMSR_SOCKET0_4KB 0x02
421 #define W5100S_RMSR_SOCKET0_8KB 0x03
422 
423 //TX Memory Size register
424 #define W5100S_TMSR_SOCKET3 0xC0
425 #define W5100S_TMSR_SOCKET3_1KB 0x00
426 #define W5100S_TMSR_SOCKET3_2KB 0x40
427 #define W5100S_TMSR_SOCKET3_4KB 0x80
428 #define W5100S_TMSR_SOCKET3_8KB 0xC0
429 #define W5100S_TMSR_SOCKET2 0x30
430 #define W5100S_TMSR_SOCKET2_1KB 0x00
431 #define W5100S_TMSR_SOCKET2_2KB 0x10
432 #define W5100S_TMSR_SOCKET2_4KB 0x20
433 #define W5100S_TMSR_SOCKET2_8KB 0x30
434 #define W5100S_TMSR_SOCKET1 0x0C
435 #define W5100S_TMSR_SOCKET1_1KB 0x00
436 #define W5100S_TMSR_SOCKET1_2KB 0x04
437 #define W5100S_TMSR_SOCKET1_4KB 0x08
438 #define W5100S_TMSR_SOCKET1_8KB 0x0C
439 #define W5100S_TMSR_SOCKET0 0x03
440 #define W5100S_TMSR_SOCKET0_1KB 0x00
441 #define W5100S_TMSR_SOCKET0_2KB 0x01
442 #define W5100S_TMSR_SOCKET0_4KB 0x02
443 #define W5100S_TMSR_SOCKET0_8KB 0x03
444 
445 //Interrupt 2 register
446 #define W5100S_IR2_WOL 0x01
447 
448 //Interrupt 2 Mask register
449 #define W5100S_IMR2_WOL 0x01
450 
451 //Mode 2 register
452 #define W5100S_MR2_CLKSEL 0x80
453 #define W5100S_MR2_IEN 0x40
454 #define W5100S_MR2_NOTCPRST 0x20
455 #define W5100S_MR2_UDPURB 0x10
456 #define W5100S_MR2_WOL 0x08
457 #define W5100S_MR2_FARP 0x02
458 
459 //PHY Status 0 register
460 #define W5100S_PHYSR0_CABOFF 0x80
461 #define W5100S_PHYSR0_AUTO 0x20
462 #define W5100S_PHYSR0_SPD 0x10
463 #define W5100S_PHYSR0_DPX 0x08
464 #define W5100S_PHYSR0_FDPX 0x04
465 #define W5100S_PHYSR0_FSPD 0x02
466 #define W5100S_PHYSR0_LINK 0x01
467 
468 //PHY Status 1 register
469 #define W5100S_PHYSR1_ACT 0x80
470 #define W5100S_PHYSR1_RXP 0x04
471 #define W5100S_PHYSR1_LPI 0x02
472 #define W5100S_PHYSR1_CAL 0x01
473 
474 //PHY Register Address register
475 #define W5100S_PHYRAR_ADDR 0x1F
476 
477 //PHY Division register
478 #define W5100S_PHYDIVR_DIV32 0x00
479 #define W5100S_PHYDIVR_DIV64 0x01
480 #define W5100S_PHYDIVR_DIV128 0x02
481 
482 //PHY Control 0 register
483 #define W5100S_PHYCR0_MODE 0x07
484 #define W5100S_PHYCR0_MODE_AN 0x00
485 #define W5100S_PHYCR0_MODE_100BTX_FD 0x04
486 #define W5100S_PHYCR0_MODE_100BTX_HD 0x05
487 #define W5100S_PHYCR0_MODE_10BT_FD 0x06
488 #define W5100S_PHYCR0_MODE_10BT_HD 0x07
489 
490 //PHY Control 1 register
491 #define W5100S_PHYCR1_WOL 0x80
492 #define W5100S_PHYCR1_PWDN 0x20
493 #define W5100S_PHYCR1_RST 0x01
494 
495 //Socket-less Command register
496 #define W5100S_SLCR_ARP 0x02
497 #define W5100S_SLCR_PING 0x01
498 
499 //Socket-less Interrupt Mask register
500 #define W5100S_SLIMR_TIMEOUT 0x04
501 #define W5100S_SLIMR_ARP 0x02
502 #define W5100S_SLIMR_PING 0x01
503 
504 //Socket-less Interrupt register
505 #define W5100S_SLIR_TIMEOUT 0x04
506 #define W5100S_SLIR_ARP 0x02
507 #define W5100S_SLIR_PING 0x01
508 
509 //Clock Lock register
510 #define W5100S_CLKLCKR_LOCK 0x00
511 #define W5100S_CLKLCKR_UNLOCK 0xCE
512 
513 //Network Lock register
514 #define W5100S_NETLCKR_UNLOCK 0x3A
515 #define W5100S_NETLCKR_LOCK 0xC5
516 
517 //PHY Lock register
518 #define W5100S_PHYLCKR_LOCK 0x00
519 #define W5100S_PHYLCKR_UNLOCK 0x53
520 
521 //Chip Version register
522 #define W5100S_VERR_DEFAULT 0x51
523 
524 //Socket n Mode register
525 #define W5100S_Sn_MR_MULTI 0x80
526 #define W5100S_Sn_MR_MF 0x40
527 #define W5100S_Sn_MR_ND 0x20
528 #define W5100S_Sn_MR_MC 0x20
529 #define W5100S_Sn_MR_PROTOCOL 0x0F
530 #define W5100S_Sn_MR_PROTOCOL_CLOSED 0x00
531 #define W5100S_Sn_MR_PROTOCOL_TCP 0x01
532 #define W5100S_Sn_MR_PROTOCOL_UDP 0x02
533 #define W5100S_Sn_MR_PROTOCOL_IPRAW 0x03
534 #define W5100S_Sn_MR_PROTOCOL_MACRAW 0x04
535 
536 //Socket n Command register
537 #define W5100S_Sn_CR_OPEN 0x01
538 #define W5100S_Sn_CR_LISTEN 0x02
539 #define W5100S_Sn_CR_CONNECT 0x04
540 #define W5100S_Sn_CR_DISCON 0x08
541 #define W5100S_Sn_CR_CLOSE 0x10
542 #define W5100S_Sn_CR_SEND 0x20
543 #define W5100S_Sn_CR_SEND_MAC 0x21
544 #define W5100S_Sn_CR_SEND_KEEP 0x22
545 #define W5100S_Sn_CR_RECV 0x40
546 
547 //Socket n Interrupt register
548 #define W5100S_Sn_IR_SENDOK 0x10
549 #define W5100S_Sn_IR_TIMEOUT 0x08
550 #define W5100S_Sn_IR_RECV 0x04
551 #define W5100S_Sn_IR_DISCON 0x02
552 #define W5100S_Sn_IR_CON 0x01
553 
554 //Socket n Status register
555 #define W5100S_Sn_SR_SOCK_CLOSED 0x00
556 #define W5100S_Sn_SR_SOCK_INIT 0x13
557 #define W5100S_Sn_SR_SOCK_LISTEN 0x14
558 #define W5100S_Sn_SR_SOCK_SYNSENT 0x15
559 #define W5100S_Sn_SR_SOCK_SYNRECV 0x16
560 #define W5100S_Sn_SR_SOCK_ESTABLISHED 0x17
561 #define W5100S_Sn_SR_SOCK_FIN_WAIT 0x18
562 #define W5100S_Sn_SR_SOCK_TIME_WAIT 0x1B
563 #define W5100S_Sn_SR_SOCK_CLOSE_WAIT 0x1C
564 #define W5100S_Sn_SR_SOCK_LAST_ACK 0x1D
565 #define W5100S_Sn_SR_SOCK_UDP 0x22
566 #define W5100S_Sn_SR_SOCK_IPRAW 0x32
567 #define W5100S_Sn_SR_SOCK_MACRAW 0x42
568 
569 //Socket n RX Buffer Size register
570 #define W5100S_Sn_RXBUF_SIZE_0KB 0x00
571 #define W5100S_Sn_RXBUF_SIZE_1KB 0x01
572 #define W5100S_Sn_RXBUF_SIZE_2KB 0x02
573 #define W5100S_Sn_RXBUF_SIZE_4KB 0x04
574 #define W5100S_Sn_RXBUF_SIZE_8KB 0x08
575 
576 //Socket n TX Buffer Size register
577 #define W5100S_Sn_TXBUF_SIZE_0KB 0x00
578 #define W5100S_Sn_TXBUF_SIZE_1KB 0x01
579 #define W5100S_Sn_TXBUF_SIZE_2KB 0x02
580 #define W5100S_Sn_TXBUF_SIZE_4KB 0x04
581 #define W5100S_Sn_TXBUF_SIZE_8KB 0x08
582 
583 //Socket n Interrupt Mask register
584 #define W5100S_Sn_IMR_SENDOK 0x10
585 #define W5100S_Sn_IMR_TIMEOUT 0x08
586 #define W5100S_Sn_IMR_RECV 0x04
587 #define W5100S_Sn_IMR_DISCON 0x02
588 #define W5100S_Sn_IMR_CON 0x01
589 
590 //Socket n Mode 2 register
591 #define W5100S_Sn_MR2_MBBLK 0x40
592 #define W5100S_Sn_MR2_MMBLK 0x20
593 #define W5100S_Sn_MR2_IPV6BLK 0x10
594 #define W5100S_Sn_MR2_BRDB 0x02
595 #define W5100S_Sn_MR2_UNIB 0x01
596 
597 //C++ guard
598 #ifdef __cplusplus
599 extern "C" {
600 #endif
601 
602 //W5100S driver
603 extern const NicDriver w5100sDriver;
604 
605 //W5100S related functions
606 error_t w5100sInit(NetInterface *interface);
607 void w5100sInitHook(NetInterface *interface);
608 
609 void w5100sTick(NetInterface *interface);
610 
611 void w5100sEnableIrq(NetInterface *interface);
612 void w5100sDisableIrq(NetInterface *interface);
614 void w5100sEventHandler(NetInterface *interface);
615 
617  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
618 
620 
622 
623 void w5100sWriteReg8(NetInterface *interface, uint16_t address, uint8_t data);
624 uint8_t w5100sReadReg8(NetInterface *interface, uint16_t address);
625 
626 void w5100sWriteReg16(NetInterface *interface, uint16_t address, uint16_t data);
627 uint16_t w5100sReadReg16(NetInterface *interface, uint16_t address);
628 
629 void w5100sWriteData(NetInterface *interface, const uint8_t *data,
630  size_t length);
631 
632 void w5100sReadData(NetInterface *interface, uint8_t *data, size_t length);
633 
634 void w5100sWriteBuffer(NetInterface *interface, uint16_t offset,
635  const uint8_t *data, size_t length);
636 
637 void w5100sReadBuffer(NetInterface *interface, uint16_t address, uint8_t *data,
638  size_t length);
639 
640 void w5100sDumpReg(NetInterface *interface);
641 
642 //C++ guard
643 #ifdef __cplusplus
644 }
645 #endif
646 
647 #endif
int bool_t
Definition: compiler_port.h:53
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint16_t w5100sReadReg16(NetInterface *interface, uint16_t address)
Read 16-bit register.
const NicDriver w5100sDriver
W5100S driver.
Definition: w5100s_driver.c:44
void w5100sDumpReg(NetInterface *interface)
Dump registers for debugging purpose.
void w5100sReadBuffer(NetInterface *interface, uint16_t address, uint8_t *data, size_t length)
Read RX buffer.
error_t w5100sSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void w5100sWriteReg8(NetInterface *interface, uint16_t address, uint8_t data)
Write 8-bit register.
void w5100sInitHook(NetInterface *interface)
W5100S custom configuration.
void w5100sWriteData(NetInterface *interface, const uint8_t *data, size_t length)
Write data.
uint8_t w5100sReadReg8(NetInterface *interface, uint16_t address)
Read 8-bit register.
void w5100sEnableIrq(NetInterface *interface)
Enable interrupts.
void w5100sReadData(NetInterface *interface, uint8_t *data, size_t length)
Read data.
void w5100sWriteBuffer(NetInterface *interface, uint16_t offset, const uint8_t *data, size_t length)
Write TX buffer.
error_t w5100sReceivePacket(NetInterface *interface)
Receive a packet.
void w5100sDisableIrq(NetInterface *interface)
Disable interrupts.
error_t w5100sUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void w5100sWriteReg16(NetInterface *interface, uint16_t address, uint16_t data)
Write 16-bit register.
void w5100sTick(NetInterface *interface)
W5100S timer handler.
error_t w5100sInit(NetInterface *interface)
W5100S controller initialization.
Definition: w5100s_driver.c:71
void w5100sEventHandler(NetInterface *interface)
W5100S event handler.
bool_t w5100sIrqHandler(NetInterface *interface)
W5100S interrupt service routine.