/**
 * @file dp83822_driver.c
 * @brief DP83822 Ethernet PHY driver
 *
 * @section License
 *
 * Copyright (C) 2021-2026 Oryx Embedded SARL. All rights reserved.
 *
 * This file is part of CycloneTCP Eval
 * 
 * This software is provided in source form for a short-term evaluation only. The
 * evaluation license expires 90 days after the date you first download the software.
 *
 * If you plan to use this software in a commercial product, you are required to
 * purchase a commercial license from Oryx Embedded SARL.
 *
 * After the 90-day evaluation period, you agree to either purchase a commercial
 * license or delete all copies of this software. If you wish to extend the
 * evaluation period, you must contact sales@oryx-embedded.com.
 *
 * This evaluation software is provided "as is" without warranty of any kind.
 * Technical support is available as an option during the evaluation period.

 *
 * @author Oryx Embedded SARL (www.oryx-embedded.com)
 * @version 2.6.2
 **/

//Switch to the appropriate trace level
#define TRACE_LEVEL NIC_TRACE_LEVEL

//Dependencies
#include "core/net.h"
#include "drivers/phy/dp83822_driver.h"
#include "debug.h"


/**
 * @brief DP83822 Ethernet PHY driver
 **/

const PhyDriver dp83822PhyDriver =
{
   dp83822Init,
   dp83822Tick,
   dp83822EnableIrq,
   dp83822DisableIrq,
   dp83822EventHandler
};


/**
 * @brief DP83822 PHY transceiver initialization
 * @param[in] interface Underlying network interface
 * @return Error code
 **/

error_t dp83822Init(NetInterface *interface)
{
   uint16_t value;

   //Debug message
   TRACE_INFO("Initializing DP83822...\r\n");

   //Undefined PHY address?
   if(interface->phyAddr >= 32)
   {
      //Use the default address
      interface->phyAddr = DP83822_PHY_ADDR;
   }

   //Initialize serial management interface
   if(interface->smiDriver != NULL)
   {
      interface->smiDriver->init();
   }

   //Initialize external interrupt line driver
   if(interface->extIntDriver != NULL)
   {
      interface->extIntDriver->init();
   }

   //Reset PHY transceiver
   dp83822WritePhyReg(interface, DP83822_BMCR, DP83822_BMCR_RESET);

   //Wait for the reset to complete
   while(dp83822ReadPhyReg(interface, DP83822_BMCR) & DP83822_BMCR_RESET)
   {
   }

   //Dump PHY registers for debugging purpose
   dp83822DumpPhyReg(interface);

   //Configure PWR_DOWN/INT pin as an interrupt output
   value = dp83822ReadPhyReg(interface, DP83822_PHYSCR);
   value |= DP83822_PHYSCR_INT_EN | DP83822_PHYSCR_INT_OE;
   dp83822WritePhyReg(interface, DP83822_PHYSCR, value);

   //The PHY will generate interrupts when link status changes are detected
   dp83822WritePhyReg(interface, DP83822_MISR1, DP83822_MISR1_LINK_INT_EN);

   //Perform custom configuration
   dp83822InitHook(interface);

   //Force the TCP/IP stack to poll the link state at startup
   interface->phyEvent = TRUE;
   //Notify the TCP/IP stack of the event
   osSetEvent(&interface->netContext->event);

   //Successful initialization
   return NO_ERROR;
}


/**
 * @brief DP83822 custom configuration
 * @param[in] interface Underlying network interface
 **/

__weak_func void dp83822InitHook(NetInterface *interface)
{
}


/**
 * @brief DP83822 timer handler
 * @param[in] interface Underlying network interface
 **/

void dp83822Tick(NetInterface *interface)
{
   uint16_t value;
   bool_t linkState;

   //No external interrupt line driver?
   if(interface->extIntDriver == NULL)
   {
      //Read basic status register
      value = dp83822ReadPhyReg(interface, DP83822_BMSR);
      //Retrieve current link state
      linkState = (value & DP83822_BMSR_LINK_STATUS) ? TRUE : FALSE;

      //Link up event?
      if(linkState && !interface->linkState)
      {
         //Set event flag
         interface->phyEvent = TRUE;
         //Notify the TCP/IP stack of the event
         osSetEvent(&interface->netContext->event);
      }
      //Link down event?
      else if(!linkState && interface->linkState)
      {
         //Set event flag
         interface->phyEvent = TRUE;
         //Notify the TCP/IP stack of the event
         osSetEvent(&interface->netContext->event);
      }
   }
}


/**
 * @brief Enable interrupts
 * @param[in] interface Underlying network interface
 **/

void dp83822EnableIrq(NetInterface *interface)
{
   //Enable PHY transceiver interrupts
   if(interface->extIntDriver != NULL)
   {
      interface->extIntDriver->enableIrq();
   }
}


/**
 * @brief Disable interrupts
 * @param[in] interface Underlying network interface
 **/

void dp83822DisableIrq(NetInterface *interface)
{
   //Disable PHY transceiver interrupts
   if(interface->extIntDriver != NULL)
   {
      interface->extIntDriver->disableIrq();
   }
}


/**
 * @brief DP83822 event handler
 * @param[in] interface Underlying network interface
 **/

void dp83822EventHandler(NetInterface *interface)
{
   uint16_t status;

   //Read status register to acknowledge the interrupt
   status = dp83822ReadPhyReg(interface, DP83822_MISR1);

   //Link status change?
   if((status & DP83822_MISR1_LINK_INT) != 0)
   {
      //Read PHY status register
      status = dp83822ReadPhyReg(interface, DP83822_PHYSTS);

      //Check link state
      if((status & DP83822_PHYSTS_LINK_STATUS) != 0)
      {
         //Check current speed
         if((status & DP83822_PHYSTS_SPEED_STATUS) != 0)
         {
            interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
         }
         else
         {
            interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
         }

         //Check duplex mode
         if((status & DP83822_PHYSTS_DUPLEX_STATUS) != 0)
         {
            interface->duplexMode = NIC_FULL_DUPLEX_MODE;
         }
         else
         {
            interface->duplexMode = NIC_HALF_DUPLEX_MODE;
         }

         //Update link state
         interface->linkState = TRUE;

         //Adjust MAC configuration parameters for proper operation
         interface->nicDriver->updateMacConfig(interface);
      }
      else
      {
         //Update link state
         interface->linkState = FALSE;
      }

      //Process link state change event
      nicNotifyLinkChange(interface);
   }
}


/**
 * @brief Write PHY register
 * @param[in] interface Underlying network interface
 * @param[in] address PHY register address
 * @param[in] data Register value
 **/

void dp83822WritePhyReg(NetInterface *interface, uint8_t address,
   uint16_t data)
{
   //Write the specified PHY register
   if(interface->smiDriver != NULL)
   {
      interface->smiDriver->writePhyReg(SMI_OPCODE_WRITE,
         interface->phyAddr, address, data);
   }
   else
   {
      interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE,
         interface->phyAddr, address, data);
   }
}


/**
 * @brief Read PHY register
 * @param[in] interface Underlying network interface
 * @param[in] address PHY register address
 * @return Register value
 **/

uint16_t dp83822ReadPhyReg(NetInterface *interface, uint8_t address)
{
   uint16_t data;

   //Read the specified PHY register
   if(interface->smiDriver != NULL)
   {
      data = interface->smiDriver->readPhyReg(SMI_OPCODE_READ,
         interface->phyAddr, address);
   }
   else
   {
      data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ,
         interface->phyAddr, address);
   }

   //Return the value of the PHY register
   return data;
}


/**
 * @brief Dump PHY registers for debugging purpose
 * @param[in] interface Underlying network interface
 **/

void dp83822DumpPhyReg(NetInterface *interface)
{
   uint8_t i;

   //Loop through PHY registers
   for(i = 0; i < 32; i++)
   {
      //Display current PHY register
      TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
         dp83822ReadPhyReg(interface, i));
   }

   //Terminate with a line feed
   TRACE_DEBUG("\r\n");
}


/**
 * @brief Write MMD register
 * @param[in] interface Underlying network interface
 * @param[in] devAddr Device address
 * @param[in] regAddr Register address
 * @param[in] data MMD register value
 **/

void dp83822WriteMmdReg(NetInterface *interface, uint8_t devAddr,
   uint16_t regAddr, uint16_t data)
{
   //Select register operation
   dp83822WritePhyReg(interface, DP83822_REGCR,
      DP83822_REGCR_CMD_ADDR | (devAddr & DP83822_REGCR_DEVAD));

   //Write MMD register address
   dp83822WritePhyReg(interface, DP83822_ADDAR, regAddr);

   //Select data operation
   dp83822WritePhyReg(interface, DP83822_REGCR,
      DP83822_REGCR_CMD_DATA_NO_POST_INC | (devAddr & DP83822_REGCR_DEVAD));

   //Write the content of the MMD register
   dp83822WritePhyReg(interface, DP83822_ADDAR, data);
}


/**
 * @brief Read MMD register
 * @param[in] interface Underlying network interface
 * @param[in] devAddr Device address
 * @param[in] regAddr Register address
 * @return MMD register value
 **/

uint16_t dp83822ReadMmdReg(NetInterface *interface, uint8_t devAddr,
   uint16_t regAddr)
{
   //Select register operation
   dp83822WritePhyReg(interface, DP83822_REGCR,
      DP83822_REGCR_CMD_ADDR | (devAddr & DP83822_REGCR_DEVAD));

   //Write MMD register address
   dp83822WritePhyReg(interface, DP83822_ADDAR, regAddr);

   //Select data operation
   dp83822WritePhyReg(interface, DP83822_REGCR,
      DP83822_REGCR_CMD_DATA_NO_POST_INC | (devAddr & DP83822_REGCR_DEVAD));

   //Read the content of the MMD register
   return dp83822ReadPhyReg(interface, DP83822_ADDAR);
}
