
/****************************************************************************************************//**
 * @file     LPC43xx.h
 *
 * @status   RELEASE
 *
 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
 *           default LPC43xx Device Series
 *
 * @version  V5
 * @date     9. December 2011
 *
 * @note     Generated with SVDConv V2.6 Build 6c  on Friday, 09.12.2011 13:56:08
 *
 *           from CMSIS SVD File 'LPC43xxv5.xml' Version 5,
 *           created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04
 *
 *           Modified by KEIL
 *******************************************************************************************************/



/** @addtogroup (null)
  * @{
  */

/** @addtogroup LPC43xx
  * @{
  */

#ifndef __LPC43XX_H__
#define __LPC43XX_H__

#ifdef __cplusplus
extern "C" {
#endif



/********************************************
** Start of section using anonymous unions **
*********************************************/

#if defined(__ARMCC_VERSION)
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma push
  #pragma language=extended
#else
  #error Not supported compiler type
#endif


 /* Interrupt Number Definition */

typedef enum {
// -------------------------  Cortex-M4 Processor Exceptions Numbers  -----------------------------
  Reset_IRQn                        = -15,
  NonMaskableInt_IRQn               = -14,
  HardFault_IRQn                    = -13,
  MemoryManagement_IRQn             = -12,
  BusFault_IRQn                     = -11,
  UsageFault_IRQn                   = -10,
  SVCall_IRQn                       =  -5,
  DebugMonitor_IRQn                 =  -4,
  PendSV_IRQn                       =  -2,
  SysTick_IRQn                      =  -1,
// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
  DAC_IRQn                          =   0,
  M0CORE_IRQn                       =   1,
  DMA_IRQn                          =   2,
  RESERVED1_IRQn                    =   3,
  RESERVED2_IRQn                    =   4,
  ETHERNET_IRQn                     =   5,
  SDIO_IRQn                         =   6,
  LCD_IRQn                          =   7,
  USB0_IRQn                         =   8,
  USB1_IRQn                         =   9,
  SCT_IRQn                          =  10,
  RITIMER_IRQn                      =  11,
  TIMER0_IRQn                       =  12,
  TIMER1_IRQn                       =  13,
  TIMER2_IRQn                       =  14,
  TIMER3_IRQn                       =  15,
  MCPWM_IRQn                        =  16,
  ADC0_IRQn                         =  17,
  I2C0_IRQn                         =  18,
  I2C1_IRQn                         =  19,
  SPI_INT_IRQn                      =  20,
  ADC1_IRQn                         =  21,
  SSP0_IRQn                         =  22,
  SSP1_IRQn                         =  23,
  USART0_IRQn                       =  24,
  UART1_IRQn                        =  25,
  USART2_IRQn                       =  26,
  USART3_IRQn                       =  27,
  I2S0_IRQn                         =  28,
  I2S1_IRQn                         =  29,
  RESERVED4_IRQn                    =  30,
  SGPIO_IINT_IRQn                   =  31,
  PIN_INT0_IRQn                     =  32,
  PIN_INT1_IRQn                     =  33,
  PIN_INT2_IRQn                     =  34,
  PIN_INT3_IRQn                     =  35,
  PIN_INT4_IRQn                     =  36,
  PIN_INT5_IRQn                     =  37,
  PIN_INT6_IRQn                     =  38,
  PIN_INT7_IRQn                     =  39,
  GINT0_IRQn                        =  40,
  GINT1_IRQn                        =  41,
  EVENTROUTER_IRQn                  =  42,
  C_CAN1_IRQn                       =  43,
  RESERVED6_IRQn                    =  44,
  RESERVED7_IRQn                    =  45,
  ATIMER_IRQn                       =  46,
  RTC_IRQn                          =  47,
  RESERVED8_IRQn                    =  48,
  WWDT_IRQn                         =  49,
  RESERVED9_IRQn                    =  50,
  C_CAN0_IRQn                       =  51,
  QEI_IRQn                          =  52,

// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
  M0_Reset_IRQn                     = -15,
  M0_NonMaskableInt_IRQn            = -14,
  M0_HardFault_IRQn                 = -13,
  M0_SVCall_IRQn                    =  -5,
  M0_DebugMonitor_IRQn              =  -4,
  M0_PendSV_IRQn                    =  -2,
  M0_SysTick_IRQn                   =  -1,
// ---------------------------  LPC43xx Specific Interrupt Numbers  -------------------------------
  M0_RTC_IRQn                       =   0,
  M0_M4CORE_IRQn                    =   1,
  M0_DMA_IRQn                       =   2,
  M0_RESERVED0_IRQn                 =   3,
  M0_RESERVED1_IRQn                 =   4,
  M0_ETHERNET_IRQn                  =   5,
  M0_SDIO_IRQn                      =   6,
  M0_LCD_IRQn                       =   7,
  M0_USB0_IRQn                      =   8,
  M0_USB1_IRQn                      =   9,
  M0_SCT_IRQn                       =  10,
  M0_RITIMER_OR_WWDT_IRQn           =  11,
  M0_TIMER0_IRQn                    =  12,
  M0_GINT1_IRQn                     =  13,
  M0_TIMER3_IRQn                    =  15,
  M0_RESERVED2_IRQn                 =  14,
  M0_RESERVED3_IRQn                 =  15,
  M0_MCPWM_IRQn                     =  16,
  M0_ADC0_IRQn                      =  17,
  M0_I2C0_OR_I2C1_IRQn              =  18,
  M0_SGPIO_IRQn                     =  19,
  M0_SPI_OR_DAC_IRQn                =  20,
  M0_ADC1_IRQn                      =  21,
  M0_SSP0_OR_SSP1_IRQn              =  22,
  M0_EVENTROUTER_IRQn               =  23,
  M0_USART0_IRQn                    =  24,
  M0_UART1_IRQn                     =  25,
  M0_USART2_OR_C_CAN1_IRQn          =  26,
  M0_USART3_IRQn                    =  27,
  M0_I2S0_OR_I2S1_OR_QEI_IRQn       =  28,
  M0_C_CAN0_IRQn                    =  29
} IRQn_Type;

 /* Event Router Input (ERI) Number Definitions */
typedef enum {
  WAKEUP0_ERIn                      = 0,
  WAKEUP1_ERIn                      = 1,
  WAKEUP2_ERIn                      = 2,
  WAKEUP3_ERIn                      = 3,
  ATIMER_ERIn                       = 4,
  RTC_ERIn                          = 5,
  BOD1_ERIn                         = 6,  /* Bod trip 1 */
  WWDT_ERIn                         = 7,
  ETH_ERIn                          = 8,
  USB0_ERIn                         = 9,
  USB1_ERIn                         = 10,
  SDIO_ERIn                         = 11,
  CAN_ERIn                          = 12, /* CAN0/1 or'ed */
  TIM2_ERIn                         = 13,
  TIM6_ERIn                         = 14,
  QEI_ERIn                          = 15,
  TIM14_ERIn                        = 16,
  RESERVED0_ERIn                    = 17, /* M0s */
  RESERVED1_ERIn                    = 18, /* M3/M4 */
  RESET_ERIn                        = 19
}ERIn_Type;

/** @addtogroup Configuration_of_CMSIS
  * @{
  */

/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */

#ifndef CORE_M0
#define __CM4_REV              0x0000
#define __MPU_PRESENT             1
#define __NVIC_PRIO_BITS          3
#define __Vendor_SysTickConfig    0
#define __FPU_PRESENT             1
/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm4.h>
#else
#ifdef CORE_M0
#define __MPU_PRESENT             0
#define __NVIC_PRIO_BITS          2
#define __Vendor_SysTickConfig    0
#define __FPU_PRESENT             0
/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm0.h>
#else
#error Please #define CORE_M0 or CORE_M4
#endif
#endif

/** @} */ /* End of group Configuration_of_CMSIS */
#include "system_LPC43xx.h"

/** @addtogroup Device_Peripheral_Registers
  * @{
  */


// ------------------------------------------------------------------------------------------------
// -----                                          SCT                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
  */

#define CONFIG_SCT_nEV   (16)            /* Number of events */
#define CONFIG_SCT_nRG   (16)            /* Number of match/compare registers */
#define CONFIG_SCT_nOU   (16)            /* Number of outputs */

typedef struct
{
    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
    union {
        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
        struct {
            __IO uint16_t CTRL_L;       /* 0x004 low control register */
            __IO uint16_t CTRL_H;       /* 0x006 high control register */
        };
    };
    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
    __IO uint16_t START_L;              /* 0x014 start register for counter L */
    __IO uint16_t START_H;              /* 0x016 start register for counter H */
         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
    union {
        __IO uint32_t COUNT_U;          /* 0x040 counter register */
        struct {
            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
        };
    };
    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
    __I  uint32_t INPUT;                /* 0x048 input register */
    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
    __IO uint32_t OUTPUT;               /* 0x050 output register */
    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
    __IO uint32_t DMA0REQUEST;          /* 0x05C DMA0 Request Register */
    __IO uint32_t DMA1REQUEST;          /* 0x060 DMA1 Request Register */
         uint32_t RESERVED2[35];        /* 0x064-0x0EC reserved */
    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */

    union {
        __IO union {                    /* 0x100-... Match / Capture value */
            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
            };
        } MATCH[CONFIG_SCT_nRG];
        __I union {
            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
            };
        } CAP[CONFIG_SCT_nRG];
    };

         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */

    union {
        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
    };
         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
    union {
        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
    };
         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */

    union {
        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
            };
        } MATCHREL[CONFIG_SCT_nRG];
        __IO union {
            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
            struct {
                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
            };
        } CAPCTRL[CONFIG_SCT_nRG];
    };

         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */

    union {
        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
    };
         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
    union {
        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
    };
         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */

    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
        uint32_t STATE;                 /* Event State Register */
        uint32_t CTRL;                  /* Event Control Register */
    } EVENT[CONFIG_SCT_nEV];

         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */

    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
        uint32_t SET;                   /* Output n Set Register */
        uint32_t CLR;                   /* Output n Clear Register */
    } OUT[CONFIG_SCT_nOU];

         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */

    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */

} LPC_SCT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         GPDMA                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (GPDMA)
  */

typedef struct {
  __I  uint32_t  INTSTAT;
  __I  uint32_t  INTTCSTAT;
  __O  uint32_t  INTTCCLEAR;
  __I  uint32_t  INTERRSTAT;
  __O  uint32_t  INTERRCLR;
  __I  uint32_t  RAWINTTCSTAT;
  __I  uint32_t  RAWINTERRSTAT;
  __I  uint32_t  ENBLDCHNS;
  __IO uint32_t  SOFTBREQ;
  __IO uint32_t  SOFTSREQ;
  __IO uint32_t  SOFTLBREQ;
  __IO uint32_t  SOFTLSREQ;
  __IO uint32_t  CONFIG;
  __IO uint32_t  SYNC;
  __I  uint32_t  RESERVED0[50];
  __IO uint32_t  C0SRCADDR;
  __IO uint32_t  C0DESTADDR;
  __IO uint32_t  C0LLI;
  __IO uint32_t  C0CONTROL;
  __IO uint32_t  C0CONFIG;
  __I  uint32_t  RESERVED1[3];
  __IO uint32_t  C1SRCADDR;
  __IO uint32_t  C1DESTADDR;
  __IO uint32_t  C1LLI;
  __IO uint32_t  C1CONTROL;
  __IO uint32_t  C1CONFIG;
  __I  uint32_t  RESERVED2[3];
  __IO uint32_t  C2SRCADDR;
  __IO uint32_t  C2DESTADDR;
  __IO uint32_t  C2LLI;
  __IO uint32_t  C2CONTROL;
  __IO uint32_t  C2CONFIG;
  __I  uint32_t  RESERVED3[3];
  __IO uint32_t  C3SRCADDR;
  __IO uint32_t  C3DESTADDR;
  __IO uint32_t  C3LLI;
  __IO uint32_t  C3CONTROL;
  __IO uint32_t  C3CONFIG;
  __I  uint32_t  RESERVED4[3];
  __IO uint32_t  C4SRCADDR;
  __IO uint32_t  C4DESTADDR;
  __IO uint32_t  C4LLI;
  __IO uint32_t  C4CONTROL;
  __IO uint32_t  C4CONFIG;
  __I  uint32_t  RESERVED5[3];
  __IO uint32_t  C5SRCADDR;
  __IO uint32_t  C5DESTADDR;
  __IO uint32_t  C5LLI;
  __IO uint32_t  C5CONTROL;
  __IO uint32_t  C5CONFIG;
  __I  uint32_t  RESERVED6[3];
  __IO uint32_t  C6SRCADDR;
  __IO uint32_t  C6DESTADDR;
  __IO uint32_t  C6LLI;
  __IO uint32_t  C6CONTROL;
  __IO uint32_t  C6CONFIG;
  __I  uint32_t  RESERVED7[3];
  __IO uint32_t  C7SRCADDR;
  __IO uint32_t  C7DESTADDR;
  __IO uint32_t  C7LLI;
  __IO uint32_t  C7CONTROL;
  __IO uint32_t  C7CONFIG;
} LPC_GPDMA_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SDMMC                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a  (SDMMC)
  */

typedef struct {
  __IO uint32_t  CTRL;
  __IO uint32_t  PWREN;
  __IO uint32_t  CLKDIV;
  __IO uint32_t  CLKSRC;
  __IO uint32_t  CLKENA;
  __IO uint32_t  TMOUT;
  __IO uint32_t  CTYPE;
  __IO uint32_t  BLKSIZ;
  __IO uint32_t  BYTCNT;
  __IO uint32_t  INTMASK;
  __IO uint32_t  CMDARG;
  __IO uint32_t  CMD;
  __I  uint32_t  RESP0;
  __I  uint32_t  RESP1;
  __I  uint32_t  RESP2;
  __I  uint32_t  RESP3;
  __I  uint32_t  MINTSTS;
  __IO uint32_t  RINTSTS;
  __I  uint32_t  STATUS;
  __IO uint32_t  FIFOTH;
  __I  uint32_t  CDETECT;
  __I  uint32_t  WRTPRT;
  __IO uint32_t  GPIO;
  __I  uint32_t  TCBCNT;
  __I  uint32_t  TBBCNT;
  __IO uint32_t  DEBNCE;
  __IO uint32_t  USRID;
  __I  uint32_t  VERID;
  __I  uint32_t  RESERVED0;
  __IO uint32_t  UHS_REG;
  __IO uint32_t  RST_N;
  __I  uint32_t  RESERVED1;
  __IO uint32_t  BMOD;
  __O  uint32_t  PLDMND;
  __IO uint32_t  DBADDR;
  __IO uint32_t  IDSTS;
  __IO uint32_t  IDINTEN;
  __I  uint32_t  DSCADDR;
  __I  uint32_t  BUFADDR;
} LPC_SDMMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          EMC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7  (EMC)
  */

typedef struct {
  __IO uint32_t  CONTROL;
  __I  uint32_t  STATUS;
  __IO uint32_t  CONFIG;
  __I  uint32_t  RESERVED0[5];
  __IO uint32_t  DYNAMICCONTROL;
  __IO uint32_t  DYNAMICREFRESH;
  __IO uint32_t  DYNAMICREADCONFIG;
  __I  uint32_t  RESERVED1;
  __IO uint32_t  DYNAMICRP;
  __IO uint32_t  DYNAMICRAS;
  __IO uint32_t  DYNAMICSREX;
  __IO uint32_t  DYNAMICAPR;
  __IO uint32_t  DYNAMICDAL;
  __IO uint32_t  DYNAMICWR;
  __IO uint32_t  DYNAMICRC;
  __IO uint32_t  DYNAMICRFC;
  __IO uint32_t  DYNAMICXSR;
  __IO uint32_t  DYNAMICRRD;
  __IO uint32_t  DYNAMICMRD;
  __I  uint32_t  RESERVED2[9];
  __IO uint32_t  STATICEXTENDEDWAIT;
  __I  uint32_t  RESERVED3[31];
  __IO uint32_t  DYNAMICCONFIG0;
  __IO uint32_t  DYNAMICRASCAS0;
  __I  uint32_t  RESERVED4[6];
  __IO uint32_t  DYNAMICCONFIG1;
  __IO uint32_t  DYNAMICRASCAS1;
  __I  uint32_t  RESERVED5[6];
  __IO uint32_t  DYNAMICCONFIG2;
  __IO uint32_t  DYNAMICRASCAS2;
  __I  uint32_t  RESERVED6[6];
  __IO uint32_t  DYNAMICCONFIG3;
  __IO uint32_t  DYNAMICRASCAS3;
  __I  uint32_t  RESERVED7[38];
  __IO uint32_t  STATICCONFIG0;
  __IO uint32_t  STATICWAITWEN0;
  __IO uint32_t  STATICWAITOEN0;
  __IO uint32_t  STATICWAITRD0;
  __IO uint32_t  STATICWAITPAG0;
  __IO uint32_t  STATICWAITWR0;
  __IO uint32_t  STATICWAITTURN0;
  __I  uint32_t  RESERVED8;
  __IO uint32_t  STATICCONFIG1;
  __IO uint32_t  STATICWAITWEN1;
  __IO uint32_t  STATICWAITOEN1;
  __IO uint32_t  STATICWAITRD1;
  __IO uint32_t  STATICWAITPAG1;
  __IO uint32_t  STATICWAITWR1;
  __IO uint32_t  STATICWAITTURN1;
  __I  uint32_t  RESERVED9;
  __IO uint32_t  STATICCONFIG2;
  __IO uint32_t  STATICWAITWEN2;
  __IO uint32_t  STATICWAITOEN2;
  __IO uint32_t  STATICWAITRD2;
  __IO uint32_t  STATICWAITPAG2;
  __IO uint32_t  STATICWAITWR2;
  __IO uint32_t  STATICWAITTURN2;
  __I  uint32_t  RESERVED10;
  __IO uint32_t  STATICCONFIG3;
  __IO uint32_t  STATICWAITWEN3;
  __IO uint32_t  STATICWAITOEN3;
  __IO uint32_t  STATICWAITRD3;
  __IO uint32_t  STATICWAITPAG3;
  __IO uint32_t  STATICWAITWR3;
  __IO uint32_t  STATICWAITTURN3;
} LPC_EMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         USB0                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB0)
  */

typedef struct {
  __I  uint32_t  RESERVED0[64];
  __I  uint32_t  CAPLENGTH;
  __I  uint32_t  HCSPARAMS;
  __I  uint32_t  HCCPARAMS;
  __I  uint32_t  RESERVED1[5];
  __I  uint32_t  DCIVERSION;
  __I  uint32_t  RESERVED2[7];

  union {
    __IO uint32_t  USBCMD_H;
    __IO uint32_t  USBCMD_D;
  } ;

  union {
    __IO uint32_t  USBSTS_H;
    __IO uint32_t  USBSTS_D;
  } ;

  union {
    __IO uint32_t  USBINTR_H;
    __IO uint32_t  USBINTR_D;
  } ;

  union {
    __IO uint32_t  FRINDEX_H;
    __IO uint32_t  FRINDEX_D;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t  PERIODICLISTBASE;
    __IO uint32_t  DEVICEADDR;
  } ;

  union {
    __IO uint32_t  ASYNCLISTADDR;
    __IO uint32_t  ENDPOINTLISTADDR;
  } ;
  __IO uint32_t  TTCTRL;
  __IO uint32_t  BURSTSIZE;
  __IO uint32_t  TXFILLTUNING;
  __I  uint32_t  RESERVED4[3];
  __IO uint32_t  BINTERVAL;
  __IO uint32_t  ENDPTNAK;
  __IO uint32_t  ENDPTNAKEN;
  __I  uint32_t  RESERVED5;

  union {
    __IO uint32_t  PORTSC1_H;
    __IO uint32_t  PORTSC1_D;
  } ;
  __I  uint32_t  RESERVED6[7];
  __IO uint32_t  OTGSC;

  union {
    __IO uint32_t  USBMODE_H;
    __IO uint32_t  USBMODE_D;
  } ;
  __IO uint32_t  ENDPTSETUPSTAT;
  __IO uint32_t  ENDPTPRIME;
  __IO uint32_t  ENDPTFLUSH;
  __I  uint32_t  ENDPTSTAT;
  __IO uint32_t  ENDPTCOMPLETE;
  __IO uint32_t  ENDPTCTRL0;
  __IO uint32_t  ENDPTCTRL1;
  __IO uint32_t  ENDPTCTRL2;
  __IO uint32_t  ENDPTCTRL3;
  __IO uint32_t  ENDPTCTRL4;
  __IO uint32_t  ENDPTCTRL5;
} LPC_USB0_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         USB1                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7  (USB1)
  */

typedef struct {
  __I  uint32_t  RESERVED0[64];
  __I  uint32_t  CAPLENGTH;
  __I  uint32_t  HCSPARAMS;
  __I  uint32_t  HCCPARAMS;
  __I  uint32_t  RESERVED1[5];
  __I  uint32_t  DCIVERSION;
  __I  uint32_t  RESERVED2[7];

  union {
    __IO uint32_t  USBCMD_H;
    __IO uint32_t  USBCMD_D;
  } ;

  union {
    __IO uint32_t  USBSTS_H;
    __IO uint32_t  USBSTS_D;
  } ;

  union {
    __IO uint32_t  USBINTR_H;
    __IO uint32_t  USBINTR_D;
  } ;

  union {
    __IO uint32_t  FRINDEX_H;
    __I  uint32_t  FRINDEX_D;
  } ;
  __I  uint32_t  RESERVED3;

  union {
    __IO uint32_t  PERIODICLISTBASE;
    __IO uint32_t  DEVICEADDR;
  } ;

  union {
    __IO uint32_t  ASYNCLISTADDR;
    __IO uint32_t  ENDPOINTLISTADDR;
  } ;
  __IO uint32_t  TTCTRL;
  __IO uint32_t  BURSTSIZE;
  __IO uint32_t  TXFILLTUNING;
  __I  uint32_t  RESERVED4[2];
  __IO uint32_t  ULPIVIEWPORT;
  __IO uint32_t  BINTERVAL;
  __IO uint32_t  ENDPTNAK;
  __IO uint32_t  ENDPTNAKEN;
  __I  uint32_t  RESERVED5;

  union {
    __IO uint32_t  PORTSC1_H;
    __IO uint32_t  PORTSC1_D;
  } ;
  __I  uint32_t  RESERVED6[8];

  union {
    __IO uint32_t  USBMODE_H;
    __IO uint32_t  USBMODE_D;
  } ;
  __IO uint32_t  ENDPTSETUPSTAT;
  __IO uint32_t  ENDPTPRIME;
  __IO uint32_t  ENDPTFLUSH;
  __I  uint32_t  ENDPTSTAT;
  __IO uint32_t  ENDPTCOMPLETE;
  __IO uint32_t  ENDPTCTRL0;
  __IO uint32_t  ENDPTCTRL1;
  __IO uint32_t  ENDPTCTRL2;
  __IO uint32_t  ENDPTCTRL3;
} LPC_USB1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          LCD                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7  (LCD)
  */

typedef struct {
  __IO uint32_t  TIMH;
  __IO uint32_t  TIMV;
  __IO uint32_t  POL;
  __IO uint32_t  LE;
  __IO uint32_t  UPBASE;
  __IO uint32_t  LPBASE;
  __IO uint32_t  CTRL;
  __IO uint32_t  INTMSK;
  __I  uint32_t  INTRAW;
  __I  uint32_t  INTSTAT;
  __O  uint32_t  INTCLR;
  __I  uint32_t  UPCURR;
  __I  uint32_t  LPCURR;
  __I  uint32_t  RESERVED0[115];
  __IO uint32_t PAL[256];
  __I  uint32_t  RESERVED1[128];
  __IO uint32_t CRSR_IMG[256];
  __IO uint32_t  CRSR_CTRL;
  __IO uint32_t  CRSR_CFG;
  __IO uint32_t  CRSR_PAL0;
  __IO uint32_t  CRSR_PAL1;
  __IO uint32_t  CRSR_XY;
  __IO uint32_t  CRSR_CLIP;
  __I  uint32_t  RESERVED2[2];
  __IO uint32_t  CRSR_INTMSK;
  __O  uint32_t  CRSR_INTCLR;
  __I  uint32_t  CRSR_INTRAW;
  __I  uint32_t  CRSR_INTSTAT;
} LPC_LCD_Type;


// ------------------------------------------------------------------------------------------------
// -----                                       ETHERNET                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available  (ETHERNET)
  */

typedef struct {
  __IO uint32_t  MAC_CONFIG;
  __IO uint32_t  MAC_FRAME_FILTER;
  __IO uint32_t  MAC_HASHTABLE_HIGH;
  __IO uint32_t  MAC_HASHTABLE_LOW;
  __IO uint32_t  MAC_MII_ADDR;
  __IO uint32_t  MAC_MII_DATA;
  __IO uint32_t  MAC_FLOW_CTRL;
  __IO uint32_t  MAC_VLAN_TAG;
  __I  uint32_t  RESERVED0;
  __I  uint32_t  MAC_DEBUG;
  __IO uint32_t  MAC_RWAKE_FRFLT;
  __IO uint32_t  MAC_PMT_CTRL_STAT;
  __I  uint32_t  RESERVED1[2];
  __I  uint32_t  MAC_INTR;
  __IO uint32_t  MAC_INTR_MASK;
  __IO uint32_t  MAC_ADDR0_HIGH;
  __IO uint32_t  MAC_ADDR0_LOW;
  __I  uint32_t  RESERVED2[430];
  __IO uint32_t  MAC_TIMESTP_CTRL;
  __IO uint32_t  SUBSECOND_INCR;
  __I  uint32_t  SECONDS;
  __I  uint32_t  NANOSECONDS;
  __IO uint32_t  SECONDSUPDATE;
  __IO uint32_t  NANOSECONDSUPDATE;
  __IO uint32_t  ADDEND;
  __IO uint32_t  TARGETSECONDS;
  __IO uint32_t  TARGETNANOSECONDS;
  __IO uint32_t  HIGHWORD;
  __I  uint32_t  TIMESTAMPSTAT;
  __IO uint32_t  PPSCTRL;
  __I  uint32_t  AUXNANOSECONDS;
  __I  uint32_t  AUXSECONDS;
  __I  uint32_t  RESERVED3[562];
  __IO uint32_t  DMA_BUS_MODE;
  __IO uint32_t  DMA_TRANS_POLL_DEMAND;
  __IO uint32_t  DMA_REC_POLL_DEMAND;
  __IO uint32_t  DMA_REC_DES_ADDR;
  __IO uint32_t  DMA_TRANS_DES_ADDR;
  __IO uint32_t  DMA_STAT;
  __IO uint32_t  DMA_OP_MODE;
  __IO uint32_t  DMA_INT_EN;
  __I  uint32_t  DMA_MFRM_BUFOF;
  __IO uint32_t  DMA_REC_INT_WDT;
  __I  uint32_t  RESERVED4[8];
  __I  uint32_t  DMA_CURHOST_TRANS_DES;
  __I  uint32_t  DMA_CURHOST_REC_DES;
  __I  uint32_t  DMA_CURHOST_TRANS_BUF;
  __I  uint32_t  DMA_CURHOST_REC_BUF;
} LPC_ETHERNET_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        ATIMER                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6  (ATIMER)
  */

typedef struct {
  __IO uint32_t  DOWNCOUNTER;
  __IO uint32_t  PRESET;
  __I  uint32_t  RESERVED0[1012];
  __O  uint32_t  CLR_EN;
  __O  uint32_t  SET_EN;
  __I  uint32_t  STATUS;
  __I  uint32_t  ENABLE;
  __O  uint32_t  CLR_STAT;
  __O  uint32_t  SET_STAT;
} LPC_ATIMER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        REGFILE                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7  (REGFILE)
  */

typedef struct {
  __IO uint32_t REGFILE[64];
} LPC_REGFILE_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          PMC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (PMC)
  */

typedef struct {
  __IO uint32_t  PD0_SLEEP0_HW_ENA;
  __I  uint32_t  RESERVED0[6];
  __IO uint32_t  PD0_SLEEP0_MODE;
} LPC_PMC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CREG                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3  (CREG)
  */

typedef struct {
  __I  uint32_t  IRCTRM;
  __IO uint32_t  CREG0;
  __I  uint32_t  RESERVED1[62];
  __IO uint32_t  M4MEMMAP;
  __I  uint32_t  RESERVED2[5];
  __IO uint32_t  CREG5;
  __IO uint32_t  DMAMUX;
  __I  uint32_t  RESERVED3[2];
  __IO uint32_t  ETBCFG;
  __IO uint32_t  CREG6;
  __IO uint32_t  M4TXEVENT;
  __I  uint32_t  RESERVED4[51];
  __I  uint32_t  CHIPID;
  __I  uint32_t  RESERVED5[127];
  __IO uint32_t  M0TXEVENT;
  __IO uint32_t  M0APPMEMMAP;
} LPC_CREG_Type;


// ------------------------------------------------------------------------------------------------
// -----                                      EVENTROUTER                                     -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3  (EVENTROUTER)
  */

typedef struct {
  __IO uint32_t  HILO;
  __IO uint32_t  EDGE;
  __I  uint32_t  RESERVED0[1012];
  __O  uint32_t  CLR_EN;
  __O  uint32_t  SET_EN;
  __I  uint32_t  STATUS;
  __I  uint32_t  ENABLE;
  __O  uint32_t  CLR_STAT;
  __O  uint32_t  SET_STAT;
} LPC_EVENTROUTER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          RTC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7  (RTC)
  */

typedef struct {
  __O  uint32_t  ILR;
  __I  uint32_t  RESERVED0;
  __IO uint32_t  CCR;
  __IO uint32_t  CIIR;
  __IO uint32_t  AMR;
  __I  uint32_t  CTIME0;
  __I  uint32_t  CTIME1;
  __I  uint32_t  CTIME2;
  __IO uint32_t  SEC;
  __IO uint32_t  MIN;
  __IO uint32_t  HRS;
  __IO uint32_t  DOM;
  __IO uint32_t  DOW;
  __IO uint32_t  DOY;
  __IO uint32_t  MONTH;
  __IO uint32_t  YEAR;
  __IO uint32_t  CALIBRATION;
  __I  uint32_t  RESERVED1[7];
  __IO uint32_t  ASEC;
  __IO uint32_t  AMIN;
  __IO uint32_t  AHRS;
  __IO uint32_t  ADOM;
  __IO uint32_t  ADOW;
  __IO uint32_t  ADOY;
  __IO uint32_t  AMON;
  __IO uint32_t  AYRS;
} LPC_RTC_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          CGU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1  (CGU)
  */

typedef struct {
  __I  uint32_t  RESERVED0[5];
  __IO uint32_t  FREQ_MON;
  __IO uint32_t  XTAL_OSC_CTRL;
  __I  uint32_t  PLL0USB_STAT;
  __IO uint32_t  PLL0USB_CTRL;
  __IO uint32_t  PLL0USB_MDIV;
  __IO uint32_t  PLL0USB_NP_DIV;
  __I  uint32_t  PLL0AUDIO_STAT;
  __IO uint32_t  PLL0AUDIO_CTRL;
  __IO uint32_t  PLL0AUDIO_MDIV;
  __IO uint32_t  PLL0AUDIO_NP_DIV;
  __IO uint32_t  PLL0AUDIO_FRAC;
  __I  uint32_t  PLL1_STAT;
  __IO uint32_t  PLL1_CTRL;
  __IO uint32_t  IDIVA_CTRL;
  __IO uint32_t  IDIVB_CTRL;
  __IO uint32_t  IDIVC_CTRL;
  __IO uint32_t  IDIVD_CTRL;
  __IO uint32_t  IDIVE_CTRL;
  __IO uint32_t  BASE_SAFE_CLK;
  __IO uint32_t  BASE_USB0_CLK;
  __IO uint32_t  BASE_PERIPH_CLK;
  __IO uint32_t  BASE_USB1_CLK;
  __IO uint32_t  BASE_M4_CLK;
  __IO uint32_t  BASE_SPIFI_CLK;
  __IO uint32_t  BASE_SPI_CLK;
  __IO uint32_t  BASE_PHY_RX_CLK;
  __IO uint32_t  BASE_PHY_TX_CLK;
  __IO uint32_t  BASE_APB1_CLK;
  __IO uint32_t  BASE_APB3_CLK;
  __IO uint32_t  BASE_LCD_CLK;
  __I  uint32_t  RESERVED2;
  __IO uint32_t  BASE_SDIO_CLK;
  __IO uint32_t  BASE_SSP0_CLK;
  __IO uint32_t  BASE_SSP1_CLK;
  __IO uint32_t  BASE_UART0_CLK;
  __IO uint32_t  BASE_UART1_CLK;
  __IO uint32_t  BASE_UART2_CLK;
  __IO uint32_t  BASE_UART3_CLK;
  __IO uint32_t  BASE_OUT_CLK;
  __I  uint32_t  RESERVED3[4];
  __IO uint32_t  BASE_APLL_CLK;
  __IO uint32_t  BASE_CGU_OUT0_CLK;
  __IO uint32_t  BASE_CGU_OUT1_CLK;
} LPC_CGU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CCU1                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1)
  */

typedef struct {
  __IO uint32_t  PM;
  __I  uint32_t  BASE_STAT;
  __I  uint32_t  RESERVED0[62];
  __IO uint32_t  CLK_APB3_BUS_CFG;
  __I  uint32_t  CLK_APB3_BUS_STAT;
  __IO uint32_t  CLK_APB3_I2C1_CFG;
  __I  uint32_t  CLK_APB3_I2C1_STAT;
  __IO uint32_t  CLK_APB3_DAC_CFG;
  __I  uint32_t  CLK_APB3_DAC_STAT;
  __IO uint32_t  CLK_APB3_ADC0_CFG;
  __I  uint32_t  CLK_APB3_ADC0_STAT;
  __IO uint32_t  CLK_APB3_ADC1_CFG;
  __I  uint32_t  CLK_APB3_ADC1_STAT;
  __IO uint32_t  CLK_APB3_CAN0_CFG;
  __I  uint32_t  CLK_APB3_CAN0_STAT;
  __I  uint32_t  RESERVED1[52];
  __IO uint32_t  CLK_APB1_BUS_CFG;
  __I  uint32_t  CLK_APB1_BUS_STAT;
  __IO uint32_t  CLK_APB1_MOTOCONPWM_CFG;
  __I  uint32_t  CLK_APB1_MOTOCONPWM_STAT;
  __IO uint32_t  CLK_APB1_I2C0_CFG;
  __I  uint32_t  CLK_APB1_I2C0_STAT;
  __IO uint32_t  CLK_APB1_I2S_CFG;
  __I  uint32_t  CLK_APB1_I2S_STAT;
  __IO uint32_t  CLK_APB1_CAN1_CFG;
  __I  uint32_t  CLK_APB1_CAN1_STAT;
  __I  uint32_t  RESERVED2[54];
  __IO uint32_t  CLK_SPIFI_CFG;
  __I  uint32_t  CLK_SPIFI_STAT;
  __I  uint32_t  RESERVED3[62];
  __IO uint32_t  CLK_M4_BUS_CFG;
  __I  uint32_t  CLK_M4_BUS_STAT;
  __IO uint32_t  CLK_M4_SPIFI_CFG;
  __I  uint32_t  CLK_M4_SPIFI_STAT;
  __IO uint32_t  CLK_M4_GPIO_CFG;
  __I  uint32_t  CLK_M4_GPIO_STAT;
  __IO uint32_t  CLK_M4_LCD_CFG;
  __I  uint32_t  CLK_M4_LCD_STAT;
  __IO uint32_t  CLK_M4_ETHERNET_CFG;
  __I  uint32_t  CLK_M4_ETHERNET_STAT;
  __IO uint32_t  CLK_M4_USB0_CFG;
  __I  uint32_t  CLK_M4_USB0_STAT;
  __IO uint32_t  CLK_M4_EMC_CFG;
  __I  uint32_t  CLK_M4_EMC_STAT;
  __IO uint32_t  CLK_M4_SDIO_CFG;
  __I  uint32_t  CLK_M4_SDIO_STAT;
  __IO uint32_t  CLK_M4_DMA_CFG;
  __I  uint32_t  CLK_M4_DMA_STAT;
  __IO uint32_t  CLK_M4_M4CORE_CFG;
  __I  uint32_t  CLK_M4_M3CORE_STAT;
  __I  uint32_t  RESERVED4[6];
  __IO uint32_t  CLK_M4_SCT_CFG;
  __I  uint32_t  CLK_M4_SCT_STAT;
  __IO uint32_t  CLK_M4_USB1_CFG;
  __I  uint32_t  CLK_M4_USB1_STAT;
  __IO uint32_t  CLK_M4_EMCDIV_CFG;
  __I  uint32_t  CLK_M4_EMCDIV_STAT;
  __I  uint32_t  RESERVED5[4];
  __IO uint32_t  CLK_M4_M0APP_CFG;
  __I  uint32_t  CLK_M4_M0APP_STAT;
  __I  uint32_t  RESERVED6[26];
  __IO uint32_t  CLK_M4_WWDT_CFG;
  __I  uint32_t  CLK_M4_WWDT_STAT;
  __IO uint32_t  CLK_M4_USART0_CFG;
  __I  uint32_t  CLK_M4_USART0_STAT;
  __IO uint32_t  CLK_M4_UART1_CFG;
  __I  uint32_t  CLK_M4_UART1_STAT;
  __IO uint32_t  CLK_M4_SSP0_CFG;
  __I  uint32_t  CLK_M4_SSP0_STAT;
  __IO uint32_t  CLK_M4_TIMER0_CFG;
  __I  uint32_t  CLK_M4_TIMER0_STAT;
  __IO uint32_t  CLK_M4_TIMER1_CFG;
  __I  uint32_t  CLK_M4_TIMER1_STAT;
  __IO uint32_t  CLK_M4_SCU_CFG;
  __I  uint32_t  CLK_M4_SCU_STAT;
  __IO uint32_t  CLK_M4_CREG_CFG;
  __I  uint32_t  CLK_M4_CREG_STAT;
  __I  uint32_t  RESERVED7[48];
  __IO uint32_t  CLK_M4_RITIMER_CFG;
  __I  uint32_t  CLK_M4_RITIMER_STAT;
  __IO uint32_t  CLK_M4_USART2_CFG;
  __I  uint32_t  CLK_M4_USART2_STAT;
  __IO uint32_t  CLK_M4_USART3_CFG;
  __I  uint32_t  CLK_M4_USART3_STAT;
  __IO uint32_t  CLK_M4_TIMER2_CFG;
  __I  uint32_t  CLK_M4_TIMER2_STAT;
  __IO uint32_t  CLK_M4_TIMER3_CFG;
  __I  uint32_t  CLK_M4_TIMER3_STAT;
  __IO uint32_t  CLK_M4_SSP1_CFG;
  __I  uint32_t  CLK_M4_SSP1_STAT;
  __IO uint32_t  CLK_M4_QEI_CFG;
  __I  uint32_t  CLK_M4_QEI_STAT;
  __I  uint32_t  RESERVED8[50];
  __IO uint32_t  CLK_PERIPH_BUS_CFG;
  __I  uint32_t  CLK_PERIPH_BUS_STAT;
  __I  uint32_t  RESERVED9[2];
  __IO uint32_t  CLK_PERIPH_CORE_CFG;
  __I  uint32_t  CLK_PERIPH_CORE_STAT;
  __IO uint32_t  CLK_PERIPH_SGPIO_CFG;
  __I  uint32_t  CLK_PERIPH_SGPIO_STAT;
  __I  uint32_t  RESERVED10[56];
  __IO uint32_t  CLK_USB0_CFG;
  __I  uint32_t  CLK_USB0_STAT;
  __I  uint32_t  RESERVED11[62];
  __IO uint32_t  CLK_USB1_CFG;
  __I  uint32_t  CLK_USB1_STAT;
  __I  uint32_t  RESERVED12[62];
  __IO uint32_t  CLK_SPI_CFG;
  __I  uint32_t  CLK_SPI_STAT;
  __I  uint32_t  RESERVED13[62];
  __IO uint32_t  CLK_VADC_CFG;
  __I  uint32_t  CLK_VADC_STAT;
} LPC_CCU1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         CCU2                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7  (CCU2)
  */

typedef struct {
  __IO uint32_t  PM;
  __I  uint32_t  BASE_STAT;
  __I  uint32_t  RESERVED0[62];
  __IO uint32_t  CLK_APLL_CFG;
  __I  uint32_t  CLK_APLL_STAT;
  __I  uint32_t  RESERVED1[62];
  __IO uint32_t  CLK_APB2_USART3_CFG;
  __I  uint32_t  CLK_APB2_USART3_STAT;
  __I  uint32_t  RESERVED2[62];
  __IO uint32_t  CLK_APB2_USART2_CFG;
  __I  uint32_t  CLK_APB2_USART2_STAT;
  __I  uint32_t  RESERVED3[62];
  __IO uint32_t  CLK_APB0_UART1_CFG;
  __I  uint32_t  CLK_APB0_UART1_STAT;
  __I  uint32_t  RESERVED4[62];
  __IO uint32_t  CLK_APB0_USART0_CFG;
  __I  uint32_t  CLK_APB0_USART0_STAT;
  __I  uint32_t  RESERVED5[62];
  __IO uint32_t  CLK_APB2_SSP1_CFG;
  __I  uint32_t  CLK_APB2_SSP1_STAT;
  __I  uint32_t  RESERVED6[62];
  __IO uint32_t  CLK_APB0_SSP0_CFG;
  __I  uint32_t  CLK_APB0_SSP0_STAT;
  __I  uint32_t  RESERVED7[62];
  __IO uint32_t  CLK_SDIO_CFG;
  __I  uint32_t  CLK_SDIO_STAT;
} LPC_CCU2_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          RGU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13  (RGU)
  */

typedef struct {
  __I  uint32_t  RESERVED0[64];
  __O  uint32_t  RESET_CTRL0;
  __O  uint32_t  RESET_CTRL1;
  __I  uint32_t  RESERVED1[2];
  __IO uint32_t  RESET_STATUS0;
  __IO uint32_t  RESET_STATUS1;
  __IO uint32_t  RESET_STATUS2;
  __IO uint32_t  RESET_STATUS3;
  __I  uint32_t  RESERVED2[12];
  __I  uint32_t  RESET_ACTIVE_STATUS0;
  __I  uint32_t  RESET_ACTIVE_STATUS1;
  __I  uint32_t  RESERVED3[170];
  __IO uint32_t  RESET_EXT_STAT0;
  __IO uint32_t  RESET_EXT_STAT1;
  __IO uint32_t  RESET_EXT_STAT2;
  __I  uint32_t  RESERVED4;
  __IO uint32_t  RESET_EXT_STAT4;
  __IO uint32_t  RESET_EXT_STAT5;
  __I  uint32_t  RESERVED5[2];
  __IO uint32_t  RESET_EXT_STAT8;
  __IO uint32_t  RESET_EXT_STAT9;
  __I  uint32_t  RESERVED6[3];
  __IO uint32_t  RESET_EXT_STAT13;
  __I  uint32_t  RESERVED7[2];
  __IO uint32_t  RESET_EXT_STAT16;
  __IO uint32_t  RESET_EXT_STAT17;
  __IO uint32_t  RESET_EXT_STAT18;
  __IO uint32_t  RESET_EXT_STAT19;
  __IO uint32_t  RESET_EXT_STAT20;
  __IO uint32_t  RESET_EXT_STAT21;
  __IO uint32_t  RESET_EXT_STAT22;
  __IO uint32_t  RESET_EXT_STAT23;
  __I  uint32_t  RESERVED8[4];
  __IO uint32_t  RESET_EXT_STAT28;
  __I  uint32_t  RESERVED9[3];
  __IO uint32_t  RESET_EXT_STAT32;
  __IO uint32_t  RESET_EXT_STAT33;
  __IO uint32_t  RESET_EXT_STAT34;
  __IO uint32_t  RESET_EXT_STAT35;
  __IO uint32_t  RESET_EXT_STAT36;
  __IO uint32_t  RESET_EXT_STAT37;
  __IO uint32_t  RESET_EXT_STAT38;
  __IO uint32_t  RESET_EXT_STAT39;
  __IO uint32_t  RESET_EXT_STAT40;
  __IO uint32_t  RESET_EXT_STAT41;
  __IO uint32_t  RESET_EXT_STAT42;
  __I  uint32_t  RESERVED10;
  __IO uint32_t  RESET_EXT_STAT44;
  __IO uint32_t  RESET_EXT_STAT45;
  __IO uint32_t  RESET_EXT_STAT46;
  __IO uint32_t  RESET_EXT_STAT47;
  __IO uint32_t  RESET_EXT_STAT48;
  __IO uint32_t  RESET_EXT_STAT49;
  __IO uint32_t  RESET_EXT_STAT50;
  __IO uint32_t  RESET_EXT_STAT51;
  __IO uint32_t  RESET_EXT_STAT52;
  __IO uint32_t  RESET_EXT_STAT53;
  __IO uint32_t  RESET_EXT_STAT54;
  __IO uint32_t  RESET_EXT_STAT55;
} LPC_RGU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         WWDT                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (WWDT)
  */

typedef struct {
  __IO uint32_t  MOD;
  __IO uint32_t  TC;
  __O  uint32_t  FEED;
  __I  uint32_t  TV;
  __I  uint32_t  RESERVED0;
  __IO uint32_t  WARNINT;
  __IO uint32_t  WINDOW;
} LPC_WWDT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        USARTn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (USARTn)
  */

typedef struct {

  union {
    __IO uint32_t  DLL;
    __O  uint32_t  THR;
    __I  uint32_t  RBR;
  } ;

  union {
    __IO uint32_t IER;
    __IO uint32_t DLM;
  } ;

  union {
    __O  uint32_t FCR;
    __I  uint32_t IIR;
  } ;
  __IO uint32_t LCR;
  __I  uint32_t RESERVED0[1];
  __I  uint32_t LSR;
  __I  uint32_t RESERVED1[1];
  __IO uint32_t SCR;
  __IO uint32_t ACR;
  __IO uint32_t ICR;
  __IO uint32_t FDR;
  __IO uint32_t OSR;
  __I  uint32_t  RESERVED2[4];
  __IO uint32_t HDEN;
  __I  uint32_t RESERVED3[1];
  __IO uint32_t SCICTRL;
  __IO uint32_t RS485CTRL;
  __IO uint32_t RS485ADRMATCH;
  __IO uint32_t RS485DLY;
  __IO uint32_t SYNCCTRL;
  __IO uint32_t TER;
} LPC_USARTn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         UART1                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (UART1)
  */

typedef struct {

  union {
    __IO uint32_t  DLL;
    __O  uint32_t  THR;
    __I  uint32_t  RBR;
  } ;

  union {
    __IO uint32_t  IER;
    __IO uint32_t  DLM;
  } ;

  union {
    __O  uint32_t  FCR;
    __I  uint32_t  IIR;
  } ;
  __IO uint32_t  LCR;
  __IO uint32_t  MCR;
  __I  uint32_t  LSR;
  __I  uint32_t  MSR;
  __IO uint32_t  SCR;
  __IO uint32_t  ACR;
  __I  uint32_t  RESERVED0;
  __IO uint32_t  FDR;
  __I  uint32_t  RESERVED1;
  __IO uint32_t  TER;
  __I  uint32_t  RESERVED2[6];
  __IO uint32_t  RS485CTRL;
  __IO uint32_t  RS485ADRMATCH;
  __IO uint32_t  RS485DLY;
  __I  uint32_t  FIFOLVL;
} LPC_UART1_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SSPn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7  (SSP0)
  */

typedef struct {
  __IO uint32_t CR0;
  __IO uint32_t CR1;
  __IO uint32_t DR;
  __I  uint32_t SR;
  __IO uint32_t CPSR;
  __IO uint32_t IMSC;
  __I  uint32_t RIS;
  __I  uint32_t MIS;
  __O  uint32_t ICR;
  __IO uint32_t DMACR;
} LPC_SSPn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        TIMERn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7  (TIMERn)
  */

typedef struct {
  __IO uint32_t IR;
  __IO uint32_t TCR;
  __IO uint32_t TC;
  __IO uint32_t PR;
  __IO uint32_t PC;
  __IO uint32_t MCR;
  __IO uint32_t MR[4];
  __IO uint32_t CCR;
  __IO uint32_t CR[4];
  __IO uint32_t EMR;
  __I  uint32_t  RESERVED0[12];
  __IO uint32_t CTCR;
} LPC_TIMERn_Type;




// ------------------------------------------------------------------------------------------------
// -----                                          SCU                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10  (SCU)
  */

typedef struct {
  __IO uint32_t  SFSP0_0;
  __IO uint32_t  SFSP0_1;
  __I  uint32_t  RESERVED0[30];
  __IO uint32_t  SFSP1_0;
  __IO uint32_t  SFSP1_1;
  __IO uint32_t  SFSP1_2;
  __IO uint32_t  SFSP1_3;
  __IO uint32_t  SFSP1_4;
  __IO uint32_t  SFSP1_5;
  __IO uint32_t  SFSP1_6;
  __IO uint32_t  SFSP1_7;
  __IO uint32_t  SFSP1_8;
  __IO uint32_t  SFSP1_9;
  __IO uint32_t  SFSP1_10;
  __IO uint32_t  SFSP1_11;
  __IO uint32_t  SFSP1_12;
  __IO uint32_t  SFSP1_13;
  __IO uint32_t  SFSP1_14;
  __IO uint32_t  SFSP1_15;
  __IO uint32_t  SFSP1_16;
  __IO uint32_t  SFSP1_17;
  __IO uint32_t  SFSP1_18;
  __IO uint32_t  SFSP1_19;
  __IO uint32_t  SFSP1_20;
  __I  uint32_t  RESERVED1[11];
  __IO uint32_t  SFSP2_0;
  __IO uint32_t  SFSP2_1;
  __IO uint32_t  SFSP2_2;
  __IO uint32_t  SFSP2_3;
  __IO uint32_t  SFSP2_4;
  __IO uint32_t  SFSP2_5;
  __IO uint32_t  SFSP2_6;
  __IO uint32_t  SFSP2_7;
  __IO uint32_t  SFSP2_8;
  __IO uint32_t  SFSP2_9;
  __IO uint32_t  SFSP2_10;
  __IO uint32_t  SFSP2_11;
  __IO uint32_t  SFSP2_12;
  __IO uint32_t  SFSP2_13;
  __I  uint32_t  RESERVED2[18];
  __IO uint32_t  SFSP3_0;
  __IO uint32_t  SFSP3_1;
  __IO uint32_t  SFSP3_2;
  __IO uint32_t  SFSP3_3;
  __IO uint32_t  SFSP3_4;
  __IO uint32_t  SFSP3_5;
  __IO uint32_t  SFSP3_6;
  __IO uint32_t  SFSP3_7;
  __IO uint32_t  SFSP3_8;
  __I  uint32_t  RESERVED3[23];
  __IO uint32_t  SFSP4_0;
  __IO uint32_t  SFSP4_1;
  __IO uint32_t  SFSP4_2;
  __IO uint32_t  SFSP4_3;
  __IO uint32_t  SFSP4_4;
  __IO uint32_t  SFSP4_5;
  __IO uint32_t  SFSP4_6;
  __IO uint32_t  SFSP4_7;
  __IO uint32_t  SFSP4_8;
  __IO uint32_t  SFSP4_9;
  __IO uint32_t  SFSP4_10;
  __I  uint32_t  RESERVED4[21];
  __IO uint32_t  SFSP5_0;
  __IO uint32_t  SFSP5_1;
  __IO uint32_t  SFSP5_2;
  __IO uint32_t  SFSP5_3;
  __IO uint32_t  SFSP5_4;
  __IO uint32_t  SFSP5_5;
  __IO uint32_t  SFSP5_6;
  __IO uint32_t  SFSP5_7;
  __I  uint32_t  RESERVED5[24];
  __IO uint32_t  SFSP6_0;
  __IO uint32_t  SFSP6_1;
  __IO uint32_t  SFSP6_2;
  __IO uint32_t  SFSP6_3;
  __IO uint32_t  SFSP6_4;
  __IO uint32_t  SFSP6_5;
  __IO uint32_t  SFSP6_6;
  __IO uint32_t  SFSP6_7;
  __IO uint32_t  SFSP6_8;
  __IO uint32_t  SFSP6_9;
  __IO uint32_t  SFSP6_10;
  __IO uint32_t  SFSP6_11;
  __IO uint32_t  SFSP6_12;
  __I  uint32_t  RESERVED6[19];
  __IO uint32_t  SFSP7_0;
  __IO uint32_t  SFSP7_1;
  __IO uint32_t  SFSP7_2;
  __IO uint32_t  SFSP7_3;
  __IO uint32_t  SFSP7_4;
  __IO uint32_t  SFSP7_5;
  __IO uint32_t  SFSP7_6;
  __IO uint32_t  SFSP7_7;
  __I  uint32_t  RESERVED7[24];
  __IO uint32_t  SFSP8_0;
  __IO uint32_t  SFSP8_1;
  __IO uint32_t  SFSP8_2;
  __IO uint32_t  SFSP8_3;
  __IO uint32_t  SFSP8_4;
  __IO uint32_t  SFSP8_5;
  __IO uint32_t  SFSP8_6;
  __IO uint32_t  SFSP8_7;
  __IO uint32_t  SFSP8_8;
  __I  uint32_t  RESERVED8[23];
  __IO uint32_t  SFSP9_0;
  __IO uint32_t  SFSP9_1;
  __IO uint32_t  SFSP9_2;
  __IO uint32_t  SFSP9_3;
  __IO uint32_t  SFSP9_4;
  __IO uint32_t  SFSP9_5;
  __IO uint32_t  SFSP9_6;
  __I  uint32_t  RESERVED9[25];
  __IO uint32_t  SFSPA_0;
  __IO uint32_t  SFSPA_1;
  __IO uint32_t  SFSPA_2;
  __IO uint32_t  SFSPA_3;
  __IO uint32_t  SFSPA_4;
  __I  uint32_t  RESERVED10[27];
  __IO uint32_t  SFSPB_0;
  __IO uint32_t  SFSPB_1;
  __IO uint32_t  SFSPB_2;
  __IO uint32_t  SFSPB_3;
  __IO uint32_t  SFSPB_4;
  __IO uint32_t  SFSPB_5;
  __IO uint32_t  SFSPB_6;
  __I  uint32_t  RESERVED11[25];
  __IO uint32_t  SFSPC_0;
  __IO uint32_t  SFSPC_1;
  __IO uint32_t  SFSPC_2;
  __IO uint32_t  SFSPC_3;
  __IO uint32_t  SFSPC_4;
  __IO uint32_t  SFSPC_5;
  __IO uint32_t  SFSPC_6;
  __IO uint32_t  SFSPC_7;
  __IO uint32_t  SFSPC_8;
  __IO uint32_t  SFSPC_9;
  __IO uint32_t  SFSPC_10;
  __IO uint32_t  SFSPC_11;
  __IO uint32_t  SFSPC_12;
  __IO uint32_t  SFSPC_13;
  __IO uint32_t  SFSPC_14;
  __I  uint32_t  RESERVED12[17];
  __IO uint32_t  SFSPD_0;
  __IO uint32_t  SFSPD_1;
  __IO uint32_t  SFSPD_2;
  __IO uint32_t  SFSPD_3;
  __IO uint32_t  SFSPD_4;
  __IO uint32_t  SFSPD_5;
  __IO uint32_t  SFSPD_6;
  __IO uint32_t  SFSPD_7;
  __IO uint32_t  SFSPD_8;
  __IO uint32_t  SFSPD_9;
  __IO uint32_t  SFSPD_10;
  __IO uint32_t  SFSPD_11;
  __IO uint32_t  SFSPD_12;
  __IO uint32_t  SFSPD_13;
  __IO uint32_t  SFSPD_14;
  __IO uint32_t  SFSPD_15;
  __IO uint32_t  SFSPD_16;
  __I  uint32_t  RESERVED13[15];
  __IO uint32_t  SFSPE_0;
  __IO uint32_t  SFSPE_1;
  __IO uint32_t  SFSPE_2;
  __IO uint32_t  SFSPE_3;
  __IO uint32_t  SFSPE_4;
  __IO uint32_t  SFSPE_5;
  __IO uint32_t  SFSPE_6;
  __IO uint32_t  SFSPE_7;
  __IO uint32_t  SFSPE_8;
  __IO uint32_t  SFSPE_9;
  __IO uint32_t  SFSPE_10;
  __IO uint32_t  SFSPE_11;
  __IO uint32_t  SFSPE_12;
  __IO uint32_t  SFSPE_13;
  __IO uint32_t  SFSPE_14;
  __IO uint32_t  SFSPE_15;
  __I  uint32_t  RESERVED14[16];
  __IO uint32_t  SFSPF_0;
  __IO uint32_t  SFSPF_1;
  __IO uint32_t  SFSPF_2;
  __IO uint32_t  SFSPF_3;
  __IO uint32_t  SFSPF_4;
  __IO uint32_t  SFSPF_5;
  __IO uint32_t  SFSPF_6;
  __IO uint32_t  SFSPF_7;
  __IO uint32_t  SFSPF_8;
  __IO uint32_t  SFSPF_9;
  __IO uint32_t  SFSPF_10;
  __IO uint32_t  SFSPF_11;
  __I  uint32_t  RESERVED15[276];
  __IO uint32_t  SFSCLK_0;
  __IO uint32_t  SFSCLK_1;
  __IO uint32_t  SFSCLK_2;
  __IO uint32_t  SFSCLK_3;
  __I  uint32_t  RESERVED16[28];
  __IO uint32_t  SFSUSB;
  __IO uint32_t  SFSI2C0;
  __IO uint32_t  ENAIO0;
  __IO uint32_t  ENAIO1;
  __IO uint32_t  ENAIO2;
  __I  uint32_t  RESERVED17[27];
  __IO uint32_t  EMCDELAYCLK;
  __I  uint32_t  RESERVED18[63];
  __IO uint32_t  PINTSEL0;
  __IO uint32_t  PINTSEL1;
} LPC_SCU_Type;


// ------------------------------------------------------------------------------------------------
// -----                                     GPIO_PIN_INT                                     -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO pin interrupt (GPIO_PIN_INT)
  */

typedef struct {
  __IO uint32_t  ISEL;
  __IO uint32_t  IENR;
  __O  uint32_t  SIENR;
  __O  uint32_t  CIENR;
  __IO uint32_t  IENF;
  __O  uint32_t  SIENF;
  __O  uint32_t  CIENF;
  __IO uint32_t  RISE;
  __IO uint32_t  FALL;
  __IO uint32_t  IST;
} LPC_GPIO_PIN_INT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                    GPIO_GROUP_INTn                                   -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)
  */

typedef struct {
  __IO uint32_t  CTRL;
  __I  uint32_t  RESERVED0[7];
  __IO uint32_t  PORT_POL0;
  __IO uint32_t  PORT_POL1;
  __IO uint32_t  PORT_POL2;
  __IO uint32_t  PORT_POL3;
  __IO uint32_t  PORT_POL4;
  __IO uint32_t  PORT_POL5;
  __IO uint32_t  PORT_POL6;
  __IO uint32_t  PORT_POL7;
  __IO uint32_t  PORT_ENA0;
  __IO uint32_t  PORT_ENA1;
  __IO uint32_t  PORT_ENA2;
  __IO uint32_t  PORT_ENA3;
  __IO uint32_t  PORT_ENA4;
  __IO uint32_t  PORT_ENA5;
  __IO uint32_t  PORT_ENA6;
  __IO uint32_t  PORT_ENA7;
} LPC_GPIO_GROUP_INTn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         MCPWM                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7  (MCPWM)
  */

typedef struct {
  __I  uint32_t  CON;
  __O  uint32_t  CON_SET;
  __O  uint32_t  CON_CLR;
  __I  uint32_t  CAPCON;
  __O  uint32_t  CAPCON_SET;
  __O  uint32_t  CAPCON_CLR;
  __IO uint32_t TC[3];
  __IO uint32_t LIM[3];
  __IO uint32_t MAT[3];
  __IO uint32_t  DT;
  __IO uint32_t  CCP;
  __I  uint32_t CAP[3];
  __I  uint32_t  INTEN;
  __O  uint32_t  INTEN_SET;
  __O  uint32_t  INTEN_CLR;
  __I  uint32_t  CNTCON;
  __O  uint32_t  CNTCON_SET;
  __O  uint32_t  CNTCON_CLR;
  __I  uint32_t  INTF;
  __O  uint32_t  INTF_SET;
  __O  uint32_t  INTF_CLR;
  __O  uint32_t  CAP_CLR;
} LPC_MCPWM_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         I2C0                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Cn)
  */

typedef struct {
  __IO uint32_t CONSET;
  __I  uint32_t STAT;
  __IO uint32_t DAT;
  __IO uint32_t ADR0;
  __IO uint32_t SCLH;
  __IO uint32_t SCLL;
  __O  uint32_t CONCLR;
  __IO uint32_t MMCTRL;
  __IO uint32_t ADR1;
  __IO uint32_t ADR2;
  __IO uint32_t ADR3;
  __I  uint32_t DATA_BUFFER;
  __IO uint32_t MASK[4];
} LPC_I2Cn_Type;

// ------------------------------------------------------------------------------------------------
// -----                                         I2Sn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7  (I2Sn)
    0x400A2000 / 0x400A3000
  */

typedef struct {
  __IO uint32_t DAO;
  __IO uint32_t DAI;
  __O  uint32_t TXFIFO;
  __I  uint32_t RXFIFO;
  __I  uint32_t STATE;
  __IO uint32_t DMA1;
  __IO uint32_t DMA2;
  __IO uint32_t IRQ;
  __IO uint32_t TXRATE;
  __IO uint32_t RXRATE;
  __IO uint32_t TXBITRATE;
  __IO uint32_t RXBITRATE;
  __IO uint32_t TXMODE;
  __IO uint32_t RXMODE;
} LPC_I2Sn_Type;

// ------------------------------------------------------------------------------------------------
// -----                                        C_CANn                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7  (C_CANn)
    0x400A4000 / 0x400E2000
  */

typedef struct {
  __IO uint32_t CNTL;
  __IO uint32_t STAT;
  __I  uint32_t EC;
  __IO uint32_t BT;
  __I  uint32_t INT;
  __IO uint32_t TEST;
  __IO uint32_t BRPE;
  __I  uint32_t  RESERVED0;
  __IO uint32_t IF1_CMDREQ;

  union {
    __IO uint32_t IF1_CMDMSK_R;
    __IO uint32_t IF1_CMDMSK_W;
  } ;
  __IO uint32_t IF1_MSK1;
  __IO uint32_t IF1_MSK2;
  __IO uint32_t IF1_ARB1;
  __IO uint32_t IF1_ARB2;
  __IO uint32_t IF1_MCTRL;
  __IO uint32_t IF1_DA1;
  __IO uint32_t IF1_DA2;
  __IO uint32_t IF1_DB1;
  __IO uint32_t IF1_DB2;
  __I  uint32_t  RESERVED1[13];
  __IO uint32_t IF2_CMDREQ;

  union {
    __IO uint32_t IF2_CMDMSK_R;
    __IO uint32_t IF2_CMDMSK_W;
  } ;
  __IO uint32_t IF2_MSK1;
  __IO uint32_t IF2_MSK2;
  __IO uint32_t IF2_ARB1;
  __IO uint32_t IF2_ARB2;
  __IO uint32_t IF2_MCTRL;
  __IO uint32_t IF2_DA1;
  __IO uint32_t IF2_DA2;
  __IO uint32_t IF2_DB1;
  __IO uint32_t IF2_DB2;
  __I  uint32_t  RESERVED2[21];
  __I  uint32_t TXREQ1;
  __I  uint32_t TXREQ2;
  __I  uint32_t  RESERVED3[6];
  __I  uint32_t ND1;
  __I  uint32_t ND2;
  __I  uint32_t  RESERVED4[6];
  __I  uint32_t IR1;
  __I  uint32_t IR2;
  __I  uint32_t  RESERVED5[6];
  __I  uint32_t MSGV1;
  __I  uint32_t MSGV2;
  __I  uint32_t  RESERVED6[6];
  __IO uint32_t CLKDIV;
} LPC_C_CANn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                        RITIMER                                       -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7  (RITIMER)
  */

typedef struct {
  __IO uint32_t  COMPVAL;
  __IO uint32_t  MASK;
  __IO uint32_t  CTRL;
  __IO uint32_t  COUNTER;
} LPC_RITIMER_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          QEI                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7  (QEI)
  */

typedef struct {
  __O  uint32_t  CON;
  __I  uint32_t  STAT;
  __IO uint32_t  CONF;
  __I  uint32_t  POS;
  __IO uint32_t  MAXPOS;
  __IO uint32_t  CMPOS0;
  __IO uint32_t  CMPOS1;
  __IO uint32_t  CMPOS2;
  __I  uint32_t  INXCNT;
  __IO uint32_t  INXCMP0;
  __IO uint32_t  LOAD;
  __I  uint32_t  TIME;
  __I  uint32_t  VEL;
  __I  uint32_t  CAP;
  __IO uint32_t  VELCOMP;
  __IO uint32_t  FILTERPHA;
  __IO uint32_t  FILTERPHB;
  __IO uint32_t  FILTERINX;
  __IO uint32_t  WINDOW;
  __IO uint32_t  INXCMP1;
  __IO uint32_t  INXCMP2;
  __I  uint32_t  RESERVED0[993];
  __O  uint32_t  IEC;
  __O  uint32_t  IES;
  __I  uint32_t  INTSTAT;
  __I  uint32_t  IE;
  __O  uint32_t  CLR;
  __O  uint32_t  SET;
} LPC_QEI_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         GIMA                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3  (GIMA)
  */

typedef struct {
  __IO uint32_t  CAP0_0_IN;
  __IO uint32_t  CAP0_1_IN;
  __IO uint32_t  CAP0_2_IN;
  __IO uint32_t  CAP0_3_IN;
  __IO uint32_t  CAP1_0_IN;
  __IO uint32_t  CAP1_1_IN;
  __IO uint32_t  CAP1_2_IN;
  __IO uint32_t  CAP1_3_IN;
  __IO uint32_t  CAP2_0_IN;
  __IO uint32_t  CAP2_1_IN;
  __IO uint32_t  CAP2_2_IN;
  __IO uint32_t  CAP2_3_IN;
  __IO uint32_t  CAP3_0_IN;
  __IO uint32_t  CAP3_1_IN;
  __IO uint32_t  CAP3_2_IN;
  __IO uint32_t  CAP3_3_IN;
  __IO uint32_t  CTIN_0_IN;
  __IO uint32_t  CTIN_1_IN;
  __IO uint32_t  CTIN_2_IN;
  __IO uint32_t  CTIN_3_IN;
  __IO uint32_t  CTIN_4_IN;
  __IO uint32_t  CTIN_5_IN;
  __IO uint32_t  CTIN_6_IN;
  __IO uint32_t  CTIN_7_IN;
  __IO uint32_t  VADC_TRIGGER_IN;
  __IO uint32_t  EVENTROUTER_13_IN;
  __IO uint32_t  EVENTROUTER_14_IN;
  __IO uint32_t  EVENTROUTER_16_IN;
  __IO uint32_t  ADCSTART0_IN;
  __IO uint32_t  ADCSTART1_IN;
} LPC_GIMA_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          DAC                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7  (DAC)
  */

typedef struct {
  __IO uint32_t  CR;
  __IO uint32_t  CTRL;
  __IO uint32_t  CNTVAL;
} LPC_DAC_Type;



// ------------------------------------------------------------------------------------------------
// -----                                         ADCn                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7  (ADCn)
    0x400E3000 / 0x400E4000
  */

typedef struct {
  __IO uint32_t CR;
  __I  uint32_t GDR;
  __I  uint32_t  RESERVED0;
  __IO uint32_t INTEN;
  __I  uint32_t DR[8];
  __I  uint32_t STAT;
} LPC_ADCn_Type;


// ------------------------------------------------------------------------------------------------
// -----                                       GPIO_PORT                                      -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief GPIO port  (GPIO_PORT)
  */

typedef struct {
  __IO uint8_t B[256];
  __I  uint32_t  RESERVED0[960];
  __IO uint32_t W[256];
  __I  uint32_t  RESERVED1[768];
  __IO uint32_t DIR[8];
  __I  uint32_t  RESERVED2[24];
  __IO uint32_t MASK[8];
  __I  uint32_t  RESERVED3[24];
  __IO uint32_t PIN[8];
  __I  uint32_t  RESERVED4[24];
  __IO uint32_t MPIN[8];
  __I  uint32_t  RESERVED5[24];
  __IO uint32_t SET[8];
  __I  uint32_t  RESERVED6[24];
  __O  uint32_t CLR[8];
  __I  uint32_t  RESERVED7[24];
  __O  uint32_t NOT[8];
} LPC_GPIO_PORT_Type;


// ------------------------------------------------------------------------------------------------
// -----                                          SPI                                         -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3  (SPI)
  */

typedef struct {
  __IO uint32_t  CR;
  __I  uint32_t  SR;
  __IO uint32_t  DR;
  __IO uint32_t  CCR;
  __IO uint32_t  TCR;
  __IO uint32_t  TSR;
  __I  uint32_t  RESERVED0;
  __IO uint32_t  INT;
} LPC_SPI_Type;


// ------------------------------------------------------------------------------------------------
// -----                                         SGPIO                                        -----
// ------------------------------------------------------------------------------------------------


/**
  * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3  (SGPIO)
  */

typedef struct {
  __IO uint32_t  OUT_MUX_CFG[16];
  __IO uint32_t  SGPIO_MUX_CFG[16];
  __IO uint32_t  SLICE_MUX_CFG[16];
  __IO uint32_t  REG[16];
  __IO uint32_t  REG_SS[16];
  __IO uint32_t  PRESET[16];
  __IO uint32_t  COUNT[16];
  __IO uint32_t  POS[16];
  __IO uint32_t  MASK_A;
  __IO uint32_t  MASK_H;
  __IO uint32_t  MASK_I;
  __IO uint32_t  MASK_P;
  __I  uint32_t  GPIO_INREG;
  __IO uint32_t  GPIO_OUTREG;
  __IO uint32_t  GPIO_OENREG;
  __IO uint32_t  CTRL_ENABLED;
  __IO uint32_t  CTRL_DISABLED;
  __I  uint32_t  RESERVED0[823];
  __O  uint32_t  CLR_EN_0;
  __O  uint32_t  SET_EN_0;
  __I  uint32_t  ENABLE_0;
  __I  uint32_t  STATUS_0;
  __O  uint32_t  CTR_STATUS_0;
  __O  uint32_t  SET_STATUS_0;
  __I  uint32_t  RESERVED1[2];
  __O  uint32_t  CLR_EN_1;
  __O  uint32_t  SET_EN_1;
  __I  uint32_t  ENABLE_1;
  __I  uint32_t  STATUS_1;
  __O  uint32_t  CTR_STATUS_1;
  __O  uint32_t  SET_STATUS_1;
  __I  uint32_t  RESERVED2[2];
  __O  uint32_t  CLR_EN_2;
  __O  uint32_t  SET_EN_2;
  __I  uint32_t  ENABLE_2;
  __I  uint32_t  STATUS_2;
  __O  uint32_t  CTR_STATUS_2;
  __O  uint32_t  SET_STATUS_2;
  __I  uint32_t  RESERVED3[2];
  __O  uint32_t  CLR_EN_3;
  __O  uint32_t  SET_EN_3;
  __I  uint32_t  ENABLE_3;
  __I  uint32_t  STATUS_3;
  __O  uint32_t  CTR_STATUS_3;
  __O  uint32_t  SET_STATUS_3;
} LPC_SGPIO_Type;



/********************************************
** End of section using anonymous unions   **
*********************************************/

#if defined(__ARMCC_VERSION)
  #pragma pop
#elif defined(__CWCC__)
  #pragma pop
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma pop
#else
  #error Not supported compiler type
#endif


#ifdef CMSIS_BITPOSITIONS
// ------------------------------------------------------------------------------------------------
// -----                                  SCT Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SCT_CONFIG  -------------------------------------------
#define SCT_CONFIG_UNIFY_Pos                                  0
#define SCT_CONFIG_UNIFY_Msk                                  (0x01UL << SCT_CONFIG_UNIFY_Pos)
#define SCT_CONFIG_CLKMODE_Pos                                1
#define SCT_CONFIG_CLKMODE_Msk                                (0x03UL << SCT_CONFIG_CLKMODE_Pos)
#define SCT_CONFIG_CLKSEL_Pos                                 3
#define SCT_CONFIG_CLKSEL_Msk                                 (0x0fUL << SCT_CONFIG_CLKSEL_Pos)
#define SCT_CONFIG_NORELAODL_NORELOADU_Pos                    7
#define SCT_CONFIG_NORELAODL_NORELOADU_Msk                    (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos)
#define SCT_CONFIG_NORELOADH_Pos                              8
#define SCT_CONFIG_NORELOADH_Msk                              (0x01UL << SCT_CONFIG_NORELOADH_Pos)
#define SCT_CONFIG_INSYNCn_Pos                                9
#define SCT_CONFIG_INSYNCn_Msk                                (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos)

// ----------------------------------------  SCT_CTRL  --------------------------------------------
#define SCT_CTRL_DOWN_L_Pos                                   0
#define SCT_CTRL_DOWN_L_Msk                                   (0x01UL << SCT_CTRL_DOWN_L_Pos)
#define SCT_CTRL_STOP_L_Pos                                   1
#define SCT_CTRL_STOP_L_Msk                                   (0x01UL << SCT_CTRL_STOP_L_Pos)
#define SCT_CTRL_HALT_L_Pos                                   2
#define SCT_CTRL_HALT_L_Msk                                   (0x01UL << SCT_CTRL_HALT_L_Pos)
#define SCT_CTRL_CLRCTR_L_Pos                                 3
#define SCT_CTRL_CLRCTR_L_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_L_Pos)
#define SCT_CTRL_BIDIR_L_Pos                                  4
#define SCT_CTRL_BIDIR_L_Msk                                  (0x01UL << SCT_CTRL_BIDIR_L_Pos)
#define SCT_CTRL_PRE_L_Pos                                    5
#define SCT_CTRL_PRE_L_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_L_Pos)
#define SCT_CTRL_DOWN_H_Pos                                   16
#define SCT_CTRL_DOWN_H_Msk                                   (0x01UL << SCT_CTRL_DOWN_H_Pos)
#define SCT_CTRL_STOP_H_Pos                                   17
#define SCT_CTRL_STOP_H_Msk                                   (0x01UL << SCT_CTRL_STOP_H_Pos)
#define SCT_CTRL_HALT_H_Pos                                   18
#define SCT_CTRL_HALT_H_Msk                                   (0x01UL << SCT_CTRL_HALT_H_Pos)
#define SCT_CTRL_CLRCTR_H_Pos                                 19
#define SCT_CTRL_CLRCTR_H_Msk                                 (0x01UL << SCT_CTRL_CLRCTR_H_Pos)
#define SCT_CTRL_BIDIR_H_Pos                                  20
#define SCT_CTRL_BIDIR_H_Msk                                  (0x01UL << SCT_CTRL_BIDIR_H_Pos)
#define SCT_CTRL_PRE_H_Pos                                    21
#define SCT_CTRL_PRE_H_Msk                                    (0x000000ffUL << SCT_CTRL_PRE_H_Pos)

// ----------------------------------------  SCT_LIMIT  -------------------------------------------
#define SCT_LIMIT_LIMMSK_L_Pos                                0
#define SCT_LIMIT_LIMMSK_L_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos)
#define SCT_LIMIT_LIMMSK_H_Pos                                16
#define SCT_LIMIT_LIMMSK_H_Msk                                (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos)

// ----------------------------------------  SCT_HALT  --------------------------------------------
#define SCT_HALT_HALTMSK_L_Pos                                0
#define SCT_HALT_HALTMSK_L_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos)
#define SCT_HALT_HALTMSK_H_Pos                                16
#define SCT_HALT_HALTMSK_H_Msk                                (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos)

// ----------------------------------------  SCT_STOP  --------------------------------------------
#define SCT_STOP_STOPMSK_L_Pos                                0
#define SCT_STOP_STOPMSK_L_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos)
#define SCT_STOP_STOPMSK_H_Pos                                16
#define SCT_STOP_STOPMSK_H_Msk                                (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos)

// ----------------------------------------  SCT_START  -------------------------------------------
#define SCT_START_STARTMSK_L_Pos                              0
#define SCT_START_STARTMSK_L_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_L_Pos)
#define SCT_START_STARTMSK_H_Pos                              16
#define SCT_START_STARTMSK_H_Msk                              (0x0000ffffUL << SCT_START_STARTMSK_H_Pos)

// ----------------------------------------  SCT_COUNT  -------------------------------------------
#define SCT_COUNT_CTR_L_Pos                                   0
#define SCT_COUNT_CTR_L_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_L_Pos)
#define SCT_COUNT_CTR_H_Pos                                   16
#define SCT_COUNT_CTR_H_Msk                                   (0x0000ffffUL << SCT_COUNT_CTR_H_Pos)

// ----------------------------------------  SCT_STATE  -------------------------------------------
#define SCT_STATE_STATE_L_Pos                                 0
#define SCT_STATE_STATE_L_Msk                                 (0x1fUL << SCT_STATE_STATE_L_Pos)
#define SCT_STATE_STATE_H_Pos                                 16
#define SCT_STATE_STATE_H_Msk                                 (0x1fUL << SCT_STATE_STATE_H_Pos)

// ----------------------------------------  SCT_INPUT  -------------------------------------------
#define SCT_INPUT_AIN0_Pos                                    0
#define SCT_INPUT_AIN0_Msk                                    (0x01UL << SCT_INPUT_AIN0_Pos)
#define SCT_INPUT_AIN1_Pos                                    1
#define SCT_INPUT_AIN1_Msk                                    (0x01UL << SCT_INPUT_AIN1_Pos)
#define SCT_INPUT_AIN2_Pos                                    2
#define SCT_INPUT_AIN2_Msk                                    (0x01UL << SCT_INPUT_AIN2_Pos)
#define SCT_INPUT_AIN3_Pos                                    3
#define SCT_INPUT_AIN3_Msk                                    (0x01UL << SCT_INPUT_AIN3_Pos)
#define SCT_INPUT_AIN4_Pos                                    4
#define SCT_INPUT_AIN4_Msk                                    (0x01UL << SCT_INPUT_AIN4_Pos)
#define SCT_INPUT_AIN5_Pos                                    5
#define SCT_INPUT_AIN5_Msk                                    (0x01UL << SCT_INPUT_AIN5_Pos)
#define SCT_INPUT_AIN6_Pos                                    6
#define SCT_INPUT_AIN6_Msk                                    (0x01UL << SCT_INPUT_AIN6_Pos)
#define SCT_INPUT_AIN7_Pos                                    7
#define SCT_INPUT_AIN7_Msk                                    (0x01UL << SCT_INPUT_AIN7_Pos)
#define SCT_INPUT_SIN0_Pos                                    16
#define SCT_INPUT_SIN0_Msk                                    (0x01UL << SCT_INPUT_SIN0_Pos)
#define SCT_INPUT_SIN1_Pos                                    17
#define SCT_INPUT_SIN1_Msk                                    (0x01UL << SCT_INPUT_SIN1_Pos)
#define SCT_INPUT_SIN2_Pos                                    18
#define SCT_INPUT_SIN2_Msk                                    (0x01UL << SCT_INPUT_SIN2_Pos)
#define SCT_INPUT_SIN3_Pos                                    19
#define SCT_INPUT_SIN3_Msk                                    (0x01UL << SCT_INPUT_SIN3_Pos)
#define SCT_INPUT_SIN4_Pos                                    20
#define SCT_INPUT_SIN4_Msk                                    (0x01UL << SCT_INPUT_SIN4_Pos)
#define SCT_INPUT_SIN5_Pos                                    21
#define SCT_INPUT_SIN5_Msk                                    (0x01UL << SCT_INPUT_SIN5_Pos)
#define SCT_INPUT_SIN6_Pos                                    22
#define SCT_INPUT_SIN6_Msk                                    (0x01UL << SCT_INPUT_SIN6_Pos)
#define SCT_INPUT_SIN7_Pos                                    23
#define SCT_INPUT_SIN7_Msk                                    (0x01UL << SCT_INPUT_SIN7_Pos)

// ---------------------------------------  SCT_REGMODE  ------------------------------------------
#define SCT_REGMODE_REGMOD_L0_Pos                             0
#define SCT_REGMODE_REGMOD_L0_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L0_Pos)
#define SCT_REGMODE_REGMOD_L1_Pos                             1
#define SCT_REGMODE_REGMOD_L1_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L1_Pos)
#define SCT_REGMODE_REGMOD_L2_Pos                             2
#define SCT_REGMODE_REGMOD_L2_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L2_Pos)
#define SCT_REGMODE_REGMOD_L3_Pos                             3
#define SCT_REGMODE_REGMOD_L3_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L3_Pos)
#define SCT_REGMODE_REGMOD_L4_Pos                             4
#define SCT_REGMODE_REGMOD_L4_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L4_Pos)
#define SCT_REGMODE_REGMOD_L5_Pos                             5
#define SCT_REGMODE_REGMOD_L5_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L5_Pos)
#define SCT_REGMODE_REGMOD_L6_Pos                             6
#define SCT_REGMODE_REGMOD_L6_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L6_Pos)
#define SCT_REGMODE_REGMOD_L7_Pos                             7
#define SCT_REGMODE_REGMOD_L7_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L7_Pos)
#define SCT_REGMODE_REGMOD_L8_Pos                             8
#define SCT_REGMODE_REGMOD_L8_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L8_Pos)
#define SCT_REGMODE_REGMOD_L9_Pos                             9
#define SCT_REGMODE_REGMOD_L9_Msk                             (0x01UL << SCT_REGMODE_REGMOD_L9_Pos)
#define SCT_REGMODE_REGMOD_L10_Pos                            10
#define SCT_REGMODE_REGMOD_L10_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L10_Pos)
#define SCT_REGMODE_REGMOD_L11_Pos                            11
#define SCT_REGMODE_REGMOD_L11_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L11_Pos)
#define SCT_REGMODE_REGMOD_L12_Pos                            12
#define SCT_REGMODE_REGMOD_L12_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L12_Pos)
#define SCT_REGMODE_REGMOD_L13_Pos                            13
#define SCT_REGMODE_REGMOD_L13_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L13_Pos)
#define SCT_REGMODE_REGMOD_L14_Pos                            14
#define SCT_REGMODE_REGMOD_L14_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L14_Pos)
#define SCT_REGMODE_REGMOD_L15_Pos                            15
#define SCT_REGMODE_REGMOD_L15_Msk                            (0x01UL << SCT_REGMODE_REGMOD_L15_Pos)
#define SCT_REGMODE_REGMOD_H16_Pos                            16
#define SCT_REGMODE_REGMOD_H16_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H16_Pos)
#define SCT_REGMODE_REGMOD_H17_Pos                            17
#define SCT_REGMODE_REGMOD_H17_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H17_Pos)
#define SCT_REGMODE_REGMOD_H18_Pos                            18
#define SCT_REGMODE_REGMOD_H18_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H18_Pos)
#define SCT_REGMODE_REGMOD_H19_Pos                            19
#define SCT_REGMODE_REGMOD_H19_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H19_Pos)
#define SCT_REGMODE_REGMOD_H20_Pos                            20
#define SCT_REGMODE_REGMOD_H20_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H20_Pos)
#define SCT_REGMODE_REGMOD_H21_Pos                            21
#define SCT_REGMODE_REGMOD_H21_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H21_Pos)
#define SCT_REGMODE_REGMOD_H22_Pos                            22
#define SCT_REGMODE_REGMOD_H22_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H22_Pos)
#define SCT_REGMODE_REGMOD_H23_Pos                            23
#define SCT_REGMODE_REGMOD_H23_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H23_Pos)
#define SCT_REGMODE_REGMOD_H24_Pos                            24
#define SCT_REGMODE_REGMOD_H24_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H24_Pos)
#define SCT_REGMODE_REGMOD_H25_Pos                            25
#define SCT_REGMODE_REGMOD_H25_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H25_Pos)
#define SCT_REGMODE_REGMOD_H26_Pos                            26
#define SCT_REGMODE_REGMOD_H26_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H26_Pos)
#define SCT_REGMODE_REGMOD_H27_Pos                            27
#define SCT_REGMODE_REGMOD_H27_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H27_Pos)
#define SCT_REGMODE_REGMOD_H28_Pos                            28
#define SCT_REGMODE_REGMOD_H28_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H28_Pos)
#define SCT_REGMODE_REGMOD_H29_Pos                            29
#define SCT_REGMODE_REGMOD_H29_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H29_Pos)
#define SCT_REGMODE_REGMOD_H30_Pos                            30
#define SCT_REGMODE_REGMOD_H30_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H30_Pos)
#define SCT_REGMODE_REGMOD_H31_Pos                            31
#define SCT_REGMODE_REGMOD_H31_Msk                            (0x01UL << SCT_REGMODE_REGMOD_H31_Pos)

// ---------------------------------------  SCT_OUTPUT  -------------------------------------------
#define SCT_OUTPUT_OUT0_Pos                                   0
#define SCT_OUTPUT_OUT0_Msk                                   (0x01UL << SCT_OUTPUT_OUT0_Pos)
#define SCT_OUTPUT_OUT1_Pos                                   1
#define SCT_OUTPUT_OUT1_Msk                                   (0x01UL << SCT_OUTPUT_OUT1_Pos)
#define SCT_OUTPUT_OUT2_Pos                                   2
#define SCT_OUTPUT_OUT2_Msk                                   (0x01UL << SCT_OUTPUT_OUT2_Pos)
#define SCT_OUTPUT_OUT3_Pos                                   3
#define SCT_OUTPUT_OUT3_Msk                                   (0x01UL << SCT_OUTPUT_OUT3_Pos)
#define SCT_OUTPUT_OUT4_Pos                                   4
#define SCT_OUTPUT_OUT4_Msk                                   (0x01UL << SCT_OUTPUT_OUT4_Pos)
#define SCT_OUTPUT_OUT5_Pos                                   5
#define SCT_OUTPUT_OUT5_Msk                                   (0x01UL << SCT_OUTPUT_OUT5_Pos)
#define SCT_OUTPUT_OUT6_Pos                                   6
#define SCT_OUTPUT_OUT6_Msk                                   (0x01UL << SCT_OUTPUT_OUT6_Pos)
#define SCT_OUTPUT_OUT7_Pos                                   7
#define SCT_OUTPUT_OUT7_Msk                                   (0x01UL << SCT_OUTPUT_OUT7_Pos)
#define SCT_OUTPUT_OUT8_Pos                                   8
#define SCT_OUTPUT_OUT8_Msk                                   (0x01UL << SCT_OUTPUT_OUT8_Pos)
#define SCT_OUTPUT_OUT9_Pos                                   9
#define SCT_OUTPUT_OUT9_Msk                                   (0x01UL << SCT_OUTPUT_OUT9_Pos)
#define SCT_OUTPUT_OUT10_Pos                                  10
#define SCT_OUTPUT_OUT10_Msk                                  (0x01UL << SCT_OUTPUT_OUT10_Pos)
#define SCT_OUTPUT_OUT11_Pos                                  11
#define SCT_OUTPUT_OUT11_Msk                                  (0x01UL << SCT_OUTPUT_OUT11_Pos)
#define SCT_OUTPUT_OUT12_Pos                                  12
#define SCT_OUTPUT_OUT12_Msk                                  (0x01UL << SCT_OUTPUT_OUT12_Pos)
#define SCT_OUTPUT_OUT13_Pos                                  13
#define SCT_OUTPUT_OUT13_Msk                                  (0x01UL << SCT_OUTPUT_OUT13_Pos)
#define SCT_OUTPUT_OUT14_Pos                                  14
#define SCT_OUTPUT_OUT14_Msk                                  (0x01UL << SCT_OUTPUT_OUT14_Pos)
#define SCT_OUTPUT_OUT15_Pos                                  15
#define SCT_OUTPUT_OUT15_Msk                                  (0x01UL << SCT_OUTPUT_OUT15_Pos)

// ------------------------------------  SCT_OUTPUTDIRCTRL  ---------------------------------------
#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos                         0
#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos                         2
#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos                         4
#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos                         6
#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos                         8
#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos                         10
#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos                         12
#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos                         14
#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos                         16
#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos                         18
#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk                         (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos                        20
#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos                        22
#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos                        24
#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos                        26
#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos                        28
#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos)
#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos                        30
#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk                        (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos)

// -----------------------------------------  SCT_RES  --------------------------------------------
#define SCT_RES_O0RES_Pos                                     0
#define SCT_RES_O0RES_Msk                                     (0x03UL << SCT_RES_O0RES_Pos)
#define SCT_RES_O1RES_Pos                                     2
#define SCT_RES_O1RES_Msk                                     (0x03UL << SCT_RES_O1RES_Pos)
#define SCT_RES_O2RES_Pos                                     4
#define SCT_RES_O2RES_Msk                                     (0x03UL << SCT_RES_O2RES_Pos)
#define SCT_RES_O3RES_Pos                                     6
#define SCT_RES_O3RES_Msk                                     (0x03UL << SCT_RES_O3RES_Pos)
#define SCT_RES_O4RES_Pos                                     8
#define SCT_RES_O4RES_Msk                                     (0x03UL << SCT_RES_O4RES_Pos)
#define SCT_RES_O5RES_Pos                                     10
#define SCT_RES_O5RES_Msk                                     (0x03UL << SCT_RES_O5RES_Pos)
#define SCT_RES_O6RES_Pos                                     12
#define SCT_RES_O6RES_Msk                                     (0x03UL << SCT_RES_O6RES_Pos)
#define SCT_RES_O7RES_Pos                                     14
#define SCT_RES_O7RES_Msk                                     (0x03UL << SCT_RES_O7RES_Pos)
#define SCT_RES_O8RES_Pos                                     16
#define SCT_RES_O8RES_Msk                                     (0x03UL << SCT_RES_O8RES_Pos)
#define SCT_RES_O9RES_Pos                                     18
#define SCT_RES_O9RES_Msk                                     (0x03UL << SCT_RES_O9RES_Pos)
#define SCT_RES_O10RES_Pos                                    20
#define SCT_RES_O10RES_Msk                                    (0x03UL << SCT_RES_O10RES_Pos)
#define SCT_RES_O11RES_Pos                                    22
#define SCT_RES_O11RES_Msk                                    (0x03UL << SCT_RES_O11RES_Pos)
#define SCT_RES_O12RES_Pos                                    24
#define SCT_RES_O12RES_Msk                                    (0x03UL << SCT_RES_O12RES_Pos)
#define SCT_RES_O13RES_Pos                                    26
#define SCT_RES_O13RES_Msk                                    (0x03UL << SCT_RES_O13RES_Pos)
#define SCT_RES_O14RES_Pos                                    28
#define SCT_RES_O14RES_Msk                                    (0x03UL << SCT_RES_O14RES_Pos)
#define SCT_RES_O15RES_Pos                                    30
#define SCT_RES_O15RES_Msk                                    (0x03UL << SCT_RES_O15RES_Pos)

// ---------------------------------------  SCT_DMAREQ0  ------------------------------------------
#define SCT_DMAREQ0_DEV_0_0_Pos                               0
#define SCT_DMAREQ0_DEV_0_0_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos)
#define SCT_DMAREQ0_DEV_0_1_Pos                               1
#define SCT_DMAREQ0_DEV_0_1_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos)
#define SCT_DMAREQ0_DEV_0_2_Pos                               2
#define SCT_DMAREQ0_DEV_0_2_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos)
#define SCT_DMAREQ0_DEV_0_3_Pos                               3
#define SCT_DMAREQ0_DEV_0_3_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos)
#define SCT_DMAREQ0_DEV_0_4_Pos                               4
#define SCT_DMAREQ0_DEV_0_4_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos)
#define SCT_DMAREQ0_DEV_0_5_Pos                               5
#define SCT_DMAREQ0_DEV_0_5_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos)
#define SCT_DMAREQ0_DEV_0_6_Pos                               6
#define SCT_DMAREQ0_DEV_0_6_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos)
#define SCT_DMAREQ0_DEV_0_7_Pos                               7
#define SCT_DMAREQ0_DEV_0_7_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos)
#define SCT_DMAREQ0_DEV_0_8_Pos                               8
#define SCT_DMAREQ0_DEV_0_8_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos)
#define SCT_DMAREQ0_DEV_0_9_Pos                               9
#define SCT_DMAREQ0_DEV_0_9_Msk                               (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos)
#define SCT_DMAREQ0_DEV_0_10_Pos                              10
#define SCT_DMAREQ0_DEV_0_10_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos)
#define SCT_DMAREQ0_DEV_0_11_Pos                              11
#define SCT_DMAREQ0_DEV_0_11_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos)
#define SCT_DMAREQ0_DEV_0_12_Pos                              12
#define SCT_DMAREQ0_DEV_0_12_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos)
#define SCT_DMAREQ0_DEV_0_13_Pos                              13
#define SCT_DMAREQ0_DEV_0_13_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos)
#define SCT_DMAREQ0_DEV_0_14_Pos                              14
#define SCT_DMAREQ0_DEV_0_14_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos)
#define SCT_DMAREQ0_DEV_0_15_Pos                              15
#define SCT_DMAREQ0_DEV_0_15_Msk                              (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos)
#define SCT_DMAREQ0_DRL0_Pos                                  30
#define SCT_DMAREQ0_DRL0_Msk                                  (0x01UL << SCT_DMAREQ0_DRL0_Pos)
#define SCT_DMAREQ0_DRQ0_Pos                                  31
#define SCT_DMAREQ0_DRQ0_Msk                                  (0x01UL << SCT_DMAREQ0_DRQ0_Pos)

// ---------------------------------------  SCT_DMAREQ1  ------------------------------------------
#define SCT_DMAREQ1_DEV_1_0_Pos                               0
#define SCT_DMAREQ1_DEV_1_0_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos)
#define SCT_DMAREQ1_DEV_1_1_Pos                               1
#define SCT_DMAREQ1_DEV_1_1_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos)
#define SCT_DMAREQ1_DEV_1_2_Pos                               2
#define SCT_DMAREQ1_DEV_1_2_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos)
#define SCT_DMAREQ1_DEV_1_3_Pos                               3
#define SCT_DMAREQ1_DEV_1_3_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos)
#define SCT_DMAREQ1_DEV_1_4_Pos                               4
#define SCT_DMAREQ1_DEV_1_4_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos)
#define SCT_DMAREQ1_DEV_1_5_Pos                               5
#define SCT_DMAREQ1_DEV_1_5_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos)
#define SCT_DMAREQ1_DEV_1_6_Pos                               6
#define SCT_DMAREQ1_DEV_1_6_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos)
#define SCT_DMAREQ1_DEV_1_7_Pos                               7
#define SCT_DMAREQ1_DEV_1_7_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos)
#define SCT_DMAREQ1_DEV_1_8_Pos                               8
#define SCT_DMAREQ1_DEV_1_8_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos)
#define SCT_DMAREQ1_DEV_1_9_Pos                               9
#define SCT_DMAREQ1_DEV_1_9_Msk                               (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos)
#define SCT_DMAREQ1_DEV_1_10_Pos                              10
#define SCT_DMAREQ1_DEV_1_10_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos)
#define SCT_DMAREQ1_DEV_1_11_Pos                              11
#define SCT_DMAREQ1_DEV_1_11_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos)
#define SCT_DMAREQ1_DEV_1_12_Pos                              12
#define SCT_DMAREQ1_DEV_1_12_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos)
#define SCT_DMAREQ1_DEV_1_13_Pos                              13
#define SCT_DMAREQ1_DEV_1_13_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos)
#define SCT_DMAREQ1_DEV_1_14_Pos                              14
#define SCT_DMAREQ1_DEV_1_14_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos)
#define SCT_DMAREQ1_DEV_1_15_Pos                              15
#define SCT_DMAREQ1_DEV_1_15_Msk                              (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos)
#define SCT_DMAREQ1_DRL1_Pos                                  30
#define SCT_DMAREQ1_DRL1_Msk                                  (0x01UL << SCT_DMAREQ1_DRL1_Pos)
#define SCT_DMAREQ1_DRQ1_Pos                                  31
#define SCT_DMAREQ1_DRQ1_Msk                                  (0x01UL << SCT_DMAREQ1_DRQ1_Pos)

// ----------------------------------------  SCT_EVEN  --------------------------------------------
#define SCT_EVEN_IEN0_Pos                                     0
#define SCT_EVEN_IEN0_Msk                                     (0x01UL << SCT_EVEN_IEN0_Pos)
#define SCT_EVEN_IEN1_Pos                                     1
#define SCT_EVEN_IEN1_Msk                                     (0x01UL << SCT_EVEN_IEN1_Pos)
#define SCT_EVEN_IEN2_Pos                                     2
#define SCT_EVEN_IEN2_Msk                                     (0x01UL << SCT_EVEN_IEN2_Pos)
#define SCT_EVEN_IEN3_Pos                                     3
#define SCT_EVEN_IEN3_Msk                                     (0x01UL << SCT_EVEN_IEN3_Pos)
#define SCT_EVEN_IEN4_Pos                                     4
#define SCT_EVEN_IEN4_Msk                                     (0x01UL << SCT_EVEN_IEN4_Pos)
#define SCT_EVEN_IEN5_Pos                                     5
#define SCT_EVEN_IEN5_Msk                                     (0x01UL << SCT_EVEN_IEN5_Pos)
#define SCT_EVEN_IEN6_Pos                                     6
#define SCT_EVEN_IEN6_Msk                                     (0x01UL << SCT_EVEN_IEN6_Pos)
#define SCT_EVEN_IEN7_Pos                                     7
#define SCT_EVEN_IEN7_Msk                                     (0x01UL << SCT_EVEN_IEN7_Pos)
#define SCT_EVEN_IEN8_Pos                                     8
#define SCT_EVEN_IEN8_Msk                                     (0x01UL << SCT_EVEN_IEN8_Pos)
#define SCT_EVEN_IEN9_Pos                                     9
#define SCT_EVEN_IEN9_Msk                                     (0x01UL << SCT_EVEN_IEN9_Pos)
#define SCT_EVEN_IEN10_Pos                                    10
#define SCT_EVEN_IEN10_Msk                                    (0x01UL << SCT_EVEN_IEN10_Pos)
#define SCT_EVEN_IEN11_Pos                                    11
#define SCT_EVEN_IEN11_Msk                                    (0x01UL << SCT_EVEN_IEN11_Pos)
#define SCT_EVEN_IEN12_Pos                                    12
#define SCT_EVEN_IEN12_Msk                                    (0x01UL << SCT_EVEN_IEN12_Pos)
#define SCT_EVEN_IEN13_Pos                                    13
#define SCT_EVEN_IEN13_Msk                                    (0x01UL << SCT_EVEN_IEN13_Pos)
#define SCT_EVEN_IEN14_Pos                                    14
#define SCT_EVEN_IEN14_Msk                                    (0x01UL << SCT_EVEN_IEN14_Pos)
#define SCT_EVEN_IEN15_Pos                                    15
#define SCT_EVEN_IEN15_Msk                                    (0x01UL << SCT_EVEN_IEN15_Pos)

// ---------------------------------------  SCT_EVFLAG  -------------------------------------------
#define SCT_EVFLAG_FLAG0_Pos                                  0
#define SCT_EVFLAG_FLAG0_Msk                                  (0x01UL << SCT_EVFLAG_FLAG0_Pos)
#define SCT_EVFLAG_FLAG1_Pos                                  1
#define SCT_EVFLAG_FLAG1_Msk                                  (0x01UL << SCT_EVFLAG_FLAG1_Pos)
#define SCT_EVFLAG_FLAG2_Pos                                  2
#define SCT_EVFLAG_FLAG2_Msk                                  (0x01UL << SCT_EVFLAG_FLAG2_Pos)
#define SCT_EVFLAG_FLAG3_Pos                                  3
#define SCT_EVFLAG_FLAG3_Msk                                  (0x01UL << SCT_EVFLAG_FLAG3_Pos)
#define SCT_EVFLAG_FLAG4_Pos                                  4
#define SCT_EVFLAG_FLAG4_Msk                                  (0x01UL << SCT_EVFLAG_FLAG4_Pos)
#define SCT_EVFLAG_FLAG5_Pos                                  5
#define SCT_EVFLAG_FLAG5_Msk                                  (0x01UL << SCT_EVFLAG_FLAG5_Pos)
#define SCT_EVFLAG_FLAG6_Pos                                  6
#define SCT_EVFLAG_FLAG6_Msk                                  (0x01UL << SCT_EVFLAG_FLAG6_Pos)
#define SCT_EVFLAG_FLAG7_Pos                                  7
#define SCT_EVFLAG_FLAG7_Msk                                  (0x01UL << SCT_EVFLAG_FLAG7_Pos)
#define SCT_EVFLAG_FLAG8_Pos                                  8
#define SCT_EVFLAG_FLAG8_Msk                                  (0x01UL << SCT_EVFLAG_FLAG8_Pos)
#define SCT_EVFLAG_FLAG9_Pos                                  9
#define SCT_EVFLAG_FLAG9_Msk                                  (0x01UL << SCT_EVFLAG_FLAG9_Pos)
#define SCT_EVFLAG_FLAG10_Pos                                 10
#define SCT_EVFLAG_FLAG10_Msk                                 (0x01UL << SCT_EVFLAG_FLAG10_Pos)
#define SCT_EVFLAG_FLAG11_Pos                                 11
#define SCT_EVFLAG_FLAG11_Msk                                 (0x01UL << SCT_EVFLAG_FLAG11_Pos)
#define SCT_EVFLAG_FLAG12_Pos                                 12
#define SCT_EVFLAG_FLAG12_Msk                                 (0x01UL << SCT_EVFLAG_FLAG12_Pos)
#define SCT_EVFLAG_FLAG13_Pos                                 13
#define SCT_EVFLAG_FLAG13_Msk                                 (0x01UL << SCT_EVFLAG_FLAG13_Pos)
#define SCT_EVFLAG_FLAG14_Pos                                 14
#define SCT_EVFLAG_FLAG14_Msk                                 (0x01UL << SCT_EVFLAG_FLAG14_Pos)
#define SCT_EVFLAG_FLAG15_Pos                                 15
#define SCT_EVFLAG_FLAG15_Msk                                 (0x01UL << SCT_EVFLAG_FLAG15_Pos)

// ----------------------------------------  SCT_CONEN  -------------------------------------------
#define SCT_CONEN_NCEN0_Pos                                   0
#define SCT_CONEN_NCEN0_Msk                                   (0x01UL << SCT_CONEN_NCEN0_Pos)
#define SCT_CONEN_NCEN1_Pos                                   1
#define SCT_CONEN_NCEN1_Msk                                   (0x01UL << SCT_CONEN_NCEN1_Pos)
#define SCT_CONEN_NCEN2_Pos                                   2
#define SCT_CONEN_NCEN2_Msk                                   (0x01UL << SCT_CONEN_NCEN2_Pos)
#define SCT_CONEN_NCEN3_Pos                                   3
#define SCT_CONEN_NCEN3_Msk                                   (0x01UL << SCT_CONEN_NCEN3_Pos)
#define SCT_CONEN_NCEN4_Pos                                   4
#define SCT_CONEN_NCEN4_Msk                                   (0x01UL << SCT_CONEN_NCEN4_Pos)
#define SCT_CONEN_NCEN5_Pos                                   5
#define SCT_CONEN_NCEN5_Msk                                   (0x01UL << SCT_CONEN_NCEN5_Pos)
#define SCT_CONEN_NCEN6_Pos                                   6
#define SCT_CONEN_NCEN6_Msk                                   (0x01UL << SCT_CONEN_NCEN6_Pos)
#define SCT_CONEN_NCEN7_Pos                                   7
#define SCT_CONEN_NCEN7_Msk                                   (0x01UL << SCT_CONEN_NCEN7_Pos)
#define SCT_CONEN_NCEN8_Pos                                   8
#define SCT_CONEN_NCEN8_Msk                                   (0x01UL << SCT_CONEN_NCEN8_Pos)
#define SCT_CONEN_NCEN9_Pos                                   9
#define SCT_CONEN_NCEN9_Msk                                   (0x01UL << SCT_CONEN_NCEN9_Pos)
#define SCT_CONEN_NCEN10_Pos                                  10
#define SCT_CONEN_NCEN10_Msk                                  (0x01UL << SCT_CONEN_NCEN10_Pos)
#define SCT_CONEN_NCEN11_Pos                                  11
#define SCT_CONEN_NCEN11_Msk                                  (0x01UL << SCT_CONEN_NCEN11_Pos)
#define SCT_CONEN_NCEN12_Pos                                  12
#define SCT_CONEN_NCEN12_Msk                                  (0x01UL << SCT_CONEN_NCEN12_Pos)
#define SCT_CONEN_NCEN13_Pos                                  13
#define SCT_CONEN_NCEN13_Msk                                  (0x01UL << SCT_CONEN_NCEN13_Pos)
#define SCT_CONEN_NCEN14_Pos                                  14
#define SCT_CONEN_NCEN14_Msk                                  (0x01UL << SCT_CONEN_NCEN14_Pos)
#define SCT_CONEN_NCEN15_Pos                                  15
#define SCT_CONEN_NCEN15_Msk                                  (0x01UL << SCT_CONEN_NCEN15_Pos)

// ---------------------------------------  SCT_CONFLAG  ------------------------------------------
#define SCT_CONFLAG_NCFLAG0_Pos                               0
#define SCT_CONFLAG_NCFLAG0_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG0_Pos)
#define SCT_CONFLAG_NCFLAG1_Pos                               1
#define SCT_CONFLAG_NCFLAG1_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG1_Pos)
#define SCT_CONFLAG_NCFLAG2_Pos                               2
#define SCT_CONFLAG_NCFLAG2_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG2_Pos)
#define SCT_CONFLAG_NCFLAG3_Pos                               3
#define SCT_CONFLAG_NCFLAG3_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG3_Pos)
#define SCT_CONFLAG_NCFLAG4_Pos                               4
#define SCT_CONFLAG_NCFLAG4_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG4_Pos)
#define SCT_CONFLAG_NCFLAG5_Pos                               5
#define SCT_CONFLAG_NCFLAG5_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG5_Pos)
#define SCT_CONFLAG_NCFLAG6_Pos                               6
#define SCT_CONFLAG_NCFLAG6_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG6_Pos)
#define SCT_CONFLAG_NCFLAG7_Pos                               7
#define SCT_CONFLAG_NCFLAG7_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG7_Pos)
#define SCT_CONFLAG_NCFLAG8_Pos                               8
#define SCT_CONFLAG_NCFLAG8_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG8_Pos)
#define SCT_CONFLAG_NCFLAG9_Pos                               9
#define SCT_CONFLAG_NCFLAG9_Msk                               (0x01UL << SCT_CONFLAG_NCFLAG9_Pos)
#define SCT_CONFLAG_NCFLAG10_Pos                              10
#define SCT_CONFLAG_NCFLAG10_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG10_Pos)
#define SCT_CONFLAG_NCFLAG11_Pos                              11
#define SCT_CONFLAG_NCFLAG11_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG11_Pos)
#define SCT_CONFLAG_NCFLAG12_Pos                              12
#define SCT_CONFLAG_NCFLAG12_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG12_Pos)
#define SCT_CONFLAG_NCFLAG13_Pos                              13
#define SCT_CONFLAG_NCFLAG13_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG13_Pos)
#define SCT_CONFLAG_NCFLAG14_Pos                              14
#define SCT_CONFLAG_NCFLAG14_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG14_Pos)
#define SCT_CONFLAG_NCFLAG15_Pos                              15
#define SCT_CONFLAG_NCFLAG15_Msk                              (0x01UL << SCT_CONFLAG_NCFLAG15_Pos)
#define SCT_CONFLAG_BUSERRL_Pos                               30
#define SCT_CONFLAG_BUSERRL_Msk                               (0x01UL << SCT_CONFLAG_BUSERRL_Pos)
#define SCT_CONFLAG_BUSERRH_Pos                               31
#define SCT_CONFLAG_BUSERRH_Msk                               (0x01UL << SCT_CONFLAG_BUSERRH_Pos)

// ---------------------------------------  SCT_MATCH0  -------------------------------------------
#define SCT_MATCH0_MATCHn_L_Pos                               0
#define SCT_MATCH0_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos)
#define SCT_MATCH0_MATCHn_H_Pos                               16
#define SCT_MATCH0_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP0  --------------------------------------------
#define SCT_CAP0_CAPn_L_Pos                                   0
#define SCT_CAP0_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos)
#define SCT_CAP0_CAPn_H_Pos                                   16
#define SCT_CAP0_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH1  -------------------------------------------
#define SCT_MATCH1_MATCHn_L_Pos                               0
#define SCT_MATCH1_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos)
#define SCT_MATCH1_MATCHn_H_Pos                               16
#define SCT_MATCH1_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP1  --------------------------------------------
#define SCT_CAP1_CAPn_L_Pos                                   0
#define SCT_CAP1_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos)
#define SCT_CAP1_CAPn_H_Pos                                   16
#define SCT_CAP1_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH2  -------------------------------------------
#define SCT_MATCH2_MATCHn_L_Pos                               0
#define SCT_MATCH2_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos)
#define SCT_MATCH2_MATCHn_H_Pos                               16
#define SCT_MATCH2_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP2  --------------------------------------------
#define SCT_CAP2_CAPn_L_Pos                                   0
#define SCT_CAP2_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos)
#define SCT_CAP2_CAPn_H_Pos                                   16
#define SCT_CAP2_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos)

// ----------------------------------------  SCT_CAP3  --------------------------------------------
#define SCT_CAP3_CAPn_L_Pos                                   0
#define SCT_CAP3_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos)
#define SCT_CAP3_CAPn_H_Pos                                   16
#define SCT_CAP3_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH3  -------------------------------------------
#define SCT_MATCH3_MATCHn_L_Pos                               0
#define SCT_MATCH3_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos)
#define SCT_MATCH3_MATCHn_H_Pos                               16
#define SCT_MATCH3_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos)

// ---------------------------------------  SCT_MATCH4  -------------------------------------------
#define SCT_MATCH4_MATCHn_L_Pos                               0
#define SCT_MATCH4_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos)
#define SCT_MATCH4_MATCHn_H_Pos                               16
#define SCT_MATCH4_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP4  --------------------------------------------
#define SCT_CAP4_CAPn_L_Pos                                   0
#define SCT_CAP4_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos)
#define SCT_CAP4_CAPn_H_Pos                                   16
#define SCT_CAP4_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH5  -------------------------------------------
#define SCT_MATCH5_MATCHn_L_Pos                               0
#define SCT_MATCH5_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos)
#define SCT_MATCH5_MATCHn_H_Pos                               16
#define SCT_MATCH5_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP5  --------------------------------------------
#define SCT_CAP5_CAPn_L_Pos                                   0
#define SCT_CAP5_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos)
#define SCT_CAP5_CAPn_H_Pos                                   16
#define SCT_CAP5_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH6  -------------------------------------------
#define SCT_MATCH6_MATCHn_L_Pos                               0
#define SCT_MATCH6_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos)
#define SCT_MATCH6_MATCHn_H_Pos                               16
#define SCT_MATCH6_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP6  --------------------------------------------
#define SCT_CAP6_CAPn_L_Pos                                   0
#define SCT_CAP6_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos)
#define SCT_CAP6_CAPn_H_Pos                                   16
#define SCT_CAP6_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos)

// ----------------------------------------  SCT_CAP7  --------------------------------------------
#define SCT_CAP7_CAPn_L_Pos                                   0
#define SCT_CAP7_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos)
#define SCT_CAP7_CAPn_H_Pos                                   16
#define SCT_CAP7_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH7  -------------------------------------------
#define SCT_MATCH7_MATCHn_L_Pos                               0
#define SCT_MATCH7_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos)
#define SCT_MATCH7_MATCHn_H_Pos                               16
#define SCT_MATCH7_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP8  --------------------------------------------
#define SCT_CAP8_CAPn_L_Pos                                   0
#define SCT_CAP8_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos)
#define SCT_CAP8_CAPn_H_Pos                                   16
#define SCT_CAP8_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH8  -------------------------------------------
#define SCT_MATCH8_MATCHn_L_Pos                               0
#define SCT_MATCH8_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos)
#define SCT_MATCH8_MATCHn_H_Pos                               16
#define SCT_MATCH8_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos)

// ---------------------------------------  SCT_MATCH9  -------------------------------------------
#define SCT_MATCH9_MATCHn_L_Pos                               0
#define SCT_MATCH9_MATCHn_L_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos)
#define SCT_MATCH9_MATCHn_H_Pos                               16
#define SCT_MATCH9_MATCHn_H_Msk                               (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP9  --------------------------------------------
#define SCT_CAP9_CAPn_L_Pos                                   0
#define SCT_CAP9_CAPn_L_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos)
#define SCT_CAP9_CAPn_H_Pos                                   16
#define SCT_CAP9_CAPn_H_Msk                                   (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos)

// ----------------------------------------  SCT_CAP10  -------------------------------------------
#define SCT_CAP10_CAPn_L_Pos                                  0
#define SCT_CAP10_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos)
#define SCT_CAP10_CAPn_H_Pos                                  16
#define SCT_CAP10_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH10  ------------------------------------------
#define SCT_MATCH10_MATCHn_L_Pos                              0
#define SCT_MATCH10_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos)
#define SCT_MATCH10_MATCHn_H_Pos                              16
#define SCT_MATCH10_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP11  -------------------------------------------
#define SCT_CAP11_CAPn_L_Pos                                  0
#define SCT_CAP11_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos)
#define SCT_CAP11_CAPn_H_Pos                                  16
#define SCT_CAP11_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH11  ------------------------------------------
#define SCT_MATCH11_MATCHn_L_Pos                              0
#define SCT_MATCH11_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos)
#define SCT_MATCH11_MATCHn_H_Pos                              16
#define SCT_MATCH11_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos)

// ---------------------------------------  SCT_MATCH12  ------------------------------------------
#define SCT_MATCH12_MATCHn_L_Pos                              0
#define SCT_MATCH12_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos)
#define SCT_MATCH12_MATCHn_H_Pos                              16
#define SCT_MATCH12_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP12  -------------------------------------------
#define SCT_CAP12_CAPn_L_Pos                                  0
#define SCT_CAP12_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos)
#define SCT_CAP12_CAPn_H_Pos                                  16
#define SCT_CAP12_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos)

// ----------------------------------------  SCT_CAP13  -------------------------------------------
#define SCT_CAP13_CAPn_L_Pos                                  0
#define SCT_CAP13_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos)
#define SCT_CAP13_CAPn_H_Pos                                  16
#define SCT_CAP13_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH13  ------------------------------------------
#define SCT_MATCH13_MATCHn_L_Pos                              0
#define SCT_MATCH13_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos)
#define SCT_MATCH13_MATCHn_H_Pos                              16
#define SCT_MATCH13_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos)

// ---------------------------------------  SCT_MATCH14  ------------------------------------------
#define SCT_MATCH14_MATCHn_L_Pos                              0
#define SCT_MATCH14_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos)
#define SCT_MATCH14_MATCHn_H_Pos                              16
#define SCT_MATCH14_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP14  -------------------------------------------
#define SCT_CAP14_CAPn_L_Pos                                  0
#define SCT_CAP14_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos)
#define SCT_CAP14_CAPn_H_Pos                                  16
#define SCT_CAP14_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos)

// ---------------------------------------  SCT_MATCH15  ------------------------------------------
#define SCT_MATCH15_MATCHn_L_Pos                              0
#define SCT_MATCH15_MATCHn_L_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos)
#define SCT_MATCH15_MATCHn_H_Pos                              16
#define SCT_MATCH15_MATCHn_H_Msk                              (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos)

// ----------------------------------------  SCT_CAP15  -------------------------------------------
#define SCT_CAP15_CAPn_L_Pos                                  0
#define SCT_CAP15_CAPn_L_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos)
#define SCT_CAP15_CAPn_H_Pos                                  16
#define SCT_CAP15_CAPn_H_Msk                                  (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos)

// --------------------------------------  SCT_MATCHREL0  -----------------------------------------
#define SCT_MATCHREL0_RELOADn_L_Pos                           0
#define SCT_MATCHREL0_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos)
#define SCT_MATCHREL0_RELOADn_H_Pos                           16
#define SCT_MATCHREL0_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL0  ------------------------------------------
#define SCT_CAPCTRL0_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL0_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos)
#define SCT_CAPCTRL0_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL0_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos)
#define SCT_CAPCTRL0_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL0_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos)
#define SCT_CAPCTRL0_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL0_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos)
#define SCT_CAPCTRL0_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL0_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos)
#define SCT_CAPCTRL0_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL0_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos)
#define SCT_CAPCTRL0_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL0_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos)
#define SCT_CAPCTRL0_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL0_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos)
#define SCT_CAPCTRL0_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL0_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos)
#define SCT_CAPCTRL0_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL0_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos)
#define SCT_CAPCTRL0_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL0_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos)
#define SCT_CAPCTRL0_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL0_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos)
#define SCT_CAPCTRL0_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL0_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos)
#define SCT_CAPCTRL0_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL0_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos)
#define SCT_CAPCTRL0_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL0_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos)
#define SCT_CAPCTRL0_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL0_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos)
#define SCT_CAPCTRL0_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL0_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL1  -----------------------------------------
#define SCT_MATCHREL1_RELOADn_L_Pos                           0
#define SCT_MATCHREL1_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos)
#define SCT_MATCHREL1_RELOADn_H_Pos                           16
#define SCT_MATCHREL1_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL1  ------------------------------------------
#define SCT_CAPCTRL1_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL1_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos)
#define SCT_CAPCTRL1_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL1_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos)
#define SCT_CAPCTRL1_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL1_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos)
#define SCT_CAPCTRL1_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL1_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos)
#define SCT_CAPCTRL1_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL1_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos)
#define SCT_CAPCTRL1_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL1_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos)
#define SCT_CAPCTRL1_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL1_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos)
#define SCT_CAPCTRL1_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL1_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos)
#define SCT_CAPCTRL1_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL1_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos)
#define SCT_CAPCTRL1_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL1_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos)
#define SCT_CAPCTRL1_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL1_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos)
#define SCT_CAPCTRL1_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL1_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos)
#define SCT_CAPCTRL1_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL1_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos)
#define SCT_CAPCTRL1_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL1_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos)
#define SCT_CAPCTRL1_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL1_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos)
#define SCT_CAPCTRL1_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL1_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos)
#define SCT_CAPCTRL1_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL1_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL2  -----------------------------------------
#define SCT_MATCHREL2_RELOADn_L_Pos                           0
#define SCT_MATCHREL2_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos)
#define SCT_MATCHREL2_RELOADn_H_Pos                           16
#define SCT_MATCHREL2_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL2  ------------------------------------------
#define SCT_CAPCTRL2_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL2_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos)
#define SCT_CAPCTRL2_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL2_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos)
#define SCT_CAPCTRL2_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL2_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos)
#define SCT_CAPCTRL2_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL2_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos)
#define SCT_CAPCTRL2_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL2_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos)
#define SCT_CAPCTRL2_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL2_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos)
#define SCT_CAPCTRL2_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL2_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos)
#define SCT_CAPCTRL2_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL2_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos)
#define SCT_CAPCTRL2_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL2_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos)
#define SCT_CAPCTRL2_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL2_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos)
#define SCT_CAPCTRL2_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL2_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos)
#define SCT_CAPCTRL2_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL2_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos)
#define SCT_CAPCTRL2_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL2_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos)
#define SCT_CAPCTRL2_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL2_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos)
#define SCT_CAPCTRL2_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL2_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos)
#define SCT_CAPCTRL2_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL2_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos)
#define SCT_CAPCTRL2_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL2_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL3  -----------------------------------------
#define SCT_MATCHREL3_RELOADn_L_Pos                           0
#define SCT_MATCHREL3_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos)
#define SCT_MATCHREL3_RELOADn_H_Pos                           16
#define SCT_MATCHREL3_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL3  ------------------------------------------
#define SCT_CAPCTRL3_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL3_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos)
#define SCT_CAPCTRL3_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL3_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos)
#define SCT_CAPCTRL3_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL3_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos)
#define SCT_CAPCTRL3_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL3_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos)
#define SCT_CAPCTRL3_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL3_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos)
#define SCT_CAPCTRL3_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL3_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos)
#define SCT_CAPCTRL3_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL3_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos)
#define SCT_CAPCTRL3_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL3_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos)
#define SCT_CAPCTRL3_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL3_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos)
#define SCT_CAPCTRL3_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL3_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos)
#define SCT_CAPCTRL3_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL3_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos)
#define SCT_CAPCTRL3_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL3_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos)
#define SCT_CAPCTRL3_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL3_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos)
#define SCT_CAPCTRL3_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL3_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos)
#define SCT_CAPCTRL3_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL3_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos)
#define SCT_CAPCTRL3_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL3_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos)
#define SCT_CAPCTRL3_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL3_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos)

// --------------------------------------  SCT_CAPCTRL4  ------------------------------------------
#define SCT_CAPCTRL4_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL4_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos)
#define SCT_CAPCTRL4_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL4_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos)
#define SCT_CAPCTRL4_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL4_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos)
#define SCT_CAPCTRL4_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL4_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos)
#define SCT_CAPCTRL4_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL4_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos)
#define SCT_CAPCTRL4_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL4_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos)
#define SCT_CAPCTRL4_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL4_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos)
#define SCT_CAPCTRL4_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL4_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos)
#define SCT_CAPCTRL4_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL4_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos)
#define SCT_CAPCTRL4_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL4_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos)
#define SCT_CAPCTRL4_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL4_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos)
#define SCT_CAPCTRL4_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL4_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos)
#define SCT_CAPCTRL4_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL4_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos)
#define SCT_CAPCTRL4_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL4_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos)
#define SCT_CAPCTRL4_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL4_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos)
#define SCT_CAPCTRL4_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL4_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos)
#define SCT_CAPCTRL4_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL4_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL4  -----------------------------------------
#define SCT_MATCHREL4_RELOADn_L_Pos                           0
#define SCT_MATCHREL4_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos)
#define SCT_MATCHREL4_RELOADn_H_Pos                           16
#define SCT_MATCHREL4_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL5  ------------------------------------------
#define SCT_CAPCTRL5_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL5_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos)
#define SCT_CAPCTRL5_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL5_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos)
#define SCT_CAPCTRL5_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL5_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos)
#define SCT_CAPCTRL5_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL5_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos)
#define SCT_CAPCTRL5_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL5_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos)
#define SCT_CAPCTRL5_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL5_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos)
#define SCT_CAPCTRL5_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL5_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos)
#define SCT_CAPCTRL5_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL5_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos)
#define SCT_CAPCTRL5_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL5_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos)
#define SCT_CAPCTRL5_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL5_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos)
#define SCT_CAPCTRL5_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL5_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos)
#define SCT_CAPCTRL5_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL5_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos)
#define SCT_CAPCTRL5_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL5_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos)
#define SCT_CAPCTRL5_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL5_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos)
#define SCT_CAPCTRL5_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL5_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos)
#define SCT_CAPCTRL5_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL5_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos)
#define SCT_CAPCTRL5_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL5_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL5  -----------------------------------------
#define SCT_MATCHREL5_RELOADn_L_Pos                           0
#define SCT_MATCHREL5_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos)
#define SCT_MATCHREL5_RELOADn_H_Pos                           16
#define SCT_MATCHREL5_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos)

// --------------------------------------  SCT_MATCHREL6  -----------------------------------------
#define SCT_MATCHREL6_RELOADn_L_Pos                           0
#define SCT_MATCHREL6_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos)
#define SCT_MATCHREL6_RELOADn_H_Pos                           16
#define SCT_MATCHREL6_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL6  ------------------------------------------
#define SCT_CAPCTRL6_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL6_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos)
#define SCT_CAPCTRL6_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL6_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos)
#define SCT_CAPCTRL6_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL6_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos)
#define SCT_CAPCTRL6_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL6_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos)
#define SCT_CAPCTRL6_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL6_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos)
#define SCT_CAPCTRL6_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL6_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos)
#define SCT_CAPCTRL6_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL6_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos)
#define SCT_CAPCTRL6_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL6_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos)
#define SCT_CAPCTRL6_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL6_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos)
#define SCT_CAPCTRL6_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL6_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos)
#define SCT_CAPCTRL6_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL6_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos)
#define SCT_CAPCTRL6_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL6_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos)
#define SCT_CAPCTRL6_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL6_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos)
#define SCT_CAPCTRL6_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL6_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos)
#define SCT_CAPCTRL6_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL6_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos)
#define SCT_CAPCTRL6_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL6_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos)
#define SCT_CAPCTRL6_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL6_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos)

// --------------------------------------  SCT_CAPCTRL7  ------------------------------------------
#define SCT_CAPCTRL7_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL7_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos)
#define SCT_CAPCTRL7_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL7_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos)
#define SCT_CAPCTRL7_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL7_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos)
#define SCT_CAPCTRL7_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL7_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos)
#define SCT_CAPCTRL7_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL7_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos)
#define SCT_CAPCTRL7_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL7_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos)
#define SCT_CAPCTRL7_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL7_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos)
#define SCT_CAPCTRL7_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL7_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos)
#define SCT_CAPCTRL7_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL7_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos)
#define SCT_CAPCTRL7_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL7_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos)
#define SCT_CAPCTRL7_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL7_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos)
#define SCT_CAPCTRL7_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL7_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos)
#define SCT_CAPCTRL7_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL7_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos)
#define SCT_CAPCTRL7_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL7_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos)
#define SCT_CAPCTRL7_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL7_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos)
#define SCT_CAPCTRL7_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL7_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos)
#define SCT_CAPCTRL7_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL7_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL7  -----------------------------------------
#define SCT_MATCHREL7_RELOADn_L_Pos                           0
#define SCT_MATCHREL7_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos)
#define SCT_MATCHREL7_RELOADn_H_Pos                           16
#define SCT_MATCHREL7_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL8  ------------------------------------------
#define SCT_CAPCTRL8_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL8_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos)
#define SCT_CAPCTRL8_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL8_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos)
#define SCT_CAPCTRL8_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL8_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos)
#define SCT_CAPCTRL8_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL8_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos)
#define SCT_CAPCTRL8_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL8_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos)
#define SCT_CAPCTRL8_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL8_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos)
#define SCT_CAPCTRL8_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL8_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos)
#define SCT_CAPCTRL8_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL8_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos)
#define SCT_CAPCTRL8_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL8_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos)
#define SCT_CAPCTRL8_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL8_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos)
#define SCT_CAPCTRL8_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL8_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos)
#define SCT_CAPCTRL8_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL8_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos)
#define SCT_CAPCTRL8_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL8_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos)
#define SCT_CAPCTRL8_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL8_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos)
#define SCT_CAPCTRL8_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL8_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos)
#define SCT_CAPCTRL8_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL8_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos)
#define SCT_CAPCTRL8_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL8_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos)

// --------------------------------------  SCT_MATCHREL8  -----------------------------------------
#define SCT_MATCHREL8_RELOADn_L_Pos                           0
#define SCT_MATCHREL8_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos)
#define SCT_MATCHREL8_RELOADn_H_Pos                           16
#define SCT_MATCHREL8_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos)

// --------------------------------------  SCT_MATCHREL9  -----------------------------------------
#define SCT_MATCHREL9_RELOADn_L_Pos                           0
#define SCT_MATCHREL9_RELOADn_L_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos)
#define SCT_MATCHREL9_RELOADn_H_Pos                           16
#define SCT_MATCHREL9_RELOADn_H_Msk                           (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL9  ------------------------------------------
#define SCT_CAPCTRL9_CAPCONn_L0_Pos                           0
#define SCT_CAPCTRL9_CAPCONn_L0_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos)
#define SCT_CAPCTRL9_CAPCONn_L1_Pos                           1
#define SCT_CAPCTRL9_CAPCONn_L1_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos)
#define SCT_CAPCTRL9_CAPCONn_L2_Pos                           2
#define SCT_CAPCTRL9_CAPCONn_L2_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos)
#define SCT_CAPCTRL9_CAPCONn_L3_Pos                           3
#define SCT_CAPCTRL9_CAPCONn_L3_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos)
#define SCT_CAPCTRL9_CAPCONn_L4_Pos                           4
#define SCT_CAPCTRL9_CAPCONn_L4_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos)
#define SCT_CAPCTRL9_CAPCONn_L5_Pos                           5
#define SCT_CAPCTRL9_CAPCONn_L5_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos)
#define SCT_CAPCTRL9_CAPCONn_L6_Pos                           6
#define SCT_CAPCTRL9_CAPCONn_L6_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos)
#define SCT_CAPCTRL9_CAPCONn_L7_Pos                           7
#define SCT_CAPCTRL9_CAPCONn_L7_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos)
#define SCT_CAPCTRL9_CAPCONn_L8_Pos                           8
#define SCT_CAPCTRL9_CAPCONn_L8_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos)
#define SCT_CAPCTRL9_CAPCONn_L9_Pos                           9
#define SCT_CAPCTRL9_CAPCONn_L9_Msk                           (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos)
#define SCT_CAPCTRL9_CAPCONn_L10_Pos                          10
#define SCT_CAPCTRL9_CAPCONn_L10_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos)
#define SCT_CAPCTRL9_CAPCONn_L11_Pos                          11
#define SCT_CAPCTRL9_CAPCONn_L11_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos)
#define SCT_CAPCTRL9_CAPCONn_L12_Pos                          12
#define SCT_CAPCTRL9_CAPCONn_L12_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos)
#define SCT_CAPCTRL9_CAPCONn_L13_Pos                          13
#define SCT_CAPCTRL9_CAPCONn_L13_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos)
#define SCT_CAPCTRL9_CAPCONn_L14_Pos                          14
#define SCT_CAPCTRL9_CAPCONn_L14_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos)
#define SCT_CAPCTRL9_CAPCONn_L15_Pos                          15
#define SCT_CAPCTRL9_CAPCONn_L15_Msk                          (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos)
#define SCT_CAPCTRL9_CAPCONn_H_Pos                            16
#define SCT_CAPCTRL9_CAPCONn_H_Msk                            (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL10  -----------------------------------------
#define SCT_MATCHREL10_RELOADn_L_Pos                          0
#define SCT_MATCHREL10_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos)
#define SCT_MATCHREL10_RELOADn_H_Pos                          16
#define SCT_MATCHREL10_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL10  -----------------------------------------
#define SCT_CAPCTRL10_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL10_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos)
#define SCT_CAPCTRL10_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL10_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos)
#define SCT_CAPCTRL10_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL10_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos)
#define SCT_CAPCTRL10_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL10_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos)
#define SCT_CAPCTRL10_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL10_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos)
#define SCT_CAPCTRL10_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL10_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos)
#define SCT_CAPCTRL10_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL10_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos)
#define SCT_CAPCTRL10_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL10_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos)
#define SCT_CAPCTRL10_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL10_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos)
#define SCT_CAPCTRL10_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL10_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos)
#define SCT_CAPCTRL10_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL10_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos)
#define SCT_CAPCTRL10_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL10_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos)
#define SCT_CAPCTRL10_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL10_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos)
#define SCT_CAPCTRL10_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL10_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos)
#define SCT_CAPCTRL10_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL10_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos)
#define SCT_CAPCTRL10_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL10_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos)
#define SCT_CAPCTRL10_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL10_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL11  -----------------------------------------
#define SCT_MATCHREL11_RELOADn_L_Pos                          0
#define SCT_MATCHREL11_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos)
#define SCT_MATCHREL11_RELOADn_H_Pos                          16
#define SCT_MATCHREL11_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL11  -----------------------------------------
#define SCT_CAPCTRL11_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL11_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos)
#define SCT_CAPCTRL11_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL11_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos)
#define SCT_CAPCTRL11_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL11_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos)
#define SCT_CAPCTRL11_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL11_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos)
#define SCT_CAPCTRL11_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL11_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos)
#define SCT_CAPCTRL11_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL11_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos)
#define SCT_CAPCTRL11_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL11_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos)
#define SCT_CAPCTRL11_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL11_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos)
#define SCT_CAPCTRL11_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL11_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos)
#define SCT_CAPCTRL11_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL11_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos)
#define SCT_CAPCTRL11_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL11_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos)
#define SCT_CAPCTRL11_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL11_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos)
#define SCT_CAPCTRL11_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL11_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos)
#define SCT_CAPCTRL11_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL11_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos)
#define SCT_CAPCTRL11_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL11_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos)
#define SCT_CAPCTRL11_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL11_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos)
#define SCT_CAPCTRL11_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL11_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL12  -----------------------------------------
#define SCT_MATCHREL12_RELOADn_L_Pos                          0
#define SCT_MATCHREL12_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos)
#define SCT_MATCHREL12_RELOADn_H_Pos                          16
#define SCT_MATCHREL12_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL12  -----------------------------------------
#define SCT_CAPCTRL12_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL12_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos)
#define SCT_CAPCTRL12_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL12_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos)
#define SCT_CAPCTRL12_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL12_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos)
#define SCT_CAPCTRL12_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL12_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos)
#define SCT_CAPCTRL12_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL12_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos)
#define SCT_CAPCTRL12_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL12_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos)
#define SCT_CAPCTRL12_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL12_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos)
#define SCT_CAPCTRL12_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL12_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos)
#define SCT_CAPCTRL12_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL12_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos)
#define SCT_CAPCTRL12_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL12_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos)
#define SCT_CAPCTRL12_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL12_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos)
#define SCT_CAPCTRL12_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL12_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos)
#define SCT_CAPCTRL12_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL12_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos)
#define SCT_CAPCTRL12_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL12_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos)
#define SCT_CAPCTRL12_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL12_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos)
#define SCT_CAPCTRL12_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL12_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos)
#define SCT_CAPCTRL12_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL12_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL13  -----------------------------------------
#define SCT_MATCHREL13_RELOADn_L_Pos                          0
#define SCT_MATCHREL13_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos)
#define SCT_MATCHREL13_RELOADn_H_Pos                          16
#define SCT_MATCHREL13_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL13  -----------------------------------------
#define SCT_CAPCTRL13_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL13_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos)
#define SCT_CAPCTRL13_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL13_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos)
#define SCT_CAPCTRL13_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL13_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos)
#define SCT_CAPCTRL13_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL13_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos)
#define SCT_CAPCTRL13_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL13_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos)
#define SCT_CAPCTRL13_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL13_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos)
#define SCT_CAPCTRL13_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL13_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos)
#define SCT_CAPCTRL13_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL13_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos)
#define SCT_CAPCTRL13_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL13_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos)
#define SCT_CAPCTRL13_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL13_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos)
#define SCT_CAPCTRL13_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL13_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos)
#define SCT_CAPCTRL13_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL13_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos)
#define SCT_CAPCTRL13_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL13_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos)
#define SCT_CAPCTRL13_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL13_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos)
#define SCT_CAPCTRL13_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL13_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos)
#define SCT_CAPCTRL13_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL13_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos)
#define SCT_CAPCTRL13_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL13_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL14  -----------------------------------------
#define SCT_MATCHREL14_RELOADn_L_Pos                          0
#define SCT_MATCHREL14_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos)
#define SCT_MATCHREL14_RELOADn_H_Pos                          16
#define SCT_MATCHREL14_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL14  -----------------------------------------
#define SCT_CAPCTRL14_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL14_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos)
#define SCT_CAPCTRL14_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL14_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos)
#define SCT_CAPCTRL14_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL14_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos)
#define SCT_CAPCTRL14_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL14_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos)
#define SCT_CAPCTRL14_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL14_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos)
#define SCT_CAPCTRL14_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL14_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos)
#define SCT_CAPCTRL14_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL14_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos)
#define SCT_CAPCTRL14_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL14_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos)
#define SCT_CAPCTRL14_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL14_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos)
#define SCT_CAPCTRL14_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL14_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos)
#define SCT_CAPCTRL14_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL14_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos)
#define SCT_CAPCTRL14_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL14_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos)
#define SCT_CAPCTRL14_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL14_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos)
#define SCT_CAPCTRL14_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL14_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos)
#define SCT_CAPCTRL14_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL14_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos)
#define SCT_CAPCTRL14_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL14_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos)
#define SCT_CAPCTRL14_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL14_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos)

// -------------------------------------  SCT_MATCHREL15  -----------------------------------------
#define SCT_MATCHREL15_RELOADn_L_Pos                          0
#define SCT_MATCHREL15_RELOADn_L_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos)
#define SCT_MATCHREL15_RELOADn_H_Pos                          16
#define SCT_MATCHREL15_RELOADn_H_Msk                          (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos)

// --------------------------------------  SCT_CAPCTRL15  -----------------------------------------
#define SCT_CAPCTRL15_CAPCONn_L0_Pos                          0
#define SCT_CAPCTRL15_CAPCONn_L0_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos)
#define SCT_CAPCTRL15_CAPCONn_L1_Pos                          1
#define SCT_CAPCTRL15_CAPCONn_L1_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos)
#define SCT_CAPCTRL15_CAPCONn_L2_Pos                          2
#define SCT_CAPCTRL15_CAPCONn_L2_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos)
#define SCT_CAPCTRL15_CAPCONn_L3_Pos                          3
#define SCT_CAPCTRL15_CAPCONn_L3_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos)
#define SCT_CAPCTRL15_CAPCONn_L4_Pos                          4
#define SCT_CAPCTRL15_CAPCONn_L4_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos)
#define SCT_CAPCTRL15_CAPCONn_L5_Pos                          5
#define SCT_CAPCTRL15_CAPCONn_L5_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos)
#define SCT_CAPCTRL15_CAPCONn_L6_Pos                          6
#define SCT_CAPCTRL15_CAPCONn_L6_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos)
#define SCT_CAPCTRL15_CAPCONn_L7_Pos                          7
#define SCT_CAPCTRL15_CAPCONn_L7_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos)
#define SCT_CAPCTRL15_CAPCONn_L8_Pos                          8
#define SCT_CAPCTRL15_CAPCONn_L8_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos)
#define SCT_CAPCTRL15_CAPCONn_L9_Pos                          9
#define SCT_CAPCTRL15_CAPCONn_L9_Msk                          (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos)
#define SCT_CAPCTRL15_CAPCONn_L10_Pos                         10
#define SCT_CAPCTRL15_CAPCONn_L10_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos)
#define SCT_CAPCTRL15_CAPCONn_L11_Pos                         11
#define SCT_CAPCTRL15_CAPCONn_L11_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos)
#define SCT_CAPCTRL15_CAPCONn_L12_Pos                         12
#define SCT_CAPCTRL15_CAPCONn_L12_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos)
#define SCT_CAPCTRL15_CAPCONn_L13_Pos                         13
#define SCT_CAPCTRL15_CAPCONn_L13_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos)
#define SCT_CAPCTRL15_CAPCONn_L14_Pos                         14
#define SCT_CAPCTRL15_CAPCONn_L14_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos)
#define SCT_CAPCTRL15_CAPCONn_L15_Pos                         15
#define SCT_CAPCTRL15_CAPCONn_L15_Msk                         (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos)
#define SCT_CAPCTRL15_CAPCONn_H_Pos                           16
#define SCT_CAPCTRL15_CAPCONn_H_Msk                           (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos)

// -------------------------------------  SCT_EVSTATEMSK0  ----------------------------------------
#define SCT_EVSTATEMSK0_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK0_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK0_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK0_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK0_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK0_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK0_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK0_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK0_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK0_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK0_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK0_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK0_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK0_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK0_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK0_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK0_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK0_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK0_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK0_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK0_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK0_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK0_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK0_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK0_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK0_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK0_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK0_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK0_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK0_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK0_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK0_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK0_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK0_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL0  ------------------------------------------
#define SCT_EVCTRL0_MATCHSEL_Pos                              0
#define SCT_EVCTRL0_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos)
#define SCT_EVCTRL0_HEVENT_Pos                                4
#define SCT_EVCTRL0_HEVENT_Msk                                (0x01UL << SCT_EVCTRL0_HEVENT_Pos)
#define SCT_EVCTRL0_OUTSEL_Pos                                5
#define SCT_EVCTRL0_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL0_OUTSEL_Pos)
#define SCT_EVCTRL0_IOSEL_Pos                                 6
#define SCT_EVCTRL0_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL0_IOSEL_Pos)
#define SCT_EVCTRL0_IOCOND_Pos                                10
#define SCT_EVCTRL0_IOCOND_Msk                                (0x03UL << SCT_EVCTRL0_IOCOND_Pos)
#define SCT_EVCTRL0_COMBMODE_Pos                              12
#define SCT_EVCTRL0_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL0_COMBMODE_Pos)
#define SCT_EVCTRL0_STATELD_Pos                               14
#define SCT_EVCTRL0_STATELD_Msk                               (0x01UL << SCT_EVCTRL0_STATELD_Pos)
#define SCT_EVCTRL0_STATEV_Pos                                15
#define SCT_EVCTRL0_STATEV_Msk                                (0x1fUL << SCT_EVCTRL0_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK1  ----------------------------------------
#define SCT_EVSTATEMSK1_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK1_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK1_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK1_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK1_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK1_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK1_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK1_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK1_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK1_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK1_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK1_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK1_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK1_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK1_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK1_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK1_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK1_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK1_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK1_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK1_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK1_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK1_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK1_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK1_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK1_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK1_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK1_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK1_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK1_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK1_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK1_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK1_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK1_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL1  ------------------------------------------
#define SCT_EVCTRL1_MATCHSEL_Pos                              0
#define SCT_EVCTRL1_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos)
#define SCT_EVCTRL1_HEVENT_Pos                                4
#define SCT_EVCTRL1_HEVENT_Msk                                (0x01UL << SCT_EVCTRL1_HEVENT_Pos)
#define SCT_EVCTRL1_OUTSEL_Pos                                5
#define SCT_EVCTRL1_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL1_OUTSEL_Pos)
#define SCT_EVCTRL1_IOSEL_Pos                                 6
#define SCT_EVCTRL1_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL1_IOSEL_Pos)
#define SCT_EVCTRL1_IOCOND_Pos                                10
#define SCT_EVCTRL1_IOCOND_Msk                                (0x03UL << SCT_EVCTRL1_IOCOND_Pos)
#define SCT_EVCTRL1_COMBMODE_Pos                              12
#define SCT_EVCTRL1_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL1_COMBMODE_Pos)
#define SCT_EVCTRL1_STATELD_Pos                               14
#define SCT_EVCTRL1_STATELD_Msk                               (0x01UL << SCT_EVCTRL1_STATELD_Pos)
#define SCT_EVCTRL1_STATEV_Pos                                15
#define SCT_EVCTRL1_STATEV_Msk                                (0x1fUL << SCT_EVCTRL1_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK2  ----------------------------------------
#define SCT_EVSTATEMSK2_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK2_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK2_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK2_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK2_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK2_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK2_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK2_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK2_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK2_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK2_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK2_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK2_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK2_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK2_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK2_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK2_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK2_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK2_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK2_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK2_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK2_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK2_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK2_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK2_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK2_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK2_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK2_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK2_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK2_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK2_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK2_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK2_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK2_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL2  ------------------------------------------
#define SCT_EVCTRL2_MATCHSEL_Pos                              0
#define SCT_EVCTRL2_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos)
#define SCT_EVCTRL2_HEVENT_Pos                                4
#define SCT_EVCTRL2_HEVENT_Msk                                (0x01UL << SCT_EVCTRL2_HEVENT_Pos)
#define SCT_EVCTRL2_OUTSEL_Pos                                5
#define SCT_EVCTRL2_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL2_OUTSEL_Pos)
#define SCT_EVCTRL2_IOSEL_Pos                                 6
#define SCT_EVCTRL2_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL2_IOSEL_Pos)
#define SCT_EVCTRL2_IOCOND_Pos                                10
#define SCT_EVCTRL2_IOCOND_Msk                                (0x03UL << SCT_EVCTRL2_IOCOND_Pos)
#define SCT_EVCTRL2_COMBMODE_Pos                              12
#define SCT_EVCTRL2_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL2_COMBMODE_Pos)
#define SCT_EVCTRL2_STATELD_Pos                               14
#define SCT_EVCTRL2_STATELD_Msk                               (0x01UL << SCT_EVCTRL2_STATELD_Pos)
#define SCT_EVCTRL2_STATEV_Pos                                15
#define SCT_EVCTRL2_STATEV_Msk                                (0x1fUL << SCT_EVCTRL2_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK3  ----------------------------------------
#define SCT_EVSTATEMSK3_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK3_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK3_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK3_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK3_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK3_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK3_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK3_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK3_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK3_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK3_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK3_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK3_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK3_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK3_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK3_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK3_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK3_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK3_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK3_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK3_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK3_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK3_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK3_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK3_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK3_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK3_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK3_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK3_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK3_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK3_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK3_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK3_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK3_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL3  ------------------------------------------
#define SCT_EVCTRL3_MATCHSEL_Pos                              0
#define SCT_EVCTRL3_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos)
#define SCT_EVCTRL3_HEVENT_Pos                                4
#define SCT_EVCTRL3_HEVENT_Msk                                (0x01UL << SCT_EVCTRL3_HEVENT_Pos)
#define SCT_EVCTRL3_OUTSEL_Pos                                5
#define SCT_EVCTRL3_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL3_OUTSEL_Pos)
#define SCT_EVCTRL3_IOSEL_Pos                                 6
#define SCT_EVCTRL3_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL3_IOSEL_Pos)
#define SCT_EVCTRL3_IOCOND_Pos                                10
#define SCT_EVCTRL3_IOCOND_Msk                                (0x03UL << SCT_EVCTRL3_IOCOND_Pos)
#define SCT_EVCTRL3_COMBMODE_Pos                              12
#define SCT_EVCTRL3_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL3_COMBMODE_Pos)
#define SCT_EVCTRL3_STATELD_Pos                               14
#define SCT_EVCTRL3_STATELD_Msk                               (0x01UL << SCT_EVCTRL3_STATELD_Pos)
#define SCT_EVCTRL3_STATEV_Pos                                15
#define SCT_EVCTRL3_STATEV_Msk                                (0x1fUL << SCT_EVCTRL3_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK4  ----------------------------------------
#define SCT_EVSTATEMSK4_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK4_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK4_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK4_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK4_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK4_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK4_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK4_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK4_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK4_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK4_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK4_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK4_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK4_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK4_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK4_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK4_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK4_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK4_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK4_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK4_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK4_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK4_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK4_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK4_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK4_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK4_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK4_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK4_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK4_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK4_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK4_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK4_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK4_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL4  ------------------------------------------
#define SCT_EVCTRL4_MATCHSEL_Pos                              0
#define SCT_EVCTRL4_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos)
#define SCT_EVCTRL4_HEVENT_Pos                                4
#define SCT_EVCTRL4_HEVENT_Msk                                (0x01UL << SCT_EVCTRL4_HEVENT_Pos)
#define SCT_EVCTRL4_OUTSEL_Pos                                5
#define SCT_EVCTRL4_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL4_OUTSEL_Pos)
#define SCT_EVCTRL4_IOSEL_Pos                                 6
#define SCT_EVCTRL4_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL4_IOSEL_Pos)
#define SCT_EVCTRL4_IOCOND_Pos                                10
#define SCT_EVCTRL4_IOCOND_Msk                                (0x03UL << SCT_EVCTRL4_IOCOND_Pos)
#define SCT_EVCTRL4_COMBMODE_Pos                              12
#define SCT_EVCTRL4_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL4_COMBMODE_Pos)
#define SCT_EVCTRL4_STATELD_Pos                               14
#define SCT_EVCTRL4_STATELD_Msk                               (0x01UL << SCT_EVCTRL4_STATELD_Pos)
#define SCT_EVCTRL4_STATEV_Pos                                15
#define SCT_EVCTRL4_STATEV_Msk                                (0x1fUL << SCT_EVCTRL4_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK5  ----------------------------------------
#define SCT_EVSTATEMSK5_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK5_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK5_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK5_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK5_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK5_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK5_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK5_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK5_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK5_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK5_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK5_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK5_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK5_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK5_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK5_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK5_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK5_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK5_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK5_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK5_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK5_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK5_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK5_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK5_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK5_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK5_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK5_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK5_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK5_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK5_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK5_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK5_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK5_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL5  ------------------------------------------
#define SCT_EVCTRL5_MATCHSEL_Pos                              0
#define SCT_EVCTRL5_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos)
#define SCT_EVCTRL5_HEVENT_Pos                                4
#define SCT_EVCTRL5_HEVENT_Msk                                (0x01UL << SCT_EVCTRL5_HEVENT_Pos)
#define SCT_EVCTRL5_OUTSEL_Pos                                5
#define SCT_EVCTRL5_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL5_OUTSEL_Pos)
#define SCT_EVCTRL5_IOSEL_Pos                                 6
#define SCT_EVCTRL5_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL5_IOSEL_Pos)
#define SCT_EVCTRL5_IOCOND_Pos                                10
#define SCT_EVCTRL5_IOCOND_Msk                                (0x03UL << SCT_EVCTRL5_IOCOND_Pos)
#define SCT_EVCTRL5_COMBMODE_Pos                              12
#define SCT_EVCTRL5_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL5_COMBMODE_Pos)
#define SCT_EVCTRL5_STATELD_Pos                               14
#define SCT_EVCTRL5_STATELD_Msk                               (0x01UL << SCT_EVCTRL5_STATELD_Pos)
#define SCT_EVCTRL5_STATEV_Pos                                15
#define SCT_EVCTRL5_STATEV_Msk                                (0x1fUL << SCT_EVCTRL5_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK6  ----------------------------------------
#define SCT_EVSTATEMSK6_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK6_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK6_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK6_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK6_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK6_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK6_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK6_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK6_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK6_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK6_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK6_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK6_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK6_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK6_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK6_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK6_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK6_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK6_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK6_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK6_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK6_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK6_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK6_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK6_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK6_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK6_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK6_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK6_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK6_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK6_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK6_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK6_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK6_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL6  ------------------------------------------
#define SCT_EVCTRL6_MATCHSEL_Pos                              0
#define SCT_EVCTRL6_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos)
#define SCT_EVCTRL6_HEVENT_Pos                                4
#define SCT_EVCTRL6_HEVENT_Msk                                (0x01UL << SCT_EVCTRL6_HEVENT_Pos)
#define SCT_EVCTRL6_OUTSEL_Pos                                5
#define SCT_EVCTRL6_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL6_OUTSEL_Pos)
#define SCT_EVCTRL6_IOSEL_Pos                                 6
#define SCT_EVCTRL6_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL6_IOSEL_Pos)
#define SCT_EVCTRL6_IOCOND_Pos                                10
#define SCT_EVCTRL6_IOCOND_Msk                                (0x03UL << SCT_EVCTRL6_IOCOND_Pos)
#define SCT_EVCTRL6_COMBMODE_Pos                              12
#define SCT_EVCTRL6_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL6_COMBMODE_Pos)
#define SCT_EVCTRL6_STATELD_Pos                               14
#define SCT_EVCTRL6_STATELD_Msk                               (0x01UL << SCT_EVCTRL6_STATELD_Pos)
#define SCT_EVCTRL6_STATEV_Pos                                15
#define SCT_EVCTRL6_STATEV_Msk                                (0x1fUL << SCT_EVCTRL6_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK7  ----------------------------------------
#define SCT_EVSTATEMSK7_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK7_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK7_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK7_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK7_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK7_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK7_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK7_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK7_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK7_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK7_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK7_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK7_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK7_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK7_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK7_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK7_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK7_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK7_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK7_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK7_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK7_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK7_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK7_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK7_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK7_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK7_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK7_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK7_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK7_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK7_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK7_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK7_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK7_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL7  ------------------------------------------
#define SCT_EVCTRL7_MATCHSEL_Pos                              0
#define SCT_EVCTRL7_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos)
#define SCT_EVCTRL7_HEVENT_Pos                                4
#define SCT_EVCTRL7_HEVENT_Msk                                (0x01UL << SCT_EVCTRL7_HEVENT_Pos)
#define SCT_EVCTRL7_OUTSEL_Pos                                5
#define SCT_EVCTRL7_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL7_OUTSEL_Pos)
#define SCT_EVCTRL7_IOSEL_Pos                                 6
#define SCT_EVCTRL7_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL7_IOSEL_Pos)
#define SCT_EVCTRL7_IOCOND_Pos                                10
#define SCT_EVCTRL7_IOCOND_Msk                                (0x03UL << SCT_EVCTRL7_IOCOND_Pos)
#define SCT_EVCTRL7_COMBMODE_Pos                              12
#define SCT_EVCTRL7_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL7_COMBMODE_Pos)
#define SCT_EVCTRL7_STATELD_Pos                               14
#define SCT_EVCTRL7_STATELD_Msk                               (0x01UL << SCT_EVCTRL7_STATELD_Pos)
#define SCT_EVCTRL7_STATEV_Pos                                15
#define SCT_EVCTRL7_STATEV_Msk                                (0x1fUL << SCT_EVCTRL7_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK8  ----------------------------------------
#define SCT_EVSTATEMSK8_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK8_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK8_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK8_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK8_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK8_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK8_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK8_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK8_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK8_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK8_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK8_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK8_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK8_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK8_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK8_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK8_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK8_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK8_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK8_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK8_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK8_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK8_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK8_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK8_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK8_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK8_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK8_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK8_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK8_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK8_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK8_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK8_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK8_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL8  ------------------------------------------
#define SCT_EVCTRL8_MATCHSEL_Pos                              0
#define SCT_EVCTRL8_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos)
#define SCT_EVCTRL8_HEVENT_Pos                                4
#define SCT_EVCTRL8_HEVENT_Msk                                (0x01UL << SCT_EVCTRL8_HEVENT_Pos)
#define SCT_EVCTRL8_OUTSEL_Pos                                5
#define SCT_EVCTRL8_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL8_OUTSEL_Pos)
#define SCT_EVCTRL8_IOSEL_Pos                                 6
#define SCT_EVCTRL8_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL8_IOSEL_Pos)
#define SCT_EVCTRL8_IOCOND_Pos                                10
#define SCT_EVCTRL8_IOCOND_Msk                                (0x03UL << SCT_EVCTRL8_IOCOND_Pos)
#define SCT_EVCTRL8_COMBMODE_Pos                              12
#define SCT_EVCTRL8_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL8_COMBMODE_Pos)
#define SCT_EVCTRL8_STATELD_Pos                               14
#define SCT_EVCTRL8_STATELD_Msk                               (0x01UL << SCT_EVCTRL8_STATELD_Pos)
#define SCT_EVCTRL8_STATEV_Pos                                15
#define SCT_EVCTRL8_STATEV_Msk                                (0x1fUL << SCT_EVCTRL8_STATEV_Pos)

// -------------------------------------  SCT_EVSTATEMSK9  ----------------------------------------
#define SCT_EVSTATEMSK9_STATEMSKn0_Pos                        0
#define SCT_EVSTATEMSK9_STATEMSKn0_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn1_Pos                        1
#define SCT_EVSTATEMSK9_STATEMSKn1_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn2_Pos                        2
#define SCT_EVSTATEMSK9_STATEMSKn2_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn3_Pos                        3
#define SCT_EVSTATEMSK9_STATEMSKn3_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn4_Pos                        4
#define SCT_EVSTATEMSK9_STATEMSKn4_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn5_Pos                        5
#define SCT_EVSTATEMSK9_STATEMSKn5_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn6_Pos                        6
#define SCT_EVSTATEMSK9_STATEMSKn6_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn7_Pos                        7
#define SCT_EVSTATEMSK9_STATEMSKn7_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn8_Pos                        8
#define SCT_EVSTATEMSK9_STATEMSKn8_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn9_Pos                        9
#define SCT_EVSTATEMSK9_STATEMSKn9_Msk                        (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn10_Pos                       10
#define SCT_EVSTATEMSK9_STATEMSKn10_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn11_Pos                       11
#define SCT_EVSTATEMSK9_STATEMSKn11_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn12_Pos                       12
#define SCT_EVSTATEMSK9_STATEMSKn12_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn13_Pos                       13
#define SCT_EVSTATEMSK9_STATEMSKn13_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn14_Pos                       14
#define SCT_EVSTATEMSK9_STATEMSKn14_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn15_Pos                       15
#define SCT_EVSTATEMSK9_STATEMSKn15_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn16_Pos                       16
#define SCT_EVSTATEMSK9_STATEMSKn16_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn17_Pos                       17
#define SCT_EVSTATEMSK9_STATEMSKn17_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn18_Pos                       18
#define SCT_EVSTATEMSK9_STATEMSKn18_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn19_Pos                       19
#define SCT_EVSTATEMSK9_STATEMSKn19_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn20_Pos                       20
#define SCT_EVSTATEMSK9_STATEMSKn20_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn21_Pos                       21
#define SCT_EVSTATEMSK9_STATEMSKn21_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn22_Pos                       22
#define SCT_EVSTATEMSK9_STATEMSKn22_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn23_Pos                       23
#define SCT_EVSTATEMSK9_STATEMSKn23_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn24_Pos                       24
#define SCT_EVSTATEMSK9_STATEMSKn24_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn25_Pos                       25
#define SCT_EVSTATEMSK9_STATEMSKn25_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn26_Pos                       26
#define SCT_EVSTATEMSK9_STATEMSKn26_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn27_Pos                       27
#define SCT_EVSTATEMSK9_STATEMSKn27_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn28_Pos                       28
#define SCT_EVSTATEMSK9_STATEMSKn28_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn29_Pos                       29
#define SCT_EVSTATEMSK9_STATEMSKn29_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn30_Pos                       30
#define SCT_EVSTATEMSK9_STATEMSKn30_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK9_STATEMSKn31_Pos                       31
#define SCT_EVSTATEMSK9_STATEMSKn31_Msk                       (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos)

// ---------------------------------------  SCT_EVCTRL9  ------------------------------------------
#define SCT_EVCTRL9_MATCHSEL_Pos                              0
#define SCT_EVCTRL9_MATCHSEL_Msk                              (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos)
#define SCT_EVCTRL9_HEVENT_Pos                                4
#define SCT_EVCTRL9_HEVENT_Msk                                (0x01UL << SCT_EVCTRL9_HEVENT_Pos)
#define SCT_EVCTRL9_OUTSEL_Pos                                5
#define SCT_EVCTRL9_OUTSEL_Msk                                (0x01UL << SCT_EVCTRL9_OUTSEL_Pos)
#define SCT_EVCTRL9_IOSEL_Pos                                 6
#define SCT_EVCTRL9_IOSEL_Msk                                 (0x0fUL << SCT_EVCTRL9_IOSEL_Pos)
#define SCT_EVCTRL9_IOCOND_Pos                                10
#define SCT_EVCTRL9_IOCOND_Msk                                (0x03UL << SCT_EVCTRL9_IOCOND_Pos)
#define SCT_EVCTRL9_COMBMODE_Pos                              12
#define SCT_EVCTRL9_COMBMODE_Msk                              (0x03UL << SCT_EVCTRL9_COMBMODE_Pos)
#define SCT_EVCTRL9_STATELD_Pos                               14
#define SCT_EVCTRL9_STATELD_Msk                               (0x01UL << SCT_EVCTRL9_STATELD_Pos)
#define SCT_EVCTRL9_STATEV_Pos                                15
#define SCT_EVCTRL9_STATEV_Msk                                (0x1fUL << SCT_EVCTRL9_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK10  ----------------------------------------
#define SCT_EVSTATEMSK10_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK10_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK10_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK10_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK10_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK10_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK10_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK10_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK10_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK10_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK10_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK10_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK10_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK10_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK10_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK10_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK10_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK10_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK10_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK10_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK10_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK10_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK10_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK10_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK10_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK10_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK10_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK10_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK10_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK10_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK10_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK10_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK10_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK10_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL10  ------------------------------------------
#define SCT_EVCTRL10_MATCHSEL_Pos                             0
#define SCT_EVCTRL10_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos)
#define SCT_EVCTRL10_HEVENT_Pos                               4
#define SCT_EVCTRL10_HEVENT_Msk                               (0x01UL << SCT_EVCTRL10_HEVENT_Pos)
#define SCT_EVCTRL10_OUTSEL_Pos                               5
#define SCT_EVCTRL10_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL10_OUTSEL_Pos)
#define SCT_EVCTRL10_IOSEL_Pos                                6
#define SCT_EVCTRL10_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL10_IOSEL_Pos)
#define SCT_EVCTRL10_IOCOND_Pos                               10
#define SCT_EVCTRL10_IOCOND_Msk                               (0x03UL << SCT_EVCTRL10_IOCOND_Pos)
#define SCT_EVCTRL10_COMBMODE_Pos                             12
#define SCT_EVCTRL10_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL10_COMBMODE_Pos)
#define SCT_EVCTRL10_STATELD_Pos                              14
#define SCT_EVCTRL10_STATELD_Msk                              (0x01UL << SCT_EVCTRL10_STATELD_Pos)
#define SCT_EVCTRL10_STATEV_Pos                               15
#define SCT_EVCTRL10_STATEV_Msk                               (0x1fUL << SCT_EVCTRL10_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK11  ----------------------------------------
#define SCT_EVSTATEMSK11_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK11_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK11_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK11_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK11_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK11_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK11_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK11_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK11_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK11_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK11_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK11_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK11_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK11_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK11_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK11_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK11_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK11_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK11_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK11_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK11_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK11_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK11_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK11_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK11_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK11_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK11_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK11_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK11_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK11_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK11_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK11_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK11_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK11_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL11  ------------------------------------------
#define SCT_EVCTRL11_MATCHSEL_Pos                             0
#define SCT_EVCTRL11_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos)
#define SCT_EVCTRL11_HEVENT_Pos                               4
#define SCT_EVCTRL11_HEVENT_Msk                               (0x01UL << SCT_EVCTRL11_HEVENT_Pos)
#define SCT_EVCTRL11_OUTSEL_Pos                               5
#define SCT_EVCTRL11_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL11_OUTSEL_Pos)
#define SCT_EVCTRL11_IOSEL_Pos                                6
#define SCT_EVCTRL11_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL11_IOSEL_Pos)
#define SCT_EVCTRL11_IOCOND_Pos                               10
#define SCT_EVCTRL11_IOCOND_Msk                               (0x03UL << SCT_EVCTRL11_IOCOND_Pos)
#define SCT_EVCTRL11_COMBMODE_Pos                             12
#define SCT_EVCTRL11_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL11_COMBMODE_Pos)
#define SCT_EVCTRL11_STATELD_Pos                              14
#define SCT_EVCTRL11_STATELD_Msk                              (0x01UL << SCT_EVCTRL11_STATELD_Pos)
#define SCT_EVCTRL11_STATEV_Pos                               15
#define SCT_EVCTRL11_STATEV_Msk                               (0x1fUL << SCT_EVCTRL11_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK12  ----------------------------------------
#define SCT_EVSTATEMSK12_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK12_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK12_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK12_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK12_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK12_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK12_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK12_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK12_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK12_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK12_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK12_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK12_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK12_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK12_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK12_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK12_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK12_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK12_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK12_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK12_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK12_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK12_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK12_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK12_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK12_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK12_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK12_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK12_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK12_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK12_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK12_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK12_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK12_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL12  ------------------------------------------
#define SCT_EVCTRL12_MATCHSEL_Pos                             0
#define SCT_EVCTRL12_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos)
#define SCT_EVCTRL12_HEVENT_Pos                               4
#define SCT_EVCTRL12_HEVENT_Msk                               (0x01UL << SCT_EVCTRL12_HEVENT_Pos)
#define SCT_EVCTRL12_OUTSEL_Pos                               5
#define SCT_EVCTRL12_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL12_OUTSEL_Pos)
#define SCT_EVCTRL12_IOSEL_Pos                                6
#define SCT_EVCTRL12_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL12_IOSEL_Pos)
#define SCT_EVCTRL12_IOCOND_Pos                               10
#define SCT_EVCTRL12_IOCOND_Msk                               (0x03UL << SCT_EVCTRL12_IOCOND_Pos)
#define SCT_EVCTRL12_COMBMODE_Pos                             12
#define SCT_EVCTRL12_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL12_COMBMODE_Pos)
#define SCT_EVCTRL12_STATELD_Pos                              14
#define SCT_EVCTRL12_STATELD_Msk                              (0x01UL << SCT_EVCTRL12_STATELD_Pos)
#define SCT_EVCTRL12_STATEV_Pos                               15
#define SCT_EVCTRL12_STATEV_Msk                               (0x1fUL << SCT_EVCTRL12_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK13  ----------------------------------------
#define SCT_EVSTATEMSK13_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK13_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK13_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK13_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK13_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK13_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK13_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK13_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK13_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK13_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK13_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK13_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK13_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK13_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK13_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK13_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK13_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK13_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK13_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK13_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK13_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK13_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK13_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK13_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK13_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK13_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK13_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK13_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK13_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK13_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK13_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK13_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK13_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK13_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL13  ------------------------------------------
#define SCT_EVCTRL13_MATCHSEL_Pos                             0
#define SCT_EVCTRL13_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos)
#define SCT_EVCTRL13_HEVENT_Pos                               4
#define SCT_EVCTRL13_HEVENT_Msk                               (0x01UL << SCT_EVCTRL13_HEVENT_Pos)
#define SCT_EVCTRL13_OUTSEL_Pos                               5
#define SCT_EVCTRL13_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL13_OUTSEL_Pos)
#define SCT_EVCTRL13_IOSEL_Pos                                6
#define SCT_EVCTRL13_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL13_IOSEL_Pos)
#define SCT_EVCTRL13_IOCOND_Pos                               10
#define SCT_EVCTRL13_IOCOND_Msk                               (0x03UL << SCT_EVCTRL13_IOCOND_Pos)
#define SCT_EVCTRL13_COMBMODE_Pos                             12
#define SCT_EVCTRL13_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL13_COMBMODE_Pos)
#define SCT_EVCTRL13_STATELD_Pos                              14
#define SCT_EVCTRL13_STATELD_Msk                              (0x01UL << SCT_EVCTRL13_STATELD_Pos)
#define SCT_EVCTRL13_STATEV_Pos                               15
#define SCT_EVCTRL13_STATEV_Msk                               (0x1fUL << SCT_EVCTRL13_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK14  ----------------------------------------
#define SCT_EVSTATEMSK14_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK14_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK14_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK14_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK14_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK14_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK14_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK14_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK14_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK14_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK14_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK14_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK14_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK14_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK14_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK14_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK14_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK14_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK14_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK14_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK14_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK14_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK14_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK14_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK14_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK14_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK14_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK14_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK14_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK14_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK14_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK14_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK14_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK14_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL14  ------------------------------------------
#define SCT_EVCTRL14_MATCHSEL_Pos                             0
#define SCT_EVCTRL14_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos)
#define SCT_EVCTRL14_HEVENT_Pos                               4
#define SCT_EVCTRL14_HEVENT_Msk                               (0x01UL << SCT_EVCTRL14_HEVENT_Pos)
#define SCT_EVCTRL14_OUTSEL_Pos                               5
#define SCT_EVCTRL14_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL14_OUTSEL_Pos)
#define SCT_EVCTRL14_IOSEL_Pos                                6
#define SCT_EVCTRL14_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL14_IOSEL_Pos)
#define SCT_EVCTRL14_IOCOND_Pos                               10
#define SCT_EVCTRL14_IOCOND_Msk                               (0x03UL << SCT_EVCTRL14_IOCOND_Pos)
#define SCT_EVCTRL14_COMBMODE_Pos                             12
#define SCT_EVCTRL14_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL14_COMBMODE_Pos)
#define SCT_EVCTRL14_STATELD_Pos                              14
#define SCT_EVCTRL14_STATELD_Msk                              (0x01UL << SCT_EVCTRL14_STATELD_Pos)
#define SCT_EVCTRL14_STATEV_Pos                               15
#define SCT_EVCTRL14_STATEV_Msk                               (0x1fUL << SCT_EVCTRL14_STATEV_Pos)

// ------------------------------------  SCT_EVSTATEMSK15  ----------------------------------------
#define SCT_EVSTATEMSK15_STATEMSKn0_Pos                       0
#define SCT_EVSTATEMSK15_STATEMSKn0_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn1_Pos                       1
#define SCT_EVSTATEMSK15_STATEMSKn1_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn2_Pos                       2
#define SCT_EVSTATEMSK15_STATEMSKn2_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn3_Pos                       3
#define SCT_EVSTATEMSK15_STATEMSKn3_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn4_Pos                       4
#define SCT_EVSTATEMSK15_STATEMSKn4_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn5_Pos                       5
#define SCT_EVSTATEMSK15_STATEMSKn5_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn6_Pos                       6
#define SCT_EVSTATEMSK15_STATEMSKn6_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn7_Pos                       7
#define SCT_EVSTATEMSK15_STATEMSKn7_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn8_Pos                       8
#define SCT_EVSTATEMSK15_STATEMSKn8_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn9_Pos                       9
#define SCT_EVSTATEMSK15_STATEMSKn9_Msk                       (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn10_Pos                      10
#define SCT_EVSTATEMSK15_STATEMSKn10_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn11_Pos                      11
#define SCT_EVSTATEMSK15_STATEMSKn11_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn12_Pos                      12
#define SCT_EVSTATEMSK15_STATEMSKn12_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn13_Pos                      13
#define SCT_EVSTATEMSK15_STATEMSKn13_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn14_Pos                      14
#define SCT_EVSTATEMSK15_STATEMSKn14_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn15_Pos                      15
#define SCT_EVSTATEMSK15_STATEMSKn15_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn16_Pos                      16
#define SCT_EVSTATEMSK15_STATEMSKn16_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn17_Pos                      17
#define SCT_EVSTATEMSK15_STATEMSKn17_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn18_Pos                      18
#define SCT_EVSTATEMSK15_STATEMSKn18_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn19_Pos                      19
#define SCT_EVSTATEMSK15_STATEMSKn19_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn20_Pos                      20
#define SCT_EVSTATEMSK15_STATEMSKn20_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn21_Pos                      21
#define SCT_EVSTATEMSK15_STATEMSKn21_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn22_Pos                      22
#define SCT_EVSTATEMSK15_STATEMSKn22_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn23_Pos                      23
#define SCT_EVSTATEMSK15_STATEMSKn23_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn24_Pos                      24
#define SCT_EVSTATEMSK15_STATEMSKn24_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn25_Pos                      25
#define SCT_EVSTATEMSK15_STATEMSKn25_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn26_Pos                      26
#define SCT_EVSTATEMSK15_STATEMSKn26_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn27_Pos                      27
#define SCT_EVSTATEMSK15_STATEMSKn27_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn28_Pos                      28
#define SCT_EVSTATEMSK15_STATEMSKn28_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn29_Pos                      29
#define SCT_EVSTATEMSK15_STATEMSKn29_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn30_Pos                      30
#define SCT_EVSTATEMSK15_STATEMSKn30_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos)
#define SCT_EVSTATEMSK15_STATEMSKn31_Pos                      31
#define SCT_EVSTATEMSK15_STATEMSKn31_Msk                      (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos)

// --------------------------------------  SCT_EVCTRL15  ------------------------------------------
#define SCT_EVCTRL15_MATCHSEL_Pos                             0
#define SCT_EVCTRL15_MATCHSEL_Msk                             (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos)
#define SCT_EVCTRL15_HEVENT_Pos                               4
#define SCT_EVCTRL15_HEVENT_Msk                               (0x01UL << SCT_EVCTRL15_HEVENT_Pos)
#define SCT_EVCTRL15_OUTSEL_Pos                               5
#define SCT_EVCTRL15_OUTSEL_Msk                               (0x01UL << SCT_EVCTRL15_OUTSEL_Pos)
#define SCT_EVCTRL15_IOSEL_Pos                                6
#define SCT_EVCTRL15_IOSEL_Msk                                (0x0fUL << SCT_EVCTRL15_IOSEL_Pos)
#define SCT_EVCTRL15_IOCOND_Pos                               10
#define SCT_EVCTRL15_IOCOND_Msk                               (0x03UL << SCT_EVCTRL15_IOCOND_Pos)
#define SCT_EVCTRL15_COMBMODE_Pos                             12
#define SCT_EVCTRL15_COMBMODE_Msk                             (0x03UL << SCT_EVCTRL15_COMBMODE_Pos)
#define SCT_EVCTRL15_STATELD_Pos                              14
#define SCT_EVCTRL15_STATELD_Msk                              (0x01UL << SCT_EVCTRL15_STATELD_Pos)
#define SCT_EVCTRL15_STATEV_Pos                               15
#define SCT_EVCTRL15_STATEV_Msk                               (0x1fUL << SCT_EVCTRL15_STATEV_Pos)

// -------------------------------------  SCT_OUTPUTSET0  -----------------------------------------
#define SCT_OUTPUTSET0_SETn0_Pos                              0
#define SCT_OUTPUTSET0_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn0_Pos)
#define SCT_OUTPUTSET0_SETn1_Pos                              1
#define SCT_OUTPUTSET0_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn1_Pos)
#define SCT_OUTPUTSET0_SETn2_Pos                              2
#define SCT_OUTPUTSET0_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn2_Pos)
#define SCT_OUTPUTSET0_SETn3_Pos                              3
#define SCT_OUTPUTSET0_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn3_Pos)
#define SCT_OUTPUTSET0_SETn4_Pos                              4
#define SCT_OUTPUTSET0_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn4_Pos)
#define SCT_OUTPUTSET0_SETn5_Pos                              5
#define SCT_OUTPUTSET0_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn5_Pos)
#define SCT_OUTPUTSET0_SETn6_Pos                              6
#define SCT_OUTPUTSET0_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn6_Pos)
#define SCT_OUTPUTSET0_SETn7_Pos                              7
#define SCT_OUTPUTSET0_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn7_Pos)
#define SCT_OUTPUTSET0_SETn8_Pos                              8
#define SCT_OUTPUTSET0_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn8_Pos)
#define SCT_OUTPUTSET0_SETn9_Pos                              9
#define SCT_OUTPUTSET0_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET0_SETn9_Pos)
#define SCT_OUTPUTSET0_SETn10_Pos                             10
#define SCT_OUTPUTSET0_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn10_Pos)
#define SCT_OUTPUTSET0_SETn11_Pos                             11
#define SCT_OUTPUTSET0_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn11_Pos)
#define SCT_OUTPUTSET0_SETn12_Pos                             12
#define SCT_OUTPUTSET0_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn12_Pos)
#define SCT_OUTPUTSET0_SETn13_Pos                             13
#define SCT_OUTPUTSET0_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn13_Pos)
#define SCT_OUTPUTSET0_SETn14_Pos                             14
#define SCT_OUTPUTSET0_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn14_Pos)
#define SCT_OUTPUTSET0_SETn15_Pos                             15
#define SCT_OUTPUTSET0_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET0_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR0  -----------------------------------------
#define SCT_OUTPUTCLR0_CLRn0_Pos                              0
#define SCT_OUTPUTCLR0_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos)
#define SCT_OUTPUTCLR0_CLRn1_Pos                              1
#define SCT_OUTPUTCLR0_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos)
#define SCT_OUTPUTCLR0_CLRn2_Pos                              2
#define SCT_OUTPUTCLR0_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos)
#define SCT_OUTPUTCLR0_CLRn3_Pos                              3
#define SCT_OUTPUTCLR0_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos)
#define SCT_OUTPUTCLR0_CLRn4_Pos                              4
#define SCT_OUTPUTCLR0_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos)
#define SCT_OUTPUTCLR0_CLRn5_Pos                              5
#define SCT_OUTPUTCLR0_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos)
#define SCT_OUTPUTCLR0_CLRn6_Pos                              6
#define SCT_OUTPUTCLR0_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos)
#define SCT_OUTPUTCLR0_CLRn7_Pos                              7
#define SCT_OUTPUTCLR0_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos)
#define SCT_OUTPUTCLR0_CLRn8_Pos                              8
#define SCT_OUTPUTCLR0_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos)
#define SCT_OUTPUTCLR0_CLRn9_Pos                              9
#define SCT_OUTPUTCLR0_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos)
#define SCT_OUTPUTCLR0_CLRn10_Pos                             10
#define SCT_OUTPUTCLR0_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos)
#define SCT_OUTPUTCLR0_CLRn11_Pos                             11
#define SCT_OUTPUTCLR0_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos)
#define SCT_OUTPUTCLR0_CLRn12_Pos                             12
#define SCT_OUTPUTCLR0_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos)
#define SCT_OUTPUTCLR0_CLRn13_Pos                             13
#define SCT_OUTPUTCLR0_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos)
#define SCT_OUTPUTCLR0_CLRn14_Pos                             14
#define SCT_OUTPUTCLR0_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos)
#define SCT_OUTPUTCLR0_CLRn15_Pos                             15
#define SCT_OUTPUTCLR0_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET1  -----------------------------------------
#define SCT_OUTPUTSET1_SETn0_Pos                              0
#define SCT_OUTPUTSET1_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn0_Pos)
#define SCT_OUTPUTSET1_SETn1_Pos                              1
#define SCT_OUTPUTSET1_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn1_Pos)
#define SCT_OUTPUTSET1_SETn2_Pos                              2
#define SCT_OUTPUTSET1_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn2_Pos)
#define SCT_OUTPUTSET1_SETn3_Pos                              3
#define SCT_OUTPUTSET1_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn3_Pos)
#define SCT_OUTPUTSET1_SETn4_Pos                              4
#define SCT_OUTPUTSET1_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn4_Pos)
#define SCT_OUTPUTSET1_SETn5_Pos                              5
#define SCT_OUTPUTSET1_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn5_Pos)
#define SCT_OUTPUTSET1_SETn6_Pos                              6
#define SCT_OUTPUTSET1_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn6_Pos)
#define SCT_OUTPUTSET1_SETn7_Pos                              7
#define SCT_OUTPUTSET1_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn7_Pos)
#define SCT_OUTPUTSET1_SETn8_Pos                              8
#define SCT_OUTPUTSET1_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn8_Pos)
#define SCT_OUTPUTSET1_SETn9_Pos                              9
#define SCT_OUTPUTSET1_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET1_SETn9_Pos)
#define SCT_OUTPUTSET1_SETn10_Pos                             10
#define SCT_OUTPUTSET1_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn10_Pos)
#define SCT_OUTPUTSET1_SETn11_Pos                             11
#define SCT_OUTPUTSET1_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn11_Pos)
#define SCT_OUTPUTSET1_SETn12_Pos                             12
#define SCT_OUTPUTSET1_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn12_Pos)
#define SCT_OUTPUTSET1_SETn13_Pos                             13
#define SCT_OUTPUTSET1_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn13_Pos)
#define SCT_OUTPUTSET1_SETn14_Pos                             14
#define SCT_OUTPUTSET1_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn14_Pos)
#define SCT_OUTPUTSET1_SETn15_Pos                             15
#define SCT_OUTPUTSET1_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET1_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR1  -----------------------------------------
#define SCT_OUTPUTCLR1_CLRn0_Pos                              0
#define SCT_OUTPUTCLR1_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos)
#define SCT_OUTPUTCLR1_CLRn1_Pos                              1
#define SCT_OUTPUTCLR1_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos)
#define SCT_OUTPUTCLR1_CLRn2_Pos                              2
#define SCT_OUTPUTCLR1_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos)
#define SCT_OUTPUTCLR1_CLRn3_Pos                              3
#define SCT_OUTPUTCLR1_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos)
#define SCT_OUTPUTCLR1_CLRn4_Pos                              4
#define SCT_OUTPUTCLR1_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos)
#define SCT_OUTPUTCLR1_CLRn5_Pos                              5
#define SCT_OUTPUTCLR1_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos)
#define SCT_OUTPUTCLR1_CLRn6_Pos                              6
#define SCT_OUTPUTCLR1_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos)
#define SCT_OUTPUTCLR1_CLRn7_Pos                              7
#define SCT_OUTPUTCLR1_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos)
#define SCT_OUTPUTCLR1_CLRn8_Pos                              8
#define SCT_OUTPUTCLR1_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos)
#define SCT_OUTPUTCLR1_CLRn9_Pos                              9
#define SCT_OUTPUTCLR1_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos)
#define SCT_OUTPUTCLR1_CLRn10_Pos                             10
#define SCT_OUTPUTCLR1_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos)
#define SCT_OUTPUTCLR1_CLRn11_Pos                             11
#define SCT_OUTPUTCLR1_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos)
#define SCT_OUTPUTCLR1_CLRn12_Pos                             12
#define SCT_OUTPUTCLR1_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos)
#define SCT_OUTPUTCLR1_CLRn13_Pos                             13
#define SCT_OUTPUTCLR1_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos)
#define SCT_OUTPUTCLR1_CLRn14_Pos                             14
#define SCT_OUTPUTCLR1_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos)
#define SCT_OUTPUTCLR1_CLRn15_Pos                             15
#define SCT_OUTPUTCLR1_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET2  -----------------------------------------
#define SCT_OUTPUTSET2_SETn0_Pos                              0
#define SCT_OUTPUTSET2_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn0_Pos)
#define SCT_OUTPUTSET2_SETn1_Pos                              1
#define SCT_OUTPUTSET2_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn1_Pos)
#define SCT_OUTPUTSET2_SETn2_Pos                              2
#define SCT_OUTPUTSET2_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn2_Pos)
#define SCT_OUTPUTSET2_SETn3_Pos                              3
#define SCT_OUTPUTSET2_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn3_Pos)
#define SCT_OUTPUTSET2_SETn4_Pos                              4
#define SCT_OUTPUTSET2_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn4_Pos)
#define SCT_OUTPUTSET2_SETn5_Pos                              5
#define SCT_OUTPUTSET2_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn5_Pos)
#define SCT_OUTPUTSET2_SETn6_Pos                              6
#define SCT_OUTPUTSET2_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn6_Pos)
#define SCT_OUTPUTSET2_SETn7_Pos                              7
#define SCT_OUTPUTSET2_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn7_Pos)
#define SCT_OUTPUTSET2_SETn8_Pos                              8
#define SCT_OUTPUTSET2_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn8_Pos)
#define SCT_OUTPUTSET2_SETn9_Pos                              9
#define SCT_OUTPUTSET2_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET2_SETn9_Pos)
#define SCT_OUTPUTSET2_SETn10_Pos                             10
#define SCT_OUTPUTSET2_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn10_Pos)
#define SCT_OUTPUTSET2_SETn11_Pos                             11
#define SCT_OUTPUTSET2_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn11_Pos)
#define SCT_OUTPUTSET2_SETn12_Pos                             12
#define SCT_OUTPUTSET2_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn12_Pos)
#define SCT_OUTPUTSET2_SETn13_Pos                             13
#define SCT_OUTPUTSET2_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn13_Pos)
#define SCT_OUTPUTSET2_SETn14_Pos                             14
#define SCT_OUTPUTSET2_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn14_Pos)
#define SCT_OUTPUTSET2_SETn15_Pos                             15
#define SCT_OUTPUTSET2_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET2_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR2  -----------------------------------------
#define SCT_OUTPUTCLR2_CLRn0_Pos                              0
#define SCT_OUTPUTCLR2_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos)
#define SCT_OUTPUTCLR2_CLRn1_Pos                              1
#define SCT_OUTPUTCLR2_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos)
#define SCT_OUTPUTCLR2_CLRn2_Pos                              2
#define SCT_OUTPUTCLR2_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos)
#define SCT_OUTPUTCLR2_CLRn3_Pos                              3
#define SCT_OUTPUTCLR2_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos)
#define SCT_OUTPUTCLR2_CLRn4_Pos                              4
#define SCT_OUTPUTCLR2_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos)
#define SCT_OUTPUTCLR2_CLRn5_Pos                              5
#define SCT_OUTPUTCLR2_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos)
#define SCT_OUTPUTCLR2_CLRn6_Pos                              6
#define SCT_OUTPUTCLR2_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos)
#define SCT_OUTPUTCLR2_CLRn7_Pos                              7
#define SCT_OUTPUTCLR2_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos)
#define SCT_OUTPUTCLR2_CLRn8_Pos                              8
#define SCT_OUTPUTCLR2_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos)
#define SCT_OUTPUTCLR2_CLRn9_Pos                              9
#define SCT_OUTPUTCLR2_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos)
#define SCT_OUTPUTCLR2_CLRn10_Pos                             10
#define SCT_OUTPUTCLR2_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos)
#define SCT_OUTPUTCLR2_CLRn11_Pos                             11
#define SCT_OUTPUTCLR2_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos)
#define SCT_OUTPUTCLR2_CLRn12_Pos                             12
#define SCT_OUTPUTCLR2_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos)
#define SCT_OUTPUTCLR2_CLRn13_Pos                             13
#define SCT_OUTPUTCLR2_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos)
#define SCT_OUTPUTCLR2_CLRn14_Pos                             14
#define SCT_OUTPUTCLR2_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos)
#define SCT_OUTPUTCLR2_CLRn15_Pos                             15
#define SCT_OUTPUTCLR2_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET3  -----------------------------------------
#define SCT_OUTPUTSET3_SETn0_Pos                              0
#define SCT_OUTPUTSET3_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn0_Pos)
#define SCT_OUTPUTSET3_SETn1_Pos                              1
#define SCT_OUTPUTSET3_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn1_Pos)
#define SCT_OUTPUTSET3_SETn2_Pos                              2
#define SCT_OUTPUTSET3_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn2_Pos)
#define SCT_OUTPUTSET3_SETn3_Pos                              3
#define SCT_OUTPUTSET3_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn3_Pos)
#define SCT_OUTPUTSET3_SETn4_Pos                              4
#define SCT_OUTPUTSET3_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn4_Pos)
#define SCT_OUTPUTSET3_SETn5_Pos                              5
#define SCT_OUTPUTSET3_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn5_Pos)
#define SCT_OUTPUTSET3_SETn6_Pos                              6
#define SCT_OUTPUTSET3_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn6_Pos)
#define SCT_OUTPUTSET3_SETn7_Pos                              7
#define SCT_OUTPUTSET3_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn7_Pos)
#define SCT_OUTPUTSET3_SETn8_Pos                              8
#define SCT_OUTPUTSET3_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn8_Pos)
#define SCT_OUTPUTSET3_SETn9_Pos                              9
#define SCT_OUTPUTSET3_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET3_SETn9_Pos)
#define SCT_OUTPUTSET3_SETn10_Pos                             10
#define SCT_OUTPUTSET3_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn10_Pos)
#define SCT_OUTPUTSET3_SETn11_Pos                             11
#define SCT_OUTPUTSET3_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn11_Pos)
#define SCT_OUTPUTSET3_SETn12_Pos                             12
#define SCT_OUTPUTSET3_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn12_Pos)
#define SCT_OUTPUTSET3_SETn13_Pos                             13
#define SCT_OUTPUTSET3_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn13_Pos)
#define SCT_OUTPUTSET3_SETn14_Pos                             14
#define SCT_OUTPUTSET3_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn14_Pos)
#define SCT_OUTPUTSET3_SETn15_Pos                             15
#define SCT_OUTPUTSET3_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET3_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR3  -----------------------------------------
#define SCT_OUTPUTCLR3_CLRn0_Pos                              0
#define SCT_OUTPUTCLR3_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos)
#define SCT_OUTPUTCLR3_CLRn1_Pos                              1
#define SCT_OUTPUTCLR3_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos)
#define SCT_OUTPUTCLR3_CLRn2_Pos                              2
#define SCT_OUTPUTCLR3_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos)
#define SCT_OUTPUTCLR3_CLRn3_Pos                              3
#define SCT_OUTPUTCLR3_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos)
#define SCT_OUTPUTCLR3_CLRn4_Pos                              4
#define SCT_OUTPUTCLR3_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos)
#define SCT_OUTPUTCLR3_CLRn5_Pos                              5
#define SCT_OUTPUTCLR3_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos)
#define SCT_OUTPUTCLR3_CLRn6_Pos                              6
#define SCT_OUTPUTCLR3_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos)
#define SCT_OUTPUTCLR3_CLRn7_Pos                              7
#define SCT_OUTPUTCLR3_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos)
#define SCT_OUTPUTCLR3_CLRn8_Pos                              8
#define SCT_OUTPUTCLR3_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos)
#define SCT_OUTPUTCLR3_CLRn9_Pos                              9
#define SCT_OUTPUTCLR3_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos)
#define SCT_OUTPUTCLR3_CLRn10_Pos                             10
#define SCT_OUTPUTCLR3_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos)
#define SCT_OUTPUTCLR3_CLRn11_Pos                             11
#define SCT_OUTPUTCLR3_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos)
#define SCT_OUTPUTCLR3_CLRn12_Pos                             12
#define SCT_OUTPUTCLR3_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos)
#define SCT_OUTPUTCLR3_CLRn13_Pos                             13
#define SCT_OUTPUTCLR3_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos)
#define SCT_OUTPUTCLR3_CLRn14_Pos                             14
#define SCT_OUTPUTCLR3_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos)
#define SCT_OUTPUTCLR3_CLRn15_Pos                             15
#define SCT_OUTPUTCLR3_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET4  -----------------------------------------
#define SCT_OUTPUTSET4_SETn0_Pos                              0
#define SCT_OUTPUTSET4_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn0_Pos)
#define SCT_OUTPUTSET4_SETn1_Pos                              1
#define SCT_OUTPUTSET4_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn1_Pos)
#define SCT_OUTPUTSET4_SETn2_Pos                              2
#define SCT_OUTPUTSET4_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn2_Pos)
#define SCT_OUTPUTSET4_SETn3_Pos                              3
#define SCT_OUTPUTSET4_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn3_Pos)
#define SCT_OUTPUTSET4_SETn4_Pos                              4
#define SCT_OUTPUTSET4_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn4_Pos)
#define SCT_OUTPUTSET4_SETn5_Pos                              5
#define SCT_OUTPUTSET4_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn5_Pos)
#define SCT_OUTPUTSET4_SETn6_Pos                              6
#define SCT_OUTPUTSET4_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn6_Pos)
#define SCT_OUTPUTSET4_SETn7_Pos                              7
#define SCT_OUTPUTSET4_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn7_Pos)
#define SCT_OUTPUTSET4_SETn8_Pos                              8
#define SCT_OUTPUTSET4_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn8_Pos)
#define SCT_OUTPUTSET4_SETn9_Pos                              9
#define SCT_OUTPUTSET4_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET4_SETn9_Pos)
#define SCT_OUTPUTSET4_SETn10_Pos                             10
#define SCT_OUTPUTSET4_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn10_Pos)
#define SCT_OUTPUTSET4_SETn11_Pos                             11
#define SCT_OUTPUTSET4_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn11_Pos)
#define SCT_OUTPUTSET4_SETn12_Pos                             12
#define SCT_OUTPUTSET4_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn12_Pos)
#define SCT_OUTPUTSET4_SETn13_Pos                             13
#define SCT_OUTPUTSET4_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn13_Pos)
#define SCT_OUTPUTSET4_SETn14_Pos                             14
#define SCT_OUTPUTSET4_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn14_Pos)
#define SCT_OUTPUTSET4_SETn15_Pos                             15
#define SCT_OUTPUTSET4_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET4_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR4  -----------------------------------------
#define SCT_OUTPUTCLR4_CLRn0_Pos                              0
#define SCT_OUTPUTCLR4_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos)
#define SCT_OUTPUTCLR4_CLRn1_Pos                              1
#define SCT_OUTPUTCLR4_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos)
#define SCT_OUTPUTCLR4_CLRn2_Pos                              2
#define SCT_OUTPUTCLR4_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos)
#define SCT_OUTPUTCLR4_CLRn3_Pos                              3
#define SCT_OUTPUTCLR4_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos)
#define SCT_OUTPUTCLR4_CLRn4_Pos                              4
#define SCT_OUTPUTCLR4_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos)
#define SCT_OUTPUTCLR4_CLRn5_Pos                              5
#define SCT_OUTPUTCLR4_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos)
#define SCT_OUTPUTCLR4_CLRn6_Pos                              6
#define SCT_OUTPUTCLR4_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos)
#define SCT_OUTPUTCLR4_CLRn7_Pos                              7
#define SCT_OUTPUTCLR4_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos)
#define SCT_OUTPUTCLR4_CLRn8_Pos                              8
#define SCT_OUTPUTCLR4_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos)
#define SCT_OUTPUTCLR4_CLRn9_Pos                              9
#define SCT_OUTPUTCLR4_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos)
#define SCT_OUTPUTCLR4_CLRn10_Pos                             10
#define SCT_OUTPUTCLR4_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos)
#define SCT_OUTPUTCLR4_CLRn11_Pos                             11
#define SCT_OUTPUTCLR4_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos)
#define SCT_OUTPUTCLR4_CLRn12_Pos                             12
#define SCT_OUTPUTCLR4_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos)
#define SCT_OUTPUTCLR4_CLRn13_Pos                             13
#define SCT_OUTPUTCLR4_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos)
#define SCT_OUTPUTCLR4_CLRn14_Pos                             14
#define SCT_OUTPUTCLR4_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos)
#define SCT_OUTPUTCLR4_CLRn15_Pos                             15
#define SCT_OUTPUTCLR4_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET5  -----------------------------------------
#define SCT_OUTPUTSET5_SETn0_Pos                              0
#define SCT_OUTPUTSET5_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn0_Pos)
#define SCT_OUTPUTSET5_SETn1_Pos                              1
#define SCT_OUTPUTSET5_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn1_Pos)
#define SCT_OUTPUTSET5_SETn2_Pos                              2
#define SCT_OUTPUTSET5_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn2_Pos)
#define SCT_OUTPUTSET5_SETn3_Pos                              3
#define SCT_OUTPUTSET5_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn3_Pos)
#define SCT_OUTPUTSET5_SETn4_Pos                              4
#define SCT_OUTPUTSET5_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn4_Pos)
#define SCT_OUTPUTSET5_SETn5_Pos                              5
#define SCT_OUTPUTSET5_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn5_Pos)
#define SCT_OUTPUTSET5_SETn6_Pos                              6
#define SCT_OUTPUTSET5_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn6_Pos)
#define SCT_OUTPUTSET5_SETn7_Pos                              7
#define SCT_OUTPUTSET5_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn7_Pos)
#define SCT_OUTPUTSET5_SETn8_Pos                              8
#define SCT_OUTPUTSET5_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn8_Pos)
#define SCT_OUTPUTSET5_SETn9_Pos                              9
#define SCT_OUTPUTSET5_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET5_SETn9_Pos)
#define SCT_OUTPUTSET5_SETn10_Pos                             10
#define SCT_OUTPUTSET5_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn10_Pos)
#define SCT_OUTPUTSET5_SETn11_Pos                             11
#define SCT_OUTPUTSET5_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn11_Pos)
#define SCT_OUTPUTSET5_SETn12_Pos                             12
#define SCT_OUTPUTSET5_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn12_Pos)
#define SCT_OUTPUTSET5_SETn13_Pos                             13
#define SCT_OUTPUTSET5_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn13_Pos)
#define SCT_OUTPUTSET5_SETn14_Pos                             14
#define SCT_OUTPUTSET5_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn14_Pos)
#define SCT_OUTPUTSET5_SETn15_Pos                             15
#define SCT_OUTPUTSET5_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET5_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR5  -----------------------------------------
#define SCT_OUTPUTCLR5_CLRn0_Pos                              0
#define SCT_OUTPUTCLR5_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos)
#define SCT_OUTPUTCLR5_CLRn1_Pos                              1
#define SCT_OUTPUTCLR5_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos)
#define SCT_OUTPUTCLR5_CLRn2_Pos                              2
#define SCT_OUTPUTCLR5_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos)
#define SCT_OUTPUTCLR5_CLRn3_Pos                              3
#define SCT_OUTPUTCLR5_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos)
#define SCT_OUTPUTCLR5_CLRn4_Pos                              4
#define SCT_OUTPUTCLR5_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos)
#define SCT_OUTPUTCLR5_CLRn5_Pos                              5
#define SCT_OUTPUTCLR5_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos)
#define SCT_OUTPUTCLR5_CLRn6_Pos                              6
#define SCT_OUTPUTCLR5_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos)
#define SCT_OUTPUTCLR5_CLRn7_Pos                              7
#define SCT_OUTPUTCLR5_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos)
#define SCT_OUTPUTCLR5_CLRn8_Pos                              8
#define SCT_OUTPUTCLR5_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos)
#define SCT_OUTPUTCLR5_CLRn9_Pos                              9
#define SCT_OUTPUTCLR5_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos)
#define SCT_OUTPUTCLR5_CLRn10_Pos                             10
#define SCT_OUTPUTCLR5_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos)
#define SCT_OUTPUTCLR5_CLRn11_Pos                             11
#define SCT_OUTPUTCLR5_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos)
#define SCT_OUTPUTCLR5_CLRn12_Pos                             12
#define SCT_OUTPUTCLR5_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos)
#define SCT_OUTPUTCLR5_CLRn13_Pos                             13
#define SCT_OUTPUTCLR5_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos)
#define SCT_OUTPUTCLR5_CLRn14_Pos                             14
#define SCT_OUTPUTCLR5_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos)
#define SCT_OUTPUTCLR5_CLRn15_Pos                             15
#define SCT_OUTPUTCLR5_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET6  -----------------------------------------
#define SCT_OUTPUTSET6_SETn0_Pos                              0
#define SCT_OUTPUTSET6_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn0_Pos)
#define SCT_OUTPUTSET6_SETn1_Pos                              1
#define SCT_OUTPUTSET6_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn1_Pos)
#define SCT_OUTPUTSET6_SETn2_Pos                              2
#define SCT_OUTPUTSET6_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn2_Pos)
#define SCT_OUTPUTSET6_SETn3_Pos                              3
#define SCT_OUTPUTSET6_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn3_Pos)
#define SCT_OUTPUTSET6_SETn4_Pos                              4
#define SCT_OUTPUTSET6_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn4_Pos)
#define SCT_OUTPUTSET6_SETn5_Pos                              5
#define SCT_OUTPUTSET6_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn5_Pos)
#define SCT_OUTPUTSET6_SETn6_Pos                              6
#define SCT_OUTPUTSET6_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn6_Pos)
#define SCT_OUTPUTSET6_SETn7_Pos                              7
#define SCT_OUTPUTSET6_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn7_Pos)
#define SCT_OUTPUTSET6_SETn8_Pos                              8
#define SCT_OUTPUTSET6_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn8_Pos)
#define SCT_OUTPUTSET6_SETn9_Pos                              9
#define SCT_OUTPUTSET6_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET6_SETn9_Pos)
#define SCT_OUTPUTSET6_SETn10_Pos                             10
#define SCT_OUTPUTSET6_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn10_Pos)
#define SCT_OUTPUTSET6_SETn11_Pos                             11
#define SCT_OUTPUTSET6_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn11_Pos)
#define SCT_OUTPUTSET6_SETn12_Pos                             12
#define SCT_OUTPUTSET6_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn12_Pos)
#define SCT_OUTPUTSET6_SETn13_Pos                             13
#define SCT_OUTPUTSET6_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn13_Pos)
#define SCT_OUTPUTSET6_SETn14_Pos                             14
#define SCT_OUTPUTSET6_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn14_Pos)
#define SCT_OUTPUTSET6_SETn15_Pos                             15
#define SCT_OUTPUTSET6_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET6_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR6  -----------------------------------------
#define SCT_OUTPUTCLR6_CLRn0_Pos                              0
#define SCT_OUTPUTCLR6_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos)
#define SCT_OUTPUTCLR6_CLRn1_Pos                              1
#define SCT_OUTPUTCLR6_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos)
#define SCT_OUTPUTCLR6_CLRn2_Pos                              2
#define SCT_OUTPUTCLR6_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos)
#define SCT_OUTPUTCLR6_CLRn3_Pos                              3
#define SCT_OUTPUTCLR6_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos)
#define SCT_OUTPUTCLR6_CLRn4_Pos                              4
#define SCT_OUTPUTCLR6_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos)
#define SCT_OUTPUTCLR6_CLRn5_Pos                              5
#define SCT_OUTPUTCLR6_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos)
#define SCT_OUTPUTCLR6_CLRn6_Pos                              6
#define SCT_OUTPUTCLR6_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos)
#define SCT_OUTPUTCLR6_CLRn7_Pos                              7
#define SCT_OUTPUTCLR6_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos)
#define SCT_OUTPUTCLR6_CLRn8_Pos                              8
#define SCT_OUTPUTCLR6_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos)
#define SCT_OUTPUTCLR6_CLRn9_Pos                              9
#define SCT_OUTPUTCLR6_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos)
#define SCT_OUTPUTCLR6_CLRn10_Pos                             10
#define SCT_OUTPUTCLR6_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos)
#define SCT_OUTPUTCLR6_CLRn11_Pos                             11
#define SCT_OUTPUTCLR6_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos)
#define SCT_OUTPUTCLR6_CLRn12_Pos                             12
#define SCT_OUTPUTCLR6_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos)
#define SCT_OUTPUTCLR6_CLRn13_Pos                             13
#define SCT_OUTPUTCLR6_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos)
#define SCT_OUTPUTCLR6_CLRn14_Pos                             14
#define SCT_OUTPUTCLR6_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos)
#define SCT_OUTPUTCLR6_CLRn15_Pos                             15
#define SCT_OUTPUTCLR6_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET7  -----------------------------------------
#define SCT_OUTPUTSET7_SETn0_Pos                              0
#define SCT_OUTPUTSET7_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn0_Pos)
#define SCT_OUTPUTSET7_SETn1_Pos                              1
#define SCT_OUTPUTSET7_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn1_Pos)
#define SCT_OUTPUTSET7_SETn2_Pos                              2
#define SCT_OUTPUTSET7_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn2_Pos)
#define SCT_OUTPUTSET7_SETn3_Pos                              3
#define SCT_OUTPUTSET7_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn3_Pos)
#define SCT_OUTPUTSET7_SETn4_Pos                              4
#define SCT_OUTPUTSET7_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn4_Pos)
#define SCT_OUTPUTSET7_SETn5_Pos                              5
#define SCT_OUTPUTSET7_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn5_Pos)
#define SCT_OUTPUTSET7_SETn6_Pos                              6
#define SCT_OUTPUTSET7_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn6_Pos)
#define SCT_OUTPUTSET7_SETn7_Pos                              7
#define SCT_OUTPUTSET7_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn7_Pos)
#define SCT_OUTPUTSET7_SETn8_Pos                              8
#define SCT_OUTPUTSET7_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn8_Pos)
#define SCT_OUTPUTSET7_SETn9_Pos                              9
#define SCT_OUTPUTSET7_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET7_SETn9_Pos)
#define SCT_OUTPUTSET7_SETn10_Pos                             10
#define SCT_OUTPUTSET7_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn10_Pos)
#define SCT_OUTPUTSET7_SETn11_Pos                             11
#define SCT_OUTPUTSET7_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn11_Pos)
#define SCT_OUTPUTSET7_SETn12_Pos                             12
#define SCT_OUTPUTSET7_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn12_Pos)
#define SCT_OUTPUTSET7_SETn13_Pos                             13
#define SCT_OUTPUTSET7_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn13_Pos)
#define SCT_OUTPUTSET7_SETn14_Pos                             14
#define SCT_OUTPUTSET7_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn14_Pos)
#define SCT_OUTPUTSET7_SETn15_Pos                             15
#define SCT_OUTPUTSET7_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET7_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR7  -----------------------------------------
#define SCT_OUTPUTCLR7_CLRn0_Pos                              0
#define SCT_OUTPUTCLR7_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos)
#define SCT_OUTPUTCLR7_CLRn1_Pos                              1
#define SCT_OUTPUTCLR7_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos)
#define SCT_OUTPUTCLR7_CLRn2_Pos                              2
#define SCT_OUTPUTCLR7_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos)
#define SCT_OUTPUTCLR7_CLRn3_Pos                              3
#define SCT_OUTPUTCLR7_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos)
#define SCT_OUTPUTCLR7_CLRn4_Pos                              4
#define SCT_OUTPUTCLR7_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos)
#define SCT_OUTPUTCLR7_CLRn5_Pos                              5
#define SCT_OUTPUTCLR7_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos)
#define SCT_OUTPUTCLR7_CLRn6_Pos                              6
#define SCT_OUTPUTCLR7_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos)
#define SCT_OUTPUTCLR7_CLRn7_Pos                              7
#define SCT_OUTPUTCLR7_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos)
#define SCT_OUTPUTCLR7_CLRn8_Pos                              8
#define SCT_OUTPUTCLR7_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos)
#define SCT_OUTPUTCLR7_CLRn9_Pos                              9
#define SCT_OUTPUTCLR7_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos)
#define SCT_OUTPUTCLR7_CLRn10_Pos                             10
#define SCT_OUTPUTCLR7_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos)
#define SCT_OUTPUTCLR7_CLRn11_Pos                             11
#define SCT_OUTPUTCLR7_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos)
#define SCT_OUTPUTCLR7_CLRn12_Pos                             12
#define SCT_OUTPUTCLR7_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos)
#define SCT_OUTPUTCLR7_CLRn13_Pos                             13
#define SCT_OUTPUTCLR7_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos)
#define SCT_OUTPUTCLR7_CLRn14_Pos                             14
#define SCT_OUTPUTCLR7_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos)
#define SCT_OUTPUTCLR7_CLRn15_Pos                             15
#define SCT_OUTPUTCLR7_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET8  -----------------------------------------
#define SCT_OUTPUTSET8_SETn0_Pos                              0
#define SCT_OUTPUTSET8_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn0_Pos)
#define SCT_OUTPUTSET8_SETn1_Pos                              1
#define SCT_OUTPUTSET8_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn1_Pos)
#define SCT_OUTPUTSET8_SETn2_Pos                              2
#define SCT_OUTPUTSET8_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn2_Pos)
#define SCT_OUTPUTSET8_SETn3_Pos                              3
#define SCT_OUTPUTSET8_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn3_Pos)
#define SCT_OUTPUTSET8_SETn4_Pos                              4
#define SCT_OUTPUTSET8_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn4_Pos)
#define SCT_OUTPUTSET8_SETn5_Pos                              5
#define SCT_OUTPUTSET8_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn5_Pos)
#define SCT_OUTPUTSET8_SETn6_Pos                              6
#define SCT_OUTPUTSET8_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn6_Pos)
#define SCT_OUTPUTSET8_SETn7_Pos                              7
#define SCT_OUTPUTSET8_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn7_Pos)
#define SCT_OUTPUTSET8_SETn8_Pos                              8
#define SCT_OUTPUTSET8_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn8_Pos)
#define SCT_OUTPUTSET8_SETn9_Pos                              9
#define SCT_OUTPUTSET8_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET8_SETn9_Pos)
#define SCT_OUTPUTSET8_SETn10_Pos                             10
#define SCT_OUTPUTSET8_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn10_Pos)
#define SCT_OUTPUTSET8_SETn11_Pos                             11
#define SCT_OUTPUTSET8_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn11_Pos)
#define SCT_OUTPUTSET8_SETn12_Pos                             12
#define SCT_OUTPUTSET8_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn12_Pos)
#define SCT_OUTPUTSET8_SETn13_Pos                             13
#define SCT_OUTPUTSET8_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn13_Pos)
#define SCT_OUTPUTSET8_SETn14_Pos                             14
#define SCT_OUTPUTSET8_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn14_Pos)
#define SCT_OUTPUTSET8_SETn15_Pos                             15
#define SCT_OUTPUTSET8_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET8_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR8  -----------------------------------------
#define SCT_OUTPUTCLR8_CLRn0_Pos                              0
#define SCT_OUTPUTCLR8_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos)
#define SCT_OUTPUTCLR8_CLRn1_Pos                              1
#define SCT_OUTPUTCLR8_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos)
#define SCT_OUTPUTCLR8_CLRn2_Pos                              2
#define SCT_OUTPUTCLR8_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos)
#define SCT_OUTPUTCLR8_CLRn3_Pos                              3
#define SCT_OUTPUTCLR8_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos)
#define SCT_OUTPUTCLR8_CLRn4_Pos                              4
#define SCT_OUTPUTCLR8_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos)
#define SCT_OUTPUTCLR8_CLRn5_Pos                              5
#define SCT_OUTPUTCLR8_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos)
#define SCT_OUTPUTCLR8_CLRn6_Pos                              6
#define SCT_OUTPUTCLR8_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos)
#define SCT_OUTPUTCLR8_CLRn7_Pos                              7
#define SCT_OUTPUTCLR8_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos)
#define SCT_OUTPUTCLR8_CLRn8_Pos                              8
#define SCT_OUTPUTCLR8_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos)
#define SCT_OUTPUTCLR8_CLRn9_Pos                              9
#define SCT_OUTPUTCLR8_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos)
#define SCT_OUTPUTCLR8_CLRn10_Pos                             10
#define SCT_OUTPUTCLR8_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos)
#define SCT_OUTPUTCLR8_CLRn11_Pos                             11
#define SCT_OUTPUTCLR8_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos)
#define SCT_OUTPUTCLR8_CLRn12_Pos                             12
#define SCT_OUTPUTCLR8_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos)
#define SCT_OUTPUTCLR8_CLRn13_Pos                             13
#define SCT_OUTPUTCLR8_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos)
#define SCT_OUTPUTCLR8_CLRn14_Pos                             14
#define SCT_OUTPUTCLR8_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos)
#define SCT_OUTPUTCLR8_CLRn15_Pos                             15
#define SCT_OUTPUTCLR8_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET9  -----------------------------------------
#define SCT_OUTPUTSET9_SETn0_Pos                              0
#define SCT_OUTPUTSET9_SETn0_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn0_Pos)
#define SCT_OUTPUTSET9_SETn1_Pos                              1
#define SCT_OUTPUTSET9_SETn1_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn1_Pos)
#define SCT_OUTPUTSET9_SETn2_Pos                              2
#define SCT_OUTPUTSET9_SETn2_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn2_Pos)
#define SCT_OUTPUTSET9_SETn3_Pos                              3
#define SCT_OUTPUTSET9_SETn3_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn3_Pos)
#define SCT_OUTPUTSET9_SETn4_Pos                              4
#define SCT_OUTPUTSET9_SETn4_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn4_Pos)
#define SCT_OUTPUTSET9_SETn5_Pos                              5
#define SCT_OUTPUTSET9_SETn5_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn5_Pos)
#define SCT_OUTPUTSET9_SETn6_Pos                              6
#define SCT_OUTPUTSET9_SETn6_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn6_Pos)
#define SCT_OUTPUTSET9_SETn7_Pos                              7
#define SCT_OUTPUTSET9_SETn7_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn7_Pos)
#define SCT_OUTPUTSET9_SETn8_Pos                              8
#define SCT_OUTPUTSET9_SETn8_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn8_Pos)
#define SCT_OUTPUTSET9_SETn9_Pos                              9
#define SCT_OUTPUTSET9_SETn9_Msk                              (0x01UL << SCT_OUTPUTSET9_SETn9_Pos)
#define SCT_OUTPUTSET9_SETn10_Pos                             10
#define SCT_OUTPUTSET9_SETn10_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn10_Pos)
#define SCT_OUTPUTSET9_SETn11_Pos                             11
#define SCT_OUTPUTSET9_SETn11_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn11_Pos)
#define SCT_OUTPUTSET9_SETn12_Pos                             12
#define SCT_OUTPUTSET9_SETn12_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn12_Pos)
#define SCT_OUTPUTSET9_SETn13_Pos                             13
#define SCT_OUTPUTSET9_SETn13_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn13_Pos)
#define SCT_OUTPUTSET9_SETn14_Pos                             14
#define SCT_OUTPUTSET9_SETn14_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn14_Pos)
#define SCT_OUTPUTSET9_SETn15_Pos                             15
#define SCT_OUTPUTSET9_SETn15_Msk                             (0x01UL << SCT_OUTPUTSET9_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR9  -----------------------------------------
#define SCT_OUTPUTCLR9_CLRn0_Pos                              0
#define SCT_OUTPUTCLR9_CLRn0_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos)
#define SCT_OUTPUTCLR9_CLRn1_Pos                              1
#define SCT_OUTPUTCLR9_CLRn1_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos)
#define SCT_OUTPUTCLR9_CLRn2_Pos                              2
#define SCT_OUTPUTCLR9_CLRn2_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos)
#define SCT_OUTPUTCLR9_CLRn3_Pos                              3
#define SCT_OUTPUTCLR9_CLRn3_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos)
#define SCT_OUTPUTCLR9_CLRn4_Pos                              4
#define SCT_OUTPUTCLR9_CLRn4_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos)
#define SCT_OUTPUTCLR9_CLRn5_Pos                              5
#define SCT_OUTPUTCLR9_CLRn5_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos)
#define SCT_OUTPUTCLR9_CLRn6_Pos                              6
#define SCT_OUTPUTCLR9_CLRn6_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos)
#define SCT_OUTPUTCLR9_CLRn7_Pos                              7
#define SCT_OUTPUTCLR9_CLRn7_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos)
#define SCT_OUTPUTCLR9_CLRn8_Pos                              8
#define SCT_OUTPUTCLR9_CLRn8_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos)
#define SCT_OUTPUTCLR9_CLRn9_Pos                              9
#define SCT_OUTPUTCLR9_CLRn9_Msk                              (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos)
#define SCT_OUTPUTCLR9_CLRn10_Pos                             10
#define SCT_OUTPUTCLR9_CLRn10_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos)
#define SCT_OUTPUTCLR9_CLRn11_Pos                             11
#define SCT_OUTPUTCLR9_CLRn11_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos)
#define SCT_OUTPUTCLR9_CLRn12_Pos                             12
#define SCT_OUTPUTCLR9_CLRn12_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos)
#define SCT_OUTPUTCLR9_CLRn13_Pos                             13
#define SCT_OUTPUTCLR9_CLRn13_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos)
#define SCT_OUTPUTCLR9_CLRn14_Pos                             14
#define SCT_OUTPUTCLR9_CLRn14_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos)
#define SCT_OUTPUTCLR9_CLRn15_Pos                             15
#define SCT_OUTPUTCLR9_CLRn15_Msk                             (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET10  ----------------------------------------
#define SCT_OUTPUTSET10_SETn0_Pos                             0
#define SCT_OUTPUTSET10_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn0_Pos)
#define SCT_OUTPUTSET10_SETn1_Pos                             1
#define SCT_OUTPUTSET10_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn1_Pos)
#define SCT_OUTPUTSET10_SETn2_Pos                             2
#define SCT_OUTPUTSET10_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn2_Pos)
#define SCT_OUTPUTSET10_SETn3_Pos                             3
#define SCT_OUTPUTSET10_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn3_Pos)
#define SCT_OUTPUTSET10_SETn4_Pos                             4
#define SCT_OUTPUTSET10_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn4_Pos)
#define SCT_OUTPUTSET10_SETn5_Pos                             5
#define SCT_OUTPUTSET10_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn5_Pos)
#define SCT_OUTPUTSET10_SETn6_Pos                             6
#define SCT_OUTPUTSET10_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn6_Pos)
#define SCT_OUTPUTSET10_SETn7_Pos                             7
#define SCT_OUTPUTSET10_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn7_Pos)
#define SCT_OUTPUTSET10_SETn8_Pos                             8
#define SCT_OUTPUTSET10_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn8_Pos)
#define SCT_OUTPUTSET10_SETn9_Pos                             9
#define SCT_OUTPUTSET10_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET10_SETn9_Pos)
#define SCT_OUTPUTSET10_SETn10_Pos                            10
#define SCT_OUTPUTSET10_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn10_Pos)
#define SCT_OUTPUTSET10_SETn11_Pos                            11
#define SCT_OUTPUTSET10_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn11_Pos)
#define SCT_OUTPUTSET10_SETn12_Pos                            12
#define SCT_OUTPUTSET10_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn12_Pos)
#define SCT_OUTPUTSET10_SETn13_Pos                            13
#define SCT_OUTPUTSET10_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn13_Pos)
#define SCT_OUTPUTSET10_SETn14_Pos                            14
#define SCT_OUTPUTSET10_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn14_Pos)
#define SCT_OUTPUTSET10_SETn15_Pos                            15
#define SCT_OUTPUTSET10_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET10_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR10  ----------------------------------------
#define SCT_OUTPUTCLR10_CLRn0_Pos                             0
#define SCT_OUTPUTCLR10_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos)
#define SCT_OUTPUTCLR10_CLRn1_Pos                             1
#define SCT_OUTPUTCLR10_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos)
#define SCT_OUTPUTCLR10_CLRn2_Pos                             2
#define SCT_OUTPUTCLR10_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos)
#define SCT_OUTPUTCLR10_CLRn3_Pos                             3
#define SCT_OUTPUTCLR10_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos)
#define SCT_OUTPUTCLR10_CLRn4_Pos                             4
#define SCT_OUTPUTCLR10_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos)
#define SCT_OUTPUTCLR10_CLRn5_Pos                             5
#define SCT_OUTPUTCLR10_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos)
#define SCT_OUTPUTCLR10_CLRn6_Pos                             6
#define SCT_OUTPUTCLR10_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos)
#define SCT_OUTPUTCLR10_CLRn7_Pos                             7
#define SCT_OUTPUTCLR10_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos)
#define SCT_OUTPUTCLR10_CLRn8_Pos                             8
#define SCT_OUTPUTCLR10_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos)
#define SCT_OUTPUTCLR10_CLRn9_Pos                             9
#define SCT_OUTPUTCLR10_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos)
#define SCT_OUTPUTCLR10_CLRn10_Pos                            10
#define SCT_OUTPUTCLR10_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos)
#define SCT_OUTPUTCLR10_CLRn11_Pos                            11
#define SCT_OUTPUTCLR10_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos)
#define SCT_OUTPUTCLR10_CLRn12_Pos                            12
#define SCT_OUTPUTCLR10_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos)
#define SCT_OUTPUTCLR10_CLRn13_Pos                            13
#define SCT_OUTPUTCLR10_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos)
#define SCT_OUTPUTCLR10_CLRn14_Pos                            14
#define SCT_OUTPUTCLR10_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos)
#define SCT_OUTPUTCLR10_CLRn15_Pos                            15
#define SCT_OUTPUTCLR10_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET11  ----------------------------------------
#define SCT_OUTPUTSET11_SETn0_Pos                             0
#define SCT_OUTPUTSET11_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn0_Pos)
#define SCT_OUTPUTSET11_SETn1_Pos                             1
#define SCT_OUTPUTSET11_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn1_Pos)
#define SCT_OUTPUTSET11_SETn2_Pos                             2
#define SCT_OUTPUTSET11_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn2_Pos)
#define SCT_OUTPUTSET11_SETn3_Pos                             3
#define SCT_OUTPUTSET11_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn3_Pos)
#define SCT_OUTPUTSET11_SETn4_Pos                             4
#define SCT_OUTPUTSET11_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn4_Pos)
#define SCT_OUTPUTSET11_SETn5_Pos                             5
#define SCT_OUTPUTSET11_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn5_Pos)
#define SCT_OUTPUTSET11_SETn6_Pos                             6
#define SCT_OUTPUTSET11_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn6_Pos)
#define SCT_OUTPUTSET11_SETn7_Pos                             7
#define SCT_OUTPUTSET11_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn7_Pos)
#define SCT_OUTPUTSET11_SETn8_Pos                             8
#define SCT_OUTPUTSET11_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn8_Pos)
#define SCT_OUTPUTSET11_SETn9_Pos                             9
#define SCT_OUTPUTSET11_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET11_SETn9_Pos)
#define SCT_OUTPUTSET11_SETn10_Pos                            10
#define SCT_OUTPUTSET11_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn10_Pos)
#define SCT_OUTPUTSET11_SETn11_Pos                            11
#define SCT_OUTPUTSET11_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn11_Pos)
#define SCT_OUTPUTSET11_SETn12_Pos                            12
#define SCT_OUTPUTSET11_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn12_Pos)
#define SCT_OUTPUTSET11_SETn13_Pos                            13
#define SCT_OUTPUTSET11_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn13_Pos)
#define SCT_OUTPUTSET11_SETn14_Pos                            14
#define SCT_OUTPUTSET11_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn14_Pos)
#define SCT_OUTPUTSET11_SETn15_Pos                            15
#define SCT_OUTPUTSET11_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET11_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR11  ----------------------------------------
#define SCT_OUTPUTCLR11_CLRn0_Pos                             0
#define SCT_OUTPUTCLR11_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos)
#define SCT_OUTPUTCLR11_CLRn1_Pos                             1
#define SCT_OUTPUTCLR11_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos)
#define SCT_OUTPUTCLR11_CLRn2_Pos                             2
#define SCT_OUTPUTCLR11_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos)
#define SCT_OUTPUTCLR11_CLRn3_Pos                             3
#define SCT_OUTPUTCLR11_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos)
#define SCT_OUTPUTCLR11_CLRn4_Pos                             4
#define SCT_OUTPUTCLR11_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos)
#define SCT_OUTPUTCLR11_CLRn5_Pos                             5
#define SCT_OUTPUTCLR11_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos)
#define SCT_OUTPUTCLR11_CLRn6_Pos                             6
#define SCT_OUTPUTCLR11_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos)
#define SCT_OUTPUTCLR11_CLRn7_Pos                             7
#define SCT_OUTPUTCLR11_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos)
#define SCT_OUTPUTCLR11_CLRn8_Pos                             8
#define SCT_OUTPUTCLR11_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos)
#define SCT_OUTPUTCLR11_CLRn9_Pos                             9
#define SCT_OUTPUTCLR11_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos)
#define SCT_OUTPUTCLR11_CLRn10_Pos                            10
#define SCT_OUTPUTCLR11_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos)
#define SCT_OUTPUTCLR11_CLRn11_Pos                            11
#define SCT_OUTPUTCLR11_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos)
#define SCT_OUTPUTCLR11_CLRn12_Pos                            12
#define SCT_OUTPUTCLR11_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos)
#define SCT_OUTPUTCLR11_CLRn13_Pos                            13
#define SCT_OUTPUTCLR11_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos)
#define SCT_OUTPUTCLR11_CLRn14_Pos                            14
#define SCT_OUTPUTCLR11_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos)
#define SCT_OUTPUTCLR11_CLRn15_Pos                            15
#define SCT_OUTPUTCLR11_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET12  ----------------------------------------
#define SCT_OUTPUTSET12_SETn0_Pos                             0
#define SCT_OUTPUTSET12_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn0_Pos)
#define SCT_OUTPUTSET12_SETn1_Pos                             1
#define SCT_OUTPUTSET12_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn1_Pos)
#define SCT_OUTPUTSET12_SETn2_Pos                             2
#define SCT_OUTPUTSET12_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn2_Pos)
#define SCT_OUTPUTSET12_SETn3_Pos                             3
#define SCT_OUTPUTSET12_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn3_Pos)
#define SCT_OUTPUTSET12_SETn4_Pos                             4
#define SCT_OUTPUTSET12_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn4_Pos)
#define SCT_OUTPUTSET12_SETn5_Pos                             5
#define SCT_OUTPUTSET12_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn5_Pos)
#define SCT_OUTPUTSET12_SETn6_Pos                             6
#define SCT_OUTPUTSET12_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn6_Pos)
#define SCT_OUTPUTSET12_SETn7_Pos                             7
#define SCT_OUTPUTSET12_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn7_Pos)
#define SCT_OUTPUTSET12_SETn8_Pos                             8
#define SCT_OUTPUTSET12_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn8_Pos)
#define SCT_OUTPUTSET12_SETn9_Pos                             9
#define SCT_OUTPUTSET12_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET12_SETn9_Pos)
#define SCT_OUTPUTSET12_SETn10_Pos                            10
#define SCT_OUTPUTSET12_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn10_Pos)
#define SCT_OUTPUTSET12_SETn11_Pos                            11
#define SCT_OUTPUTSET12_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn11_Pos)
#define SCT_OUTPUTSET12_SETn12_Pos                            12
#define SCT_OUTPUTSET12_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn12_Pos)
#define SCT_OUTPUTSET12_SETn13_Pos                            13
#define SCT_OUTPUTSET12_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn13_Pos)
#define SCT_OUTPUTSET12_SETn14_Pos                            14
#define SCT_OUTPUTSET12_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn14_Pos)
#define SCT_OUTPUTSET12_SETn15_Pos                            15
#define SCT_OUTPUTSET12_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET12_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR12  ----------------------------------------
#define SCT_OUTPUTCLR12_CLRn0_Pos                             0
#define SCT_OUTPUTCLR12_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos)
#define SCT_OUTPUTCLR12_CLRn1_Pos                             1
#define SCT_OUTPUTCLR12_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos)
#define SCT_OUTPUTCLR12_CLRn2_Pos                             2
#define SCT_OUTPUTCLR12_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos)
#define SCT_OUTPUTCLR12_CLRn3_Pos                             3
#define SCT_OUTPUTCLR12_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos)
#define SCT_OUTPUTCLR12_CLRn4_Pos                             4
#define SCT_OUTPUTCLR12_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos)
#define SCT_OUTPUTCLR12_CLRn5_Pos                             5
#define SCT_OUTPUTCLR12_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos)
#define SCT_OUTPUTCLR12_CLRn6_Pos                             6
#define SCT_OUTPUTCLR12_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos)
#define SCT_OUTPUTCLR12_CLRn7_Pos                             7
#define SCT_OUTPUTCLR12_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos)
#define SCT_OUTPUTCLR12_CLRn8_Pos                             8
#define SCT_OUTPUTCLR12_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos)
#define SCT_OUTPUTCLR12_CLRn9_Pos                             9
#define SCT_OUTPUTCLR12_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos)
#define SCT_OUTPUTCLR12_CLRn10_Pos                            10
#define SCT_OUTPUTCLR12_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos)
#define SCT_OUTPUTCLR12_CLRn11_Pos                            11
#define SCT_OUTPUTCLR12_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos)
#define SCT_OUTPUTCLR12_CLRn12_Pos                            12
#define SCT_OUTPUTCLR12_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos)
#define SCT_OUTPUTCLR12_CLRn13_Pos                            13
#define SCT_OUTPUTCLR12_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos)
#define SCT_OUTPUTCLR12_CLRn14_Pos                            14
#define SCT_OUTPUTCLR12_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos)
#define SCT_OUTPUTCLR12_CLRn15_Pos                            15
#define SCT_OUTPUTCLR12_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET13  ----------------------------------------
#define SCT_OUTPUTSET13_SETn0_Pos                             0
#define SCT_OUTPUTSET13_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn0_Pos)
#define SCT_OUTPUTSET13_SETn1_Pos                             1
#define SCT_OUTPUTSET13_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn1_Pos)
#define SCT_OUTPUTSET13_SETn2_Pos                             2
#define SCT_OUTPUTSET13_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn2_Pos)
#define SCT_OUTPUTSET13_SETn3_Pos                             3
#define SCT_OUTPUTSET13_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn3_Pos)
#define SCT_OUTPUTSET13_SETn4_Pos                             4
#define SCT_OUTPUTSET13_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn4_Pos)
#define SCT_OUTPUTSET13_SETn5_Pos                             5
#define SCT_OUTPUTSET13_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn5_Pos)
#define SCT_OUTPUTSET13_SETn6_Pos                             6
#define SCT_OUTPUTSET13_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn6_Pos)
#define SCT_OUTPUTSET13_SETn7_Pos                             7
#define SCT_OUTPUTSET13_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn7_Pos)
#define SCT_OUTPUTSET13_SETn8_Pos                             8
#define SCT_OUTPUTSET13_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn8_Pos)
#define SCT_OUTPUTSET13_SETn9_Pos                             9
#define SCT_OUTPUTSET13_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET13_SETn9_Pos)
#define SCT_OUTPUTSET13_SETn10_Pos                            10
#define SCT_OUTPUTSET13_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn10_Pos)
#define SCT_OUTPUTSET13_SETn11_Pos                            11
#define SCT_OUTPUTSET13_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn11_Pos)
#define SCT_OUTPUTSET13_SETn12_Pos                            12
#define SCT_OUTPUTSET13_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn12_Pos)
#define SCT_OUTPUTSET13_SETn13_Pos                            13
#define SCT_OUTPUTSET13_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn13_Pos)
#define SCT_OUTPUTSET13_SETn14_Pos                            14
#define SCT_OUTPUTSET13_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn14_Pos)
#define SCT_OUTPUTSET13_SETn15_Pos                            15
#define SCT_OUTPUTSET13_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET13_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR13  ----------------------------------------
#define SCT_OUTPUTCLR13_CLRn0_Pos                             0
#define SCT_OUTPUTCLR13_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos)
#define SCT_OUTPUTCLR13_CLRn1_Pos                             1
#define SCT_OUTPUTCLR13_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos)
#define SCT_OUTPUTCLR13_CLRn2_Pos                             2
#define SCT_OUTPUTCLR13_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos)
#define SCT_OUTPUTCLR13_CLRn3_Pos                             3
#define SCT_OUTPUTCLR13_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos)
#define SCT_OUTPUTCLR13_CLRn4_Pos                             4
#define SCT_OUTPUTCLR13_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos)
#define SCT_OUTPUTCLR13_CLRn5_Pos                             5
#define SCT_OUTPUTCLR13_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos)
#define SCT_OUTPUTCLR13_CLRn6_Pos                             6
#define SCT_OUTPUTCLR13_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos)
#define SCT_OUTPUTCLR13_CLRn7_Pos                             7
#define SCT_OUTPUTCLR13_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos)
#define SCT_OUTPUTCLR13_CLRn8_Pos                             8
#define SCT_OUTPUTCLR13_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos)
#define SCT_OUTPUTCLR13_CLRn9_Pos                             9
#define SCT_OUTPUTCLR13_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos)
#define SCT_OUTPUTCLR13_CLRn10_Pos                            10
#define SCT_OUTPUTCLR13_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos)
#define SCT_OUTPUTCLR13_CLRn11_Pos                            11
#define SCT_OUTPUTCLR13_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos)
#define SCT_OUTPUTCLR13_CLRn12_Pos                            12
#define SCT_OUTPUTCLR13_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos)
#define SCT_OUTPUTCLR13_CLRn13_Pos                            13
#define SCT_OUTPUTCLR13_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos)
#define SCT_OUTPUTCLR13_CLRn14_Pos                            14
#define SCT_OUTPUTCLR13_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos)
#define SCT_OUTPUTCLR13_CLRn15_Pos                            15
#define SCT_OUTPUTCLR13_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET14  ----------------------------------------
#define SCT_OUTPUTSET14_SETn0_Pos                             0
#define SCT_OUTPUTSET14_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn0_Pos)
#define SCT_OUTPUTSET14_SETn1_Pos                             1
#define SCT_OUTPUTSET14_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn1_Pos)
#define SCT_OUTPUTSET14_SETn2_Pos                             2
#define SCT_OUTPUTSET14_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn2_Pos)
#define SCT_OUTPUTSET14_SETn3_Pos                             3
#define SCT_OUTPUTSET14_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn3_Pos)
#define SCT_OUTPUTSET14_SETn4_Pos                             4
#define SCT_OUTPUTSET14_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn4_Pos)
#define SCT_OUTPUTSET14_SETn5_Pos                             5
#define SCT_OUTPUTSET14_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn5_Pos)
#define SCT_OUTPUTSET14_SETn6_Pos                             6
#define SCT_OUTPUTSET14_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn6_Pos)
#define SCT_OUTPUTSET14_SETn7_Pos                             7
#define SCT_OUTPUTSET14_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn7_Pos)
#define SCT_OUTPUTSET14_SETn8_Pos                             8
#define SCT_OUTPUTSET14_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn8_Pos)
#define SCT_OUTPUTSET14_SETn9_Pos                             9
#define SCT_OUTPUTSET14_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET14_SETn9_Pos)
#define SCT_OUTPUTSET14_SETn10_Pos                            10
#define SCT_OUTPUTSET14_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn10_Pos)
#define SCT_OUTPUTSET14_SETn11_Pos                            11
#define SCT_OUTPUTSET14_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn11_Pos)
#define SCT_OUTPUTSET14_SETn12_Pos                            12
#define SCT_OUTPUTSET14_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn12_Pos)
#define SCT_OUTPUTSET14_SETn13_Pos                            13
#define SCT_OUTPUTSET14_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn13_Pos)
#define SCT_OUTPUTSET14_SETn14_Pos                            14
#define SCT_OUTPUTSET14_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn14_Pos)
#define SCT_OUTPUTSET14_SETn15_Pos                            15
#define SCT_OUTPUTSET14_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET14_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR14  ----------------------------------------
#define SCT_OUTPUTCLR14_CLRn0_Pos                             0
#define SCT_OUTPUTCLR14_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos)
#define SCT_OUTPUTCLR14_CLRn1_Pos                             1
#define SCT_OUTPUTCLR14_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos)
#define SCT_OUTPUTCLR14_CLRn2_Pos                             2
#define SCT_OUTPUTCLR14_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos)
#define SCT_OUTPUTCLR14_CLRn3_Pos                             3
#define SCT_OUTPUTCLR14_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos)
#define SCT_OUTPUTCLR14_CLRn4_Pos                             4
#define SCT_OUTPUTCLR14_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos)
#define SCT_OUTPUTCLR14_CLRn5_Pos                             5
#define SCT_OUTPUTCLR14_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos)
#define SCT_OUTPUTCLR14_CLRn6_Pos                             6
#define SCT_OUTPUTCLR14_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos)
#define SCT_OUTPUTCLR14_CLRn7_Pos                             7
#define SCT_OUTPUTCLR14_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos)
#define SCT_OUTPUTCLR14_CLRn8_Pos                             8
#define SCT_OUTPUTCLR14_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos)
#define SCT_OUTPUTCLR14_CLRn9_Pos                             9
#define SCT_OUTPUTCLR14_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos)
#define SCT_OUTPUTCLR14_CLRn10_Pos                            10
#define SCT_OUTPUTCLR14_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos)
#define SCT_OUTPUTCLR14_CLRn11_Pos                            11
#define SCT_OUTPUTCLR14_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos)
#define SCT_OUTPUTCLR14_CLRn12_Pos                            12
#define SCT_OUTPUTCLR14_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos)
#define SCT_OUTPUTCLR14_CLRn13_Pos                            13
#define SCT_OUTPUTCLR14_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos)
#define SCT_OUTPUTCLR14_CLRn14_Pos                            14
#define SCT_OUTPUTCLR14_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos)
#define SCT_OUTPUTCLR14_CLRn15_Pos                            15
#define SCT_OUTPUTCLR14_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos)

// -------------------------------------  SCT_OUTPUTSET15  ----------------------------------------
#define SCT_OUTPUTSET15_SETn0_Pos                             0
#define SCT_OUTPUTSET15_SETn0_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn0_Pos)
#define SCT_OUTPUTSET15_SETn1_Pos                             1
#define SCT_OUTPUTSET15_SETn1_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn1_Pos)
#define SCT_OUTPUTSET15_SETn2_Pos                             2
#define SCT_OUTPUTSET15_SETn2_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn2_Pos)
#define SCT_OUTPUTSET15_SETn3_Pos                             3
#define SCT_OUTPUTSET15_SETn3_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn3_Pos)
#define SCT_OUTPUTSET15_SETn4_Pos                             4
#define SCT_OUTPUTSET15_SETn4_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn4_Pos)
#define SCT_OUTPUTSET15_SETn5_Pos                             5
#define SCT_OUTPUTSET15_SETn5_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn5_Pos)
#define SCT_OUTPUTSET15_SETn6_Pos                             6
#define SCT_OUTPUTSET15_SETn6_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn6_Pos)
#define SCT_OUTPUTSET15_SETn7_Pos                             7
#define SCT_OUTPUTSET15_SETn7_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn7_Pos)
#define SCT_OUTPUTSET15_SETn8_Pos                             8
#define SCT_OUTPUTSET15_SETn8_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn8_Pos)
#define SCT_OUTPUTSET15_SETn9_Pos                             9
#define SCT_OUTPUTSET15_SETn9_Msk                             (0x01UL << SCT_OUTPUTSET15_SETn9_Pos)
#define SCT_OUTPUTSET15_SETn10_Pos                            10
#define SCT_OUTPUTSET15_SETn10_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn10_Pos)
#define SCT_OUTPUTSET15_SETn11_Pos                            11
#define SCT_OUTPUTSET15_SETn11_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn11_Pos)
#define SCT_OUTPUTSET15_SETn12_Pos                            12
#define SCT_OUTPUTSET15_SETn12_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn12_Pos)
#define SCT_OUTPUTSET15_SETn13_Pos                            13
#define SCT_OUTPUTSET15_SETn13_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn13_Pos)
#define SCT_OUTPUTSET15_SETn14_Pos                            14
#define SCT_OUTPUTSET15_SETn14_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn14_Pos)
#define SCT_OUTPUTSET15_SETn15_Pos                            15
#define SCT_OUTPUTSET15_SETn15_Msk                            (0x01UL << SCT_OUTPUTSET15_SETn15_Pos)

// -------------------------------------  SCT_OUTPUTCLR15  ----------------------------------------
#define SCT_OUTPUTCLR15_CLRn0_Pos                             0
#define SCT_OUTPUTCLR15_CLRn0_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos)
#define SCT_OUTPUTCLR15_CLRn1_Pos                             1
#define SCT_OUTPUTCLR15_CLRn1_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos)
#define SCT_OUTPUTCLR15_CLRn2_Pos                             2
#define SCT_OUTPUTCLR15_CLRn2_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos)
#define SCT_OUTPUTCLR15_CLRn3_Pos                             3
#define SCT_OUTPUTCLR15_CLRn3_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos)
#define SCT_OUTPUTCLR15_CLRn4_Pos                             4
#define SCT_OUTPUTCLR15_CLRn4_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos)
#define SCT_OUTPUTCLR15_CLRn5_Pos                             5
#define SCT_OUTPUTCLR15_CLRn5_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos)
#define SCT_OUTPUTCLR15_CLRn6_Pos                             6
#define SCT_OUTPUTCLR15_CLRn6_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos)
#define SCT_OUTPUTCLR15_CLRn7_Pos                             7
#define SCT_OUTPUTCLR15_CLRn7_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos)
#define SCT_OUTPUTCLR15_CLRn8_Pos                             8
#define SCT_OUTPUTCLR15_CLRn8_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos)
#define SCT_OUTPUTCLR15_CLRn9_Pos                             9
#define SCT_OUTPUTCLR15_CLRn9_Msk                             (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos)
#define SCT_OUTPUTCLR15_CLRn10_Pos                            10
#define SCT_OUTPUTCLR15_CLRn10_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos)
#define SCT_OUTPUTCLR15_CLRn11_Pos                            11
#define SCT_OUTPUTCLR15_CLRn11_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos)
#define SCT_OUTPUTCLR15_CLRn12_Pos                            12
#define SCT_OUTPUTCLR15_CLRn12_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos)
#define SCT_OUTPUTCLR15_CLRn13_Pos                            13
#define SCT_OUTPUTCLR15_CLRn13_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos)
#define SCT_OUTPUTCLR15_CLRn14_Pos                            14
#define SCT_OUTPUTCLR15_CLRn14_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos)
#define SCT_OUTPUTCLR15_CLRn15_Pos                            15
#define SCT_OUTPUTCLR15_CLRn15_Msk                            (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 GPDMA Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  GPDMA_INTSTAT  -----------------------------------------
#define GPDMA_INTSTAT_INTSTAT0_Pos                            0
#define GPDMA_INTSTAT_INTSTAT0_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos)
#define GPDMA_INTSTAT_INTSTAT1_Pos                            1
#define GPDMA_INTSTAT_INTSTAT1_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos)
#define GPDMA_INTSTAT_INTSTAT2_Pos                            2
#define GPDMA_INTSTAT_INTSTAT2_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos)
#define GPDMA_INTSTAT_INTSTAT3_Pos                            3
#define GPDMA_INTSTAT_INTSTAT3_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos)
#define GPDMA_INTSTAT_INTSTAT4_Pos                            4
#define GPDMA_INTSTAT_INTSTAT4_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos)
#define GPDMA_INTSTAT_INTSTAT5_Pos                            5
#define GPDMA_INTSTAT_INTSTAT5_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos)
#define GPDMA_INTSTAT_INTSTAT6_Pos                            6
#define GPDMA_INTSTAT_INTSTAT6_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos)
#define GPDMA_INTSTAT_INTSTAT7_Pos                            7
#define GPDMA_INTSTAT_INTSTAT7_Msk                            (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos)

// -------------------------------------  GPDMA_INTTCSTAT  ----------------------------------------
#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos                        0
#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos                        1
#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos                        2
#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos                        3
#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos                        4
#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos                        5
#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos                        6
#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos)
#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos                        7
#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk                        (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos)

// ------------------------------------  GPDMA_INTTCCLEAR  ----------------------------------------
#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos                      0
#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos                      1
#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos                      2
#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos                      3
#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos                      4
#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos                      5
#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos                      6
#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos)
#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos                      7
#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk                      (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos)

// ------------------------------------  GPDMA_INTERRSTAT  ----------------------------------------
#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos                      0
#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos                      1
#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos                      2
#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos                      3
#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos                      4
#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos                      5
#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos                      6
#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos)
#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos                      7
#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk                      (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos)

// -------------------------------------  GPDMA_INTERRCLR  ----------------------------------------
#define GPDMA_INTERRCLR_INTERRCLR0_Pos                        0
#define GPDMA_INTERRCLR_INTERRCLR0_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos)
#define GPDMA_INTERRCLR_INTERRCLR1_Pos                        1
#define GPDMA_INTERRCLR_INTERRCLR1_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos)
#define GPDMA_INTERRCLR_INTERRCLR2_Pos                        2
#define GPDMA_INTERRCLR_INTERRCLR2_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos)
#define GPDMA_INTERRCLR_INTERRCLR3_Pos                        3
#define GPDMA_INTERRCLR_INTERRCLR3_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos)
#define GPDMA_INTERRCLR_INTERRCLR4_Pos                        4
#define GPDMA_INTERRCLR_INTERRCLR4_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos)
#define GPDMA_INTERRCLR_INTERRCLR5_Pos                        5
#define GPDMA_INTERRCLR_INTERRCLR5_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos)
#define GPDMA_INTERRCLR_INTERRCLR6_Pos                        6
#define GPDMA_INTERRCLR_INTERRCLR6_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos)
#define GPDMA_INTERRCLR_INTERRCLR7_Pos                        7
#define GPDMA_INTERRCLR_INTERRCLR7_Msk                        (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos)

// -----------------------------------  GPDMA_RAWINTTCSTAT  ---------------------------------------
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos                  0
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos                  1
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos                  2
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos                  3
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos                  4
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos                  5
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos                  6
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos                  7
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk                  (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos)

// -----------------------------------  GPDMA_RAWINTERRSTAT  --------------------------------------
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos                0
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos                1
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos                2
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos                3
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos                4
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos                5
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos                6
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos                7
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk                (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos)

// -------------------------------------  GPDMA_ENBLDCHNS  ----------------------------------------
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos                  0
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos                  1
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos                  2
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos                  3
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos                  4
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos                  5
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos                  6
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos                  7
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk                  (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos)

// -------------------------------------  GPDMA_SOFTBREQ  -----------------------------------------
#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos                          0
#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos                          1
#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos                          2
#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos                          3
#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos                          4
#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos                          5
#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos                          6
#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos                          7
#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos                          8
#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos                          9
#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk                          (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos                         10
#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos                         11
#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos                         12
#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos                         13
#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos                         14
#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos)
#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos                         15
#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk                         (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos)

// -------------------------------------  GPDMA_SOFTSREQ  -----------------------------------------
#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos                          0
#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos                          1
#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos                          2
#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos                          3
#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos                          4
#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos                          5
#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos                          6
#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos                          7
#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos                          8
#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos                          9
#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk                          (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos                         10
#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos                         11
#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos                         12
#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos                         13
#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos                         14
#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos)
#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos                         15
#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk                         (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos)

// -------------------------------------  GPDMA_SOFTLBREQ  ----------------------------------------
#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos                        0
#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos                        1
#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos                        2
#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos                        3
#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos                        4
#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos                        5
#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos                        6
#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos                        7
#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos                        8
#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos                        9
#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk                        (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos                       10
#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos                       11
#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos                       12
#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos                       13
#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos                       14
#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos)
#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos                       15
#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk                       (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos)

// -------------------------------------  GPDMA_SOFTLSREQ  ----------------------------------------
#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos                        0
#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos                        1
#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos                        2
#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos                        3
#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos                        4
#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos                        5
#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos                        6
#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos                        7
#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos                        8
#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos                        9
#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk                        (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos                       10
#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos                       11
#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos                       12
#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos                       13
#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos                       14
#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos)
#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos                       15
#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk                       (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos)

// --------------------------------------  GPDMA_CONFIG  ------------------------------------------
#define GPDMA_CONFIG_E_Pos                                    0
#define GPDMA_CONFIG_E_Msk                                    (0x01UL << GPDMA_CONFIG_E_Pos)
#define GPDMA_CONFIG_M0_Pos                                   1
#define GPDMA_CONFIG_M0_Msk                                   (0x01UL << GPDMA_CONFIG_M0_Pos)
#define GPDMA_CONFIG_M1_Pos                                   2
#define GPDMA_CONFIG_M1_Msk                                   (0x01UL << GPDMA_CONFIG_M1_Pos)

// ---------------------------------------  GPDMA_SYNC  -------------------------------------------
#define GPDMA_SYNC_DMACSYNC0_Pos                              0
#define GPDMA_SYNC_DMACSYNC0_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos)
#define GPDMA_SYNC_DMACSYNC1_Pos                              1
#define GPDMA_SYNC_DMACSYNC1_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos)
#define GPDMA_SYNC_DMACSYNC2_Pos                              2
#define GPDMA_SYNC_DMACSYNC2_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos)
#define GPDMA_SYNC_DMACSYNC3_Pos                              3
#define GPDMA_SYNC_DMACSYNC3_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos)
#define GPDMA_SYNC_DMACSYNC4_Pos                              4
#define GPDMA_SYNC_DMACSYNC4_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos)
#define GPDMA_SYNC_DMACSYNC5_Pos                              5
#define GPDMA_SYNC_DMACSYNC5_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos)
#define GPDMA_SYNC_DMACSYNC6_Pos                              6
#define GPDMA_SYNC_DMACSYNC6_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos)
#define GPDMA_SYNC_DMACSYNC7_Pos                              7
#define GPDMA_SYNC_DMACSYNC7_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos)
#define GPDMA_SYNC_DMACSYNC8_Pos                              8
#define GPDMA_SYNC_DMACSYNC8_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos)
#define GPDMA_SYNC_DMACSYNC9_Pos                              9
#define GPDMA_SYNC_DMACSYNC9_Msk                              (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos)
#define GPDMA_SYNC_DMACSYNC10_Pos                             10
#define GPDMA_SYNC_DMACSYNC10_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos)
#define GPDMA_SYNC_DMACSYNC11_Pos                             11
#define GPDMA_SYNC_DMACSYNC11_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos)
#define GPDMA_SYNC_DMACSYNC12_Pos                             12
#define GPDMA_SYNC_DMACSYNC12_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos)
#define GPDMA_SYNC_DMACSYNC13_Pos                             13
#define GPDMA_SYNC_DMACSYNC13_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos)
#define GPDMA_SYNC_DMACSYNC14_Pos                             14
#define GPDMA_SYNC_DMACSYNC14_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos)
#define GPDMA_SYNC_DMACSYNC15_Pos                             15
#define GPDMA_SYNC_DMACSYNC15_Msk                             (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos)

// -------------------------------------  GPDMA_C0SRCADDR  ----------------------------------------
#define GPDMA_C0SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C0SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C0DESTADDR  ----------------------------------------
#define GPDMA_C0DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C0DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C0LLI  ------------------------------------------
#define GPDMA_C0LLI_LM_Pos                                    0
#define GPDMA_C0LLI_LM_Msk                                    (0x01UL << GPDMA_C0LLI_LM_Pos)
#define GPDMA_C0LLI_R_Pos                                     1
#define GPDMA_C0LLI_R_Msk                                     (0x01UL << GPDMA_C0LLI_R_Pos)
#define GPDMA_C0LLI_LLI_Pos                                   2
#define GPDMA_C0LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos)

// -------------------------------------  GPDMA_C0CONTROL  ----------------------------------------
#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C0CONTROL_SBSIZE_Pos                            12
#define GPDMA_C0CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos)
#define GPDMA_C0CONTROL_DBSIZE_Pos                            15
#define GPDMA_C0CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos)
#define GPDMA_C0CONTROL_SWIDTH_Pos                            18
#define GPDMA_C0CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos)
#define GPDMA_C0CONTROL_DWIDTH_Pos                            21
#define GPDMA_C0CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos)
#define GPDMA_C0CONTROL_S_Pos                                 24
#define GPDMA_C0CONTROL_S_Msk                                 (0x01UL << GPDMA_C0CONTROL_S_Pos)
#define GPDMA_C0CONTROL_D_Pos                                 25
#define GPDMA_C0CONTROL_D_Msk                                 (0x01UL << GPDMA_C0CONTROL_D_Pos)
#define GPDMA_C0CONTROL_SI_Pos                                26
#define GPDMA_C0CONTROL_SI_Msk                                (0x01UL << GPDMA_C0CONTROL_SI_Pos)
#define GPDMA_C0CONTROL_DI_Pos                                27
#define GPDMA_C0CONTROL_DI_Msk                                (0x01UL << GPDMA_C0CONTROL_DI_Pos)
#define GPDMA_C0CONTROL_PROT1_Pos                             28
#define GPDMA_C0CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT1_Pos)
#define GPDMA_C0CONTROL_PROT2_Pos                             29
#define GPDMA_C0CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT2_Pos)
#define GPDMA_C0CONTROL_PROT3_Pos                             30
#define GPDMA_C0CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C0CONTROL_PROT3_Pos)
#define GPDMA_C0CONTROL_I_Pos                                 31
#define GPDMA_C0CONTROL_I_Msk                                 (0x01UL << GPDMA_C0CONTROL_I_Pos)

// -------------------------------------  GPDMA_C0CONFIG  -----------------------------------------
#define GPDMA_C0CONFIG_E_Pos                                  0
#define GPDMA_C0CONFIG_E_Msk                                  (0x01UL << GPDMA_C0CONFIG_E_Pos)
#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C0CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C0CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C0CONFIG_IE_Pos                                 14
#define GPDMA_C0CONFIG_IE_Msk                                 (0x01UL << GPDMA_C0CONFIG_IE_Pos)
#define GPDMA_C0CONFIG_ITC_Pos                                15
#define GPDMA_C0CONFIG_ITC_Msk                                (0x01UL << GPDMA_C0CONFIG_ITC_Pos)
#define GPDMA_C0CONFIG_L_Pos                                  16
#define GPDMA_C0CONFIG_L_Msk                                  (0x01UL << GPDMA_C0CONFIG_L_Pos)
#define GPDMA_C0CONFIG_A_Pos                                  17
#define GPDMA_C0CONFIG_A_Msk                                  (0x01UL << GPDMA_C0CONFIG_A_Pos)
#define GPDMA_C0CONFIG_H_Pos                                  18
#define GPDMA_C0CONFIG_H_Msk                                  (0x01UL << GPDMA_C0CONFIG_H_Pos)

// -------------------------------------  GPDMA_C1SRCADDR  ----------------------------------------
#define GPDMA_C1SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C1SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C1DESTADDR  ----------------------------------------
#define GPDMA_C1DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C1DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C1LLI  ------------------------------------------
#define GPDMA_C1LLI_LM_Pos                                    0
#define GPDMA_C1LLI_LM_Msk                                    (0x01UL << GPDMA_C1LLI_LM_Pos)
#define GPDMA_C1LLI_R_Pos                                     1
#define GPDMA_C1LLI_R_Msk                                     (0x01UL << GPDMA_C1LLI_R_Pos)
#define GPDMA_C1LLI_LLI_Pos                                   2
#define GPDMA_C1LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos)

// -------------------------------------  GPDMA_C1CONTROL  ----------------------------------------
#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C1CONTROL_SBSIZE_Pos                            12
#define GPDMA_C1CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos)
#define GPDMA_C1CONTROL_DBSIZE_Pos                            15
#define GPDMA_C1CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos)
#define GPDMA_C1CONTROL_SWIDTH_Pos                            18
#define GPDMA_C1CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos)
#define GPDMA_C1CONTROL_DWIDTH_Pos                            21
#define GPDMA_C1CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos)
#define GPDMA_C1CONTROL_S_Pos                                 24
#define GPDMA_C1CONTROL_S_Msk                                 (0x01UL << GPDMA_C1CONTROL_S_Pos)
#define GPDMA_C1CONTROL_D_Pos                                 25
#define GPDMA_C1CONTROL_D_Msk                                 (0x01UL << GPDMA_C1CONTROL_D_Pos)
#define GPDMA_C1CONTROL_SI_Pos                                26
#define GPDMA_C1CONTROL_SI_Msk                                (0x01UL << GPDMA_C1CONTROL_SI_Pos)
#define GPDMA_C1CONTROL_DI_Pos                                27
#define GPDMA_C1CONTROL_DI_Msk                                (0x01UL << GPDMA_C1CONTROL_DI_Pos)
#define GPDMA_C1CONTROL_PROT1_Pos                             28
#define GPDMA_C1CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT1_Pos)
#define GPDMA_C1CONTROL_PROT2_Pos                             29
#define GPDMA_C1CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT2_Pos)
#define GPDMA_C1CONTROL_PROT3_Pos                             30
#define GPDMA_C1CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C1CONTROL_PROT3_Pos)
#define GPDMA_C1CONTROL_I_Pos                                 31
#define GPDMA_C1CONTROL_I_Msk                                 (0x01UL << GPDMA_C1CONTROL_I_Pos)

// -------------------------------------  GPDMA_C1CONFIG  -----------------------------------------
#define GPDMA_C1CONFIG_E_Pos                                  0
#define GPDMA_C1CONFIG_E_Msk                                  (0x01UL << GPDMA_C1CONFIG_E_Pos)
#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C1CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C1CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C1CONFIG_IE_Pos                                 14
#define GPDMA_C1CONFIG_IE_Msk                                 (0x01UL << GPDMA_C1CONFIG_IE_Pos)
#define GPDMA_C1CONFIG_ITC_Pos                                15
#define GPDMA_C1CONFIG_ITC_Msk                                (0x01UL << GPDMA_C1CONFIG_ITC_Pos)
#define GPDMA_C1CONFIG_L_Pos                                  16
#define GPDMA_C1CONFIG_L_Msk                                  (0x01UL << GPDMA_C1CONFIG_L_Pos)
#define GPDMA_C1CONFIG_A_Pos                                  17
#define GPDMA_C1CONFIG_A_Msk                                  (0x01UL << GPDMA_C1CONFIG_A_Pos)
#define GPDMA_C1CONFIG_H_Pos                                  18
#define GPDMA_C1CONFIG_H_Msk                                  (0x01UL << GPDMA_C1CONFIG_H_Pos)

// -------------------------------------  GPDMA_C2SRCADDR  ----------------------------------------
#define GPDMA_C2SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C2SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C2DESTADDR  ----------------------------------------
#define GPDMA_C2DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C2DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C2LLI  ------------------------------------------
#define GPDMA_C2LLI_LM_Pos                                    0
#define GPDMA_C2LLI_LM_Msk                                    (0x01UL << GPDMA_C2LLI_LM_Pos)
#define GPDMA_C2LLI_R_Pos                                     1
#define GPDMA_C2LLI_R_Msk                                     (0x01UL << GPDMA_C2LLI_R_Pos)
#define GPDMA_C2LLI_LLI_Pos                                   2
#define GPDMA_C2LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos)

// -------------------------------------  GPDMA_C2CONTROL  ----------------------------------------
#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C2CONTROL_SBSIZE_Pos                            12
#define GPDMA_C2CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos)
#define GPDMA_C2CONTROL_DBSIZE_Pos                            15
#define GPDMA_C2CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos)
#define GPDMA_C2CONTROL_SWIDTH_Pos                            18
#define GPDMA_C2CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos)
#define GPDMA_C2CONTROL_DWIDTH_Pos                            21
#define GPDMA_C2CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos)
#define GPDMA_C2CONTROL_S_Pos                                 24
#define GPDMA_C2CONTROL_S_Msk                                 (0x01UL << GPDMA_C2CONTROL_S_Pos)
#define GPDMA_C2CONTROL_D_Pos                                 25
#define GPDMA_C2CONTROL_D_Msk                                 (0x01UL << GPDMA_C2CONTROL_D_Pos)
#define GPDMA_C2CONTROL_SI_Pos                                26
#define GPDMA_C2CONTROL_SI_Msk                                (0x01UL << GPDMA_C2CONTROL_SI_Pos)
#define GPDMA_C2CONTROL_DI_Pos                                27
#define GPDMA_C2CONTROL_DI_Msk                                (0x01UL << GPDMA_C2CONTROL_DI_Pos)
#define GPDMA_C2CONTROL_PROT1_Pos                             28
#define GPDMA_C2CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT1_Pos)
#define GPDMA_C2CONTROL_PROT2_Pos                             29
#define GPDMA_C2CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT2_Pos)
#define GPDMA_C2CONTROL_PROT3_Pos                             30
#define GPDMA_C2CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C2CONTROL_PROT3_Pos)
#define GPDMA_C2CONTROL_I_Pos                                 31
#define GPDMA_C2CONTROL_I_Msk                                 (0x01UL << GPDMA_C2CONTROL_I_Pos)

// -------------------------------------  GPDMA_C2CONFIG  -----------------------------------------
#define GPDMA_C2CONFIG_E_Pos                                  0
#define GPDMA_C2CONFIG_E_Msk                                  (0x01UL << GPDMA_C2CONFIG_E_Pos)
#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C2CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C2CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C2CONFIG_IE_Pos                                 14
#define GPDMA_C2CONFIG_IE_Msk                                 (0x01UL << GPDMA_C2CONFIG_IE_Pos)
#define GPDMA_C2CONFIG_ITC_Pos                                15
#define GPDMA_C2CONFIG_ITC_Msk                                (0x01UL << GPDMA_C2CONFIG_ITC_Pos)
#define GPDMA_C2CONFIG_L_Pos                                  16
#define GPDMA_C2CONFIG_L_Msk                                  (0x01UL << GPDMA_C2CONFIG_L_Pos)
#define GPDMA_C2CONFIG_A_Pos                                  17
#define GPDMA_C2CONFIG_A_Msk                                  (0x01UL << GPDMA_C2CONFIG_A_Pos)
#define GPDMA_C2CONFIG_H_Pos                                  18
#define GPDMA_C2CONFIG_H_Msk                                  (0x01UL << GPDMA_C2CONFIG_H_Pos)

// -------------------------------------  GPDMA_C3SRCADDR  ----------------------------------------
#define GPDMA_C3SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C3SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C3DESTADDR  ----------------------------------------
#define GPDMA_C3DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C3DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C3LLI  ------------------------------------------
#define GPDMA_C3LLI_LM_Pos                                    0
#define GPDMA_C3LLI_LM_Msk                                    (0x01UL << GPDMA_C3LLI_LM_Pos)
#define GPDMA_C3LLI_R_Pos                                     1
#define GPDMA_C3LLI_R_Msk                                     (0x01UL << GPDMA_C3LLI_R_Pos)
#define GPDMA_C3LLI_LLI_Pos                                   2
#define GPDMA_C3LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos)

// -------------------------------------  GPDMA_C3CONTROL  ----------------------------------------
#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C3CONTROL_SBSIZE_Pos                            12
#define GPDMA_C3CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos)
#define GPDMA_C3CONTROL_DBSIZE_Pos                            15
#define GPDMA_C3CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos)
#define GPDMA_C3CONTROL_SWIDTH_Pos                            18
#define GPDMA_C3CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos)
#define GPDMA_C3CONTROL_DWIDTH_Pos                            21
#define GPDMA_C3CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos)
#define GPDMA_C3CONTROL_S_Pos                                 24
#define GPDMA_C3CONTROL_S_Msk                                 (0x01UL << GPDMA_C3CONTROL_S_Pos)
#define GPDMA_C3CONTROL_D_Pos                                 25
#define GPDMA_C3CONTROL_D_Msk                                 (0x01UL << GPDMA_C3CONTROL_D_Pos)
#define GPDMA_C3CONTROL_SI_Pos                                26
#define GPDMA_C3CONTROL_SI_Msk                                (0x01UL << GPDMA_C3CONTROL_SI_Pos)
#define GPDMA_C3CONTROL_DI_Pos                                27
#define GPDMA_C3CONTROL_DI_Msk                                (0x01UL << GPDMA_C3CONTROL_DI_Pos)
#define GPDMA_C3CONTROL_PROT1_Pos                             28
#define GPDMA_C3CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT1_Pos)
#define GPDMA_C3CONTROL_PROT2_Pos                             29
#define GPDMA_C3CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT2_Pos)
#define GPDMA_C3CONTROL_PROT3_Pos                             30
#define GPDMA_C3CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C3CONTROL_PROT3_Pos)
#define GPDMA_C3CONTROL_I_Pos                                 31
#define GPDMA_C3CONTROL_I_Msk                                 (0x01UL << GPDMA_C3CONTROL_I_Pos)

// -------------------------------------  GPDMA_C3CONFIG  -----------------------------------------
#define GPDMA_C3CONFIG_E_Pos                                  0
#define GPDMA_C3CONFIG_E_Msk                                  (0x01UL << GPDMA_C3CONFIG_E_Pos)
#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C3CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C3CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C3CONFIG_IE_Pos                                 14
#define GPDMA_C3CONFIG_IE_Msk                                 (0x01UL << GPDMA_C3CONFIG_IE_Pos)
#define GPDMA_C3CONFIG_ITC_Pos                                15
#define GPDMA_C3CONFIG_ITC_Msk                                (0x01UL << GPDMA_C3CONFIG_ITC_Pos)
#define GPDMA_C3CONFIG_L_Pos                                  16
#define GPDMA_C3CONFIG_L_Msk                                  (0x01UL << GPDMA_C3CONFIG_L_Pos)
#define GPDMA_C3CONFIG_A_Pos                                  17
#define GPDMA_C3CONFIG_A_Msk                                  (0x01UL << GPDMA_C3CONFIG_A_Pos)
#define GPDMA_C3CONFIG_H_Pos                                  18
#define GPDMA_C3CONFIG_H_Msk                                  (0x01UL << GPDMA_C3CONFIG_H_Pos)

// -------------------------------------  GPDMA_C4SRCADDR  ----------------------------------------
#define GPDMA_C4SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C4SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C4DESTADDR  ----------------------------------------
#define GPDMA_C4DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C4DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C4LLI  ------------------------------------------
#define GPDMA_C4LLI_LM_Pos                                    0
#define GPDMA_C4LLI_LM_Msk                                    (0x01UL << GPDMA_C4LLI_LM_Pos)
#define GPDMA_C4LLI_R_Pos                                     1
#define GPDMA_C4LLI_R_Msk                                     (0x01UL << GPDMA_C4LLI_R_Pos)
#define GPDMA_C4LLI_LLI_Pos                                   2
#define GPDMA_C4LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos)

// -------------------------------------  GPDMA_C4CONTROL  ----------------------------------------
#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C4CONTROL_SBSIZE_Pos                            12
#define GPDMA_C4CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos)
#define GPDMA_C4CONTROL_DBSIZE_Pos                            15
#define GPDMA_C4CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos)
#define GPDMA_C4CONTROL_SWIDTH_Pos                            18
#define GPDMA_C4CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos)
#define GPDMA_C4CONTROL_DWIDTH_Pos                            21
#define GPDMA_C4CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos)
#define GPDMA_C4CONTROL_S_Pos                                 24
#define GPDMA_C4CONTROL_S_Msk                                 (0x01UL << GPDMA_C4CONTROL_S_Pos)
#define GPDMA_C4CONTROL_D_Pos                                 25
#define GPDMA_C4CONTROL_D_Msk                                 (0x01UL << GPDMA_C4CONTROL_D_Pos)
#define GPDMA_C4CONTROL_SI_Pos                                26
#define GPDMA_C4CONTROL_SI_Msk                                (0x01UL << GPDMA_C4CONTROL_SI_Pos)
#define GPDMA_C4CONTROL_DI_Pos                                27
#define GPDMA_C4CONTROL_DI_Msk                                (0x01UL << GPDMA_C4CONTROL_DI_Pos)
#define GPDMA_C4CONTROL_PROT1_Pos                             28
#define GPDMA_C4CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT1_Pos)
#define GPDMA_C4CONTROL_PROT2_Pos                             29
#define GPDMA_C4CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT2_Pos)
#define GPDMA_C4CONTROL_PROT3_Pos                             30
#define GPDMA_C4CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C4CONTROL_PROT3_Pos)
#define GPDMA_C4CONTROL_I_Pos                                 31
#define GPDMA_C4CONTROL_I_Msk                                 (0x01UL << GPDMA_C4CONTROL_I_Pos)

// -------------------------------------  GPDMA_C4CONFIG  -----------------------------------------
#define GPDMA_C4CONFIG_E_Pos                                  0
#define GPDMA_C4CONFIG_E_Msk                                  (0x01UL << GPDMA_C4CONFIG_E_Pos)
#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C4CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C4CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C4CONFIG_IE_Pos                                 14
#define GPDMA_C4CONFIG_IE_Msk                                 (0x01UL << GPDMA_C4CONFIG_IE_Pos)
#define GPDMA_C4CONFIG_ITC_Pos                                15
#define GPDMA_C4CONFIG_ITC_Msk                                (0x01UL << GPDMA_C4CONFIG_ITC_Pos)
#define GPDMA_C4CONFIG_L_Pos                                  16
#define GPDMA_C4CONFIG_L_Msk                                  (0x01UL << GPDMA_C4CONFIG_L_Pos)
#define GPDMA_C4CONFIG_A_Pos                                  17
#define GPDMA_C4CONFIG_A_Msk                                  (0x01UL << GPDMA_C4CONFIG_A_Pos)
#define GPDMA_C4CONFIG_H_Pos                                  18
#define GPDMA_C4CONFIG_H_Msk                                  (0x01UL << GPDMA_C4CONFIG_H_Pos)

// -------------------------------------  GPDMA_C5SRCADDR  ----------------------------------------
#define GPDMA_C5SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C5SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C5DESTADDR  ----------------------------------------
#define GPDMA_C5DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C5DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C5LLI  ------------------------------------------
#define GPDMA_C5LLI_LM_Pos                                    0
#define GPDMA_C5LLI_LM_Msk                                    (0x01UL << GPDMA_C5LLI_LM_Pos)
#define GPDMA_C5LLI_R_Pos                                     1
#define GPDMA_C5LLI_R_Msk                                     (0x01UL << GPDMA_C5LLI_R_Pos)
#define GPDMA_C5LLI_LLI_Pos                                   2
#define GPDMA_C5LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos)

// -------------------------------------  GPDMA_C5CONTROL  ----------------------------------------
#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C5CONTROL_SBSIZE_Pos                            12
#define GPDMA_C5CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos)
#define GPDMA_C5CONTROL_DBSIZE_Pos                            15
#define GPDMA_C5CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos)
#define GPDMA_C5CONTROL_SWIDTH_Pos                            18
#define GPDMA_C5CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos)
#define GPDMA_C5CONTROL_DWIDTH_Pos                            21
#define GPDMA_C5CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos)
#define GPDMA_C5CONTROL_S_Pos                                 24
#define GPDMA_C5CONTROL_S_Msk                                 (0x01UL << GPDMA_C5CONTROL_S_Pos)
#define GPDMA_C5CONTROL_D_Pos                                 25
#define GPDMA_C5CONTROL_D_Msk                                 (0x01UL << GPDMA_C5CONTROL_D_Pos)
#define GPDMA_C5CONTROL_SI_Pos                                26
#define GPDMA_C5CONTROL_SI_Msk                                (0x01UL << GPDMA_C5CONTROL_SI_Pos)
#define GPDMA_C5CONTROL_DI_Pos                                27
#define GPDMA_C5CONTROL_DI_Msk                                (0x01UL << GPDMA_C5CONTROL_DI_Pos)
#define GPDMA_C5CONTROL_PROT1_Pos                             28
#define GPDMA_C5CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT1_Pos)
#define GPDMA_C5CONTROL_PROT2_Pos                             29
#define GPDMA_C5CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT2_Pos)
#define GPDMA_C5CONTROL_PROT3_Pos                             30
#define GPDMA_C5CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C5CONTROL_PROT3_Pos)
#define GPDMA_C5CONTROL_I_Pos                                 31
#define GPDMA_C5CONTROL_I_Msk                                 (0x01UL << GPDMA_C5CONTROL_I_Pos)

// -------------------------------------  GPDMA_C5CONFIG  -----------------------------------------
#define GPDMA_C5CONFIG_E_Pos                                  0
#define GPDMA_C5CONFIG_E_Msk                                  (0x01UL << GPDMA_C5CONFIG_E_Pos)
#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C5CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C5CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C5CONFIG_IE_Pos                                 14
#define GPDMA_C5CONFIG_IE_Msk                                 (0x01UL << GPDMA_C5CONFIG_IE_Pos)
#define GPDMA_C5CONFIG_ITC_Pos                                15
#define GPDMA_C5CONFIG_ITC_Msk                                (0x01UL << GPDMA_C5CONFIG_ITC_Pos)
#define GPDMA_C5CONFIG_L_Pos                                  16
#define GPDMA_C5CONFIG_L_Msk                                  (0x01UL << GPDMA_C5CONFIG_L_Pos)
#define GPDMA_C5CONFIG_A_Pos                                  17
#define GPDMA_C5CONFIG_A_Msk                                  (0x01UL << GPDMA_C5CONFIG_A_Pos)
#define GPDMA_C5CONFIG_H_Pos                                  18
#define GPDMA_C5CONFIG_H_Msk                                  (0x01UL << GPDMA_C5CONFIG_H_Pos)

// -------------------------------------  GPDMA_C6SRCADDR  ----------------------------------------
#define GPDMA_C6SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C6SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C6DESTADDR  ----------------------------------------
#define GPDMA_C6DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C6DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C6LLI  ------------------------------------------
#define GPDMA_C6LLI_LM_Pos                                    0
#define GPDMA_C6LLI_LM_Msk                                    (0x01UL << GPDMA_C6LLI_LM_Pos)
#define GPDMA_C6LLI_R_Pos                                     1
#define GPDMA_C6LLI_R_Msk                                     (0x01UL << GPDMA_C6LLI_R_Pos)
#define GPDMA_C6LLI_LLI_Pos                                   2
#define GPDMA_C6LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos)

// -------------------------------------  GPDMA_C6CONTROL  ----------------------------------------
#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C6CONTROL_SBSIZE_Pos                            12
#define GPDMA_C6CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos)
#define GPDMA_C6CONTROL_DBSIZE_Pos                            15
#define GPDMA_C6CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos)
#define GPDMA_C6CONTROL_SWIDTH_Pos                            18
#define GPDMA_C6CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos)
#define GPDMA_C6CONTROL_DWIDTH_Pos                            21
#define GPDMA_C6CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos)
#define GPDMA_C6CONTROL_S_Pos                                 24
#define GPDMA_C6CONTROL_S_Msk                                 (0x01UL << GPDMA_C6CONTROL_S_Pos)
#define GPDMA_C6CONTROL_D_Pos                                 25
#define GPDMA_C6CONTROL_D_Msk                                 (0x01UL << GPDMA_C6CONTROL_D_Pos)
#define GPDMA_C6CONTROL_SI_Pos                                26
#define GPDMA_C6CONTROL_SI_Msk                                (0x01UL << GPDMA_C6CONTROL_SI_Pos)
#define GPDMA_C6CONTROL_DI_Pos                                27
#define GPDMA_C6CONTROL_DI_Msk                                (0x01UL << GPDMA_C6CONTROL_DI_Pos)
#define GPDMA_C6CONTROL_PROT1_Pos                             28
#define GPDMA_C6CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT1_Pos)
#define GPDMA_C6CONTROL_PROT2_Pos                             29
#define GPDMA_C6CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT2_Pos)
#define GPDMA_C6CONTROL_PROT3_Pos                             30
#define GPDMA_C6CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C6CONTROL_PROT3_Pos)
#define GPDMA_C6CONTROL_I_Pos                                 31
#define GPDMA_C6CONTROL_I_Msk                                 (0x01UL << GPDMA_C6CONTROL_I_Pos)

// -------------------------------------  GPDMA_C6CONFIG  -----------------------------------------
#define GPDMA_C6CONFIG_E_Pos                                  0
#define GPDMA_C6CONFIG_E_Msk                                  (0x01UL << GPDMA_C6CONFIG_E_Pos)
#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C6CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C6CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C6CONFIG_IE_Pos                                 14
#define GPDMA_C6CONFIG_IE_Msk                                 (0x01UL << GPDMA_C6CONFIG_IE_Pos)
#define GPDMA_C6CONFIG_ITC_Pos                                15
#define GPDMA_C6CONFIG_ITC_Msk                                (0x01UL << GPDMA_C6CONFIG_ITC_Pos)
#define GPDMA_C6CONFIG_L_Pos                                  16
#define GPDMA_C6CONFIG_L_Msk                                  (0x01UL << GPDMA_C6CONFIG_L_Pos)
#define GPDMA_C6CONFIG_A_Pos                                  17
#define GPDMA_C6CONFIG_A_Msk                                  (0x01UL << GPDMA_C6CONFIG_A_Pos)
#define GPDMA_C6CONFIG_H_Pos                                  18
#define GPDMA_C6CONFIG_H_Msk                                  (0x01UL << GPDMA_C6CONFIG_H_Pos)

// -------------------------------------  GPDMA_C7SRCADDR  ----------------------------------------
#define GPDMA_C7SRCADDR_SRCADDR_Pos                           0
#define GPDMA_C7SRCADDR_SRCADDR_Msk                           (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos)

// ------------------------------------  GPDMA_C7DESTADDR  ----------------------------------------
#define GPDMA_C7DESTADDR_DESTADDR_Pos                         0
#define GPDMA_C7DESTADDR_DESTADDR_Msk                         (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos)

// ---------------------------------------  GPDMA_C7LLI  ------------------------------------------
#define GPDMA_C7LLI_LM_Pos                                    0
#define GPDMA_C7LLI_LM_Msk                                    (0x01UL << GPDMA_C7LLI_LM_Pos)
#define GPDMA_C7LLI_R_Pos                                     1
#define GPDMA_C7LLI_R_Msk                                     (0x01UL << GPDMA_C7LLI_R_Pos)
#define GPDMA_C7LLI_LLI_Pos                                   2
#define GPDMA_C7LLI_LLI_Msk                                   (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos)

// -------------------------------------  GPDMA_C7CONTROL  ----------------------------------------
#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos                      0
#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk                      (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos)
#define GPDMA_C7CONTROL_SBSIZE_Pos                            12
#define GPDMA_C7CONTROL_SBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos)
#define GPDMA_C7CONTROL_DBSIZE_Pos                            15
#define GPDMA_C7CONTROL_DBSIZE_Msk                            (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos)
#define GPDMA_C7CONTROL_SWIDTH_Pos                            18
#define GPDMA_C7CONTROL_SWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos)
#define GPDMA_C7CONTROL_DWIDTH_Pos                            21
#define GPDMA_C7CONTROL_DWIDTH_Msk                            (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos)
#define GPDMA_C7CONTROL_S_Pos                                 24
#define GPDMA_C7CONTROL_S_Msk                                 (0x01UL << GPDMA_C7CONTROL_S_Pos)
#define GPDMA_C7CONTROL_D_Pos                                 25
#define GPDMA_C7CONTROL_D_Msk                                 (0x01UL << GPDMA_C7CONTROL_D_Pos)
#define GPDMA_C7CONTROL_SI_Pos                                26
#define GPDMA_C7CONTROL_SI_Msk                                (0x01UL << GPDMA_C7CONTROL_SI_Pos)
#define GPDMA_C7CONTROL_DI_Pos                                27
#define GPDMA_C7CONTROL_DI_Msk                                (0x01UL << GPDMA_C7CONTROL_DI_Pos)
#define GPDMA_C7CONTROL_PROT1_Pos                             28
#define GPDMA_C7CONTROL_PROT1_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT1_Pos)
#define GPDMA_C7CONTROL_PROT2_Pos                             29
#define GPDMA_C7CONTROL_PROT2_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT2_Pos)
#define GPDMA_C7CONTROL_PROT3_Pos                             30
#define GPDMA_C7CONTROL_PROT3_Msk                             (0x01UL << GPDMA_C7CONTROL_PROT3_Pos)
#define GPDMA_C7CONTROL_I_Pos                                 31
#define GPDMA_C7CONTROL_I_Msk                                 (0x01UL << GPDMA_C7CONTROL_I_Pos)

// -------------------------------------  GPDMA_C7CONFIG  -----------------------------------------
#define GPDMA_C7CONFIG_E_Pos                                  0
#define GPDMA_C7CONFIG_E_Msk                                  (0x01UL << GPDMA_C7CONFIG_E_Pos)
#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos                      1
#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk                      (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos)
#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos                     6
#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk                     (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos)
#define GPDMA_C7CONFIG_FLOWCNTRL_Pos                          11
#define GPDMA_C7CONFIG_FLOWCNTRL_Msk                          (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos)
#define GPDMA_C7CONFIG_IE_Pos                                 14
#define GPDMA_C7CONFIG_IE_Msk                                 (0x01UL << GPDMA_C7CONFIG_IE_Pos)
#define GPDMA_C7CONFIG_ITC_Pos                                15
#define GPDMA_C7CONFIG_ITC_Msk                                (0x01UL << GPDMA_C7CONFIG_ITC_Pos)
#define GPDMA_C7CONFIG_L_Pos                                  16
#define GPDMA_C7CONFIG_L_Msk                                  (0x01UL << GPDMA_C7CONFIG_L_Pos)
#define GPDMA_C7CONFIG_A_Pos                                  17
#define GPDMA_C7CONFIG_A_Msk                                  (0x01UL << GPDMA_C7CONFIG_A_Pos)
#define GPDMA_C7CONFIG_H_Pos                                  18
#define GPDMA_C7CONFIG_H_Msk                                  (0x01UL << GPDMA_C7CONFIG_H_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 SDMMC Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SDMMC_CTRL  -------------------------------------------
#define SDMMC_CTRL_CONTROLLER_RESET_Pos                       0
#define SDMMC_CTRL_CONTROLLER_RESET_Msk                       (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos)
#define SDMMC_CTRL_FIFO_RESET_Pos                             1
#define SDMMC_CTRL_FIFO_RESET_Msk                             (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos)
#define SDMMC_CTRL_DMA_RESET_Pos                              2
#define SDMMC_CTRL_DMA_RESET_Msk                              (0x01UL << SDMMC_CTRL_DMA_RESET_Pos)
#define SDMMC_CTRL_INT_ENABLE_Pos                             4
#define SDMMC_CTRL_INT_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos)
#define SDMMC_CTRL_DMA_ENABLE_Pos                             5
#define SDMMC_CTRL_DMA_ENABLE_Msk                             (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos)
#define SDMMC_CTRL_READ_WAIT_Pos                              6
#define SDMMC_CTRL_READ_WAIT_Msk                              (0x01UL << SDMMC_CTRL_READ_WAIT_Pos)
#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos                      7
#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk                      (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos)
#define SDMMC_CTRL_ABORT_READ_DATA_Pos                        8
#define SDMMC_CTRL_ABORT_READ_DATA_Msk                        (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos)
#define SDMMC_CTRL_SEND_CCSD_Pos                              9
#define SDMMC_CTRL_SEND_CCSD_Msk                              (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos)
#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos                    10
#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk                    (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos)
#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos          11
#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk          (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)
#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos                         16
#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos)
#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos                         20
#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk                         (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos)
#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos                       24
#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk                       (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos)
#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos                      25
#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk                      (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos)

// ---------------------------------------  SDMMC_PWREN  ------------------------------------------
#define SDMMC_PWREN_POWER_ENABLE_Pos                          0
#define SDMMC_PWREN_POWER_ENABLE_Msk                          (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos)

// --------------------------------------  SDMMC_CLKDIV  ------------------------------------------
#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos                         0
#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos)
#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos                         8
#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos)
#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos                         16
#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos)
#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos                         24
#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk                         (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos)

// --------------------------------------  SDMMC_CLKSRC  ------------------------------------------
#define SDMMC_CLKSRC_CLK_SOURCE_Pos                           0
#define SDMMC_CLKSRC_CLK_SOURCE_Msk                           (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos)

// --------------------------------------  SDMMC_CLKENA  ------------------------------------------
#define SDMMC_CLKENA_CCLK_ENABLE_Pos                          0
#define SDMMC_CLKENA_CCLK_ENABLE_Msk                          (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos)
#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos                       16
#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk                       (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos)

// ---------------------------------------  SDMMC_TMOUT  ------------------------------------------
#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos                      0
#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk                      (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos)
#define SDMMC_TMOUT_DATA_TIMEOUT_Pos                          8
#define SDMMC_TMOUT_DATA_TIMEOUT_Msk                          (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos)

// ---------------------------------------  SDMMC_CTYPE  ------------------------------------------
#define SDMMC_CTYPE_CARD_WIDTH0_Pos                           0
#define SDMMC_CTYPE_CARD_WIDTH0_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos)
#define SDMMC_CTYPE_CARD_WIDTH1_Pos                           16
#define SDMMC_CTYPE_CARD_WIDTH1_Msk                           (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos)

// --------------------------------------  SDMMC_BLKSIZ  ------------------------------------------
#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos                           0
#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk                           (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos)

// --------------------------------------  SDMMC_BYTCNT  ------------------------------------------
#define SDMMC_BYTCNT_BYTE_COUNT_Pos                           0
#define SDMMC_BYTCNT_BYTE_COUNT_Msk                           (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos)

// --------------------------------------  SDMMC_INTMASK  -----------------------------------------
#define SDMMC_INTMASK_CDET_Pos                                0
#define SDMMC_INTMASK_CDET_Msk                                (0x01UL << SDMMC_INTMASK_CDET_Pos)
#define SDMMC_INTMASK_RE_Pos                                  1
#define SDMMC_INTMASK_RE_Msk                                  (0x01UL << SDMMC_INTMASK_RE_Pos)
#define SDMMC_INTMASK_CDONE_Pos                               2
#define SDMMC_INTMASK_CDONE_Msk                               (0x01UL << SDMMC_INTMASK_CDONE_Pos)
#define SDMMC_INTMASK_DTO_Pos                                 3
#define SDMMC_INTMASK_DTO_Msk                                 (0x01UL << SDMMC_INTMASK_DTO_Pos)
#define SDMMC_INTMASK_TXDR_Pos                                4
#define SDMMC_INTMASK_TXDR_Msk                                (0x01UL << SDMMC_INTMASK_TXDR_Pos)
#define SDMMC_INTMASK_RXDR_Pos                                5
#define SDMMC_INTMASK_RXDR_Msk                                (0x01UL << SDMMC_INTMASK_RXDR_Pos)
#define SDMMC_INTMASK_RCRC_Pos                                6
#define SDMMC_INTMASK_RCRC_Msk                                (0x01UL << SDMMC_INTMASK_RCRC_Pos)
#define SDMMC_INTMASK_DCRC_Pos                                7
#define SDMMC_INTMASK_DCRC_Msk                                (0x01UL << SDMMC_INTMASK_DCRC_Pos)
#define SDMMC_INTMASK_RTO_Pos                                 8
#define SDMMC_INTMASK_RTO_Msk                                 (0x01UL << SDMMC_INTMASK_RTO_Pos)
#define SDMMC_INTMASK_DRTO_Pos                                9
#define SDMMC_INTMASK_DRTO_Msk                                (0x01UL << SDMMC_INTMASK_DRTO_Pos)
#define SDMMC_INTMASK_HTO_Pos                                 10
#define SDMMC_INTMASK_HTO_Msk                                 (0x01UL << SDMMC_INTMASK_HTO_Pos)
#define SDMMC_INTMASK_FRUN_Pos                                11
#define SDMMC_INTMASK_FRUN_Msk                                (0x01UL << SDMMC_INTMASK_FRUN_Pos)
#define SDMMC_INTMASK_HLE_Pos                                 12
#define SDMMC_INTMASK_HLE_Msk                                 (0x01UL << SDMMC_INTMASK_HLE_Pos)
#define SDMMC_INTMASK_SBE_Pos                                 13
#define SDMMC_INTMASK_SBE_Msk                                 (0x01UL << SDMMC_INTMASK_SBE_Pos)
#define SDMMC_INTMASK_ACD_Pos                                 14
#define SDMMC_INTMASK_ACD_Msk                                 (0x01UL << SDMMC_INTMASK_ACD_Pos)
#define SDMMC_INTMASK_EBE_Pos                                 15
#define SDMMC_INTMASK_EBE_Msk                                 (0x01UL << SDMMC_INTMASK_EBE_Pos)
#define SDMMC_INTMASK_SDIO_INT_MASK_Pos                       16
#define SDMMC_INTMASK_SDIO_INT_MASK_Msk                       (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos)

// --------------------------------------  SDMMC_CMDARG  ------------------------------------------
#define SDMMC_CMDARG_CMD_ARG_Pos                              0
#define SDMMC_CMDARG_CMD_ARG_Msk                              (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos)

// ----------------------------------------  SDMMC_CMD  -------------------------------------------
#define SDMMC_CMD_CMD_INDEX_Pos                               0
#define SDMMC_CMD_CMD_INDEX_Msk                               (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos)
#define SDMMC_CMD_RESPONSE_EXPECT_Pos                         6
#define SDMMC_CMD_RESPONSE_EXPECT_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos)
#define SDMMC_CMD_RESPONSE_LENGTH_Pos                         7
#define SDMMC_CMD_RESPONSE_LENGTH_Msk                         (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos)
#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos                      8
#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk                      (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos)
#define SDMMC_CMD_DATA_EXPECTED_Pos                           9
#define SDMMC_CMD_DATA_EXPECTED_Msk                           (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos)
#define SDMMC_CMD_READ_WRITE_Pos                              10
#define SDMMC_CMD_READ_WRITE_Msk                              (0x01UL << SDMMC_CMD_READ_WRITE_Pos)
#define SDMMC_CMD_TRANSFER_MODE_Pos                           11
#define SDMMC_CMD_TRANSFER_MODE_Msk                           (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos)
#define SDMMC_CMD_SEND_AUTO_STOP_Pos                          12
#define SDMMC_CMD_SEND_AUTO_STOP_Msk                          (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos)
#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos                   13
#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk                   (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos)
#define SDMMC_CMD_STOP_ABORT_CMd_Pos                          14
#define SDMMC_CMD_STOP_ABORT_CMd_Msk                          (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos)
#define SDMMC_CMD_SEND_INITIALIZATION_Pos                     15
#define SDMMC_CMD_SEND_INITIALIZATION_Msk                     (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos)
#define SDMMC_CMD_CARD_NUMBER_Pos                             16
#define SDMMC_CMD_CARD_NUMBER_Msk                             (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos)
#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos             21
#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk             (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)
#define SDMMC_CMD_READ_CEATA_DEVICE_Pos                       22
#define SDMMC_CMD_READ_CEATA_DEVICE_Msk                       (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos)
#define SDMMC_CMD_CCS_EXPECTED_Pos                            23
#define SDMMC_CMD_CCS_EXPECTED_Msk                            (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos)
#define SDMMC_CMD_ENABLE_BOOT_Pos                             24
#define SDMMC_CMD_ENABLE_BOOT_Msk                             (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos)
#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos                         25
#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk                         (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos)
#define SDMMC_CMD_DISABLE_BOOT_Pos                            26
#define SDMMC_CMD_DISABLE_BOOT_Msk                            (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos)
#define SDMMC_CMD_BOOT_MODE_Pos                               27
#define SDMMC_CMD_BOOT_MODE_Msk                               (0x01UL << SDMMC_CMD_BOOT_MODE_Pos)
#define SDMMC_CMD_VOLT_SWITCH_Pos                             28
#define SDMMC_CMD_VOLT_SWITCH_Msk                             (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos)
#define SDMMC_CMD_START_CMD_Pos                               31
#define SDMMC_CMD_START_CMD_Msk                               (0x01UL << SDMMC_CMD_START_CMD_Pos)

// ---------------------------------------  SDMMC_RESP0  ------------------------------------------
#define SDMMC_RESP0_RESPONSE0_Pos                             0
#define SDMMC_RESP0_RESPONSE0_Msk                             (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos)

// ---------------------------------------  SDMMC_RESP1  ------------------------------------------
#define SDMMC_RESP1_RESPONSE1_Pos                             0
#define SDMMC_RESP1_RESPONSE1_Msk                             (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos)

// ---------------------------------------  SDMMC_RESP2  ------------------------------------------
#define SDMMC_RESP2_RESPONSE2_Pos                             0
#define SDMMC_RESP2_RESPONSE2_Msk                             (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos)

// ---------------------------------------  SDMMC_RESP3  ------------------------------------------
#define SDMMC_RESP3_RESPONSE3_Pos                             0
#define SDMMC_RESP3_RESPONSE3_Msk                             (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos)

// --------------------------------------  SDMMC_MINTSTS  -----------------------------------------
#define SDMMC_MINTSTS_CDET_Pos                                0
#define SDMMC_MINTSTS_CDET_Msk                                (0x01UL << SDMMC_MINTSTS_CDET_Pos)
#define SDMMC_MINTSTS_RE_Pos                                  1
#define SDMMC_MINTSTS_RE_Msk                                  (0x01UL << SDMMC_MINTSTS_RE_Pos)
#define SDMMC_MINTSTS_CDONE_Pos                               2
#define SDMMC_MINTSTS_CDONE_Msk                               (0x01UL << SDMMC_MINTSTS_CDONE_Pos)
#define SDMMC_MINTSTS_DTO_Pos                                 3
#define SDMMC_MINTSTS_DTO_Msk                                 (0x01UL << SDMMC_MINTSTS_DTO_Pos)
#define SDMMC_MINTSTS_TXDR_Pos                                4
#define SDMMC_MINTSTS_TXDR_Msk                                (0x01UL << SDMMC_MINTSTS_TXDR_Pos)
#define SDMMC_MINTSTS_RXDR_Pos                                5
#define SDMMC_MINTSTS_RXDR_Msk                                (0x01UL << SDMMC_MINTSTS_RXDR_Pos)
#define SDMMC_MINTSTS_RCRC_Pos                                6
#define SDMMC_MINTSTS_RCRC_Msk                                (0x01UL << SDMMC_MINTSTS_RCRC_Pos)
#define SDMMC_MINTSTS_DCRC_Pos                                7
#define SDMMC_MINTSTS_DCRC_Msk                                (0x01UL << SDMMC_MINTSTS_DCRC_Pos)
#define SDMMC_MINTSTS_RTO_Pos                                 8
#define SDMMC_MINTSTS_RTO_Msk                                 (0x01UL << SDMMC_MINTSTS_RTO_Pos)
#define SDMMC_MINTSTS_DRTO_Pos                                9
#define SDMMC_MINTSTS_DRTO_Msk                                (0x01UL << SDMMC_MINTSTS_DRTO_Pos)
#define SDMMC_MINTSTS_HTO_Pos                                 10
#define SDMMC_MINTSTS_HTO_Msk                                 (0x01UL << SDMMC_MINTSTS_HTO_Pos)
#define SDMMC_MINTSTS_FRUN_Pos                                11
#define SDMMC_MINTSTS_FRUN_Msk                                (0x01UL << SDMMC_MINTSTS_FRUN_Pos)
#define SDMMC_MINTSTS_HLE_Pos                                 12
#define SDMMC_MINTSTS_HLE_Msk                                 (0x01UL << SDMMC_MINTSTS_HLE_Pos)
#define SDMMC_MINTSTS_SBE_Pos                                 13
#define SDMMC_MINTSTS_SBE_Msk                                 (0x01UL << SDMMC_MINTSTS_SBE_Pos)
#define SDMMC_MINTSTS_ACD_Pos                                 14
#define SDMMC_MINTSTS_ACD_Msk                                 (0x01UL << SDMMC_MINTSTS_ACD_Pos)
#define SDMMC_MINTSTS_EBE_Pos                                 15
#define SDMMC_MINTSTS_EBE_Msk                                 (0x01UL << SDMMC_MINTSTS_EBE_Pos)
#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos                      16
#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos)

// --------------------------------------  SDMMC_RINTSTS  -----------------------------------------
#define SDMMC_RINTSTS_CDET_Pos                                0
#define SDMMC_RINTSTS_CDET_Msk                                (0x01UL << SDMMC_RINTSTS_CDET_Pos)
#define SDMMC_RINTSTS_RE_Pos                                  1
#define SDMMC_RINTSTS_RE_Msk                                  (0x01UL << SDMMC_RINTSTS_RE_Pos)
#define SDMMC_RINTSTS_CDONE_Pos                               2
#define SDMMC_RINTSTS_CDONE_Msk                               (0x01UL << SDMMC_RINTSTS_CDONE_Pos)
#define SDMMC_RINTSTS_DTO_Pos                                 3
#define SDMMC_RINTSTS_DTO_Msk                                 (0x01UL << SDMMC_RINTSTS_DTO_Pos)
#define SDMMC_RINTSTS_TXDR_Pos                                4
#define SDMMC_RINTSTS_TXDR_Msk                                (0x01UL << SDMMC_RINTSTS_TXDR_Pos)
#define SDMMC_RINTSTS_RXDR_Pos                                5
#define SDMMC_RINTSTS_RXDR_Msk                                (0x01UL << SDMMC_RINTSTS_RXDR_Pos)
#define SDMMC_RINTSTS_RCRC_Pos                                6
#define SDMMC_RINTSTS_RCRC_Msk                                (0x01UL << SDMMC_RINTSTS_RCRC_Pos)
#define SDMMC_RINTSTS_DCRC_Pos                                7
#define SDMMC_RINTSTS_DCRC_Msk                                (0x01UL << SDMMC_RINTSTS_DCRC_Pos)
#define SDMMC_RINTSTS_RTO_BAR_Pos                             8
#define SDMMC_RINTSTS_RTO_BAR_Msk                             (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos)
#define SDMMC_RINTSTS_DRTO_BDS_Pos                            9
#define SDMMC_RINTSTS_DRTO_BDS_Msk                            (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos)
#define SDMMC_RINTSTS_HTO_Pos                                 10
#define SDMMC_RINTSTS_HTO_Msk                                 (0x01UL << SDMMC_RINTSTS_HTO_Pos)
#define SDMMC_RINTSTS_FRUN_Pos                                11
#define SDMMC_RINTSTS_FRUN_Msk                                (0x01UL << SDMMC_RINTSTS_FRUN_Pos)
#define SDMMC_RINTSTS_HLE_Pos                                 12
#define SDMMC_RINTSTS_HLE_Msk                                 (0x01UL << SDMMC_RINTSTS_HLE_Pos)
#define SDMMC_RINTSTS_SBE_Pos                                 13
#define SDMMC_RINTSTS_SBE_Msk                                 (0x01UL << SDMMC_RINTSTS_SBE_Pos)
#define SDMMC_RINTSTS_ACD_Pos                                 14
#define SDMMC_RINTSTS_ACD_Msk                                 (0x01UL << SDMMC_RINTSTS_ACD_Pos)
#define SDMMC_RINTSTS_EBE_Pos                                 15
#define SDMMC_RINTSTS_EBE_Msk                                 (0x01UL << SDMMC_RINTSTS_EBE_Pos)
#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos                      16
#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk                      (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos)

// --------------------------------------  SDMMC_STATUS  ------------------------------------------
#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos                    0
#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos)
#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos                    1
#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk                    (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos)
#define SDMMC_STATUS_FIFO_EMPTY_Pos                           2
#define SDMMC_STATUS_FIFO_EMPTY_Msk                           (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos)
#define SDMMC_STATUS_FIFO_FULL_Pos                            3
#define SDMMC_STATUS_FIFO_FULL_Msk                            (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos)
#define SDMMC_STATUS_CMDFSMSTATES_Pos                         4
#define SDMMC_STATUS_CMDFSMSTATES_Msk                         (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos)
#define SDMMC_STATUS_DATA_3_STATUS_Pos                        8
#define SDMMC_STATUS_DATA_3_STATUS_Msk                        (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos)
#define SDMMC_STATUS_DATA_BUSY_Pos                            9
#define SDMMC_STATUS_DATA_BUSY_Msk                            (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos)
#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos                   10
#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk                   (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos)
#define SDMMC_STATUS_RESPONSE_INDEX_Pos                       11
#define SDMMC_STATUS_RESPONSE_INDEX_Msk                       (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos)
#define SDMMC_STATUS_FIFO_COUNT_Pos                           17
#define SDMMC_STATUS_FIFO_COUNT_Msk                           (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos)
#define SDMMC_STATUS_DMA_ACK_Pos                              30
#define SDMMC_STATUS_DMA_ACK_Msk                              (0x01UL << SDMMC_STATUS_DMA_ACK_Pos)
#define SDMMC_STATUS_DMA_REQ_Pos                              31
#define SDMMC_STATUS_DMA_REQ_Msk                              (0x01UL << SDMMC_STATUS_DMA_REQ_Pos)

// --------------------------------------  SDMMC_FIFOTH  ------------------------------------------
#define SDMMC_FIFOTH_TX_WMARK_Pos                             0
#define SDMMC_FIFOTH_TX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos)
#define SDMMC_FIFOTH_RX_WMARK_Pos                             16
#define SDMMC_FIFOTH_RX_WMARK_Msk                             (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos)
#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos      28
#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk      (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */

// --------------------------------------  SDMMC_CDETECT  -----------------------------------------
#define SDMMC_CDETECT_CARD_DETECT_N_Pos                       0
#define SDMMC_CDETECT_CARD_DETECT_N_Msk                       (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos)

// --------------------------------------  SDMMC_WRTPRT  ------------------------------------------
#define SDMMC_WRTPRT_WRITE_PROTECT_Pos                        0
#define SDMMC_WRTPRT_WRITE_PROTECT_Msk                        (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos)

// ---------------------------------------  SDMMC_GPIO  -------------------------------------------
#define SDMMC_GPIO_GPI_Pos                                    0
#define SDMMC_GPIO_GPI_Msk                                    (0x000000ffUL << SDMMC_GPIO_GPI_Pos)
#define SDMMC_GPIO_GPO_Pos                                    8
#define SDMMC_GPIO_GPO_Msk                                    (0x0000ffffUL << SDMMC_GPIO_GPO_Pos)

// --------------------------------------  SDMMC_TCBCNT  ------------------------------------------
#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos                0
#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)

// --------------------------------------  SDMMC_TBBCNT  ------------------------------------------
#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos                0
#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk                (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)

// --------------------------------------  SDMMC_DEBNCE  ------------------------------------------
#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos                       0
#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk                       (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos)

// ---------------------------------------  SDMMC_USRID  ------------------------------------------
#define SDMMC_USRID_USRID_Pos                                 0
#define SDMMC_USRID_USRID_Msk                                 (0xffffffffUL << SDMMC_USRID_USRID_Pos)

// ---------------------------------------  SDMMC_VERID  ------------------------------------------
#define SDMMC_VERID_VERID_Pos                                 0
#define SDMMC_VERID_VERID_Msk                                 (0xffffffffUL << SDMMC_VERID_VERID_Pos)

// --------------------------------------  SDMMC_UHS_REG  -----------------------------------------
#define SDMMC_UHS_REG_VOLT_REG_Pos                            0
#define SDMMC_UHS_REG_VOLT_REG_Msk                            (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos)
#define SDMMC_UHS_REG_DDR_REG_Pos                             16
#define SDMMC_UHS_REG_DDR_REG_Msk                             (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos)

// ---------------------------------------  SDMMC_RST_N  ------------------------------------------
#define SDMMC_RST_N_CARD_RESET_Pos                            0
#define SDMMC_RST_N_CARD_RESET_Msk                            (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos)

// ---------------------------------------  SDMMC_BMOD  -------------------------------------------
#define SDMMC_BMOD_SWR_Pos                                    0
#define SDMMC_BMOD_SWR_Msk                                    (0x01UL << SDMMC_BMOD_SWR_Pos)
#define SDMMC_BMOD_FB_Pos                                     1
#define SDMMC_BMOD_FB_Msk                                     (0x01UL << SDMMC_BMOD_FB_Pos)
#define SDMMC_BMOD_DSL_Pos                                    2
#define SDMMC_BMOD_DSL_Msk                                    (0x1fUL << SDMMC_BMOD_DSL_Pos)
#define SDMMC_BMOD_DE_Pos                                     7
#define SDMMC_BMOD_DE_Msk                                     (0x01UL << SDMMC_BMOD_DE_Pos)
#define SDMMC_BMOD_PBL_Pos                                    8
#define SDMMC_BMOD_PBL_Msk                                    (0x07UL << SDMMC_BMOD_PBL_Pos)

// --------------------------------------  SDMMC_PLDMND  ------------------------------------------
#define SDMMC_PLDMND_PD_Pos                                   0
#define SDMMC_PLDMND_PD_Msk                                   (0xffffffffUL << SDMMC_PLDMND_PD_Pos)

// --------------------------------------  SDMMC_DBADDR  ------------------------------------------
#define SDMMC_DBADDR_SDL_Pos                                  0
#define SDMMC_DBADDR_SDL_Msk                                  (0xffffffffUL << SDMMC_DBADDR_SDL_Pos)

// ---------------------------------------  SDMMC_IDSTS  ------------------------------------------
#define SDMMC_IDSTS_TI_Pos                                    0
#define SDMMC_IDSTS_TI_Msk                                    (0x01UL << SDMMC_IDSTS_TI_Pos)
#define SDMMC_IDSTS_RI_Pos                                    1
#define SDMMC_IDSTS_RI_Msk                                    (0x01UL << SDMMC_IDSTS_RI_Pos)
#define SDMMC_IDSTS_FBE_Pos                                   2
#define SDMMC_IDSTS_FBE_Msk                                   (0x01UL << SDMMC_IDSTS_FBE_Pos)
#define SDMMC_IDSTS_DU_Pos                                    4
#define SDMMC_IDSTS_DU_Msk                                    (0x01UL << SDMMC_IDSTS_DU_Pos)
#define SDMMC_IDSTS_CES_Pos                                   5
#define SDMMC_IDSTS_CES_Msk                                   (0x01UL << SDMMC_IDSTS_CES_Pos)
#define SDMMC_IDSTS_NIS_Pos                                   8
#define SDMMC_IDSTS_NIS_Msk                                   (0x01UL << SDMMC_IDSTS_NIS_Pos)
#define SDMMC_IDSTS_AIS_Pos                                   9
#define SDMMC_IDSTS_AIS_Msk                                   (0x01UL << SDMMC_IDSTS_AIS_Pos)
#define SDMMC_IDSTS_EB_Pos                                    10
#define SDMMC_IDSTS_EB_Msk                                    (0x07UL << SDMMC_IDSTS_EB_Pos)
#define SDMMC_IDSTS_FSM_Pos                                   13
#define SDMMC_IDSTS_FSM_Msk                                   (0x0fUL << SDMMC_IDSTS_FSM_Pos)

// --------------------------------------  SDMMC_IDINTEN  -----------------------------------------
#define SDMMC_IDINTEN_TI_Pos                                  0
#define SDMMC_IDINTEN_TI_Msk                                  (0x01UL << SDMMC_IDINTEN_TI_Pos)
#define SDMMC_IDINTEN_RI_Pos                                  1
#define SDMMC_IDINTEN_RI_Msk                                  (0x01UL << SDMMC_IDINTEN_RI_Pos)
#define SDMMC_IDINTEN_FBE_Pos                                 2
#define SDMMC_IDINTEN_FBE_Msk                                 (0x01UL << SDMMC_IDINTEN_FBE_Pos)
#define SDMMC_IDINTEN_DU_Pos                                  4
#define SDMMC_IDINTEN_DU_Msk                                  (0x01UL << SDMMC_IDINTEN_DU_Pos)
#define SDMMC_IDINTEN_CES_Pos                                 5
#define SDMMC_IDINTEN_CES_Msk                                 (0x01UL << SDMMC_IDINTEN_CES_Pos)
#define SDMMC_IDINTEN_NIS_Pos                                 8
#define SDMMC_IDINTEN_NIS_Msk                                 (0x01UL << SDMMC_IDINTEN_NIS_Pos)
#define SDMMC_IDINTEN_AIS_Pos                                 9
#define SDMMC_IDINTEN_AIS_Msk                                 (0x01UL << SDMMC_IDINTEN_AIS_Pos)

// --------------------------------------  SDMMC_DSCADDR  -----------------------------------------
#define SDMMC_DSCADDR_HDA_Pos                                 0
#define SDMMC_DSCADDR_HDA_Msk                                 (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos)

// --------------------------------------  SDMMC_BUFADDR  -----------------------------------------
#define SDMMC_BUFADDR_HBA_Pos                                 0
#define SDMMC_BUFADDR_HBA_Msk                                 (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  EMC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  EMC_CONTROL  ------------------------------------------
#define EMC_CONTROL_E_Pos                                     0
#define EMC_CONTROL_E_Msk                                     (0x01UL << EMC_CONTROL_E_Pos)
#define EMC_CONTROL_M_Pos                                     1
#define EMC_CONTROL_M_Msk                                     (0x01UL << EMC_CONTROL_M_Pos)
#define EMC_CONTROL_L_Pos                                     2
#define EMC_CONTROL_L_Msk                                     (0x01UL << EMC_CONTROL_L_Pos)

// ---------------------------------------  EMC_STATUS  -------------------------------------------
#define EMC_STATUS_B_Pos                                      0
#define EMC_STATUS_B_Msk                                      (0x01UL << EMC_STATUS_B_Pos)
#define EMC_STATUS_S_Pos                                      1
#define EMC_STATUS_S_Msk                                      (0x01UL << EMC_STATUS_S_Pos)
#define EMC_STATUS_SA_Pos                                     2
#define EMC_STATUS_SA_Msk                                     (0x01UL << EMC_STATUS_SA_Pos)

// ---------------------------------------  EMC_CONFIG  -------------------------------------------
#define EMC_CONFIG_EM_Pos                                     0
#define EMC_CONFIG_EM_Msk                                     (0x01UL << EMC_CONFIG_EM_Pos)
#define EMC_CONFIG_CR_Pos                                     8
#define EMC_CONFIG_CR_Msk                                     (0x01UL << EMC_CONFIG_CR_Pos)

// -----------------------------------  EMC_DYNAMICCONTROL  ---------------------------------------
#define EMC_DYNAMICCONTROL_CE_Pos                             0
#define EMC_DYNAMICCONTROL_CE_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CE_Pos)
#define EMC_DYNAMICCONTROL_CS_Pos                             1
#define EMC_DYNAMICCONTROL_CS_Msk                             (0x01UL << EMC_DYNAMICCONTROL_CS_Pos)
#define EMC_DYNAMICCONTROL_SR_Pos                             2
#define EMC_DYNAMICCONTROL_SR_Msk                             (0x01UL << EMC_DYNAMICCONTROL_SR_Pos)
#define EMC_DYNAMICCONTROL_MMC_Pos                            5
#define EMC_DYNAMICCONTROL_MMC_Msk                            (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos)
#define EMC_DYNAMICCONTROL_I_Pos                              7
#define EMC_DYNAMICCONTROL_I_Msk                              (0x03UL << EMC_DYNAMICCONTROL_I_Pos)
#define EMC_DYNAMICCONTROL_DP_Pos                             13
#define EMC_DYNAMICCONTROL_DP_Msk                             (0x01UL << EMC_DYNAMICCONTROL_DP_Pos)

// -----------------------------------  EMC_DYNAMICREFRESH  ---------------------------------------
#define EMC_DYNAMICREFRESH_REFRESH_Pos                        0
#define EMC_DYNAMICREFRESH_REFRESH_Msk                        (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos)

// ----------------------------------  EMC_DYNAMICREADCONFIG  -------------------------------------
#define EMC_DYNAMICREADCONFIG_RD_Pos                          0
#define EMC_DYNAMICREADCONFIG_RD_Msk                          (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos)

// --------------------------------------  EMC_DYNAMICRP  -----------------------------------------
#define EMC_DYNAMICRP_tRP_Pos                                 0
#define EMC_DYNAMICRP_tRP_Msk                                 (0x0fUL << EMC_DYNAMICRP_tRP_Pos)

// -------------------------------------  EMC_DYNAMICRAS  -----------------------------------------
#define EMC_DYNAMICRAS_tRAS_Pos                               0
#define EMC_DYNAMICRAS_tRAS_Msk                               (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos)

// -------------------------------------  EMC_DYNAMICSREX  ----------------------------------------
#define EMC_DYNAMICSREX_tSREX_Pos                             0
#define EMC_DYNAMICSREX_tSREX_Msk                             (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos)

// -------------------------------------  EMC_DYNAMICAPR  -----------------------------------------
#define EMC_DYNAMICAPR_tAPR_Pos                               0
#define EMC_DYNAMICAPR_tAPR_Msk                               (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos)

// -------------------------------------  EMC_DYNAMICDAL  -----------------------------------------
#define EMC_DYNAMICDAL_tDAL_Pos                               0
#define EMC_DYNAMICDAL_tDAL_Msk                               (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos)

// --------------------------------------  EMC_DYNAMICWR  -----------------------------------------
#define EMC_DYNAMICWR_tWR_Pos                                 0
#define EMC_DYNAMICWR_tWR_Msk                                 (0x0fUL << EMC_DYNAMICWR_tWR_Pos)

// --------------------------------------  EMC_DYNAMICRC  -----------------------------------------
#define EMC_DYNAMICRC_tRC_Pos                                 0
#define EMC_DYNAMICRC_tRC_Msk                                 (0x1fUL << EMC_DYNAMICRC_tRC_Pos)

// -------------------------------------  EMC_DYNAMICRFC  -----------------------------------------
#define EMC_DYNAMICRFC_tRFC_Pos                               0
#define EMC_DYNAMICRFC_tRFC_Msk                               (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos)

// -------------------------------------  EMC_DYNAMICXSR  -----------------------------------------
#define EMC_DYNAMICXSR_tXSR_Pos                               0
#define EMC_DYNAMICXSR_tXSR_Msk                               (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos)

// -------------------------------------  EMC_DYNAMICRRD  -----------------------------------------
#define EMC_DYNAMICRRD_tRRD_Pos                               0
#define EMC_DYNAMICRRD_tRRD_Msk                               (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos)

// -------------------------------------  EMC_DYNAMICMRD  -----------------------------------------
#define EMC_DYNAMICMRD_tMRD_Pos                               0
#define EMC_DYNAMICMRD_tMRD_Msk                               (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos)

// ---------------------------------  EMC_STATICEXTENDEDWAIT  -------------------------------------
#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos               0
#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk               (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos)

// -----------------------------------  EMC_DYNAMICCONFIG0  ---------------------------------------
#define EMC_DYNAMICCONFIG0_MD_Pos                             3
#define EMC_DYNAMICCONFIG0_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos)
#define EMC_DYNAMICCONFIG0_AM0_Pos                            7
#define EMC_DYNAMICCONFIG0_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos)
#define EMC_DYNAMICCONFIG0_AM1_Pos                            14
#define EMC_DYNAMICCONFIG0_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos)
#define EMC_DYNAMICCONFIG0_B_Pos                              19
#define EMC_DYNAMICCONFIG0_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_B_Pos)
#define EMC_DYNAMICCONFIG0_P_Pos                              20
#define EMC_DYNAMICCONFIG0_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG0_P_Pos)

// -----------------------------------  EMC_DYNAMICRASCAS0  ---------------------------------------
#define EMC_DYNAMICRASCAS0_RAS_Pos                            0
#define EMC_DYNAMICRASCAS0_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos)
#define EMC_DYNAMICRASCAS0_CAS_Pos                            8
#define EMC_DYNAMICRASCAS0_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos)

// -----------------------------------  EMC_DYNAMICCONFIG1  ---------------------------------------
#define EMC_DYNAMICCONFIG1_MD_Pos                             3
#define EMC_DYNAMICCONFIG1_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos)
#define EMC_DYNAMICCONFIG1_AM0_Pos                            7
#define EMC_DYNAMICCONFIG1_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos)
#define EMC_DYNAMICCONFIG1_AM1_Pos                            14
#define EMC_DYNAMICCONFIG1_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos)
#define EMC_DYNAMICCONFIG1_B_Pos                              19
#define EMC_DYNAMICCONFIG1_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_B_Pos)
#define EMC_DYNAMICCONFIG1_P_Pos                              20
#define EMC_DYNAMICCONFIG1_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG1_P_Pos)

// -----------------------------------  EMC_DYNAMICRASCAS1  ---------------------------------------
#define EMC_DYNAMICRASCAS1_RAS_Pos                            0
#define EMC_DYNAMICRASCAS1_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos)
#define EMC_DYNAMICRASCAS1_CAS_Pos                            8
#define EMC_DYNAMICRASCAS1_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos)

// -----------------------------------  EMC_DYNAMICCONFIG2  ---------------------------------------
#define EMC_DYNAMICCONFIG2_MD_Pos                             3
#define EMC_DYNAMICCONFIG2_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos)
#define EMC_DYNAMICCONFIG2_AM0_Pos                            7
#define EMC_DYNAMICCONFIG2_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos)
#define EMC_DYNAMICCONFIG2_AM1_Pos                            14
#define EMC_DYNAMICCONFIG2_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos)
#define EMC_DYNAMICCONFIG2_B_Pos                              19
#define EMC_DYNAMICCONFIG2_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_B_Pos)
#define EMC_DYNAMICCONFIG2_P_Pos                              20
#define EMC_DYNAMICCONFIG2_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG2_P_Pos)

// -----------------------------------  EMC_DYNAMICRASCAS2  ---------------------------------------
#define EMC_DYNAMICRASCAS2_RAS_Pos                            0
#define EMC_DYNAMICRASCAS2_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos)
#define EMC_DYNAMICRASCAS2_CAS_Pos                            8
#define EMC_DYNAMICRASCAS2_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos)

// -----------------------------------  EMC_DYNAMICCONFIG3  ---------------------------------------
#define EMC_DYNAMICCONFIG3_MD_Pos                             3
#define EMC_DYNAMICCONFIG3_MD_Msk                             (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos)
#define EMC_DYNAMICCONFIG3_AM0_Pos                            7
#define EMC_DYNAMICCONFIG3_AM0_Msk                            (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos)
#define EMC_DYNAMICCONFIG3_AM1_Pos                            14
#define EMC_DYNAMICCONFIG3_AM1_Msk                            (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos)
#define EMC_DYNAMICCONFIG3_B_Pos                              19
#define EMC_DYNAMICCONFIG3_B_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_B_Pos)
#define EMC_DYNAMICCONFIG3_P_Pos                              20
#define EMC_DYNAMICCONFIG3_P_Msk                              (0x01UL << EMC_DYNAMICCONFIG3_P_Pos)

// -----------------------------------  EMC_DYNAMICRASCAS3  ---------------------------------------
#define EMC_DYNAMICRASCAS3_RAS_Pos                            0
#define EMC_DYNAMICRASCAS3_RAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos)
#define EMC_DYNAMICRASCAS3_CAS_Pos                            8
#define EMC_DYNAMICRASCAS3_CAS_Msk                            (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos)

// ------------------------------------  EMC_STATICCONFIG0  ---------------------------------------
#define EMC_STATICCONFIG0_MW_Pos                              0
#define EMC_STATICCONFIG0_MW_Msk                              (0x03UL << EMC_STATICCONFIG0_MW_Pos)
#define EMC_STATICCONFIG0_PM_Pos                              3
#define EMC_STATICCONFIG0_PM_Msk                              (0x01UL << EMC_STATICCONFIG0_PM_Pos)
#define EMC_STATICCONFIG0_PC_Pos                              6
#define EMC_STATICCONFIG0_PC_Msk                              (0x01UL << EMC_STATICCONFIG0_PC_Pos)
#define EMC_STATICCONFIG0_PB_Pos                              7
#define EMC_STATICCONFIG0_PB_Msk                              (0x01UL << EMC_STATICCONFIG0_PB_Pos)
#define EMC_STATICCONFIG0_EW_Pos                              8
#define EMC_STATICCONFIG0_EW_Msk                              (0x01UL << EMC_STATICCONFIG0_EW_Pos)
#define EMC_STATICCONFIG0_B_Pos                               19
#define EMC_STATICCONFIG0_B_Msk                               (0x01UL << EMC_STATICCONFIG0_B_Pos)
#define EMC_STATICCONFIG0_P_Pos                               20
#define EMC_STATICCONFIG0_P_Msk                               (0x01UL << EMC_STATICCONFIG0_P_Pos)

// -----------------------------------  EMC_STATICWAITWEN0  ---------------------------------------
#define EMC_STATICWAITWEN0_WAITWEN_Pos                        0
#define EMC_STATICWAITWEN0_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos)

// -----------------------------------  EMC_STATICWAITOEN0  ---------------------------------------
#define EMC_STATICWAITOEN0_WAITOEN_Pos                        0
#define EMC_STATICWAITOEN0_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos)

// ------------------------------------  EMC_STATICWAITRD0  ---------------------------------------
#define EMC_STATICWAITRD0_WAITRD_Pos                          0
#define EMC_STATICWAITRD0_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos)

// -----------------------------------  EMC_STATICWAITPAG0  ---------------------------------------
#define EMC_STATICWAITPAG0_WAITPAGE_Pos                       0
#define EMC_STATICWAITPAG0_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos)

// ------------------------------------  EMC_STATICWAITWR0  ---------------------------------------
#define EMC_STATICWAITWR0_WAITWR_Pos                          0
#define EMC_STATICWAITWR0_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos)

// -----------------------------------  EMC_STATICWAITTURN0  --------------------------------------
#define EMC_STATICWAITTURN0_WAITTURN_Pos                      0
#define EMC_STATICWAITTURN0_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos)

// ------------------------------------  EMC_STATICCONFIG1  ---------------------------------------
#define EMC_STATICCONFIG1_MW_Pos                              0
#define EMC_STATICCONFIG1_MW_Msk                              (0x03UL << EMC_STATICCONFIG1_MW_Pos)
#define EMC_STATICCONFIG1_PM_Pos                              3
#define EMC_STATICCONFIG1_PM_Msk                              (0x01UL << EMC_STATICCONFIG1_PM_Pos)
#define EMC_STATICCONFIG1_PC_Pos                              6
#define EMC_STATICCONFIG1_PC_Msk                              (0x01UL << EMC_STATICCONFIG1_PC_Pos)
#define EMC_STATICCONFIG1_PB_Pos                              7
#define EMC_STATICCONFIG1_PB_Msk                              (0x01UL << EMC_STATICCONFIG1_PB_Pos)
#define EMC_STATICCONFIG1_EW_Pos                              8
#define EMC_STATICCONFIG1_EW_Msk                              (0x01UL << EMC_STATICCONFIG1_EW_Pos)
#define EMC_STATICCONFIG1_B_Pos                               19
#define EMC_STATICCONFIG1_B_Msk                               (0x01UL << EMC_STATICCONFIG1_B_Pos)
#define EMC_STATICCONFIG1_P_Pos                               20
#define EMC_STATICCONFIG1_P_Msk                               (0x01UL << EMC_STATICCONFIG1_P_Pos)

// -----------------------------------  EMC_STATICWAITWEN1  ---------------------------------------
#define EMC_STATICWAITWEN1_WAITWEN_Pos                        0
#define EMC_STATICWAITWEN1_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos)

// -----------------------------------  EMC_STATICWAITOEN1  ---------------------------------------
#define EMC_STATICWAITOEN1_WAITOEN_Pos                        0
#define EMC_STATICWAITOEN1_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos)

// ------------------------------------  EMC_STATICWAITRD1  ---------------------------------------
#define EMC_STATICWAITRD1_WAITRD_Pos                          0
#define EMC_STATICWAITRD1_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos)

// -----------------------------------  EMC_STATICWAITPAG1  ---------------------------------------
#define EMC_STATICWAITPAG1_WAITPAGE_Pos                       0
#define EMC_STATICWAITPAG1_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos)

// ------------------------------------  EMC_STATICWAITWR1  ---------------------------------------
#define EMC_STATICWAITWR1_WAITWR_Pos                          0
#define EMC_STATICWAITWR1_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos)

// -----------------------------------  EMC_STATICWAITTURN1  --------------------------------------
#define EMC_STATICWAITTURN1_WAITTURN_Pos                      0
#define EMC_STATICWAITTURN1_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos)

// ------------------------------------  EMC_STATICCONFIG2  ---------------------------------------
#define EMC_STATICCONFIG2_MW_Pos                              0
#define EMC_STATICCONFIG2_MW_Msk                              (0x03UL << EMC_STATICCONFIG2_MW_Pos)
#define EMC_STATICCONFIG2_PM_Pos                              3
#define EMC_STATICCONFIG2_PM_Msk                              (0x01UL << EMC_STATICCONFIG2_PM_Pos)
#define EMC_STATICCONFIG2_PC_Pos                              6
#define EMC_STATICCONFIG2_PC_Msk                              (0x01UL << EMC_STATICCONFIG2_PC_Pos)
#define EMC_STATICCONFIG2_PB_Pos                              7
#define EMC_STATICCONFIG2_PB_Msk                              (0x01UL << EMC_STATICCONFIG2_PB_Pos)
#define EMC_STATICCONFIG2_EW_Pos                              8
#define EMC_STATICCONFIG2_EW_Msk                              (0x01UL << EMC_STATICCONFIG2_EW_Pos)
#define EMC_STATICCONFIG2_B_Pos                               19
#define EMC_STATICCONFIG2_B_Msk                               (0x01UL << EMC_STATICCONFIG2_B_Pos)
#define EMC_STATICCONFIG2_P_Pos                               20
#define EMC_STATICCONFIG2_P_Msk                               (0x01UL << EMC_STATICCONFIG2_P_Pos)

// -----------------------------------  EMC_STATICWAITWEN2  ---------------------------------------
#define EMC_STATICWAITWEN2_WAITWEN_Pos                        0
#define EMC_STATICWAITWEN2_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos)

// -----------------------------------  EMC_STATICWAITOEN2  ---------------------------------------
#define EMC_STATICWAITOEN2_WAITOEN_Pos                        0
#define EMC_STATICWAITOEN2_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos)

// ------------------------------------  EMC_STATICWAITRD2  ---------------------------------------
#define EMC_STATICWAITRD2_WAITRD_Pos                          0
#define EMC_STATICWAITRD2_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos)

// -----------------------------------  EMC_STATICWAITPAG2  ---------------------------------------
#define EMC_STATICWAITPAG2_WAITPAGE_Pos                       0
#define EMC_STATICWAITPAG2_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos)

// ------------------------------------  EMC_STATICWAITWR2  ---------------------------------------
#define EMC_STATICWAITWR2_WAITWR_Pos                          0
#define EMC_STATICWAITWR2_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos)

// -----------------------------------  EMC_STATICWAITTURN2  --------------------------------------
#define EMC_STATICWAITTURN2_WAITTURN_Pos                      0
#define EMC_STATICWAITTURN2_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos)

// ------------------------------------  EMC_STATICCONFIG3  ---------------------------------------
#define EMC_STATICCONFIG3_MW_Pos                              0
#define EMC_STATICCONFIG3_MW_Msk                              (0x03UL << EMC_STATICCONFIG3_MW_Pos)
#define EMC_STATICCONFIG3_PM_Pos                              3
#define EMC_STATICCONFIG3_PM_Msk                              (0x01UL << EMC_STATICCONFIG3_PM_Pos)
#define EMC_STATICCONFIG3_PC_Pos                              6
#define EMC_STATICCONFIG3_PC_Msk                              (0x01UL << EMC_STATICCONFIG3_PC_Pos)
#define EMC_STATICCONFIG3_PB_Pos                              7
#define EMC_STATICCONFIG3_PB_Msk                              (0x01UL << EMC_STATICCONFIG3_PB_Pos)
#define EMC_STATICCONFIG3_EW_Pos                              8
#define EMC_STATICCONFIG3_EW_Msk                              (0x01UL << EMC_STATICCONFIG3_EW_Pos)
#define EMC_STATICCONFIG3_B_Pos                               19
#define EMC_STATICCONFIG3_B_Msk                               (0x01UL << EMC_STATICCONFIG3_B_Pos)
#define EMC_STATICCONFIG3_P_Pos                               20
#define EMC_STATICCONFIG3_P_Msk                               (0x01UL << EMC_STATICCONFIG3_P_Pos)

// -----------------------------------  EMC_STATICWAITWEN3  ---------------------------------------
#define EMC_STATICWAITWEN3_WAITWEN_Pos                        0
#define EMC_STATICWAITWEN3_WAITWEN_Msk                        (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos)

// -----------------------------------  EMC_STATICWAITOEN3  ---------------------------------------
#define EMC_STATICWAITOEN3_WAITOEN_Pos                        0
#define EMC_STATICWAITOEN3_WAITOEN_Msk                        (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos)

// ------------------------------------  EMC_STATICWAITRD3  ---------------------------------------
#define EMC_STATICWAITRD3_WAITRD_Pos                          0
#define EMC_STATICWAITRD3_WAITRD_Msk                          (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos)

// -----------------------------------  EMC_STATICWAITPAG3  ---------------------------------------
#define EMC_STATICWAITPAG3_WAITPAGE_Pos                       0
#define EMC_STATICWAITPAG3_WAITPAGE_Msk                       (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos)

// ------------------------------------  EMC_STATICWAITWR3  ---------------------------------------
#define EMC_STATICWAITWR3_WAITWR_Pos                          0
#define EMC_STATICWAITWR3_WAITWR_Msk                          (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos)

// -----------------------------------  EMC_STATICWAITTURN3  --------------------------------------
#define EMC_STATICWAITTURN3_WAITTURN_Pos                      0
#define EMC_STATICWAITTURN3_WAITTURN_Msk                      (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 USB0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  USB0_CAPLENGTH  -----------------------------------------
#define USB0_CAPLENGTH_CAPLENGTH_Pos                          0
#define USB0_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos)
#define USB0_CAPLENGTH_HCIVERSION_Pos                         8
#define USB0_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos)

// -------------------------------------  USB0_HCSPARAMS  -----------------------------------------
#define USB0_HCSPARAMS_N_PORTS_Pos                            0
#define USB0_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos)
#define USB0_HCSPARAMS_PPC_Pos                                4
#define USB0_HCSPARAMS_PPC_Msk                                (0x01UL << USB0_HCSPARAMS_PPC_Pos)
#define USB0_HCSPARAMS_N_PCC_Pos                              8
#define USB0_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos)
#define USB0_HCSPARAMS_N_CC_Pos                               12
#define USB0_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB0_HCSPARAMS_N_CC_Pos)
#define USB0_HCSPARAMS_PI_Pos                                 16
#define USB0_HCSPARAMS_PI_Msk                                 (0x01UL << USB0_HCSPARAMS_PI_Pos)
#define USB0_HCSPARAMS_N_PTT_Pos                              20
#define USB0_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos)
#define USB0_HCSPARAMS_N_TT_Pos                               24
#define USB0_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB0_HCSPARAMS_N_TT_Pos)

// -------------------------------------  USB0_HCCPARAMS  -----------------------------------------
#define USB0_HCCPARAMS_ADC_Pos                                0
#define USB0_HCCPARAMS_ADC_Msk                                (0x01UL << USB0_HCCPARAMS_ADC_Pos)
#define USB0_HCCPARAMS_PFL_Pos                                1
#define USB0_HCCPARAMS_PFL_Msk                                (0x01UL << USB0_HCCPARAMS_PFL_Pos)
#define USB0_HCCPARAMS_ASP_Pos                                2
#define USB0_HCCPARAMS_ASP_Msk                                (0x01UL << USB0_HCCPARAMS_ASP_Pos)
#define USB0_HCCPARAMS_IST_Pos                                4
#define USB0_HCCPARAMS_IST_Msk                                (0x0fUL << USB0_HCCPARAMS_IST_Pos)
#define USB0_HCCPARAMS_EECP_Pos                               8
#define USB0_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos)

// -------------------------------------  USB0_DCIVERSION  ----------------------------------------
#define USB0_DCIVERSION_DCIVERSION_Pos                        0
#define USB0_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos)

// --------------------------------------  USB0_USBCMD_D  -----------------------------------------
#define USB0_USBCMD_D_RS_Pos                                  0
#define USB0_USBCMD_D_RS_Msk                                  (0x01UL << USB0_USBCMD_D_RS_Pos)
#define USB0_USBCMD_D_RST_Pos                                 1
#define USB0_USBCMD_D_RST_Msk                                 (0x01UL << USB0_USBCMD_D_RST_Pos)
#define USB0_USBCMD_D_SUTW_Pos                                13
#define USB0_USBCMD_D_SUTW_Msk                                (0x01UL << USB0_USBCMD_D_SUTW_Pos)
#define USB0_USBCMD_D_ATDTW_Pos                               14
#define USB0_USBCMD_D_ATDTW_Msk                               (0x01UL << USB0_USBCMD_D_ATDTW_Pos)
#define USB0_USBCMD_D_ITC_Pos                                 16
#define USB0_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_D_ITC_Pos)

// --------------------------------------  USB0_USBCMD_H  -----------------------------------------
#define USB0_USBCMD_H_RS_Pos                                  0
#define USB0_USBCMD_H_RS_Msk                                  (0x01UL << USB0_USBCMD_H_RS_Pos)
#define USB0_USBCMD_H_RST_Pos                                 1
#define USB0_USBCMD_H_RST_Msk                                 (0x01UL << USB0_USBCMD_H_RST_Pos)
#define USB0_USBCMD_H_FS0_Pos                                 2
#define USB0_USBCMD_H_FS0_Msk                                 (0x01UL << USB0_USBCMD_H_FS0_Pos)
#define USB0_USBCMD_H_FS1_Pos                                 3
#define USB0_USBCMD_H_FS1_Msk                                 (0x01UL << USB0_USBCMD_H_FS1_Pos)
#define USB0_USBCMD_H_PSE_Pos                                 4
#define USB0_USBCMD_H_PSE_Msk                                 (0x01UL << USB0_USBCMD_H_PSE_Pos)
#define USB0_USBCMD_H_ASE_Pos                                 5
#define USB0_USBCMD_H_ASE_Msk                                 (0x01UL << USB0_USBCMD_H_ASE_Pos)
#define USB0_USBCMD_H_IAA_Pos                                 6
#define USB0_USBCMD_H_IAA_Msk                                 (0x01UL << USB0_USBCMD_H_IAA_Pos)
#define USB0_USBCMD_H_ASP1_0_Pos                              8
#define USB0_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB0_USBCMD_H_ASP1_0_Pos)
#define USB0_USBCMD_H_ASPE_Pos                                11
#define USB0_USBCMD_H_ASPE_Msk                                (0x01UL << USB0_USBCMD_H_ASPE_Pos)
#define USB0_USBCMD_H_FS2_Pos                                 15
#define USB0_USBCMD_H_FS2_Msk                                 (0x01UL << USB0_USBCMD_H_FS2_Pos)
#define USB0_USBCMD_H_ITC_Pos                                 16
#define USB0_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB0_USBCMD_H_ITC_Pos)

// --------------------------------------  USB0_USBSTS_D  -----------------------------------------
#define USB0_USBSTS_D_UI_Pos                                  0
#define USB0_USBSTS_D_UI_Msk                                  (0x01UL << USB0_USBSTS_D_UI_Pos)
#define USB0_USBSTS_D_UEI_Pos                                 1
#define USB0_USBSTS_D_UEI_Msk                                 (0x01UL << USB0_USBSTS_D_UEI_Pos)
#define USB0_USBSTS_D_PCI_Pos                                 2
#define USB0_USBSTS_D_PCI_Msk                                 (0x01UL << USB0_USBSTS_D_PCI_Pos)
#define USB0_USBSTS_D_AAI_Pos                                 5
#define USB0_USBSTS_D_AAI_Msk                                 (0x01UL << USB0_USBSTS_D_AAI_Pos)
#define USB0_USBSTS_D_URI_Pos                                 6
#define USB0_USBSTS_D_URI_Msk                                 (0x01UL << USB0_USBSTS_D_URI_Pos)
#define USB0_USBSTS_D_SRI_Pos                                 7
#define USB0_USBSTS_D_SRI_Msk                                 (0x01UL << USB0_USBSTS_D_SRI_Pos)
#define USB0_USBSTS_D_SLI_Pos                                 8
#define USB0_USBSTS_D_SLI_Msk                                 (0x01UL << USB0_USBSTS_D_SLI_Pos)
#define USB0_USBSTS_D_NAKI_Pos                                16
#define USB0_USBSTS_D_NAKI_Msk                                (0x01UL << USB0_USBSTS_D_NAKI_Pos)

// --------------------------------------  USB0_USBSTS_H  -----------------------------------------
#define USB0_USBSTS_H_UI_Pos                                  0
#define USB0_USBSTS_H_UI_Msk                                  (0x01UL << USB0_USBSTS_H_UI_Pos)
#define USB0_USBSTS_H_UEI_Pos                                 1
#define USB0_USBSTS_H_UEI_Msk                                 (0x01UL << USB0_USBSTS_H_UEI_Pos)
#define USB0_USBSTS_H_PCI_Pos                                 2
#define USB0_USBSTS_H_PCI_Msk                                 (0x01UL << USB0_USBSTS_H_PCI_Pos)
#define USB0_USBSTS_H_FRI_Pos                                 3
#define USB0_USBSTS_H_FRI_Msk                                 (0x01UL << USB0_USBSTS_H_FRI_Pos)
#define USB0_USBSTS_H_AAI_Pos                                 5
#define USB0_USBSTS_H_AAI_Msk                                 (0x01UL << USB0_USBSTS_H_AAI_Pos)
#define USB0_USBSTS_H_SRI_Pos                                 7
#define USB0_USBSTS_H_SRI_Msk                                 (0x01UL << USB0_USBSTS_H_SRI_Pos)
#define USB0_USBSTS_H_HCH_Pos                                 12
#define USB0_USBSTS_H_HCH_Msk                                 (0x01UL << USB0_USBSTS_H_HCH_Pos)
#define USB0_USBSTS_H_RCL_Pos                                 13
#define USB0_USBSTS_H_RCL_Msk                                 (0x01UL << USB0_USBSTS_H_RCL_Pos)
#define USB0_USBSTS_H_PS_Pos                                  14
#define USB0_USBSTS_H_PS_Msk                                  (0x01UL << USB0_USBSTS_H_PS_Pos)
#define USB0_USBSTS_H_AS_Pos                                  15
#define USB0_USBSTS_H_AS_Msk                                  (0x01UL << USB0_USBSTS_H_AS_Pos)
#define USB0_USBSTS_H_UAI_Pos                                 18
#define USB0_USBSTS_H_UAI_Msk                                 (0x01UL << USB0_USBSTS_H_UAI_Pos)
#define USB0_USBSTS_H_UPI_Pos                                 19
#define USB0_USBSTS_H_UPI_Msk                                 (0x01UL << USB0_USBSTS_H_UPI_Pos)

// -------------------------------------  USB0_USBINTR_D  -----------------------------------------
#define USB0_USBINTR_D_UE_Pos                                 0
#define USB0_USBINTR_D_UE_Msk                                 (0x01UL << USB0_USBINTR_D_UE_Pos)
#define USB0_USBINTR_D_UEE_Pos                                1
#define USB0_USBINTR_D_UEE_Msk                                (0x01UL << USB0_USBINTR_D_UEE_Pos)
#define USB0_USBINTR_D_PCE_Pos                                2
#define USB0_USBINTR_D_PCE_Msk                                (0x01UL << USB0_USBINTR_D_PCE_Pos)
#define USB0_USBINTR_D_URE_Pos                                6
#define USB0_USBINTR_D_URE_Msk                                (0x01UL << USB0_USBINTR_D_URE_Pos)
#define USB0_USBINTR_D_SRE_Pos                                7
#define USB0_USBINTR_D_SRE_Msk                                (0x01UL << USB0_USBINTR_D_SRE_Pos)
#define USB0_USBINTR_D_SLE_Pos                                8
#define USB0_USBINTR_D_SLE_Msk                                (0x01UL << USB0_USBINTR_D_SLE_Pos)
#define USB0_USBINTR_D_NAKE_Pos                               16
#define USB0_USBINTR_D_NAKE_Msk                               (0x01UL << USB0_USBINTR_D_NAKE_Pos)

// -------------------------------------  USB0_USBINTR_H  -----------------------------------------
#define USB0_USBINTR_H_UE_Pos                                 0
#define USB0_USBINTR_H_UE_Msk                                 (0x01UL << USB0_USBINTR_H_UE_Pos)
#define USB0_USBINTR_H_UEE_Pos                                1
#define USB0_USBINTR_H_UEE_Msk                                (0x01UL << USB0_USBINTR_H_UEE_Pos)
#define USB0_USBINTR_H_PCE_Pos                                2
#define USB0_USBINTR_H_PCE_Msk                                (0x01UL << USB0_USBINTR_H_PCE_Pos)
#define USB0_USBINTR_H_FRE_Pos                                3
#define USB0_USBINTR_H_FRE_Msk                                (0x01UL << USB0_USBINTR_H_FRE_Pos)
#define USB0_USBINTR_H_AAE_Pos                                5
#define USB0_USBINTR_H_AAE_Msk                                (0x01UL << USB0_USBINTR_H_AAE_Pos)
#define USB0_USBINTR_H_SRE_Pos                                7
#define USB0_USBINTR_H_SRE_Msk                                (0x01UL << USB0_USBINTR_H_SRE_Pos)
#define USB0_USBINTR_H_UAIE_Pos                               18
#define USB0_USBINTR_H_UAIE_Msk                               (0x01UL << USB0_USBINTR_H_UAIE_Pos)
#define USB0_USBINTR_H_UPIA_Pos                               19
#define USB0_USBINTR_H_UPIA_Msk                               (0x01UL << USB0_USBINTR_H_UPIA_Pos)

// -------------------------------------  USB0_FRINDEX_D  -----------------------------------------
#define USB0_FRINDEX_D_FRINDEX2_0_Pos                         0
#define USB0_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos)
#define USB0_FRINDEX_D_FRINDEX13_3_Pos                        3
#define USB0_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos)

// -------------------------------------  USB0_FRINDEX_H  -----------------------------------------
#define USB0_FRINDEX_H_FRINDEX2_0_Pos                         0
#define USB0_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos)
#define USB0_FRINDEX_H_FRINDEX12_3_Pos                        3
#define USB0_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos)

// -------------------------------------  USB0_DEVICEADDR  ----------------------------------------
#define USB0_DEVICEADDR_USBADRA_Pos                           24
#define USB0_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB0_DEVICEADDR_USBADRA_Pos)
#define USB0_DEVICEADDR_USBADR_Pos                            25
#define USB0_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB0_DEVICEADDR_USBADR_Pos)

// ----------------------------------  USB0_PERIODICLISTBASE  -------------------------------------
#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos                12
#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)

// ----------------------------------  USB0_ENDPOINTLISTADDR  -------------------------------------
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos)

// -----------------------------------  USB0_ASYNCLISTADDR  ---------------------------------------
#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos                    5
#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos)

// ---------------------------------------  USB0_TTCTRL  ------------------------------------------
#define USB0_TTCTRL_TTHA_Pos                                  24
#define USB0_TTCTRL_TTHA_Msk                                  (0x7fUL << USB0_TTCTRL_TTHA_Pos)

// -------------------------------------  USB0_BURSTSIZE  -----------------------------------------
#define USB0_BURSTSIZE_RXPBURST_Pos                           0
#define USB0_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos)
#define USB0_BURSTSIZE_TXPBURST_Pos                           8
#define USB0_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos)

// ------------------------------------  USB0_TXFILLTUNING  ---------------------------------------
#define USB0_TXFILLTUNING_TXSCHOH_Pos                         0
#define USB0_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos)
#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos                     8
#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos)
#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos                     16
#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos)

// -------------------------------------  USB0_BINTERVAL  -----------------------------------------
#define USB0_BINTERVAL_BINT_Pos                               0
#define USB0_BINTERVAL_BINT_Msk                               (0x0fUL << USB0_BINTERVAL_BINT_Pos)

// --------------------------------------  USB0_ENDPTNAK  -----------------------------------------
#define USB0_ENDPTNAK_EPRN0_Pos                               0
#define USB0_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN0_Pos)
#define USB0_ENDPTNAK_EPRN1_Pos                               1
#define USB0_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN1_Pos)
#define USB0_ENDPTNAK_EPRN2_Pos                               2
#define USB0_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN2_Pos)
#define USB0_ENDPTNAK_EPRN3_Pos                               3
#define USB0_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN3_Pos)
#define USB0_ENDPTNAK_EPRN4_Pos                               4
#define USB0_ENDPTNAK_EPRN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN4_Pos)
#define USB0_ENDPTNAK_EPRN5_Pos                               5
#define USB0_ENDPTNAK_EPRN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPRN5_Pos)
#define USB0_ENDPTNAK_EPTN0_Pos                               16
#define USB0_ENDPTNAK_EPTN0_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN0_Pos)
#define USB0_ENDPTNAK_EPTN1_Pos                               17
#define USB0_ENDPTNAK_EPTN1_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN1_Pos)
#define USB0_ENDPTNAK_EPTN2_Pos                               18
#define USB0_ENDPTNAK_EPTN2_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN2_Pos)
#define USB0_ENDPTNAK_EPTN3_Pos                               19
#define USB0_ENDPTNAK_EPTN3_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN3_Pos)
#define USB0_ENDPTNAK_EPTN4_Pos                               20
#define USB0_ENDPTNAK_EPTN4_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN4_Pos)
#define USB0_ENDPTNAK_EPTN5_Pos                               21
#define USB0_ENDPTNAK_EPTN5_Msk                               (0x01UL << USB0_ENDPTNAK_EPTN5_Pos)

// -------------------------------------  USB0_ENDPTNAKEN  ----------------------------------------
#define USB0_ENDPTNAKEN_EPRNE0_Pos                            0
#define USB0_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos)
#define USB0_ENDPTNAKEN_EPRNE1_Pos                            1
#define USB0_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos)
#define USB0_ENDPTNAKEN_EPRNE2_Pos                            2
#define USB0_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos)
#define USB0_ENDPTNAKEN_EPRNE3_Pos                            3
#define USB0_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos)
#define USB0_ENDPTNAKEN_EPRNE4_Pos                            4
#define USB0_ENDPTNAKEN_EPRNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos)
#define USB0_ENDPTNAKEN_EPRNE5_Pos                            5
#define USB0_ENDPTNAKEN_EPRNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos)
#define USB0_ENDPTNAKEN_EPTNE0_Pos                            16
#define USB0_ENDPTNAKEN_EPTNE0_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos)
#define USB0_ENDPTNAKEN_EPTNE1_Pos                            17
#define USB0_ENDPTNAKEN_EPTNE1_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos)
#define USB0_ENDPTNAKEN_EPTNE2_Pos                            18
#define USB0_ENDPTNAKEN_EPTNE2_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos)
#define USB0_ENDPTNAKEN_EPTNE3_Pos                            19
#define USB0_ENDPTNAKEN_EPTNE3_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos)
#define USB0_ENDPTNAKEN_EPTNE4_Pos                            20
#define USB0_ENDPTNAKEN_EPTNE4_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos)
#define USB0_ENDPTNAKEN_EPTNE5_Pos                            21
#define USB0_ENDPTNAKEN_EPTNE5_Msk                            (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos)

// -------------------------------------  USB0_PORTSC1_D  -----------------------------------------
#define USB0_PORTSC1_D_CCS_Pos                                0
#define USB0_PORTSC1_D_CCS_Msk                                (0x01UL << USB0_PORTSC1_D_CCS_Pos)
#define USB0_PORTSC1_D_PE_Pos                                 2
#define USB0_PORTSC1_D_PE_Msk                                 (0x01UL << USB0_PORTSC1_D_PE_Pos)
#define USB0_PORTSC1_D_PEC_Pos                                3
#define USB0_PORTSC1_D_PEC_Msk                                (0x01UL << USB0_PORTSC1_D_PEC_Pos)
#define USB0_PORTSC1_D_FPR_Pos                                6
#define USB0_PORTSC1_D_FPR_Msk                                (0x01UL << USB0_PORTSC1_D_FPR_Pos)
#define USB0_PORTSC1_D_SUSP_Pos                               7
#define USB0_PORTSC1_D_SUSP_Msk                               (0x01UL << USB0_PORTSC1_D_SUSP_Pos)
#define USB0_PORTSC1_D_PR_Pos                                 8
#define USB0_PORTSC1_D_PR_Msk                                 (0x01UL << USB0_PORTSC1_D_PR_Pos)
#define USB0_PORTSC1_D_HSP_Pos                                9
#define USB0_PORTSC1_D_HSP_Msk                                (0x01UL << USB0_PORTSC1_D_HSP_Pos)
#define USB0_PORTSC1_D_PIC1_0_Pos                             14
#define USB0_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos)
#define USB0_PORTSC1_D_PTC3_0_Pos                             16
#define USB0_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos)
#define USB0_PORTSC1_D_PHCD_Pos                               23
#define USB0_PORTSC1_D_PHCD_Msk                               (0x01UL << USB0_PORTSC1_D_PHCD_Pos)
#define USB0_PORTSC1_D_PFSC_Pos                               24
#define USB0_PORTSC1_D_PFSC_Msk                               (0x01UL << USB0_PORTSC1_D_PFSC_Pos)
#define USB0_PORTSC1_D_PSPD_Pos                               26
#define USB0_PORTSC1_D_PSPD_Msk                               (0x03UL << USB0_PORTSC1_D_PSPD_Pos)

// -------------------------------------  USB0_PORTSC1_H  -----------------------------------------
#define USB0_PORTSC1_H_CCS_Pos                                0
#define USB0_PORTSC1_H_CCS_Msk                                (0x01UL << USB0_PORTSC1_H_CCS_Pos)
#define USB0_PORTSC1_H_CSC_Pos                                1
#define USB0_PORTSC1_H_CSC_Msk                                (0x01UL << USB0_PORTSC1_H_CSC_Pos)
#define USB0_PORTSC1_H_PE_Pos                                 2
#define USB0_PORTSC1_H_PE_Msk                                 (0x01UL << USB0_PORTSC1_H_PE_Pos)
#define USB0_PORTSC1_H_PEC_Pos                                3
#define USB0_PORTSC1_H_PEC_Msk                                (0x01UL << USB0_PORTSC1_H_PEC_Pos)
#define USB0_PORTSC1_H_OCA_Pos                                4
#define USB0_PORTSC1_H_OCA_Msk                                (0x01UL << USB0_PORTSC1_H_OCA_Pos)
#define USB0_PORTSC1_H_OCC_Pos                                5
#define USB0_PORTSC1_H_OCC_Msk                                (0x01UL << USB0_PORTSC1_H_OCC_Pos)
#define USB0_PORTSC1_H_FPR_Pos                                6
#define USB0_PORTSC1_H_FPR_Msk                                (0x01UL << USB0_PORTSC1_H_FPR_Pos)
#define USB0_PORTSC1_H_SUSP_Pos                               7
#define USB0_PORTSC1_H_SUSP_Msk                               (0x01UL << USB0_PORTSC1_H_SUSP_Pos)
#define USB0_PORTSC1_H_PR_Pos                                 8
#define USB0_PORTSC1_H_PR_Msk                                 (0x01UL << USB0_PORTSC1_H_PR_Pos)
#define USB0_PORTSC1_H_HSP_Pos                                9
#define USB0_PORTSC1_H_HSP_Msk                                (0x01UL << USB0_PORTSC1_H_HSP_Pos)
#define USB0_PORTSC1_H_LS_Pos                                 10
#define USB0_PORTSC1_H_LS_Msk                                 (0x03UL << USB0_PORTSC1_H_LS_Pos)
#define USB0_PORTSC1_H_PP_Pos                                 12
#define USB0_PORTSC1_H_PP_Msk                                 (0x01UL << USB0_PORTSC1_H_PP_Pos)
#define USB0_PORTSC1_H_PIC1_0_Pos                             14
#define USB0_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos)
#define USB0_PORTSC1_H_PTC3_0_Pos                             16
#define USB0_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos)
#define USB0_PORTSC1_H_WKCN_Pos                               20
#define USB0_PORTSC1_H_WKCN_Msk                               (0x01UL << USB0_PORTSC1_H_WKCN_Pos)
#define USB0_PORTSC1_H_WKDC_Pos                               21
#define USB0_PORTSC1_H_WKDC_Msk                               (0x01UL << USB0_PORTSC1_H_WKDC_Pos)
#define USB0_PORTSC1_H_WKOC_Pos                               22
#define USB0_PORTSC1_H_WKOC_Msk                               (0x01UL << USB0_PORTSC1_H_WKOC_Pos)
#define USB0_PORTSC1_H_PHCD_Pos                               23
#define USB0_PORTSC1_H_PHCD_Msk                               (0x01UL << USB0_PORTSC1_H_PHCD_Pos)
#define USB0_PORTSC1_H_PFSC_Pos                               24
#define USB0_PORTSC1_H_PFSC_Msk                               (0x01UL << USB0_PORTSC1_H_PFSC_Pos)
#define USB0_PORTSC1_H_PSPD_Pos                               26
#define USB0_PORTSC1_H_PSPD_Msk                               (0x03UL << USB0_PORTSC1_H_PSPD_Pos)

// ---------------------------------------  USB0_OTGSC  -------------------------------------------
#define USB0_OTGSC_VD_Pos                                     0
#define USB0_OTGSC_VD_Msk                                     (0x01UL << USB0_OTGSC_VD_Pos)
#define USB0_OTGSC_VC_Pos                                     1
#define USB0_OTGSC_VC_Msk                                     (0x01UL << USB0_OTGSC_VC_Pos)
#define USB0_OTGSC_HAAR_Pos                                   2
#define USB0_OTGSC_HAAR_Msk                                   (0x01UL << USB0_OTGSC_HAAR_Pos)
#define USB0_OTGSC_OT_Pos                                     3
#define USB0_OTGSC_OT_Msk                                     (0x01UL << USB0_OTGSC_OT_Pos)
#define USB0_OTGSC_DP_Pos                                     4
#define USB0_OTGSC_DP_Msk                                     (0x01UL << USB0_OTGSC_DP_Pos)
#define USB0_OTGSC_IDPU_Pos                                   5
#define USB0_OTGSC_IDPU_Msk                                   (0x01UL << USB0_OTGSC_IDPU_Pos)
#define USB0_OTGSC_HADP_Pos                                   6
#define USB0_OTGSC_HADP_Msk                                   (0x01UL << USB0_OTGSC_HADP_Pos)
#define USB0_OTGSC_HABA_Pos                                   7
#define USB0_OTGSC_HABA_Msk                                   (0x01UL << USB0_OTGSC_HABA_Pos)
#define USB0_OTGSC_ID_Pos                                     8
#define USB0_OTGSC_ID_Msk                                     (0x01UL << USB0_OTGSC_ID_Pos)
#define USB0_OTGSC_AVV_Pos                                    9
#define USB0_OTGSC_AVV_Msk                                    (0x01UL << USB0_OTGSC_AVV_Pos)
#define USB0_OTGSC_ASV_Pos                                    10
#define USB0_OTGSC_ASV_Msk                                    (0x01UL << USB0_OTGSC_ASV_Pos)
#define USB0_OTGSC_BSV_Pos                                    11
#define USB0_OTGSC_BSV_Msk                                    (0x01UL << USB0_OTGSC_BSV_Pos)
#define USB0_OTGSC_BSE_Pos                                    12
#define USB0_OTGSC_BSE_Msk                                    (0x01UL << USB0_OTGSC_BSE_Pos)
#define USB0_OTGSC_MS1T_Pos                                   13
#define USB0_OTGSC_MS1T_Msk                                   (0x01UL << USB0_OTGSC_MS1T_Pos)
#define USB0_OTGSC_DPS_Pos                                    14
#define USB0_OTGSC_DPS_Msk                                    (0x01UL << USB0_OTGSC_DPS_Pos)
#define USB0_OTGSC_IDIS_Pos                                   16
#define USB0_OTGSC_IDIS_Msk                                   (0x01UL << USB0_OTGSC_IDIS_Pos)
#define USB0_OTGSC_AVVIS_Pos                                  17
#define USB0_OTGSC_AVVIS_Msk                                  (0x01UL << USB0_OTGSC_AVVIS_Pos)
#define USB0_OTGSC_ASVIS_Pos                                  18
#define USB0_OTGSC_ASVIS_Msk                                  (0x01UL << USB0_OTGSC_ASVIS_Pos)
#define USB0_OTGSC_BSVIS_Pos                                  19
#define USB0_OTGSC_BSVIS_Msk                                  (0x01UL << USB0_OTGSC_BSVIS_Pos)
#define USB0_OTGSC_BSEIS_Pos                                  20
#define USB0_OTGSC_BSEIS_Msk                                  (0x01UL << USB0_OTGSC_BSEIS_Pos)
#define USB0_OTGSC_ms1S_Pos                                   21
#define USB0_OTGSC_ms1S_Msk                                   (0x01UL << USB0_OTGSC_ms1S_Pos)
#define USB0_OTGSC_DPIS_Pos                                   22
#define USB0_OTGSC_DPIS_Msk                                   (0x01UL << USB0_OTGSC_DPIS_Pos)
#define USB0_OTGSC_IDIE_Pos                                   24
#define USB0_OTGSC_IDIE_Msk                                   (0x01UL << USB0_OTGSC_IDIE_Pos)
#define USB0_OTGSC_AVVIE_Pos                                  25
#define USB0_OTGSC_AVVIE_Msk                                  (0x01UL << USB0_OTGSC_AVVIE_Pos)
#define USB0_OTGSC_ASVIE_Pos                                  26
#define USB0_OTGSC_ASVIE_Msk                                  (0x01UL << USB0_OTGSC_ASVIE_Pos)
#define USB0_OTGSC_BSVIE_Pos                                  27
#define USB0_OTGSC_BSVIE_Msk                                  (0x01UL << USB0_OTGSC_BSVIE_Pos)
#define USB0_OTGSC_BSEIE_Pos                                  28
#define USB0_OTGSC_BSEIE_Msk                                  (0x01UL << USB0_OTGSC_BSEIE_Pos)
#define USB0_OTGSC_MS1E_Pos                                   29
#define USB0_OTGSC_MS1E_Msk                                   (0x01UL << USB0_OTGSC_MS1E_Pos)
#define USB0_OTGSC_DPIE_Pos                                   30
#define USB0_OTGSC_DPIE_Msk                                   (0x01UL << USB0_OTGSC_DPIE_Pos)

// -------------------------------------  USB0_USBMODE_D  -----------------------------------------
#define USB0_USBMODE_D_CM1_0_Pos                              0
#define USB0_USBMODE_D_CM1_0_Msk                              (0x03UL << USB0_USBMODE_D_CM1_0_Pos)
#define USB0_USBMODE_D_ES_Pos                                 2
#define USB0_USBMODE_D_ES_Msk                                 (0x01UL << USB0_USBMODE_D_ES_Pos)
#define USB0_USBMODE_D_SLOM_Pos                               3
#define USB0_USBMODE_D_SLOM_Msk                               (0x01UL << USB0_USBMODE_D_SLOM_Pos)
#define USB0_USBMODE_D_SDIS_Pos                               4
#define USB0_USBMODE_D_SDIS_Msk                               (0x01UL << USB0_USBMODE_D_SDIS_Pos)

// -------------------------------------  USB0_USBMODE_H  -----------------------------------------
#define USB0_USBMODE_H_CM_Pos                                 0
#define USB0_USBMODE_H_CM_Msk                                 (0x03UL << USB0_USBMODE_H_CM_Pos)
#define USB0_USBMODE_H_ES_Pos                                 2
#define USB0_USBMODE_H_ES_Msk                                 (0x01UL << USB0_USBMODE_H_ES_Pos)
#define USB0_USBMODE_H_SDIS_Pos                               4
#define USB0_USBMODE_H_SDIS_Msk                               (0x01UL << USB0_USBMODE_H_SDIS_Pos)
#define USB0_USBMODE_H_VBPS_Pos                               5
#define USB0_USBMODE_H_VBPS_Msk                               (0x01UL << USB0_USBMODE_H_VBPS_Pos)

// -----------------------------------  USB0_ENDPTSETUPSTAT  --------------------------------------
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos               4
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos)
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos               5
#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk               (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos)

// -------------------------------------  USB0_ENDPTPRIME  ----------------------------------------
#define USB0_ENDPTPRIME_PERB0_Pos                             0
#define USB0_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB0_Pos)
#define USB0_ENDPTPRIME_PERB1_Pos                             1
#define USB0_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB1_Pos)
#define USB0_ENDPTPRIME_PERB2_Pos                             2
#define USB0_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB2_Pos)
#define USB0_ENDPTPRIME_PERB3_Pos                             3
#define USB0_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB3_Pos)
#define USB0_ENDPTPRIME_PERB4_Pos                             4
#define USB0_ENDPTPRIME_PERB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB4_Pos)
#define USB0_ENDPTPRIME_PERB5_Pos                             5
#define USB0_ENDPTPRIME_PERB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PERB5_Pos)
#define USB0_ENDPTPRIME_PETB0_Pos                             16
#define USB0_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB0_Pos)
#define USB0_ENDPTPRIME_PETB1_Pos                             17
#define USB0_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB1_Pos)
#define USB0_ENDPTPRIME_PETB2_Pos                             18
#define USB0_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB2_Pos)
#define USB0_ENDPTPRIME_PETB3_Pos                             19
#define USB0_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB3_Pos)
#define USB0_ENDPTPRIME_PETB4_Pos                             20
#define USB0_ENDPTPRIME_PETB4_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB4_Pos)
#define USB0_ENDPTPRIME_PETB5_Pos                             21
#define USB0_ENDPTPRIME_PETB5_Msk                             (0x01UL << USB0_ENDPTPRIME_PETB5_Pos)

// -------------------------------------  USB0_ENDPTFLUSH  ----------------------------------------
#define USB0_ENDPTFLUSH_FERB0_Pos                             0
#define USB0_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos)
#define USB0_ENDPTFLUSH_FERB1_Pos                             1
#define USB0_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos)
#define USB0_ENDPTFLUSH_FERB2_Pos                             2
#define USB0_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos)
#define USB0_ENDPTFLUSH_FERB3_Pos                             3
#define USB0_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos)
#define USB0_ENDPTFLUSH_FERB4_Pos                             4
#define USB0_ENDPTFLUSH_FERB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos)
#define USB0_ENDPTFLUSH_FERB5_Pos                             5
#define USB0_ENDPTFLUSH_FERB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos)
#define USB0_ENDPTFLUSH_FETB0_Pos                             16
#define USB0_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos)
#define USB0_ENDPTFLUSH_FETB1_Pos                             17
#define USB0_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos)
#define USB0_ENDPTFLUSH_FETB2_Pos                             18
#define USB0_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos)
#define USB0_ENDPTFLUSH_FETB3_Pos                             19
#define USB0_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos)
#define USB0_ENDPTFLUSH_FETB4_Pos                             20
#define USB0_ENDPTFLUSH_FETB4_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos)
#define USB0_ENDPTFLUSH_FETB5_Pos                             21
#define USB0_ENDPTFLUSH_FETB5_Msk                             (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos)

// -------------------------------------  USB0_ENDPTSTAT  -----------------------------------------
#define USB0_ENDPTSTAT_ERBR0_Pos                              0
#define USB0_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos)
#define USB0_ENDPTSTAT_ERBR1_Pos                              1
#define USB0_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos)
#define USB0_ENDPTSTAT_ERBR2_Pos                              2
#define USB0_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos)
#define USB0_ENDPTSTAT_ERBR3_Pos                              3
#define USB0_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos)
#define USB0_ENDPTSTAT_ERBR4_Pos                              4
#define USB0_ENDPTSTAT_ERBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos)
#define USB0_ENDPTSTAT_ERBR5_Pos                              5
#define USB0_ENDPTSTAT_ERBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos)
#define USB0_ENDPTSTAT_ETBR0_Pos                              16
#define USB0_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos)
#define USB0_ENDPTSTAT_ETBR1_Pos                              17
#define USB0_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos)
#define USB0_ENDPTSTAT_ETBR2_Pos                              18
#define USB0_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos)
#define USB0_ENDPTSTAT_ETBR3_Pos                              19
#define USB0_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos)
#define USB0_ENDPTSTAT_ETBR4_Pos                              20
#define USB0_ENDPTSTAT_ETBR4_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos)
#define USB0_ENDPTSTAT_ETBR5_Pos                              21
#define USB0_ENDPTSTAT_ETBR5_Msk                              (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos)

// -----------------------------------  USB0_ENDPTCOMPLETE  ---------------------------------------
#define USB0_ENDPTCOMPLETE_ERCE0_Pos                          0
#define USB0_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos)
#define USB0_ENDPTCOMPLETE_ERCE1_Pos                          1
#define USB0_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos)
#define USB0_ENDPTCOMPLETE_ERCE2_Pos                          2
#define USB0_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos)
#define USB0_ENDPTCOMPLETE_ERCE3_Pos                          3
#define USB0_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos)
#define USB0_ENDPTCOMPLETE_ERCE4_Pos                          4
#define USB0_ENDPTCOMPLETE_ERCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos)
#define USB0_ENDPTCOMPLETE_ERCE5_Pos                          5
#define USB0_ENDPTCOMPLETE_ERCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos)
#define USB0_ENDPTCOMPLETE_ETCE0_Pos                          16
#define USB0_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos)
#define USB0_ENDPTCOMPLETE_ETCE1_Pos                          17
#define USB0_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos)
#define USB0_ENDPTCOMPLETE_ETCE2_Pos                          18
#define USB0_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos)
#define USB0_ENDPTCOMPLETE_ETCE3_Pos                          19
#define USB0_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos)
#define USB0_ENDPTCOMPLETE_ETCE4_Pos                          20
#define USB0_ENDPTCOMPLETE_ETCE4_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos)
#define USB0_ENDPTCOMPLETE_ETCE5_Pos                          21
#define USB0_ENDPTCOMPLETE_ETCE5_Msk                          (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos)

// -------------------------------------  USB0_ENDPTCTRL0  ----------------------------------------
#define USB0_ENDPTCTRL0_RXS_Pos                               0
#define USB0_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXS_Pos)
#define USB0_ENDPTCTRL0_RXT1_0_Pos                            2
#define USB0_ENDPTCTRL0_RXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos)
#define USB0_ENDPTCTRL0_RXE_Pos                               7
#define USB0_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_RXE_Pos)
#define USB0_ENDPTCTRL0_TXS_Pos                               16
#define USB0_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXS_Pos)
#define USB0_ENDPTCTRL0_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL0_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos)
#define USB0_ENDPTCTRL0_TXE_Pos                               23
#define USB0_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL0_TXE_Pos)

// -------------------------------------  USB0_ENDPTCTRL1  ----------------------------------------
#define USB0_ENDPTCTRL1_RXS_Pos                               0
#define USB0_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXS_Pos)
#define USB0_ENDPTCTRL1_RXT_Pos                               2
#define USB0_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL1_RXT_Pos)
#define USB0_ENDPTCTRL1_RXI_Pos                               5
#define USB0_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXI_Pos)
#define USB0_ENDPTCTRL1_RXR_Pos                               6
#define USB0_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXR_Pos)
#define USB0_ENDPTCTRL1_RXE_Pos                               7
#define USB0_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_RXE_Pos)
#define USB0_ENDPTCTRL1_TXS_Pos                               16
#define USB0_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXS_Pos)
#define USB0_ENDPTCTRL1_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL1_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos)
#define USB0_ENDPTCTRL1_TXI_Pos                               21
#define USB0_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXI_Pos)
#define USB0_ENDPTCTRL1_TXR_Pos                               22
#define USB0_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXR_Pos)
#define USB0_ENDPTCTRL1_TXE_Pos                               23
#define USB0_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL1_TXE_Pos)

// -------------------------------------  USB0_ENDPTCTRL2  ----------------------------------------
#define USB0_ENDPTCTRL2_RXS_Pos                               0
#define USB0_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXS_Pos)
#define USB0_ENDPTCTRL2_RXT_Pos                               2
#define USB0_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL2_RXT_Pos)
#define USB0_ENDPTCTRL2_RXI_Pos                               5
#define USB0_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXI_Pos)
#define USB0_ENDPTCTRL2_RXR_Pos                               6
#define USB0_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXR_Pos)
#define USB0_ENDPTCTRL2_RXE_Pos                               7
#define USB0_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_RXE_Pos)
#define USB0_ENDPTCTRL2_TXS_Pos                               16
#define USB0_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXS_Pos)
#define USB0_ENDPTCTRL2_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL2_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos)
#define USB0_ENDPTCTRL2_TXI_Pos                               21
#define USB0_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXI_Pos)
#define USB0_ENDPTCTRL2_TXR_Pos                               22
#define USB0_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXR_Pos)
#define USB0_ENDPTCTRL2_TXE_Pos                               23
#define USB0_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL2_TXE_Pos)

// -------------------------------------  USB0_ENDPTCTRL3  ----------------------------------------
#define USB0_ENDPTCTRL3_RXS_Pos                               0
#define USB0_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXS_Pos)
#define USB0_ENDPTCTRL3_RXT_Pos                               2
#define USB0_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL3_RXT_Pos)
#define USB0_ENDPTCTRL3_RXI_Pos                               5
#define USB0_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXI_Pos)
#define USB0_ENDPTCTRL3_RXR_Pos                               6
#define USB0_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXR_Pos)
#define USB0_ENDPTCTRL3_RXE_Pos                               7
#define USB0_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_RXE_Pos)
#define USB0_ENDPTCTRL3_TXS_Pos                               16
#define USB0_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXS_Pos)
#define USB0_ENDPTCTRL3_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL3_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos)
#define USB0_ENDPTCTRL3_TXI_Pos                               21
#define USB0_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXI_Pos)
#define USB0_ENDPTCTRL3_TXR_Pos                               22
#define USB0_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXR_Pos)
#define USB0_ENDPTCTRL3_TXE_Pos                               23
#define USB0_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL3_TXE_Pos)

// -------------------------------------  USB0_ENDPTCTRL4  ----------------------------------------
#define USB0_ENDPTCTRL4_RXS_Pos                               0
#define USB0_ENDPTCTRL4_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXS_Pos)
#define USB0_ENDPTCTRL4_RXT_Pos                               2
#define USB0_ENDPTCTRL4_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL4_RXT_Pos)
#define USB0_ENDPTCTRL4_RXI_Pos                               5
#define USB0_ENDPTCTRL4_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXI_Pos)
#define USB0_ENDPTCTRL4_RXR_Pos                               6
#define USB0_ENDPTCTRL4_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXR_Pos)
#define USB0_ENDPTCTRL4_RXE_Pos                               7
#define USB0_ENDPTCTRL4_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_RXE_Pos)
#define USB0_ENDPTCTRL4_TXS_Pos                               16
#define USB0_ENDPTCTRL4_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXS_Pos)
#define USB0_ENDPTCTRL4_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL4_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos)
#define USB0_ENDPTCTRL4_TXI_Pos                               21
#define USB0_ENDPTCTRL4_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXI_Pos)
#define USB0_ENDPTCTRL4_TXR_Pos                               22
#define USB0_ENDPTCTRL4_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXR_Pos)
#define USB0_ENDPTCTRL4_TXE_Pos                               23
#define USB0_ENDPTCTRL4_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL4_TXE_Pos)

// -------------------------------------  USB0_ENDPTCTRL5  ----------------------------------------
#define USB0_ENDPTCTRL5_RXS_Pos                               0
#define USB0_ENDPTCTRL5_RXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXS_Pos)
#define USB0_ENDPTCTRL5_RXT_Pos                               2
#define USB0_ENDPTCTRL5_RXT_Msk                               (0x03UL << USB0_ENDPTCTRL5_RXT_Pos)
#define USB0_ENDPTCTRL5_RXI_Pos                               5
#define USB0_ENDPTCTRL5_RXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXI_Pos)
#define USB0_ENDPTCTRL5_RXR_Pos                               6
#define USB0_ENDPTCTRL5_RXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXR_Pos)
#define USB0_ENDPTCTRL5_RXE_Pos                               7
#define USB0_ENDPTCTRL5_RXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_RXE_Pos)
#define USB0_ENDPTCTRL5_TXS_Pos                               16
#define USB0_ENDPTCTRL5_TXS_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXS_Pos)
#define USB0_ENDPTCTRL5_TXT1_0_Pos                            18
#define USB0_ENDPTCTRL5_TXT1_0_Msk                            (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos)
#define USB0_ENDPTCTRL5_TXI_Pos                               21
#define USB0_ENDPTCTRL5_TXI_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXI_Pos)
#define USB0_ENDPTCTRL5_TXR_Pos                               22
#define USB0_ENDPTCTRL5_TXR_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXR_Pos)
#define USB0_ENDPTCTRL5_TXE_Pos                               23
#define USB0_ENDPTCTRL5_TXE_Msk                               (0x01UL << USB0_ENDPTCTRL5_TXE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 USB1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  USB1_CAPLENGTH  -----------------------------------------
#define USB1_CAPLENGTH_CAPLENGTH_Pos                          0
#define USB1_CAPLENGTH_CAPLENGTH_Msk                          (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos)
#define USB1_CAPLENGTH_HCIVERSION_Pos                         8
#define USB1_CAPLENGTH_HCIVERSION_Msk                         (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos)

// -------------------------------------  USB1_HCSPARAMS  -----------------------------------------
#define USB1_HCSPARAMS_N_PORTS_Pos                            0
#define USB1_HCSPARAMS_N_PORTS_Msk                            (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos)
#define USB1_HCSPARAMS_PPC_Pos                                4
#define USB1_HCSPARAMS_PPC_Msk                                (0x01UL << USB1_HCSPARAMS_PPC_Pos)
#define USB1_HCSPARAMS_N_PCC_Pos                              8
#define USB1_HCSPARAMS_N_PCC_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos)
#define USB1_HCSPARAMS_N_CC_Pos                               12
#define USB1_HCSPARAMS_N_CC_Msk                               (0x0fUL << USB1_HCSPARAMS_N_CC_Pos)
#define USB1_HCSPARAMS_PI_Pos                                 16
#define USB1_HCSPARAMS_PI_Msk                                 (0x01UL << USB1_HCSPARAMS_PI_Pos)
#define USB1_HCSPARAMS_N_PTT_Pos                              20
#define USB1_HCSPARAMS_N_PTT_Msk                              (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos)
#define USB1_HCSPARAMS_N_TT_Pos                               24
#define USB1_HCSPARAMS_N_TT_Msk                               (0x0fUL << USB1_HCSPARAMS_N_TT_Pos)

// -------------------------------------  USB1_HCCPARAMS  -----------------------------------------
#define USB1_HCCPARAMS_ADC_Pos                                0
#define USB1_HCCPARAMS_ADC_Msk                                (0x01UL << USB1_HCCPARAMS_ADC_Pos)
#define USB1_HCCPARAMS_PFL_Pos                                1
#define USB1_HCCPARAMS_PFL_Msk                                (0x01UL << USB1_HCCPARAMS_PFL_Pos)
#define USB1_HCCPARAMS_ASP_Pos                                2
#define USB1_HCCPARAMS_ASP_Msk                                (0x01UL << USB1_HCCPARAMS_ASP_Pos)
#define USB1_HCCPARAMS_IST_Pos                                4
#define USB1_HCCPARAMS_IST_Msk                                (0x0fUL << USB1_HCCPARAMS_IST_Pos)
#define USB1_HCCPARAMS_EECP_Pos                               8
#define USB1_HCCPARAMS_EECP_Msk                               (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos)

// -------------------------------------  USB1_DCIVERSION  ----------------------------------------
#define USB1_DCIVERSION_DCIVERSION_Pos                        0
#define USB1_DCIVERSION_DCIVERSION_Msk                        (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos)

// --------------------------------------  USB1_USBCMD_D  -----------------------------------------
#define USB1_USBCMD_D_RS_Pos                                  0
#define USB1_USBCMD_D_RS_Msk                                  (0x01UL << USB1_USBCMD_D_RS_Pos)
#define USB1_USBCMD_D_RST_Pos                                 1
#define USB1_USBCMD_D_RST_Msk                                 (0x01UL << USB1_USBCMD_D_RST_Pos)
#define USB1_USBCMD_D_SUTW_Pos                                13
#define USB1_USBCMD_D_SUTW_Msk                                (0x01UL << USB1_USBCMD_D_SUTW_Pos)
#define USB1_USBCMD_D_ATDTW_Pos                               14
#define USB1_USBCMD_D_ATDTW_Msk                               (0x01UL << USB1_USBCMD_D_ATDTW_Pos)
#define USB1_USBCMD_D_FS2_Pos                                 15
#define USB1_USBCMD_D_FS2_Msk                                 (0x01UL << USB1_USBCMD_D_FS2_Pos)
#define USB1_USBCMD_D_ITC_Pos                                 16
#define USB1_USBCMD_D_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_D_ITC_Pos)

// --------------------------------------  USB1_USBCMD_H  -----------------------------------------
#define USB1_USBCMD_H_RS_Pos                                  0
#define USB1_USBCMD_H_RS_Msk                                  (0x01UL << USB1_USBCMD_H_RS_Pos)
#define USB1_USBCMD_H_RST_Pos                                 1
#define USB1_USBCMD_H_RST_Msk                                 (0x01UL << USB1_USBCMD_H_RST_Pos)
#define USB1_USBCMD_H_FS0_Pos                                 2
#define USB1_USBCMD_H_FS0_Msk                                 (0x01UL << USB1_USBCMD_H_FS0_Pos)
#define USB1_USBCMD_H_FS1_Pos                                 3
#define USB1_USBCMD_H_FS1_Msk                                 (0x01UL << USB1_USBCMD_H_FS1_Pos)
#define USB1_USBCMD_H_PSE_Pos                                 4
#define USB1_USBCMD_H_PSE_Msk                                 (0x01UL << USB1_USBCMD_H_PSE_Pos)
#define USB1_USBCMD_H_ASE_Pos                                 5
#define USB1_USBCMD_H_ASE_Msk                                 (0x01UL << USB1_USBCMD_H_ASE_Pos)
#define USB1_USBCMD_H_IAA_Pos                                 6
#define USB1_USBCMD_H_IAA_Msk                                 (0x01UL << USB1_USBCMD_H_IAA_Pos)
#define USB1_USBCMD_H_ASP1_0_Pos                              8
#define USB1_USBCMD_H_ASP1_0_Msk                              (0x03UL << USB1_USBCMD_H_ASP1_0_Pos)
#define USB1_USBCMD_H_ASPE_Pos                                11
#define USB1_USBCMD_H_ASPE_Msk                                (0x01UL << USB1_USBCMD_H_ASPE_Pos)
#define USB1_USBCMD_H_FS2_Pos                                 15
#define USB1_USBCMD_H_FS2_Msk                                 (0x01UL << USB1_USBCMD_H_FS2_Pos)
#define USB1_USBCMD_H_ITC_Pos                                 16
#define USB1_USBCMD_H_ITC_Msk                                 (0x000000ffUL << USB1_USBCMD_H_ITC_Pos)

// --------------------------------------  USB1_USBSTS_D  -----------------------------------------
#define USB1_USBSTS_D_UI_Pos                                  0
#define USB1_USBSTS_D_UI_Msk                                  (0x01UL << USB1_USBSTS_D_UI_Pos)
#define USB1_USBSTS_D_UEI_Pos                                 1
#define USB1_USBSTS_D_UEI_Msk                                 (0x01UL << USB1_USBSTS_D_UEI_Pos)
#define USB1_USBSTS_D_PCI_Pos                                 2
#define USB1_USBSTS_D_PCI_Msk                                 (0x01UL << USB1_USBSTS_D_PCI_Pos)
#define USB1_USBSTS_D_URI_Pos                                 6
#define USB1_USBSTS_D_URI_Msk                                 (0x01UL << USB1_USBSTS_D_URI_Pos)
#define USB1_USBSTS_D_SRI_Pos                                 7
#define USB1_USBSTS_D_SRI_Msk                                 (0x01UL << USB1_USBSTS_D_SRI_Pos)
#define USB1_USBSTS_D_SLI_Pos                                 8
#define USB1_USBSTS_D_SLI_Msk                                 (0x01UL << USB1_USBSTS_D_SLI_Pos)
#define USB1_USBSTS_D_NAKI_Pos                                16
#define USB1_USBSTS_D_NAKI_Msk                                (0x01UL << USB1_USBSTS_D_NAKI_Pos)

// --------------------------------------  USB1_USBSTS_H  -----------------------------------------
#define USB1_USBSTS_H_UI_Pos                                  0
#define USB1_USBSTS_H_UI_Msk                                  (0x01UL << USB1_USBSTS_H_UI_Pos)
#define USB1_USBSTS_H_UEI_Pos                                 1
#define USB1_USBSTS_H_UEI_Msk                                 (0x01UL << USB1_USBSTS_H_UEI_Pos)
#define USB1_USBSTS_H_PCI_Pos                                 2
#define USB1_USBSTS_H_PCI_Msk                                 (0x01UL << USB1_USBSTS_H_PCI_Pos)
#define USB1_USBSTS_H_FRI_Pos                                 3
#define USB1_USBSTS_H_FRI_Msk                                 (0x01UL << USB1_USBSTS_H_FRI_Pos)
#define USB1_USBSTS_H_AAI_Pos                                 5
#define USB1_USBSTS_H_AAI_Msk                                 (0x01UL << USB1_USBSTS_H_AAI_Pos)
#define USB1_USBSTS_H_SRI_Pos                                 7
#define USB1_USBSTS_H_SRI_Msk                                 (0x01UL << USB1_USBSTS_H_SRI_Pos)
#define USB1_USBSTS_H_SLI_Pos                                 8
#define USB1_USBSTS_H_SLI_Msk                                 (0x01UL << USB1_USBSTS_H_SLI_Pos)
#define USB1_USBSTS_H_HCH_Pos                                 12
#define USB1_USBSTS_H_HCH_Msk                                 (0x01UL << USB1_USBSTS_H_HCH_Pos)
#define USB1_USBSTS_H_RCL_Pos                                 13
#define USB1_USBSTS_H_RCL_Msk                                 (0x01UL << USB1_USBSTS_H_RCL_Pos)
#define USB1_USBSTS_H_PS_Pos                                  14
#define USB1_USBSTS_H_PS_Msk                                  (0x01UL << USB1_USBSTS_H_PS_Pos)
#define USB1_USBSTS_H_AS_Pos                                  15
#define USB1_USBSTS_H_AS_Msk                                  (0x01UL << USB1_USBSTS_H_AS_Pos)
#define USB1_USBSTS_H_UAI_Pos                                 18
#define USB1_USBSTS_H_UAI_Msk                                 (0x01UL << USB1_USBSTS_H_UAI_Pos)
#define USB1_USBSTS_H_UPI_Pos                                 19
#define USB1_USBSTS_H_UPI_Msk                                 (0x01UL << USB1_USBSTS_H_UPI_Pos)

// -------------------------------------  USB1_USBINTR_D  -----------------------------------------
#define USB1_USBINTR_D_UE_Pos                                 0
#define USB1_USBINTR_D_UE_Msk                                 (0x01UL << USB1_USBINTR_D_UE_Pos)
#define USB1_USBINTR_D_UEE_Pos                                1
#define USB1_USBINTR_D_UEE_Msk                                (0x01UL << USB1_USBINTR_D_UEE_Pos)
#define USB1_USBINTR_D_PCE_Pos                                2
#define USB1_USBINTR_D_PCE_Msk                                (0x01UL << USB1_USBINTR_D_PCE_Pos)
#define USB1_USBINTR_D_URE_Pos                                6
#define USB1_USBINTR_D_URE_Msk                                (0x01UL << USB1_USBINTR_D_URE_Pos)
#define USB1_USBINTR_D_SRE_Pos                                7
#define USB1_USBINTR_D_SRE_Msk                                (0x01UL << USB1_USBINTR_D_SRE_Pos)
#define USB1_USBINTR_D_SLE_Pos                                8
#define USB1_USBINTR_D_SLE_Msk                                (0x01UL << USB1_USBINTR_D_SLE_Pos)
#define USB1_USBINTR_D_NAKE_Pos                               16
#define USB1_USBINTR_D_NAKE_Msk                               (0x01UL << USB1_USBINTR_D_NAKE_Pos)
#define USB1_USBINTR_D_UAIE_Pos                               18
#define USB1_USBINTR_D_UAIE_Msk                               (0x01UL << USB1_USBINTR_D_UAIE_Pos)
#define USB1_USBINTR_D_UPIA_Pos                               19
#define USB1_USBINTR_D_UPIA_Msk                               (0x01UL << USB1_USBINTR_D_UPIA_Pos)

// -------------------------------------  USB1_USBINTR_H  -----------------------------------------
#define USB1_USBINTR_H_UE_Pos                                 0
#define USB1_USBINTR_H_UE_Msk                                 (0x01UL << USB1_USBINTR_H_UE_Pos)
#define USB1_USBINTR_H_UEE_Pos                                1
#define USB1_USBINTR_H_UEE_Msk                                (0x01UL << USB1_USBINTR_H_UEE_Pos)
#define USB1_USBINTR_H_PCE_Pos                                2
#define USB1_USBINTR_H_PCE_Msk                                (0x01UL << USB1_USBINTR_H_PCE_Pos)
#define USB1_USBINTR_H_FRE_Pos                                3
#define USB1_USBINTR_H_FRE_Msk                                (0x01UL << USB1_USBINTR_H_FRE_Pos)
#define USB1_USBINTR_H_AAE_Pos                                5
#define USB1_USBINTR_H_AAE_Msk                                (0x01UL << USB1_USBINTR_H_AAE_Pos)
#define USB1_USBINTR_H_SRE_Pos                                7
#define USB1_USBINTR_H_SRE_Msk                                (0x01UL << USB1_USBINTR_H_SRE_Pos)
#define USB1_USBINTR_H_UAIE_Pos                               18
#define USB1_USBINTR_H_UAIE_Msk                               (0x01UL << USB1_USBINTR_H_UAIE_Pos)
#define USB1_USBINTR_H_UPIA_Pos                               19
#define USB1_USBINTR_H_UPIA_Msk                               (0x01UL << USB1_USBINTR_H_UPIA_Pos)

// -------------------------------------  USB1_FRINDEX_D  -----------------------------------------
#define USB1_FRINDEX_D_FRINDEX2_0_Pos                         0
#define USB1_FRINDEX_D_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos)
#define USB1_FRINDEX_D_FRINDEX13_3_Pos                        3
#define USB1_FRINDEX_D_FRINDEX13_3_Msk                        (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos)

// -------------------------------------  USB1_FRINDEX_H  -----------------------------------------
#define USB1_FRINDEX_H_FRINDEX2_0_Pos                         0
#define USB1_FRINDEX_H_FRINDEX2_0_Msk                         (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos)
#define USB1_FRINDEX_H_FRINDEX12_3_Pos                        3
#define USB1_FRINDEX_H_FRINDEX12_3_Msk                        (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos)

// -------------------------------------  USB1_DEVICEADDR  ----------------------------------------
#define USB1_DEVICEADDR_USBADRA_Pos                           24
#define USB1_DEVICEADDR_USBADRA_Msk                           (0x01UL << USB1_DEVICEADDR_USBADRA_Pos)
#define USB1_DEVICEADDR_USBADR_Pos                            25
#define USB1_DEVICEADDR_USBADR_Msk                            (0x7fUL << USB1_DEVICEADDR_USBADR_Pos)

// ----------------------------------  USB1_PERIODICLISTBASE  -------------------------------------
#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos                12
#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk                (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)

// ----------------------------------  USB1_ENDPOINTLISTADDR  -------------------------------------
#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos                 11
#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk                 (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos)

// -----------------------------------  USB1_ASYNCLISTADDR  ---------------------------------------
#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos                    5
#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk                    (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos)

// ---------------------------------------  USB1_TTCTRL  ------------------------------------------
#define USB1_TTCTRL_TTHA_Pos                                  24
#define USB1_TTCTRL_TTHA_Msk                                  (0x7fUL << USB1_TTCTRL_TTHA_Pos)

// -------------------------------------  USB1_BURSTSIZE  -----------------------------------------
#define USB1_BURSTSIZE_RXPBURST_Pos                           0
#define USB1_BURSTSIZE_RXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos)
#define USB1_BURSTSIZE_TXPBURST_Pos                           8
#define USB1_BURSTSIZE_TXPBURST_Msk                           (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos)

// ------------------------------------  USB1_TXFILLTUNING  ---------------------------------------
#define USB1_TXFILLTUNING_TXSCHOH_Pos                         0
#define USB1_TXFILLTUNING_TXSCHOH_Msk                         (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos)
#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos                     8
#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk                     (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos)
#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos                     16
#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk                     (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos)

// ------------------------------------  USB1_ULPIVIEWPORT  ---------------------------------------
#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos                       0
#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos)
#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos                       8
#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk                       (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos)
#define USB1_ULPIVIEWPORT_ULPIADDR_Pos                        16
#define USB1_ULPIVIEWPORT_ULPIADDR_Msk                        (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos)
#define USB1_ULPIVIEWPORT_ULPIPORT_Pos                        24
#define USB1_ULPIVIEWPORT_ULPIPORT_Msk                        (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos)
#define USB1_ULPIVIEWPORT_ULPISS_Pos                          27
#define USB1_ULPIVIEWPORT_ULPISS_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos)
#define USB1_ULPIVIEWPORT_ULPIRW_Pos                          29
#define USB1_ULPIVIEWPORT_ULPIRW_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos)
#define USB1_ULPIVIEWPORT_ULPIRUN_Pos                         30
#define USB1_ULPIVIEWPORT_ULPIRUN_Msk                         (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos)
#define USB1_ULPIVIEWPORT_ULPIWU_Pos                          31
#define USB1_ULPIVIEWPORT_ULPIWU_Msk                          (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos)

// -------------------------------------  USB1_BINTERVAL  -----------------------------------------
#define USB1_BINTERVAL_BINT_Pos                               0
#define USB1_BINTERVAL_BINT_Msk                               (0x0fUL << USB1_BINTERVAL_BINT_Pos)

// --------------------------------------  USB1_ENDPTNAK  -----------------------------------------
#define USB1_ENDPTNAK_EPRN0_Pos                               0
#define USB1_ENDPTNAK_EPRN0_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN0_Pos)
#define USB1_ENDPTNAK_EPRN1_Pos                               1
#define USB1_ENDPTNAK_EPRN1_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN1_Pos)
#define USB1_ENDPTNAK_EPRN2_Pos                               2
#define USB1_ENDPTNAK_EPRN2_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN2_Pos)
#define USB1_ENDPTNAK_EPRN3_Pos                               3
#define USB1_ENDPTNAK_EPRN3_Msk                               (0x01UL << USB1_ENDPTNAK_EPRN3_Pos)
#define USB1_ENDPTNAK_EPTN16_Pos                              16
#define USB1_ENDPTNAK_EPTN16_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN16_Pos)
#define USB1_ENDPTNAK_EPTN17_Pos                              17
#define USB1_ENDPTNAK_EPTN17_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN17_Pos)
#define USB1_ENDPTNAK_EPTN18_Pos                              18
#define USB1_ENDPTNAK_EPTN18_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN18_Pos)
#define USB1_ENDPTNAK_EPTN19_Pos                              19
#define USB1_ENDPTNAK_EPTN19_Msk                              (0x01UL << USB1_ENDPTNAK_EPTN19_Pos)

// -------------------------------------  USB1_ENDPTNAKEN  ----------------------------------------
#define USB1_ENDPTNAKEN_EPRNE0_Pos                            0
#define USB1_ENDPTNAKEN_EPRNE0_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos)
#define USB1_ENDPTNAKEN_EPRNE1_Pos                            1
#define USB1_ENDPTNAKEN_EPRNE1_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos)
#define USB1_ENDPTNAKEN_EPRNE2_Pos                            2
#define USB1_ENDPTNAKEN_EPRNE2_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos)
#define USB1_ENDPTNAKEN_EPRNE3_Pos                            3
#define USB1_ENDPTNAKEN_EPRNE3_Msk                            (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos)
#define USB1_ENDPTNAKEN_EPTNE16_Pos                           16
#define USB1_ENDPTNAKEN_EPTNE16_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos)
#define USB1_ENDPTNAKEN_EPTNE17_Pos                           17
#define USB1_ENDPTNAKEN_EPTNE17_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos)
#define USB1_ENDPTNAKEN_EPTNE18_Pos                           18
#define USB1_ENDPTNAKEN_EPTNE18_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos)
#define USB1_ENDPTNAKEN_EPTNE19_Pos                           19
#define USB1_ENDPTNAKEN_EPTNE19_Msk                           (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos)

// -------------------------------------  USB1_PORTSC1_D  -----------------------------------------
#define USB1_PORTSC1_D_CCS_Pos                                0
#define USB1_PORTSC1_D_CCS_Msk                                (0x01UL << USB1_PORTSC1_D_CCS_Pos)
#define USB1_PORTSC1_D_CSC_Pos                                1
#define USB1_PORTSC1_D_CSC_Msk                                (0x01UL << USB1_PORTSC1_D_CSC_Pos)
#define USB1_PORTSC1_D_PE_Pos                                 2
#define USB1_PORTSC1_D_PE_Msk                                 (0x01UL << USB1_PORTSC1_D_PE_Pos)
#define USB1_PORTSC1_D_PEC_Pos                                3
#define USB1_PORTSC1_D_PEC_Msk                                (0x01UL << USB1_PORTSC1_D_PEC_Pos)
#define USB1_PORTSC1_D_FPR_Pos                                6
#define USB1_PORTSC1_D_FPR_Msk                                (0x01UL << USB1_PORTSC1_D_FPR_Pos)
#define USB1_PORTSC1_D_SUSP_Pos                               7
#define USB1_PORTSC1_D_SUSP_Msk                               (0x01UL << USB1_PORTSC1_D_SUSP_Pos)
#define USB1_PORTSC1_D_PR_Pos                                 8
#define USB1_PORTSC1_D_PR_Msk                                 (0x01UL << USB1_PORTSC1_D_PR_Pos)
#define USB1_PORTSC1_D_HSP_Pos                                9
#define USB1_PORTSC1_D_HSP_Msk                                (0x01UL << USB1_PORTSC1_D_HSP_Pos)
#define USB1_PORTSC1_D_LS_Pos                                 10
#define USB1_PORTSC1_D_LS_Msk                                 (0x03UL << USB1_PORTSC1_D_LS_Pos)
#define USB1_PORTSC1_D_PP_Pos                                 12
#define USB1_PORTSC1_D_PP_Msk                                 (0x01UL << USB1_PORTSC1_D_PP_Pos)
#define USB1_PORTSC1_D_PIC1_0_Pos                             14
#define USB1_PORTSC1_D_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos)
#define USB1_PORTSC1_D_PTC3_0_Pos                             16
#define USB1_PORTSC1_D_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos)
#define USB1_PORTSC1_D_PHCD_Pos                               23
#define USB1_PORTSC1_D_PHCD_Msk                               (0x01UL << USB1_PORTSC1_D_PHCD_Pos)
#define USB1_PORTSC1_D_PFSC_Pos                               24
#define USB1_PORTSC1_D_PFSC_Msk                               (0x01UL << USB1_PORTSC1_D_PFSC_Pos)
#define USB1_PORTSC1_D_PSPD_Pos                               26
#define USB1_PORTSC1_D_PSPD_Msk                               (0x03UL << USB1_PORTSC1_D_PSPD_Pos)
#define USB1_PORTSC1_D_PTS_Pos                                30
#define USB1_PORTSC1_D_PTS_Msk                                (0x03UL << USB1_PORTSC1_D_PTS_Pos)

// -------------------------------------  USB1_PORTSC1_H  -----------------------------------------
#define USB1_PORTSC1_H_CCS_Pos                                0
#define USB1_PORTSC1_H_CCS_Msk                                (0x01UL << USB1_PORTSC1_H_CCS_Pos)
#define USB1_PORTSC1_H_CSC_Pos                                1
#define USB1_PORTSC1_H_CSC_Msk                                (0x01UL << USB1_PORTSC1_H_CSC_Pos)
#define USB1_PORTSC1_H_PE_Pos                                 2
#define USB1_PORTSC1_H_PE_Msk                                 (0x01UL << USB1_PORTSC1_H_PE_Pos)
#define USB1_PORTSC1_H_PEC_Pos                                3
#define USB1_PORTSC1_H_PEC_Msk                                (0x01UL << USB1_PORTSC1_H_PEC_Pos)
#define USB1_PORTSC1_H_OCA_Pos                                4
#define USB1_PORTSC1_H_OCA_Msk                                (0x01UL << USB1_PORTSC1_H_OCA_Pos)
#define USB1_PORTSC1_H_OCC_Pos                                5
#define USB1_PORTSC1_H_OCC_Msk                                (0x01UL << USB1_PORTSC1_H_OCC_Pos)
#define USB1_PORTSC1_H_FPR_Pos                                6
#define USB1_PORTSC1_H_FPR_Msk                                (0x01UL << USB1_PORTSC1_H_FPR_Pos)
#define USB1_PORTSC1_H_SUSP_Pos                               7
#define USB1_PORTSC1_H_SUSP_Msk                               (0x01UL << USB1_PORTSC1_H_SUSP_Pos)
#define USB1_PORTSC1_H_PR_Pos                                 8
#define USB1_PORTSC1_H_PR_Msk                                 (0x01UL << USB1_PORTSC1_H_PR_Pos)
#define USB1_PORTSC1_H_HSP_Pos                                9
#define USB1_PORTSC1_H_HSP_Msk                                (0x01UL << USB1_PORTSC1_H_HSP_Pos)
#define USB1_PORTSC1_H_LS_Pos                                 10
#define USB1_PORTSC1_H_LS_Msk                                 (0x03UL << USB1_PORTSC1_H_LS_Pos)
#define USB1_PORTSC1_H_PP_Pos                                 12
#define USB1_PORTSC1_H_PP_Msk                                 (0x01UL << USB1_PORTSC1_H_PP_Pos)
#define USB1_PORTSC1_H_PIC1_0_Pos                             14
#define USB1_PORTSC1_H_PIC1_0_Msk                             (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos)
#define USB1_PORTSC1_H_PTC3_0_Pos                             16
#define USB1_PORTSC1_H_PTC3_0_Msk                             (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos)
#define USB1_PORTSC1_H_WKCN_Pos                               20
#define USB1_PORTSC1_H_WKCN_Msk                               (0x01UL << USB1_PORTSC1_H_WKCN_Pos)
#define USB1_PORTSC1_H_WKDC_Pos                               21
#define USB1_PORTSC1_H_WKDC_Msk                               (0x01UL << USB1_PORTSC1_H_WKDC_Pos)
#define USB1_PORTSC1_H_WKOC_Pos                               22
#define USB1_PORTSC1_H_WKOC_Msk                               (0x01UL << USB1_PORTSC1_H_WKOC_Pos)
#define USB1_PORTSC1_H_PHCD_Pos                               23
#define USB1_PORTSC1_H_PHCD_Msk                               (0x01UL << USB1_PORTSC1_H_PHCD_Pos)
#define USB1_PORTSC1_H_PFSC_Pos                               24
#define USB1_PORTSC1_H_PFSC_Msk                               (0x01UL << USB1_PORTSC1_H_PFSC_Pos)
#define USB1_PORTSC1_H_PSPD_Pos                               26
#define USB1_PORTSC1_H_PSPD_Msk                               (0x03UL << USB1_PORTSC1_H_PSPD_Pos)
#define USB1_PORTSC1_H_PTS_Pos                                30
#define USB1_PORTSC1_H_PTS_Msk                                (0x03UL << USB1_PORTSC1_H_PTS_Pos)

// -------------------------------------  USB1_USBMODE_D  -----------------------------------------
#define USB1_USBMODE_D_CM1_0_Pos                              0
#define USB1_USBMODE_D_CM1_0_Msk                              (0x03UL << USB1_USBMODE_D_CM1_0_Pos)
#define USB1_USBMODE_D_ES_Pos                                 2
#define USB1_USBMODE_D_ES_Msk                                 (0x01UL << USB1_USBMODE_D_ES_Pos)
#define USB1_USBMODE_D_SLOM_Pos                               3
#define USB1_USBMODE_D_SLOM_Msk                               (0x01UL << USB1_USBMODE_D_SLOM_Pos)
#define USB1_USBMODE_D_SDIS_Pos                               4
#define USB1_USBMODE_D_SDIS_Msk                               (0x01UL << USB1_USBMODE_D_SDIS_Pos)

// -------------------------------------  USB1_USBMODE_H  -----------------------------------------
#define USB1_USBMODE_H_CM1_0_Pos                              0
#define USB1_USBMODE_H_CM1_0_Msk                              (0x03UL << USB1_USBMODE_H_CM1_0_Pos)
#define USB1_USBMODE_H_ES_Pos                                 2
#define USB1_USBMODE_H_ES_Msk                                 (0x01UL << USB1_USBMODE_H_ES_Pos)
#define USB1_USBMODE_H_SDIS_Pos                               4
#define USB1_USBMODE_H_SDIS_Msk                               (0x01UL << USB1_USBMODE_H_SDIS_Pos)
#define USB1_USBMODE_H_VBPS_Pos                               5
#define USB1_USBMODE_H_VBPS_Msk                               (0x01UL << USB1_USBMODE_H_VBPS_Pos)

// -----------------------------------  USB1_ENDPTSETUPSTAT  --------------------------------------
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos               0
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos)
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos               1
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos)
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos               2
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos)
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos               3
#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk               (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos)

// -------------------------------------  USB1_ENDPTPRIME  ----------------------------------------
#define USB1_ENDPTPRIME_PERB0_Pos                             0
#define USB1_ENDPTPRIME_PERB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB0_Pos)
#define USB1_ENDPTPRIME_PERB1_Pos                             1
#define USB1_ENDPTPRIME_PERB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB1_Pos)
#define USB1_ENDPTPRIME_PERB2_Pos                             2
#define USB1_ENDPTPRIME_PERB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB2_Pos)
#define USB1_ENDPTPRIME_PERB3_Pos                             3
#define USB1_ENDPTPRIME_PERB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PERB3_Pos)
#define USB1_ENDPTPRIME_PETB0_Pos                             16
#define USB1_ENDPTPRIME_PETB0_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB0_Pos)
#define USB1_ENDPTPRIME_PETB1_Pos                             17
#define USB1_ENDPTPRIME_PETB1_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB1_Pos)
#define USB1_ENDPTPRIME_PETB2_Pos                             18
#define USB1_ENDPTPRIME_PETB2_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB2_Pos)
#define USB1_ENDPTPRIME_PETB3_Pos                             19
#define USB1_ENDPTPRIME_PETB3_Msk                             (0x01UL << USB1_ENDPTPRIME_PETB3_Pos)

// -------------------------------------  USB1_ENDPTFLUSH  ----------------------------------------
#define USB1_ENDPTFLUSH_FERB0_Pos                             0
#define USB1_ENDPTFLUSH_FERB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos)
#define USB1_ENDPTFLUSH_FERB1_Pos                             1
#define USB1_ENDPTFLUSH_FERB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos)
#define USB1_ENDPTFLUSH_FERB2_Pos                             2
#define USB1_ENDPTFLUSH_FERB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos)
#define USB1_ENDPTFLUSH_FERB3_Pos                             3
#define USB1_ENDPTFLUSH_FERB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos)
#define USB1_ENDPTFLUSH_FETB0_Pos                             16
#define USB1_ENDPTFLUSH_FETB0_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos)
#define USB1_ENDPTFLUSH_FETB1_Pos                             17
#define USB1_ENDPTFLUSH_FETB1_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos)
#define USB1_ENDPTFLUSH_FETB2_Pos                             18
#define USB1_ENDPTFLUSH_FETB2_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos)
#define USB1_ENDPTFLUSH_FETB3_Pos                             19
#define USB1_ENDPTFLUSH_FETB3_Msk                             (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos)

// -------------------------------------  USB1_ENDPTSTAT  -----------------------------------------
#define USB1_ENDPTSTAT_ERBR0_Pos                              0
#define USB1_ENDPTSTAT_ERBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos)
#define USB1_ENDPTSTAT_ERBR1_Pos                              1
#define USB1_ENDPTSTAT_ERBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos)
#define USB1_ENDPTSTAT_ERBR2_Pos                              2
#define USB1_ENDPTSTAT_ERBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos)
#define USB1_ENDPTSTAT_ERBR3_Pos                              3
#define USB1_ENDPTSTAT_ERBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos)
#define USB1_ENDPTSTAT_ETBR0_Pos                              16
#define USB1_ENDPTSTAT_ETBR0_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos)
#define USB1_ENDPTSTAT_ETBR1_Pos                              17
#define USB1_ENDPTSTAT_ETBR1_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos)
#define USB1_ENDPTSTAT_ETBR2_Pos                              18
#define USB1_ENDPTSTAT_ETBR2_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos)
#define USB1_ENDPTSTAT_ETBR3_Pos                              19
#define USB1_ENDPTSTAT_ETBR3_Msk                              (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos)

// -----------------------------------  USB1_ENDPTCOMPLETE  ---------------------------------------
#define USB1_ENDPTCOMPLETE_ERCE0_Pos                          0
#define USB1_ENDPTCOMPLETE_ERCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos)
#define USB1_ENDPTCOMPLETE_ERCE1_Pos                          1
#define USB1_ENDPTCOMPLETE_ERCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos)
#define USB1_ENDPTCOMPLETE_ERCE2_Pos                          2
#define USB1_ENDPTCOMPLETE_ERCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos)
#define USB1_ENDPTCOMPLETE_ERCE3_Pos                          3
#define USB1_ENDPTCOMPLETE_ERCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos)
#define USB1_ENDPTCOMPLETE_ETCE0_Pos                          16
#define USB1_ENDPTCOMPLETE_ETCE0_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos)
#define USB1_ENDPTCOMPLETE_ETCE1_Pos                          17
#define USB1_ENDPTCOMPLETE_ETCE1_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos)
#define USB1_ENDPTCOMPLETE_ETCE2_Pos                          18
#define USB1_ENDPTCOMPLETE_ETCE2_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos)
#define USB1_ENDPTCOMPLETE_ETCE3_Pos                          19
#define USB1_ENDPTCOMPLETE_ETCE3_Msk                          (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos)

// -------------------------------------  USB1_ENDPTCTRL0  ----------------------------------------
#define USB1_ENDPTCTRL0_RXS_Pos                               0
#define USB1_ENDPTCTRL0_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXS_Pos)
#define USB1_ENDPTCTRL0_RXT_Pos                               2
#define USB1_ENDPTCTRL0_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_RXT_Pos)
#define USB1_ENDPTCTRL0_RXE_Pos                               7
#define USB1_ENDPTCTRL0_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_RXE_Pos)
#define USB1_ENDPTCTRL0_TXS_Pos                               16
#define USB1_ENDPTCTRL0_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXS_Pos)
#define USB1_ENDPTCTRL0_TXT_Pos                               18
#define USB1_ENDPTCTRL0_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL0_TXT_Pos)
#define USB1_ENDPTCTRL0_TXE_Pos                               23
#define USB1_ENDPTCTRL0_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL0_TXE_Pos)

// -------------------------------------  USB1_ENDPTCTRL1  ----------------------------------------
#define USB1_ENDPTCTRL1_RXS_Pos                               0
#define USB1_ENDPTCTRL1_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXS_Pos)
#define USB1_ENDPTCTRL1_RXT_Pos                               2
#define USB1_ENDPTCTRL1_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_RXT_Pos)
#define USB1_ENDPTCTRL1_RXI_Pos                               5
#define USB1_ENDPTCTRL1_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXI_Pos)
#define USB1_ENDPTCTRL1_RXR_Pos                               6
#define USB1_ENDPTCTRL1_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXR_Pos)
#define USB1_ENDPTCTRL1_RXE_Pos                               7
#define USB1_ENDPTCTRL1_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_RXE_Pos)
#define USB1_ENDPTCTRL1_TXS_Pos                               16
#define USB1_ENDPTCTRL1_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXS_Pos)
#define USB1_ENDPTCTRL1_TXT_Pos                               18
#define USB1_ENDPTCTRL1_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL1_TXT_Pos)
#define USB1_ENDPTCTRL1_TXI_Pos                               21
#define USB1_ENDPTCTRL1_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXI_Pos)
#define USB1_ENDPTCTRL1_TXR_Pos                               22
#define USB1_ENDPTCTRL1_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXR_Pos)
#define USB1_ENDPTCTRL1_TXE_Pos                               23
#define USB1_ENDPTCTRL1_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL1_TXE_Pos)

// -------------------------------------  USB1_ENDPTCTRL2  ----------------------------------------
#define USB1_ENDPTCTRL2_RXS_Pos                               0
#define USB1_ENDPTCTRL2_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXS_Pos)
#define USB1_ENDPTCTRL2_RXT_Pos                               2
#define USB1_ENDPTCTRL2_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_RXT_Pos)
#define USB1_ENDPTCTRL2_RXI_Pos                               5
#define USB1_ENDPTCTRL2_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXI_Pos)
#define USB1_ENDPTCTRL2_RXR_Pos                               6
#define USB1_ENDPTCTRL2_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXR_Pos)
#define USB1_ENDPTCTRL2_RXE_Pos                               7
#define USB1_ENDPTCTRL2_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_RXE_Pos)
#define USB1_ENDPTCTRL2_TXS_Pos                               16
#define USB1_ENDPTCTRL2_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXS_Pos)
#define USB1_ENDPTCTRL2_TXT_Pos                               18
#define USB1_ENDPTCTRL2_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL2_TXT_Pos)
#define USB1_ENDPTCTRL2_TXI_Pos                               21
#define USB1_ENDPTCTRL2_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXI_Pos)
#define USB1_ENDPTCTRL2_TXR_Pos                               22
#define USB1_ENDPTCTRL2_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXR_Pos)
#define USB1_ENDPTCTRL2_TXE_Pos                               23
#define USB1_ENDPTCTRL2_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL2_TXE_Pos)

// -------------------------------------  USB1_ENDPTCTRL3  ----------------------------------------
#define USB1_ENDPTCTRL3_RXS_Pos                               0
#define USB1_ENDPTCTRL3_RXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXS_Pos)
#define USB1_ENDPTCTRL3_RXT_Pos                               2
#define USB1_ENDPTCTRL3_RXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_RXT_Pos)
#define USB1_ENDPTCTRL3_RXI_Pos                               5
#define USB1_ENDPTCTRL3_RXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXI_Pos)
#define USB1_ENDPTCTRL3_RXR_Pos                               6
#define USB1_ENDPTCTRL3_RXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXR_Pos)
#define USB1_ENDPTCTRL3_RXE_Pos                               7
#define USB1_ENDPTCTRL3_RXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_RXE_Pos)
#define USB1_ENDPTCTRL3_TXS_Pos                               16
#define USB1_ENDPTCTRL3_TXS_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXS_Pos)
#define USB1_ENDPTCTRL3_TXT_Pos                               18
#define USB1_ENDPTCTRL3_TXT_Msk                               (0x03UL << USB1_ENDPTCTRL3_TXT_Pos)
#define USB1_ENDPTCTRL3_TXI_Pos                               21
#define USB1_ENDPTCTRL3_TXI_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXI_Pos)
#define USB1_ENDPTCTRL3_TXR_Pos                               22
#define USB1_ENDPTCTRL3_TXR_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXR_Pos)
#define USB1_ENDPTCTRL3_TXE_Pos                               23
#define USB1_ENDPTCTRL3_TXE_Msk                               (0x01UL << USB1_ENDPTCTRL3_TXE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  LCD Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  LCD_TIMH  --------------------------------------------
#define LCD_TIMH_PPL_Pos                                      2
#define LCD_TIMH_PPL_Msk                                      (0x3fUL << LCD_TIMH_PPL_Pos)
#define LCD_TIMH_HSW_Pos                                      8
#define LCD_TIMH_HSW_Msk                                      (0x000000ffUL << LCD_TIMH_HSW_Pos)
#define LCD_TIMH_HFP_Pos                                      16
#define LCD_TIMH_HFP_Msk                                      (0x000000ffUL << LCD_TIMH_HFP_Pos)
#define LCD_TIMH_HBP_Pos                                      24
#define LCD_TIMH_HBP_Msk                                      (0x000000ffUL << LCD_TIMH_HBP_Pos)

// ----------------------------------------  LCD_TIMV  --------------------------------------------
#define LCD_TIMV_LPP_Pos                                      0
#define LCD_TIMV_LPP_Msk                                      (0x000003ffUL << LCD_TIMV_LPP_Pos)
#define LCD_TIMV_VSW_Pos                                      10
#define LCD_TIMV_VSW_Msk                                      (0x3fUL << LCD_TIMV_VSW_Pos)
#define LCD_TIMV_VFP_Pos                                      16
#define LCD_TIMV_VFP_Msk                                      (0x000000ffUL << LCD_TIMV_VFP_Pos)
#define LCD_TIMV_VBP_Pos                                      24
#define LCD_TIMV_VBP_Msk                                      (0x000000ffUL << LCD_TIMV_VBP_Pos)

// -----------------------------------------  LCD_POL  --------------------------------------------
#define LCD_POL_PCD_LO_Pos                                    0
#define LCD_POL_PCD_LO_Msk                                    (0x1fUL << LCD_POL_PCD_LO_Pos)
#define LCD_POL_CLKSEL_Pos                                    5
#define LCD_POL_CLKSEL_Msk                                    (0x01UL << LCD_POL_CLKSEL_Pos)
#define LCD_POL_ACB_Pos                                       6
#define LCD_POL_ACB_Msk                                       (0x1fUL << LCD_POL_ACB_Pos)
#define LCD_POL_IVS_Pos                                       11
#define LCD_POL_IVS_Msk                                       (0x01UL << LCD_POL_IVS_Pos)
#define LCD_POL_IHS_Pos                                       12
#define LCD_POL_IHS_Msk                                       (0x01UL << LCD_POL_IHS_Pos)
#define LCD_POL_IPC_Pos                                       13
#define LCD_POL_IPC_Msk                                       (0x01UL << LCD_POL_IPC_Pos)
#define LCD_POL_IOE_Pos                                       14
#define LCD_POL_IOE_Msk                                       (0x01UL << LCD_POL_IOE_Pos)
#define LCD_POL_CPL_Pos                                       16
#define LCD_POL_CPL_Msk                                       (0x000003ffUL << LCD_POL_CPL_Pos)
#define LCD_POL_BCD_Pos                                       26
#define LCD_POL_BCD_Msk                                       (0x01UL << LCD_POL_BCD_Pos)
#define LCD_POL_PCD_HI_Pos                                    27
#define LCD_POL_PCD_HI_Msk                                    (0x1fUL << LCD_POL_PCD_HI_Pos)

// -----------------------------------------  LCD_LE  ---------------------------------------------
#define LCD_LE_LED_Pos                                        0
#define LCD_LE_LED_Msk                                        (0x7fUL << LCD_LE_LED_Pos)
#define LCD_LE_LEE_Pos                                        16
#define LCD_LE_LEE_Msk                                        (0x01UL << LCD_LE_LEE_Pos)

// ---------------------------------------  LCD_UPBASE  -------------------------------------------
#define LCD_UPBASE_LCDUPBASE_Pos                              3
#define LCD_UPBASE_LCDUPBASE_Msk                              (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos)

// ---------------------------------------  LCD_LPBASE  -------------------------------------------
#define LCD_LPBASE_LCDLPBASE_Pos                              3
#define LCD_LPBASE_LCDLPBASE_Msk                              (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos)

// ----------------------------------------  LCD_CTRL  --------------------------------------------
#define LCD_CTRL_LCDEN_Pos                                    0
#define LCD_CTRL_LCDEN_Msk                                    (0x01UL << LCD_CTRL_LCDEN_Pos)
#define LCD_CTRL_LCDBPP_Pos                                   1
#define LCD_CTRL_LCDBPP_Msk                                   (0x07UL << LCD_CTRL_LCDBPP_Pos)
#define LCD_CTRL_LCDBW_Pos                                    4
#define LCD_CTRL_LCDBW_Msk                                    (0x01UL << LCD_CTRL_LCDBW_Pos)
#define LCD_CTRL_LCDTFT_Pos                                   5
#define LCD_CTRL_LCDTFT_Msk                                   (0x01UL << LCD_CTRL_LCDTFT_Pos)
#define LCD_CTRL_LCDMONO8_Pos                                 6
#define LCD_CTRL_LCDMONO8_Msk                                 (0x01UL << LCD_CTRL_LCDMONO8_Pos)
#define LCD_CTRL_LCDDUAL_Pos                                  7
#define LCD_CTRL_LCDDUAL_Msk                                  (0x01UL << LCD_CTRL_LCDDUAL_Pos)
#define LCD_CTRL_BGR_Pos                                      8
#define LCD_CTRL_BGR_Msk                                      (0x01UL << LCD_CTRL_BGR_Pos)
#define LCD_CTRL_BEBO_Pos                                     9
#define LCD_CTRL_BEBO_Msk                                     (0x01UL << LCD_CTRL_BEBO_Pos)
#define LCD_CTRL_BEPO_Pos                                     10
#define LCD_CTRL_BEPO_Msk                                     (0x01UL << LCD_CTRL_BEPO_Pos)
#define LCD_CTRL_LCDPWR_Pos                                   11
#define LCD_CTRL_LCDPWR_Msk                                   (0x01UL << LCD_CTRL_LCDPWR_Pos)
#define LCD_CTRL_LCDVCOMP_Pos                                 12
#define LCD_CTRL_LCDVCOMP_Msk                                 (0x03UL << LCD_CTRL_LCDVCOMP_Pos)
#define LCD_CTRL_WATERMARK_Pos                                16
#define LCD_CTRL_WATERMARK_Msk                                (0x01UL << LCD_CTRL_WATERMARK_Pos)

// ---------------------------------------  LCD_INTMSK  -------------------------------------------
#define LCD_INTMSK_FUFIM_Pos                                  1
#define LCD_INTMSK_FUFIM_Msk                                  (0x01UL << LCD_INTMSK_FUFIM_Pos)
#define LCD_INTMSK_LNBUIM_Pos                                 2
#define LCD_INTMSK_LNBUIM_Msk                                 (0x01UL << LCD_INTMSK_LNBUIM_Pos)
#define LCD_INTMSK_VCOMPIM_Pos                                3
#define LCD_INTMSK_VCOMPIM_Msk                                (0x01UL << LCD_INTMSK_VCOMPIM_Pos)
#define LCD_INTMSK_BERIM_Pos                                  4
#define LCD_INTMSK_BERIM_Msk                                  (0x01UL << LCD_INTMSK_BERIM_Pos)

// ---------------------------------------  LCD_INTRAW  -------------------------------------------
#define LCD_INTRAW_FUFRIS_Pos                                 1
#define LCD_INTRAW_FUFRIS_Msk                                 (0x01UL << LCD_INTRAW_FUFRIS_Pos)
#define LCD_INTRAW_LNBURIS_Pos                                2
#define LCD_INTRAW_LNBURIS_Msk                                (0x01UL << LCD_INTRAW_LNBURIS_Pos)
#define LCD_INTRAW_VCOMPRIS_Pos                               3
#define LCD_INTRAW_VCOMPRIS_Msk                               (0x01UL << LCD_INTRAW_VCOMPRIS_Pos)
#define LCD_INTRAW_BERRAW_Pos                                 4
#define LCD_INTRAW_BERRAW_Msk                                 (0x01UL << LCD_INTRAW_BERRAW_Pos)

// ---------------------------------------  LCD_INTSTAT  ------------------------------------------
#define LCD_INTSTAT_FUFMIS_Pos                                1
#define LCD_INTSTAT_FUFMIS_Msk                                (0x01UL << LCD_INTSTAT_FUFMIS_Pos)
#define LCD_INTSTAT_LNBUMIS_Pos                               2
#define LCD_INTSTAT_LNBUMIS_Msk                               (0x01UL << LCD_INTSTAT_LNBUMIS_Pos)
#define LCD_INTSTAT_VCOMPMIS_Pos                              3
#define LCD_INTSTAT_VCOMPMIS_Msk                              (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos)
#define LCD_INTSTAT_BERMIS_Pos                                4
#define LCD_INTSTAT_BERMIS_Msk                                (0x01UL << LCD_INTSTAT_BERMIS_Pos)

// ---------------------------------------  LCD_INTCLR  -------------------------------------------
#define LCD_INTCLR_FUFIC_Pos                                  1
#define LCD_INTCLR_FUFIC_Msk                                  (0x01UL << LCD_INTCLR_FUFIC_Pos)
#define LCD_INTCLR_LNBUIC_Pos                                 2
#define LCD_INTCLR_LNBUIC_Msk                                 (0x01UL << LCD_INTCLR_LNBUIC_Pos)
#define LCD_INTCLR_VCOMPIC_Pos                                3
#define LCD_INTCLR_VCOMPIC_Msk                                (0x01UL << LCD_INTCLR_VCOMPIC_Pos)
#define LCD_INTCLR_BERIC_Pos                                  4
#define LCD_INTCLR_BERIC_Msk                                  (0x01UL << LCD_INTCLR_BERIC_Pos)

// ---------------------------------------  LCD_UPCURR  -------------------------------------------
#define LCD_UPCURR_LCDUPCURR_Pos                              0
#define LCD_UPCURR_LCDUPCURR_Msk                              (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos)

// ---------------------------------------  LCD_LPCURR  -------------------------------------------
#define LCD_LPCURR_LCDLPCURR_Pos                              0
#define LCD_LPCURR_LCDLPCURR_Msk                              (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos)

// ----------------------------------------  LCD_PAL0  --------------------------------------------
#define LCD_PAL0_R04_0_Pos                                    0
#define LCD_PAL0_R04_0_Msk                                    (0x1fUL << LCD_PAL0_R04_0_Pos)
#define LCD_PAL0_G04_0_Pos                                    5
#define LCD_PAL0_G04_0_Msk                                    (0x1fUL << LCD_PAL0_G04_0_Pos)
#define LCD_PAL0_B04_0_Pos                                    10
#define LCD_PAL0_B04_0_Msk                                    (0x1fUL << LCD_PAL0_B04_0_Pos)
#define LCD_PAL0_I0_Pos                                       15
#define LCD_PAL0_I0_Msk                                       (0x01UL << LCD_PAL0_I0_Pos)
#define LCD_PAL0_R14_0_Pos                                    16
#define LCD_PAL0_R14_0_Msk                                    (0x1fUL << LCD_PAL0_R14_0_Pos)
#define LCD_PAL0_G14_0_Pos                                    21
#define LCD_PAL0_G14_0_Msk                                    (0x1fUL << LCD_PAL0_G14_0_Pos)
#define LCD_PAL0_B14_0_Pos                                    26
#define LCD_PAL0_B14_0_Msk                                    (0x1fUL << LCD_PAL0_B14_0_Pos)
#define LCD_PAL0_I1_Pos                                       31
#define LCD_PAL0_I1_Msk                                       (0x01UL << LCD_PAL0_I1_Pos)

// ----------------------------------------  LCD_PAL1  --------------------------------------------
#define LCD_PAL1_R04_0_Pos                                    0
#define LCD_PAL1_R04_0_Msk                                    (0x1fUL << LCD_PAL1_R04_0_Pos)
#define LCD_PAL1_G04_0_Pos                                    5
#define LCD_PAL1_G04_0_Msk                                    (0x1fUL << LCD_PAL1_G04_0_Pos)
#define LCD_PAL1_B04_0_Pos                                    10
#define LCD_PAL1_B04_0_Msk                                    (0x1fUL << LCD_PAL1_B04_0_Pos)
#define LCD_PAL1_I0_Pos                                       15
#define LCD_PAL1_I0_Msk                                       (0x01UL << LCD_PAL1_I0_Pos)
#define LCD_PAL1_R14_0_Pos                                    16
#define LCD_PAL1_R14_0_Msk                                    (0x1fUL << LCD_PAL1_R14_0_Pos)
#define LCD_PAL1_G14_0_Pos                                    21
#define LCD_PAL1_G14_0_Msk                                    (0x1fUL << LCD_PAL1_G14_0_Pos)
#define LCD_PAL1_B14_0_Pos                                    26
#define LCD_PAL1_B14_0_Msk                                    (0x1fUL << LCD_PAL1_B14_0_Pos)
#define LCD_PAL1_I1_Pos                                       31
#define LCD_PAL1_I1_Msk                                       (0x01UL << LCD_PAL1_I1_Pos)

// ----------------------------------------  LCD_PAL2  --------------------------------------------
#define LCD_PAL2_R04_0_Pos                                    0
#define LCD_PAL2_R04_0_Msk                                    (0x1fUL << LCD_PAL2_R04_0_Pos)
#define LCD_PAL2_G04_0_Pos                                    5
#define LCD_PAL2_G04_0_Msk                                    (0x1fUL << LCD_PAL2_G04_0_Pos)
#define LCD_PAL2_B04_0_Pos                                    10
#define LCD_PAL2_B04_0_Msk                                    (0x1fUL << LCD_PAL2_B04_0_Pos)
#define LCD_PAL2_I0_Pos                                       15
#define LCD_PAL2_I0_Msk                                       (0x01UL << LCD_PAL2_I0_Pos)
#define LCD_PAL2_R14_0_Pos                                    16
#define LCD_PAL2_R14_0_Msk                                    (0x1fUL << LCD_PAL2_R14_0_Pos)
#define LCD_PAL2_G14_0_Pos                                    21
#define LCD_PAL2_G14_0_Msk                                    (0x1fUL << LCD_PAL2_G14_0_Pos)
#define LCD_PAL2_B14_0_Pos                                    26
#define LCD_PAL2_B14_0_Msk                                    (0x1fUL << LCD_PAL2_B14_0_Pos)
#define LCD_PAL2_I1_Pos                                       31
#define LCD_PAL2_I1_Msk                                       (0x01UL << LCD_PAL2_I1_Pos)

// ----------------------------------------  LCD_PAL3  --------------------------------------------
#define LCD_PAL3_R04_0_Pos                                    0
#define LCD_PAL3_R04_0_Msk                                    (0x1fUL << LCD_PAL3_R04_0_Pos)
#define LCD_PAL3_G04_0_Pos                                    5
#define LCD_PAL3_G04_0_Msk                                    (0x1fUL << LCD_PAL3_G04_0_Pos)
#define LCD_PAL3_B04_0_Pos                                    10
#define LCD_PAL3_B04_0_Msk                                    (0x1fUL << LCD_PAL3_B04_0_Pos)
#define LCD_PAL3_I0_Pos                                       15
#define LCD_PAL3_I0_Msk                                       (0x01UL << LCD_PAL3_I0_Pos)
#define LCD_PAL3_R14_0_Pos                                    16
#define LCD_PAL3_R14_0_Msk                                    (0x1fUL << LCD_PAL3_R14_0_Pos)
#define LCD_PAL3_G14_0_Pos                                    21
#define LCD_PAL3_G14_0_Msk                                    (0x1fUL << LCD_PAL3_G14_0_Pos)
#define LCD_PAL3_B14_0_Pos                                    26
#define LCD_PAL3_B14_0_Msk                                    (0x1fUL << LCD_PAL3_B14_0_Pos)
#define LCD_PAL3_I1_Pos                                       31
#define LCD_PAL3_I1_Msk                                       (0x01UL << LCD_PAL3_I1_Pos)

// ----------------------------------------  LCD_PAL4  --------------------------------------------
#define LCD_PAL4_R04_0_Pos                                    0
#define LCD_PAL4_R04_0_Msk                                    (0x1fUL << LCD_PAL4_R04_0_Pos)
#define LCD_PAL4_G04_0_Pos                                    5
#define LCD_PAL4_G04_0_Msk                                    (0x1fUL << LCD_PAL4_G04_0_Pos)
#define LCD_PAL4_B04_0_Pos                                    10
#define LCD_PAL4_B04_0_Msk                                    (0x1fUL << LCD_PAL4_B04_0_Pos)
#define LCD_PAL4_I0_Pos                                       15
#define LCD_PAL4_I0_Msk                                       (0x01UL << LCD_PAL4_I0_Pos)
#define LCD_PAL4_R14_0_Pos                                    16
#define LCD_PAL4_R14_0_Msk                                    (0x1fUL << LCD_PAL4_R14_0_Pos)
#define LCD_PAL4_G14_0_Pos                                    21
#define LCD_PAL4_G14_0_Msk                                    (0x1fUL << LCD_PAL4_G14_0_Pos)
#define LCD_PAL4_B14_0_Pos                                    26
#define LCD_PAL4_B14_0_Msk                                    (0x1fUL << LCD_PAL4_B14_0_Pos)
#define LCD_PAL4_I1_Pos                                       31
#define LCD_PAL4_I1_Msk                                       (0x01UL << LCD_PAL4_I1_Pos)

// ----------------------------------------  LCD_PAL5  --------------------------------------------
#define LCD_PAL5_R04_0_Pos                                    0
#define LCD_PAL5_R04_0_Msk                                    (0x1fUL << LCD_PAL5_R04_0_Pos)
#define LCD_PAL5_G04_0_Pos                                    5
#define LCD_PAL5_G04_0_Msk                                    (0x1fUL << LCD_PAL5_G04_0_Pos)
#define LCD_PAL5_B04_0_Pos                                    10
#define LCD_PAL5_B04_0_Msk                                    (0x1fUL << LCD_PAL5_B04_0_Pos)
#define LCD_PAL5_I0_Pos                                       15
#define LCD_PAL5_I0_Msk                                       (0x01UL << LCD_PAL5_I0_Pos)
#define LCD_PAL5_R14_0_Pos                                    16
#define LCD_PAL5_R14_0_Msk                                    (0x1fUL << LCD_PAL5_R14_0_Pos)
#define LCD_PAL5_G14_0_Pos                                    21
#define LCD_PAL5_G14_0_Msk                                    (0x1fUL << LCD_PAL5_G14_0_Pos)
#define LCD_PAL5_B14_0_Pos                                    26
#define LCD_PAL5_B14_0_Msk                                    (0x1fUL << LCD_PAL5_B14_0_Pos)
#define LCD_PAL5_I1_Pos                                       31
#define LCD_PAL5_I1_Msk                                       (0x01UL << LCD_PAL5_I1_Pos)

// ----------------------------------------  LCD_PAL6  --------------------------------------------
#define LCD_PAL6_R04_0_Pos                                    0
#define LCD_PAL6_R04_0_Msk                                    (0x1fUL << LCD_PAL6_R04_0_Pos)
#define LCD_PAL6_G04_0_Pos                                    5
#define LCD_PAL6_G04_0_Msk                                    (0x1fUL << LCD_PAL6_G04_0_Pos)
#define LCD_PAL6_B04_0_Pos                                    10
#define LCD_PAL6_B04_0_Msk                                    (0x1fUL << LCD_PAL6_B04_0_Pos)
#define LCD_PAL6_I0_Pos                                       15
#define LCD_PAL6_I0_Msk                                       (0x01UL << LCD_PAL6_I0_Pos)
#define LCD_PAL6_R14_0_Pos                                    16
#define LCD_PAL6_R14_0_Msk                                    (0x1fUL << LCD_PAL6_R14_0_Pos)
#define LCD_PAL6_G14_0_Pos                                    21
#define LCD_PAL6_G14_0_Msk                                    (0x1fUL << LCD_PAL6_G14_0_Pos)
#define LCD_PAL6_B14_0_Pos                                    26
#define LCD_PAL6_B14_0_Msk                                    (0x1fUL << LCD_PAL6_B14_0_Pos)
#define LCD_PAL6_I1_Pos                                       31
#define LCD_PAL6_I1_Msk                                       (0x01UL << LCD_PAL6_I1_Pos)

// ----------------------------------------  LCD_PAL7  --------------------------------------------
#define LCD_PAL7_R04_0_Pos                                    0
#define LCD_PAL7_R04_0_Msk                                    (0x1fUL << LCD_PAL7_R04_0_Pos)
#define LCD_PAL7_G04_0_Pos                                    5
#define LCD_PAL7_G04_0_Msk                                    (0x1fUL << LCD_PAL7_G04_0_Pos)
#define LCD_PAL7_B04_0_Pos                                    10
#define LCD_PAL7_B04_0_Msk                                    (0x1fUL << LCD_PAL7_B04_0_Pos)
#define LCD_PAL7_I0_Pos                                       15
#define LCD_PAL7_I0_Msk                                       (0x01UL << LCD_PAL7_I0_Pos)
#define LCD_PAL7_R14_0_Pos                                    16
#define LCD_PAL7_R14_0_Msk                                    (0x1fUL << LCD_PAL7_R14_0_Pos)
#define LCD_PAL7_G14_0_Pos                                    21
#define LCD_PAL7_G14_0_Msk                                    (0x1fUL << LCD_PAL7_G14_0_Pos)
#define LCD_PAL7_B14_0_Pos                                    26
#define LCD_PAL7_B14_0_Msk                                    (0x1fUL << LCD_PAL7_B14_0_Pos)
#define LCD_PAL7_I1_Pos                                       31
#define LCD_PAL7_I1_Msk                                       (0x01UL << LCD_PAL7_I1_Pos)

// ----------------------------------------  LCD_PAL8  --------------------------------------------
#define LCD_PAL8_R04_0_Pos                                    0
#define LCD_PAL8_R04_0_Msk                                    (0x1fUL << LCD_PAL8_R04_0_Pos)
#define LCD_PAL8_G04_0_Pos                                    5
#define LCD_PAL8_G04_0_Msk                                    (0x1fUL << LCD_PAL8_G04_0_Pos)
#define LCD_PAL8_B04_0_Pos                                    10
#define LCD_PAL8_B04_0_Msk                                    (0x1fUL << LCD_PAL8_B04_0_Pos)
#define LCD_PAL8_I0_Pos                                       15
#define LCD_PAL8_I0_Msk                                       (0x01UL << LCD_PAL8_I0_Pos)
#define LCD_PAL8_R14_0_Pos                                    16
#define LCD_PAL8_R14_0_Msk                                    (0x1fUL << LCD_PAL8_R14_0_Pos)
#define LCD_PAL8_G14_0_Pos                                    21
#define LCD_PAL8_G14_0_Msk                                    (0x1fUL << LCD_PAL8_G14_0_Pos)
#define LCD_PAL8_B14_0_Pos                                    26
#define LCD_PAL8_B14_0_Msk                                    (0x1fUL << LCD_PAL8_B14_0_Pos)
#define LCD_PAL8_I1_Pos                                       31
#define LCD_PAL8_I1_Msk                                       (0x01UL << LCD_PAL8_I1_Pos)

// ----------------------------------------  LCD_PAL9  --------------------------------------------
#define LCD_PAL9_R04_0_Pos                                    0
#define LCD_PAL9_R04_0_Msk                                    (0x1fUL << LCD_PAL9_R04_0_Pos)
#define LCD_PAL9_G04_0_Pos                                    5
#define LCD_PAL9_G04_0_Msk                                    (0x1fUL << LCD_PAL9_G04_0_Pos)
#define LCD_PAL9_B04_0_Pos                                    10
#define LCD_PAL9_B04_0_Msk                                    (0x1fUL << LCD_PAL9_B04_0_Pos)
#define LCD_PAL9_I0_Pos                                       15
#define LCD_PAL9_I0_Msk                                       (0x01UL << LCD_PAL9_I0_Pos)
#define LCD_PAL9_R14_0_Pos                                    16
#define LCD_PAL9_R14_0_Msk                                    (0x1fUL << LCD_PAL9_R14_0_Pos)
#define LCD_PAL9_G14_0_Pos                                    21
#define LCD_PAL9_G14_0_Msk                                    (0x1fUL << LCD_PAL9_G14_0_Pos)
#define LCD_PAL9_B14_0_Pos                                    26
#define LCD_PAL9_B14_0_Msk                                    (0x1fUL << LCD_PAL9_B14_0_Pos)
#define LCD_PAL9_I1_Pos                                       31
#define LCD_PAL9_I1_Msk                                       (0x01UL << LCD_PAL9_I1_Pos)

// ----------------------------------------  LCD_PAL10  -------------------------------------------
#define LCD_PAL10_R04_0_Pos                                   0
#define LCD_PAL10_R04_0_Msk                                   (0x1fUL << LCD_PAL10_R04_0_Pos)
#define LCD_PAL10_G04_0_Pos                                   5
#define LCD_PAL10_G04_0_Msk                                   (0x1fUL << LCD_PAL10_G04_0_Pos)
#define LCD_PAL10_B04_0_Pos                                   10
#define LCD_PAL10_B04_0_Msk                                   (0x1fUL << LCD_PAL10_B04_0_Pos)
#define LCD_PAL10_I0_Pos                                      15
#define LCD_PAL10_I0_Msk                                      (0x01UL << LCD_PAL10_I0_Pos)
#define LCD_PAL10_R14_0_Pos                                   16
#define LCD_PAL10_R14_0_Msk                                   (0x1fUL << LCD_PAL10_R14_0_Pos)
#define LCD_PAL10_G14_0_Pos                                   21
#define LCD_PAL10_G14_0_Msk                                   (0x1fUL << LCD_PAL10_G14_0_Pos)
#define LCD_PAL10_B14_0_Pos                                   26
#define LCD_PAL10_B14_0_Msk                                   (0x1fUL << LCD_PAL10_B14_0_Pos)
#define LCD_PAL10_I1_Pos                                      31
#define LCD_PAL10_I1_Msk                                      (0x01UL << LCD_PAL10_I1_Pos)

// ----------------------------------------  LCD_PAL11  -------------------------------------------
#define LCD_PAL11_R04_0_Pos                                   0
#define LCD_PAL11_R04_0_Msk                                   (0x1fUL << LCD_PAL11_R04_0_Pos)
#define LCD_PAL11_G04_0_Pos                                   5
#define LCD_PAL11_G04_0_Msk                                   (0x1fUL << LCD_PAL11_G04_0_Pos)
#define LCD_PAL11_B04_0_Pos                                   10
#define LCD_PAL11_B04_0_Msk                                   (0x1fUL << LCD_PAL11_B04_0_Pos)
#define LCD_PAL11_I0_Pos                                      15
#define LCD_PAL11_I0_Msk                                      (0x01UL << LCD_PAL11_I0_Pos)
#define LCD_PAL11_R14_0_Pos                                   16
#define LCD_PAL11_R14_0_Msk                                   (0x1fUL << LCD_PAL11_R14_0_Pos)
#define LCD_PAL11_G14_0_Pos                                   21
#define LCD_PAL11_G14_0_Msk                                   (0x1fUL << LCD_PAL11_G14_0_Pos)
#define LCD_PAL11_B14_0_Pos                                   26
#define LCD_PAL11_B14_0_Msk                                   (0x1fUL << LCD_PAL11_B14_0_Pos)
#define LCD_PAL11_I1_Pos                                      31
#define LCD_PAL11_I1_Msk                                      (0x01UL << LCD_PAL11_I1_Pos)

// ----------------------------------------  LCD_PAL12  -------------------------------------------
#define LCD_PAL12_R04_0_Pos                                   0
#define LCD_PAL12_R04_0_Msk                                   (0x1fUL << LCD_PAL12_R04_0_Pos)
#define LCD_PAL12_G04_0_Pos                                   5
#define LCD_PAL12_G04_0_Msk                                   (0x1fUL << LCD_PAL12_G04_0_Pos)
#define LCD_PAL12_B04_0_Pos                                   10
#define LCD_PAL12_B04_0_Msk                                   (0x1fUL << LCD_PAL12_B04_0_Pos)
#define LCD_PAL12_I0_Pos                                      15
#define LCD_PAL12_I0_Msk                                      (0x01UL << LCD_PAL12_I0_Pos)
#define LCD_PAL12_R14_0_Pos                                   16
#define LCD_PAL12_R14_0_Msk                                   (0x1fUL << LCD_PAL12_R14_0_Pos)
#define LCD_PAL12_G14_0_Pos                                   21
#define LCD_PAL12_G14_0_Msk                                   (0x1fUL << LCD_PAL12_G14_0_Pos)
#define LCD_PAL12_B14_0_Pos                                   26
#define LCD_PAL12_B14_0_Msk                                   (0x1fUL << LCD_PAL12_B14_0_Pos)
#define LCD_PAL12_I1_Pos                                      31
#define LCD_PAL12_I1_Msk                                      (0x01UL << LCD_PAL12_I1_Pos)

// ----------------------------------------  LCD_PAL13  -------------------------------------------
#define LCD_PAL13_R04_0_Pos                                   0
#define LCD_PAL13_R04_0_Msk                                   (0x1fUL << LCD_PAL13_R04_0_Pos)
#define LCD_PAL13_G04_0_Pos                                   5
#define LCD_PAL13_G04_0_Msk                                   (0x1fUL << LCD_PAL13_G04_0_Pos)
#define LCD_PAL13_B04_0_Pos                                   10
#define LCD_PAL13_B04_0_Msk                                   (0x1fUL << LCD_PAL13_B04_0_Pos)
#define LCD_PAL13_I0_Pos                                      15
#define LCD_PAL13_I0_Msk                                      (0x01UL << LCD_PAL13_I0_Pos)
#define LCD_PAL13_R14_0_Pos                                   16
#define LCD_PAL13_R14_0_Msk                                   (0x1fUL << LCD_PAL13_R14_0_Pos)
#define LCD_PAL13_G14_0_Pos                                   21
#define LCD_PAL13_G14_0_Msk                                   (0x1fUL << LCD_PAL13_G14_0_Pos)
#define LCD_PAL13_B14_0_Pos                                   26
#define LCD_PAL13_B14_0_Msk                                   (0x1fUL << LCD_PAL13_B14_0_Pos)
#define LCD_PAL13_I1_Pos                                      31
#define LCD_PAL13_I1_Msk                                      (0x01UL << LCD_PAL13_I1_Pos)

// ----------------------------------------  LCD_PAL14  -------------------------------------------
#define LCD_PAL14_R04_0_Pos                                   0
#define LCD_PAL14_R04_0_Msk                                   (0x1fUL << LCD_PAL14_R04_0_Pos)
#define LCD_PAL14_G04_0_Pos                                   5
#define LCD_PAL14_G04_0_Msk                                   (0x1fUL << LCD_PAL14_G04_0_Pos)
#define LCD_PAL14_B04_0_Pos                                   10
#define LCD_PAL14_B04_0_Msk                                   (0x1fUL << LCD_PAL14_B04_0_Pos)
#define LCD_PAL14_I0_Pos                                      15
#define LCD_PAL14_I0_Msk                                      (0x01UL << LCD_PAL14_I0_Pos)
#define LCD_PAL14_R14_0_Pos                                   16
#define LCD_PAL14_R14_0_Msk                                   (0x1fUL << LCD_PAL14_R14_0_Pos)
#define LCD_PAL14_G14_0_Pos                                   21
#define LCD_PAL14_G14_0_Msk                                   (0x1fUL << LCD_PAL14_G14_0_Pos)
#define LCD_PAL14_B14_0_Pos                                   26
#define LCD_PAL14_B14_0_Msk                                   (0x1fUL << LCD_PAL14_B14_0_Pos)
#define LCD_PAL14_I1_Pos                                      31
#define LCD_PAL14_I1_Msk                                      (0x01UL << LCD_PAL14_I1_Pos)

// ----------------------------------------  LCD_PAL15  -------------------------------------------
#define LCD_PAL15_R04_0_Pos                                   0
#define LCD_PAL15_R04_0_Msk                                   (0x1fUL << LCD_PAL15_R04_0_Pos)
#define LCD_PAL15_G04_0_Pos                                   5
#define LCD_PAL15_G04_0_Msk                                   (0x1fUL << LCD_PAL15_G04_0_Pos)
#define LCD_PAL15_B04_0_Pos                                   10
#define LCD_PAL15_B04_0_Msk                                   (0x1fUL << LCD_PAL15_B04_0_Pos)
#define LCD_PAL15_I0_Pos                                      15
#define LCD_PAL15_I0_Msk                                      (0x01UL << LCD_PAL15_I0_Pos)
#define LCD_PAL15_R14_0_Pos                                   16
#define LCD_PAL15_R14_0_Msk                                   (0x1fUL << LCD_PAL15_R14_0_Pos)
#define LCD_PAL15_G14_0_Pos                                   21
#define LCD_PAL15_G14_0_Msk                                   (0x1fUL << LCD_PAL15_G14_0_Pos)
#define LCD_PAL15_B14_0_Pos                                   26
#define LCD_PAL15_B14_0_Msk                                   (0x1fUL << LCD_PAL15_B14_0_Pos)
#define LCD_PAL15_I1_Pos                                      31
#define LCD_PAL15_I1_Msk                                      (0x01UL << LCD_PAL15_I1_Pos)

// ----------------------------------------  LCD_PAL16  -------------------------------------------
#define LCD_PAL16_R04_0_Pos                                   0
#define LCD_PAL16_R04_0_Msk                                   (0x1fUL << LCD_PAL16_R04_0_Pos)
#define LCD_PAL16_G04_0_Pos                                   5
#define LCD_PAL16_G04_0_Msk                                   (0x1fUL << LCD_PAL16_G04_0_Pos)
#define LCD_PAL16_B04_0_Pos                                   10
#define LCD_PAL16_B04_0_Msk                                   (0x1fUL << LCD_PAL16_B04_0_Pos)
#define LCD_PAL16_I0_Pos                                      15
#define LCD_PAL16_I0_Msk                                      (0x01UL << LCD_PAL16_I0_Pos)
#define LCD_PAL16_R14_0_Pos                                   16
#define LCD_PAL16_R14_0_Msk                                   (0x1fUL << LCD_PAL16_R14_0_Pos)
#define LCD_PAL16_G14_0_Pos                                   21
#define LCD_PAL16_G14_0_Msk                                   (0x1fUL << LCD_PAL16_G14_0_Pos)
#define LCD_PAL16_B14_0_Pos                                   26
#define LCD_PAL16_B14_0_Msk                                   (0x1fUL << LCD_PAL16_B14_0_Pos)
#define LCD_PAL16_I1_Pos                                      31
#define LCD_PAL16_I1_Msk                                      (0x01UL << LCD_PAL16_I1_Pos)

// ----------------------------------------  LCD_PAL17  -------------------------------------------
#define LCD_PAL17_R04_0_Pos                                   0
#define LCD_PAL17_R04_0_Msk                                   (0x1fUL << LCD_PAL17_R04_0_Pos)
#define LCD_PAL17_G04_0_Pos                                   5
#define LCD_PAL17_G04_0_Msk                                   (0x1fUL << LCD_PAL17_G04_0_Pos)
#define LCD_PAL17_B04_0_Pos                                   10
#define LCD_PAL17_B04_0_Msk                                   (0x1fUL << LCD_PAL17_B04_0_Pos)
#define LCD_PAL17_I0_Pos                                      15
#define LCD_PAL17_I0_Msk                                      (0x01UL << LCD_PAL17_I0_Pos)
#define LCD_PAL17_R14_0_Pos                                   16
#define LCD_PAL17_R14_0_Msk                                   (0x1fUL << LCD_PAL17_R14_0_Pos)
#define LCD_PAL17_G14_0_Pos                                   21
#define LCD_PAL17_G14_0_Msk                                   (0x1fUL << LCD_PAL17_G14_0_Pos)
#define LCD_PAL17_B14_0_Pos                                   26
#define LCD_PAL17_B14_0_Msk                                   (0x1fUL << LCD_PAL17_B14_0_Pos)
#define LCD_PAL17_I1_Pos                                      31
#define LCD_PAL17_I1_Msk                                      (0x01UL << LCD_PAL17_I1_Pos)

// ----------------------------------------  LCD_PAL18  -------------------------------------------
#define LCD_PAL18_R04_0_Pos                                   0
#define LCD_PAL18_R04_0_Msk                                   (0x1fUL << LCD_PAL18_R04_0_Pos)
#define LCD_PAL18_G04_0_Pos                                   5
#define LCD_PAL18_G04_0_Msk                                   (0x1fUL << LCD_PAL18_G04_0_Pos)
#define LCD_PAL18_B04_0_Pos                                   10
#define LCD_PAL18_B04_0_Msk                                   (0x1fUL << LCD_PAL18_B04_0_Pos)
#define LCD_PAL18_I0_Pos                                      15
#define LCD_PAL18_I0_Msk                                      (0x01UL << LCD_PAL18_I0_Pos)
#define LCD_PAL18_R14_0_Pos                                   16
#define LCD_PAL18_R14_0_Msk                                   (0x1fUL << LCD_PAL18_R14_0_Pos)
#define LCD_PAL18_G14_0_Pos                                   21
#define LCD_PAL18_G14_0_Msk                                   (0x1fUL << LCD_PAL18_G14_0_Pos)
#define LCD_PAL18_B14_0_Pos                                   26
#define LCD_PAL18_B14_0_Msk                                   (0x1fUL << LCD_PAL18_B14_0_Pos)
#define LCD_PAL18_I1_Pos                                      31
#define LCD_PAL18_I1_Msk                                      (0x01UL << LCD_PAL18_I1_Pos)

// ----------------------------------------  LCD_PAL19  -------------------------------------------
#define LCD_PAL19_R04_0_Pos                                   0
#define LCD_PAL19_R04_0_Msk                                   (0x1fUL << LCD_PAL19_R04_0_Pos)
#define LCD_PAL19_G04_0_Pos                                   5
#define LCD_PAL19_G04_0_Msk                                   (0x1fUL << LCD_PAL19_G04_0_Pos)
#define LCD_PAL19_B04_0_Pos                                   10
#define LCD_PAL19_B04_0_Msk                                   (0x1fUL << LCD_PAL19_B04_0_Pos)
#define LCD_PAL19_I0_Pos                                      15
#define LCD_PAL19_I0_Msk                                      (0x01UL << LCD_PAL19_I0_Pos)
#define LCD_PAL19_R14_0_Pos                                   16
#define LCD_PAL19_R14_0_Msk                                   (0x1fUL << LCD_PAL19_R14_0_Pos)
#define LCD_PAL19_G14_0_Pos                                   21
#define LCD_PAL19_G14_0_Msk                                   (0x1fUL << LCD_PAL19_G14_0_Pos)
#define LCD_PAL19_B14_0_Pos                                   26
#define LCD_PAL19_B14_0_Msk                                   (0x1fUL << LCD_PAL19_B14_0_Pos)
#define LCD_PAL19_I1_Pos                                      31
#define LCD_PAL19_I1_Msk                                      (0x01UL << LCD_PAL19_I1_Pos)

// ----------------------------------------  LCD_PAL20  -------------------------------------------
#define LCD_PAL20_R04_0_Pos                                   0
#define LCD_PAL20_R04_0_Msk                                   (0x1fUL << LCD_PAL20_R04_0_Pos)
#define LCD_PAL20_G04_0_Pos                                   5
#define LCD_PAL20_G04_0_Msk                                   (0x1fUL << LCD_PAL20_G04_0_Pos)
#define LCD_PAL20_B04_0_Pos                                   10
#define LCD_PAL20_B04_0_Msk                                   (0x1fUL << LCD_PAL20_B04_0_Pos)
#define LCD_PAL20_I0_Pos                                      15
#define LCD_PAL20_I0_Msk                                      (0x01UL << LCD_PAL20_I0_Pos)
#define LCD_PAL20_R14_0_Pos                                   16
#define LCD_PAL20_R14_0_Msk                                   (0x1fUL << LCD_PAL20_R14_0_Pos)
#define LCD_PAL20_G14_0_Pos                                   21
#define LCD_PAL20_G14_0_Msk                                   (0x1fUL << LCD_PAL20_G14_0_Pos)
#define LCD_PAL20_B14_0_Pos                                   26
#define LCD_PAL20_B14_0_Msk                                   (0x1fUL << LCD_PAL20_B14_0_Pos)
#define LCD_PAL20_I1_Pos                                      31
#define LCD_PAL20_I1_Msk                                      (0x01UL << LCD_PAL20_I1_Pos)

// ----------------------------------------  LCD_PAL21  -------------------------------------------
#define LCD_PAL21_R04_0_Pos                                   0
#define LCD_PAL21_R04_0_Msk                                   (0x1fUL << LCD_PAL21_R04_0_Pos)
#define LCD_PAL21_G04_0_Pos                                   5
#define LCD_PAL21_G04_0_Msk                                   (0x1fUL << LCD_PAL21_G04_0_Pos)
#define LCD_PAL21_B04_0_Pos                                   10
#define LCD_PAL21_B04_0_Msk                                   (0x1fUL << LCD_PAL21_B04_0_Pos)
#define LCD_PAL21_I0_Pos                                      15
#define LCD_PAL21_I0_Msk                                      (0x01UL << LCD_PAL21_I0_Pos)
#define LCD_PAL21_R14_0_Pos                                   16
#define LCD_PAL21_R14_0_Msk                                   (0x1fUL << LCD_PAL21_R14_0_Pos)
#define LCD_PAL21_G14_0_Pos                                   21
#define LCD_PAL21_G14_0_Msk                                   (0x1fUL << LCD_PAL21_G14_0_Pos)
#define LCD_PAL21_B14_0_Pos                                   26
#define LCD_PAL21_B14_0_Msk                                   (0x1fUL << LCD_PAL21_B14_0_Pos)
#define LCD_PAL21_I1_Pos                                      31
#define LCD_PAL21_I1_Msk                                      (0x01UL << LCD_PAL21_I1_Pos)

// ----------------------------------------  LCD_PAL22  -------------------------------------------
#define LCD_PAL22_R04_0_Pos                                   0
#define LCD_PAL22_R04_0_Msk                                   (0x1fUL << LCD_PAL22_R04_0_Pos)
#define LCD_PAL22_G04_0_Pos                                   5
#define LCD_PAL22_G04_0_Msk                                   (0x1fUL << LCD_PAL22_G04_0_Pos)
#define LCD_PAL22_B04_0_Pos                                   10
#define LCD_PAL22_B04_0_Msk                                   (0x1fUL << LCD_PAL22_B04_0_Pos)
#define LCD_PAL22_I0_Pos                                      15
#define LCD_PAL22_I0_Msk                                      (0x01UL << LCD_PAL22_I0_Pos)
#define LCD_PAL22_R14_0_Pos                                   16
#define LCD_PAL22_R14_0_Msk                                   (0x1fUL << LCD_PAL22_R14_0_Pos)
#define LCD_PAL22_G14_0_Pos                                   21
#define LCD_PAL22_G14_0_Msk                                   (0x1fUL << LCD_PAL22_G14_0_Pos)
#define LCD_PAL22_B14_0_Pos                                   26
#define LCD_PAL22_B14_0_Msk                                   (0x1fUL << LCD_PAL22_B14_0_Pos)
#define LCD_PAL22_I1_Pos                                      31
#define LCD_PAL22_I1_Msk                                      (0x01UL << LCD_PAL22_I1_Pos)

// ----------------------------------------  LCD_PAL23  -------------------------------------------
#define LCD_PAL23_R04_0_Pos                                   0
#define LCD_PAL23_R04_0_Msk                                   (0x1fUL << LCD_PAL23_R04_0_Pos)
#define LCD_PAL23_G04_0_Pos                                   5
#define LCD_PAL23_G04_0_Msk                                   (0x1fUL << LCD_PAL23_G04_0_Pos)
#define LCD_PAL23_B04_0_Pos                                   10
#define LCD_PAL23_B04_0_Msk                                   (0x1fUL << LCD_PAL23_B04_0_Pos)
#define LCD_PAL23_I0_Pos                                      15
#define LCD_PAL23_I0_Msk                                      (0x01UL << LCD_PAL23_I0_Pos)
#define LCD_PAL23_R14_0_Pos                                   16
#define LCD_PAL23_R14_0_Msk                                   (0x1fUL << LCD_PAL23_R14_0_Pos)
#define LCD_PAL23_G14_0_Pos                                   21
#define LCD_PAL23_G14_0_Msk                                   (0x1fUL << LCD_PAL23_G14_0_Pos)
#define LCD_PAL23_B14_0_Pos                                   26
#define LCD_PAL23_B14_0_Msk                                   (0x1fUL << LCD_PAL23_B14_0_Pos)
#define LCD_PAL23_I1_Pos                                      31
#define LCD_PAL23_I1_Msk                                      (0x01UL << LCD_PAL23_I1_Pos)

// ----------------------------------------  LCD_PAL24  -------------------------------------------
#define LCD_PAL24_R04_0_Pos                                   0
#define LCD_PAL24_R04_0_Msk                                   (0x1fUL << LCD_PAL24_R04_0_Pos)
#define LCD_PAL24_G04_0_Pos                                   5
#define LCD_PAL24_G04_0_Msk                                   (0x1fUL << LCD_PAL24_G04_0_Pos)
#define LCD_PAL24_B04_0_Pos                                   10
#define LCD_PAL24_B04_0_Msk                                   (0x1fUL << LCD_PAL24_B04_0_Pos)
#define LCD_PAL24_I0_Pos                                      15
#define LCD_PAL24_I0_Msk                                      (0x01UL << LCD_PAL24_I0_Pos)
#define LCD_PAL24_R14_0_Pos                                   16
#define LCD_PAL24_R14_0_Msk                                   (0x1fUL << LCD_PAL24_R14_0_Pos)
#define LCD_PAL24_G14_0_Pos                                   21
#define LCD_PAL24_G14_0_Msk                                   (0x1fUL << LCD_PAL24_G14_0_Pos)
#define LCD_PAL24_B14_0_Pos                                   26
#define LCD_PAL24_B14_0_Msk                                   (0x1fUL << LCD_PAL24_B14_0_Pos)
#define LCD_PAL24_I1_Pos                                      31
#define LCD_PAL24_I1_Msk                                      (0x01UL << LCD_PAL24_I1_Pos)

// ----------------------------------------  LCD_PAL25  -------------------------------------------
#define LCD_PAL25_R04_0_Pos                                   0
#define LCD_PAL25_R04_0_Msk                                   (0x1fUL << LCD_PAL25_R04_0_Pos)
#define LCD_PAL25_G04_0_Pos                                   5
#define LCD_PAL25_G04_0_Msk                                   (0x1fUL << LCD_PAL25_G04_0_Pos)
#define LCD_PAL25_B04_0_Pos                                   10
#define LCD_PAL25_B04_0_Msk                                   (0x1fUL << LCD_PAL25_B04_0_Pos)
#define LCD_PAL25_I0_Pos                                      15
#define LCD_PAL25_I0_Msk                                      (0x01UL << LCD_PAL25_I0_Pos)
#define LCD_PAL25_R14_0_Pos                                   16
#define LCD_PAL25_R14_0_Msk                                   (0x1fUL << LCD_PAL25_R14_0_Pos)
#define LCD_PAL25_G14_0_Pos                                   21
#define LCD_PAL25_G14_0_Msk                                   (0x1fUL << LCD_PAL25_G14_0_Pos)
#define LCD_PAL25_B14_0_Pos                                   26
#define LCD_PAL25_B14_0_Msk                                   (0x1fUL << LCD_PAL25_B14_0_Pos)
#define LCD_PAL25_I1_Pos                                      31
#define LCD_PAL25_I1_Msk                                      (0x01UL << LCD_PAL25_I1_Pos)

// ----------------------------------------  LCD_PAL26  -------------------------------------------
#define LCD_PAL26_R04_0_Pos                                   0
#define LCD_PAL26_R04_0_Msk                                   (0x1fUL << LCD_PAL26_R04_0_Pos)
#define LCD_PAL26_G04_0_Pos                                   5
#define LCD_PAL26_G04_0_Msk                                   (0x1fUL << LCD_PAL26_G04_0_Pos)
#define LCD_PAL26_B04_0_Pos                                   10
#define LCD_PAL26_B04_0_Msk                                   (0x1fUL << LCD_PAL26_B04_0_Pos)
#define LCD_PAL26_I0_Pos                                      15
#define LCD_PAL26_I0_Msk                                      (0x01UL << LCD_PAL26_I0_Pos)
#define LCD_PAL26_R14_0_Pos                                   16
#define LCD_PAL26_R14_0_Msk                                   (0x1fUL << LCD_PAL26_R14_0_Pos)
#define LCD_PAL26_G14_0_Pos                                   21
#define LCD_PAL26_G14_0_Msk                                   (0x1fUL << LCD_PAL26_G14_0_Pos)
#define LCD_PAL26_B14_0_Pos                                   26
#define LCD_PAL26_B14_0_Msk                                   (0x1fUL << LCD_PAL26_B14_0_Pos)
#define LCD_PAL26_I1_Pos                                      31
#define LCD_PAL26_I1_Msk                                      (0x01UL << LCD_PAL26_I1_Pos)

// ----------------------------------------  LCD_PAL27  -------------------------------------------
#define LCD_PAL27_R04_0_Pos                                   0
#define LCD_PAL27_R04_0_Msk                                   (0x1fUL << LCD_PAL27_R04_0_Pos)
#define LCD_PAL27_G04_0_Pos                                   5
#define LCD_PAL27_G04_0_Msk                                   (0x1fUL << LCD_PAL27_G04_0_Pos)
#define LCD_PAL27_B04_0_Pos                                   10
#define LCD_PAL27_B04_0_Msk                                   (0x1fUL << LCD_PAL27_B04_0_Pos)
#define LCD_PAL27_I0_Pos                                      15
#define LCD_PAL27_I0_Msk                                      (0x01UL << LCD_PAL27_I0_Pos)
#define LCD_PAL27_R14_0_Pos                                   16
#define LCD_PAL27_R14_0_Msk                                   (0x1fUL << LCD_PAL27_R14_0_Pos)
#define LCD_PAL27_G14_0_Pos                                   21
#define LCD_PAL27_G14_0_Msk                                   (0x1fUL << LCD_PAL27_G14_0_Pos)
#define LCD_PAL27_B14_0_Pos                                   26
#define LCD_PAL27_B14_0_Msk                                   (0x1fUL << LCD_PAL27_B14_0_Pos)
#define LCD_PAL27_I1_Pos                                      31
#define LCD_PAL27_I1_Msk                                      (0x01UL << LCD_PAL27_I1_Pos)

// ----------------------------------------  LCD_PAL28  -------------------------------------------
#define LCD_PAL28_R04_0_Pos                                   0
#define LCD_PAL28_R04_0_Msk                                   (0x1fUL << LCD_PAL28_R04_0_Pos)
#define LCD_PAL28_G04_0_Pos                                   5
#define LCD_PAL28_G04_0_Msk                                   (0x1fUL << LCD_PAL28_G04_0_Pos)
#define LCD_PAL28_B04_0_Pos                                   10
#define LCD_PAL28_B04_0_Msk                                   (0x1fUL << LCD_PAL28_B04_0_Pos)
#define LCD_PAL28_I0_Pos                                      15
#define LCD_PAL28_I0_Msk                                      (0x01UL << LCD_PAL28_I0_Pos)
#define LCD_PAL28_R14_0_Pos                                   16
#define LCD_PAL28_R14_0_Msk                                   (0x1fUL << LCD_PAL28_R14_0_Pos)
#define LCD_PAL28_G14_0_Pos                                   21
#define LCD_PAL28_G14_0_Msk                                   (0x1fUL << LCD_PAL28_G14_0_Pos)
#define LCD_PAL28_B14_0_Pos                                   26
#define LCD_PAL28_B14_0_Msk                                   (0x1fUL << LCD_PAL28_B14_0_Pos)
#define LCD_PAL28_I1_Pos                                      31
#define LCD_PAL28_I1_Msk                                      (0x01UL << LCD_PAL28_I1_Pos)

// ----------------------------------------  LCD_PAL29  -------------------------------------------
#define LCD_PAL29_R04_0_Pos                                   0
#define LCD_PAL29_R04_0_Msk                                   (0x1fUL << LCD_PAL29_R04_0_Pos)
#define LCD_PAL29_G04_0_Pos                                   5
#define LCD_PAL29_G04_0_Msk                                   (0x1fUL << LCD_PAL29_G04_0_Pos)
#define LCD_PAL29_B04_0_Pos                                   10
#define LCD_PAL29_B04_0_Msk                                   (0x1fUL << LCD_PAL29_B04_0_Pos)
#define LCD_PAL29_I0_Pos                                      15
#define LCD_PAL29_I0_Msk                                      (0x01UL << LCD_PAL29_I0_Pos)
#define LCD_PAL29_R14_0_Pos                                   16
#define LCD_PAL29_R14_0_Msk                                   (0x1fUL << LCD_PAL29_R14_0_Pos)
#define LCD_PAL29_G14_0_Pos                                   21
#define LCD_PAL29_G14_0_Msk                                   (0x1fUL << LCD_PAL29_G14_0_Pos)
#define LCD_PAL29_B14_0_Pos                                   26
#define LCD_PAL29_B14_0_Msk                                   (0x1fUL << LCD_PAL29_B14_0_Pos)
#define LCD_PAL29_I1_Pos                                      31
#define LCD_PAL29_I1_Msk                                      (0x01UL << LCD_PAL29_I1_Pos)

// ----------------------------------------  LCD_PAL30  -------------------------------------------
#define LCD_PAL30_R04_0_Pos                                   0
#define LCD_PAL30_R04_0_Msk                                   (0x1fUL << LCD_PAL30_R04_0_Pos)
#define LCD_PAL30_G04_0_Pos                                   5
#define LCD_PAL30_G04_0_Msk                                   (0x1fUL << LCD_PAL30_G04_0_Pos)
#define LCD_PAL30_B04_0_Pos                                   10
#define LCD_PAL30_B04_0_Msk                                   (0x1fUL << LCD_PAL30_B04_0_Pos)
#define LCD_PAL30_I0_Pos                                      15
#define LCD_PAL30_I0_Msk                                      (0x01UL << LCD_PAL30_I0_Pos)
#define LCD_PAL30_R14_0_Pos                                   16
#define LCD_PAL30_R14_0_Msk                                   (0x1fUL << LCD_PAL30_R14_0_Pos)
#define LCD_PAL30_G14_0_Pos                                   21
#define LCD_PAL30_G14_0_Msk                                   (0x1fUL << LCD_PAL30_G14_0_Pos)
#define LCD_PAL30_B14_0_Pos                                   26
#define LCD_PAL30_B14_0_Msk                                   (0x1fUL << LCD_PAL30_B14_0_Pos)
#define LCD_PAL30_I1_Pos                                      31
#define LCD_PAL30_I1_Msk                                      (0x01UL << LCD_PAL30_I1_Pos)

// ----------------------------------------  LCD_PAL31  -------------------------------------------
#define LCD_PAL31_R04_0_Pos                                   0
#define LCD_PAL31_R04_0_Msk                                   (0x1fUL << LCD_PAL31_R04_0_Pos)
#define LCD_PAL31_G04_0_Pos                                   5
#define LCD_PAL31_G04_0_Msk                                   (0x1fUL << LCD_PAL31_G04_0_Pos)
#define LCD_PAL31_B04_0_Pos                                   10
#define LCD_PAL31_B04_0_Msk                                   (0x1fUL << LCD_PAL31_B04_0_Pos)
#define LCD_PAL31_I0_Pos                                      15
#define LCD_PAL31_I0_Msk                                      (0x01UL << LCD_PAL31_I0_Pos)
#define LCD_PAL31_R14_0_Pos                                   16
#define LCD_PAL31_R14_0_Msk                                   (0x1fUL << LCD_PAL31_R14_0_Pos)
#define LCD_PAL31_G14_0_Pos                                   21
#define LCD_PAL31_G14_0_Msk                                   (0x1fUL << LCD_PAL31_G14_0_Pos)
#define LCD_PAL31_B14_0_Pos                                   26
#define LCD_PAL31_B14_0_Msk                                   (0x1fUL << LCD_PAL31_B14_0_Pos)
#define LCD_PAL31_I1_Pos                                      31
#define LCD_PAL31_I1_Msk                                      (0x01UL << LCD_PAL31_I1_Pos)

// ----------------------------------------  LCD_PAL32  -------------------------------------------
#define LCD_PAL32_R04_0_Pos                                   0
#define LCD_PAL32_R04_0_Msk                                   (0x1fUL << LCD_PAL32_R04_0_Pos)
#define LCD_PAL32_G04_0_Pos                                   5
#define LCD_PAL32_G04_0_Msk                                   (0x1fUL << LCD_PAL32_G04_0_Pos)
#define LCD_PAL32_B04_0_Pos                                   10
#define LCD_PAL32_B04_0_Msk                                   (0x1fUL << LCD_PAL32_B04_0_Pos)
#define LCD_PAL32_I0_Pos                                      15
#define LCD_PAL32_I0_Msk                                      (0x01UL << LCD_PAL32_I0_Pos)
#define LCD_PAL32_R14_0_Pos                                   16
#define LCD_PAL32_R14_0_Msk                                   (0x1fUL << LCD_PAL32_R14_0_Pos)
#define LCD_PAL32_G14_0_Pos                                   21
#define LCD_PAL32_G14_0_Msk                                   (0x1fUL << LCD_PAL32_G14_0_Pos)
#define LCD_PAL32_B14_0_Pos                                   26
#define LCD_PAL32_B14_0_Msk                                   (0x1fUL << LCD_PAL32_B14_0_Pos)
#define LCD_PAL32_I1_Pos                                      31
#define LCD_PAL32_I1_Msk                                      (0x01UL << LCD_PAL32_I1_Pos)

// ----------------------------------------  LCD_PAL33  -------------------------------------------
#define LCD_PAL33_R04_0_Pos                                   0
#define LCD_PAL33_R04_0_Msk                                   (0x1fUL << LCD_PAL33_R04_0_Pos)
#define LCD_PAL33_G04_0_Pos                                   5
#define LCD_PAL33_G04_0_Msk                                   (0x1fUL << LCD_PAL33_G04_0_Pos)
#define LCD_PAL33_B04_0_Pos                                   10
#define LCD_PAL33_B04_0_Msk                                   (0x1fUL << LCD_PAL33_B04_0_Pos)
#define LCD_PAL33_I0_Pos                                      15
#define LCD_PAL33_I0_Msk                                      (0x01UL << LCD_PAL33_I0_Pos)
#define LCD_PAL33_R14_0_Pos                                   16
#define LCD_PAL33_R14_0_Msk                                   (0x1fUL << LCD_PAL33_R14_0_Pos)
#define LCD_PAL33_G14_0_Pos                                   21
#define LCD_PAL33_G14_0_Msk                                   (0x1fUL << LCD_PAL33_G14_0_Pos)
#define LCD_PAL33_B14_0_Pos                                   26
#define LCD_PAL33_B14_0_Msk                                   (0x1fUL << LCD_PAL33_B14_0_Pos)
#define LCD_PAL33_I1_Pos                                      31
#define LCD_PAL33_I1_Msk                                      (0x01UL << LCD_PAL33_I1_Pos)

// ----------------------------------------  LCD_PAL34  -------------------------------------------
#define LCD_PAL34_R04_0_Pos                                   0
#define LCD_PAL34_R04_0_Msk                                   (0x1fUL << LCD_PAL34_R04_0_Pos)
#define LCD_PAL34_G04_0_Pos                                   5
#define LCD_PAL34_G04_0_Msk                                   (0x1fUL << LCD_PAL34_G04_0_Pos)
#define LCD_PAL34_B04_0_Pos                                   10
#define LCD_PAL34_B04_0_Msk                                   (0x1fUL << LCD_PAL34_B04_0_Pos)
#define LCD_PAL34_I0_Pos                                      15
#define LCD_PAL34_I0_Msk                                      (0x01UL << LCD_PAL34_I0_Pos)
#define LCD_PAL34_R14_0_Pos                                   16
#define LCD_PAL34_R14_0_Msk                                   (0x1fUL << LCD_PAL34_R14_0_Pos)
#define LCD_PAL34_G14_0_Pos                                   21
#define LCD_PAL34_G14_0_Msk                                   (0x1fUL << LCD_PAL34_G14_0_Pos)
#define LCD_PAL34_B14_0_Pos                                   26
#define LCD_PAL34_B14_0_Msk                                   (0x1fUL << LCD_PAL34_B14_0_Pos)
#define LCD_PAL34_I1_Pos                                      31
#define LCD_PAL34_I1_Msk                                      (0x01UL << LCD_PAL34_I1_Pos)

// ----------------------------------------  LCD_PAL35  -------------------------------------------
#define LCD_PAL35_R04_0_Pos                                   0
#define LCD_PAL35_R04_0_Msk                                   (0x1fUL << LCD_PAL35_R04_0_Pos)
#define LCD_PAL35_G04_0_Pos                                   5
#define LCD_PAL35_G04_0_Msk                                   (0x1fUL << LCD_PAL35_G04_0_Pos)
#define LCD_PAL35_B04_0_Pos                                   10
#define LCD_PAL35_B04_0_Msk                                   (0x1fUL << LCD_PAL35_B04_0_Pos)
#define LCD_PAL35_I0_Pos                                      15
#define LCD_PAL35_I0_Msk                                      (0x01UL << LCD_PAL35_I0_Pos)
#define LCD_PAL35_R14_0_Pos                                   16
#define LCD_PAL35_R14_0_Msk                                   (0x1fUL << LCD_PAL35_R14_0_Pos)
#define LCD_PAL35_G14_0_Pos                                   21
#define LCD_PAL35_G14_0_Msk                                   (0x1fUL << LCD_PAL35_G14_0_Pos)
#define LCD_PAL35_B14_0_Pos                                   26
#define LCD_PAL35_B14_0_Msk                                   (0x1fUL << LCD_PAL35_B14_0_Pos)
#define LCD_PAL35_I1_Pos                                      31
#define LCD_PAL35_I1_Msk                                      (0x01UL << LCD_PAL35_I1_Pos)

// ----------------------------------------  LCD_PAL36  -------------------------------------------
#define LCD_PAL36_R04_0_Pos                                   0
#define LCD_PAL36_R04_0_Msk                                   (0x1fUL << LCD_PAL36_R04_0_Pos)
#define LCD_PAL36_G04_0_Pos                                   5
#define LCD_PAL36_G04_0_Msk                                   (0x1fUL << LCD_PAL36_G04_0_Pos)
#define LCD_PAL36_B04_0_Pos                                   10
#define LCD_PAL36_B04_0_Msk                                   (0x1fUL << LCD_PAL36_B04_0_Pos)
#define LCD_PAL36_I0_Pos                                      15
#define LCD_PAL36_I0_Msk                                      (0x01UL << LCD_PAL36_I0_Pos)
#define LCD_PAL36_R14_0_Pos                                   16
#define LCD_PAL36_R14_0_Msk                                   (0x1fUL << LCD_PAL36_R14_0_Pos)
#define LCD_PAL36_G14_0_Pos                                   21
#define LCD_PAL36_G14_0_Msk                                   (0x1fUL << LCD_PAL36_G14_0_Pos)
#define LCD_PAL36_B14_0_Pos                                   26
#define LCD_PAL36_B14_0_Msk                                   (0x1fUL << LCD_PAL36_B14_0_Pos)
#define LCD_PAL36_I1_Pos                                      31
#define LCD_PAL36_I1_Msk                                      (0x01UL << LCD_PAL36_I1_Pos)

// ----------------------------------------  LCD_PAL37  -------------------------------------------
#define LCD_PAL37_R04_0_Pos                                   0
#define LCD_PAL37_R04_0_Msk                                   (0x1fUL << LCD_PAL37_R04_0_Pos)
#define LCD_PAL37_G04_0_Pos                                   5
#define LCD_PAL37_G04_0_Msk                                   (0x1fUL << LCD_PAL37_G04_0_Pos)
#define LCD_PAL37_B04_0_Pos                                   10
#define LCD_PAL37_B04_0_Msk                                   (0x1fUL << LCD_PAL37_B04_0_Pos)
#define LCD_PAL37_I0_Pos                                      15
#define LCD_PAL37_I0_Msk                                      (0x01UL << LCD_PAL37_I0_Pos)
#define LCD_PAL37_R14_0_Pos                                   16
#define LCD_PAL37_R14_0_Msk                                   (0x1fUL << LCD_PAL37_R14_0_Pos)
#define LCD_PAL37_G14_0_Pos                                   21
#define LCD_PAL37_G14_0_Msk                                   (0x1fUL << LCD_PAL37_G14_0_Pos)
#define LCD_PAL37_B14_0_Pos                                   26
#define LCD_PAL37_B14_0_Msk                                   (0x1fUL << LCD_PAL37_B14_0_Pos)
#define LCD_PAL37_I1_Pos                                      31
#define LCD_PAL37_I1_Msk                                      (0x01UL << LCD_PAL37_I1_Pos)

// ----------------------------------------  LCD_PAL38  -------------------------------------------
#define LCD_PAL38_R04_0_Pos                                   0
#define LCD_PAL38_R04_0_Msk                                   (0x1fUL << LCD_PAL38_R04_0_Pos)
#define LCD_PAL38_G04_0_Pos                                   5
#define LCD_PAL38_G04_0_Msk                                   (0x1fUL << LCD_PAL38_G04_0_Pos)
#define LCD_PAL38_B04_0_Pos                                   10
#define LCD_PAL38_B04_0_Msk                                   (0x1fUL << LCD_PAL38_B04_0_Pos)
#define LCD_PAL38_I0_Pos                                      15
#define LCD_PAL38_I0_Msk                                      (0x01UL << LCD_PAL38_I0_Pos)
#define LCD_PAL38_R14_0_Pos                                   16
#define LCD_PAL38_R14_0_Msk                                   (0x1fUL << LCD_PAL38_R14_0_Pos)
#define LCD_PAL38_G14_0_Pos                                   21
#define LCD_PAL38_G14_0_Msk                                   (0x1fUL << LCD_PAL38_G14_0_Pos)
#define LCD_PAL38_B14_0_Pos                                   26
#define LCD_PAL38_B14_0_Msk                                   (0x1fUL << LCD_PAL38_B14_0_Pos)
#define LCD_PAL38_I1_Pos                                      31
#define LCD_PAL38_I1_Msk                                      (0x01UL << LCD_PAL38_I1_Pos)

// ----------------------------------------  LCD_PAL39  -------------------------------------------
#define LCD_PAL39_R04_0_Pos                                   0
#define LCD_PAL39_R04_0_Msk                                   (0x1fUL << LCD_PAL39_R04_0_Pos)
#define LCD_PAL39_G04_0_Pos                                   5
#define LCD_PAL39_G04_0_Msk                                   (0x1fUL << LCD_PAL39_G04_0_Pos)
#define LCD_PAL39_B04_0_Pos                                   10
#define LCD_PAL39_B04_0_Msk                                   (0x1fUL << LCD_PAL39_B04_0_Pos)
#define LCD_PAL39_I0_Pos                                      15
#define LCD_PAL39_I0_Msk                                      (0x01UL << LCD_PAL39_I0_Pos)
#define LCD_PAL39_R14_0_Pos                                   16
#define LCD_PAL39_R14_0_Msk                                   (0x1fUL << LCD_PAL39_R14_0_Pos)
#define LCD_PAL39_G14_0_Pos                                   21
#define LCD_PAL39_G14_0_Msk                                   (0x1fUL << LCD_PAL39_G14_0_Pos)
#define LCD_PAL39_B14_0_Pos                                   26
#define LCD_PAL39_B14_0_Msk                                   (0x1fUL << LCD_PAL39_B14_0_Pos)
#define LCD_PAL39_I1_Pos                                      31
#define LCD_PAL39_I1_Msk                                      (0x01UL << LCD_PAL39_I1_Pos)

// ----------------------------------------  LCD_PAL40  -------------------------------------------
#define LCD_PAL40_R04_0_Pos                                   0
#define LCD_PAL40_R04_0_Msk                                   (0x1fUL << LCD_PAL40_R04_0_Pos)
#define LCD_PAL40_G04_0_Pos                                   5
#define LCD_PAL40_G04_0_Msk                                   (0x1fUL << LCD_PAL40_G04_0_Pos)
#define LCD_PAL40_B04_0_Pos                                   10
#define LCD_PAL40_B04_0_Msk                                   (0x1fUL << LCD_PAL40_B04_0_Pos)
#define LCD_PAL40_I0_Pos                                      15
#define LCD_PAL40_I0_Msk                                      (0x01UL << LCD_PAL40_I0_Pos)
#define LCD_PAL40_R14_0_Pos                                   16
#define LCD_PAL40_R14_0_Msk                                   (0x1fUL << LCD_PAL40_R14_0_Pos)
#define LCD_PAL40_G14_0_Pos                                   21
#define LCD_PAL40_G14_0_Msk                                   (0x1fUL << LCD_PAL40_G14_0_Pos)
#define LCD_PAL40_B14_0_Pos                                   26
#define LCD_PAL40_B14_0_Msk                                   (0x1fUL << LCD_PAL40_B14_0_Pos)
#define LCD_PAL40_I1_Pos                                      31
#define LCD_PAL40_I1_Msk                                      (0x01UL << LCD_PAL40_I1_Pos)

// ----------------------------------------  LCD_PAL41  -------------------------------------------
#define LCD_PAL41_R04_0_Pos                                   0
#define LCD_PAL41_R04_0_Msk                                   (0x1fUL << LCD_PAL41_R04_0_Pos)
#define LCD_PAL41_G04_0_Pos                                   5
#define LCD_PAL41_G04_0_Msk                                   (0x1fUL << LCD_PAL41_G04_0_Pos)
#define LCD_PAL41_B04_0_Pos                                   10
#define LCD_PAL41_B04_0_Msk                                   (0x1fUL << LCD_PAL41_B04_0_Pos)
#define LCD_PAL41_I0_Pos                                      15
#define LCD_PAL41_I0_Msk                                      (0x01UL << LCD_PAL41_I0_Pos)
#define LCD_PAL41_R14_0_Pos                                   16
#define LCD_PAL41_R14_0_Msk                                   (0x1fUL << LCD_PAL41_R14_0_Pos)
#define LCD_PAL41_G14_0_Pos                                   21
#define LCD_PAL41_G14_0_Msk                                   (0x1fUL << LCD_PAL41_G14_0_Pos)
#define LCD_PAL41_B14_0_Pos                                   26
#define LCD_PAL41_B14_0_Msk                                   (0x1fUL << LCD_PAL41_B14_0_Pos)
#define LCD_PAL41_I1_Pos                                      31
#define LCD_PAL41_I1_Msk                                      (0x01UL << LCD_PAL41_I1_Pos)

// ----------------------------------------  LCD_PAL42  -------------------------------------------
#define LCD_PAL42_R04_0_Pos                                   0
#define LCD_PAL42_R04_0_Msk                                   (0x1fUL << LCD_PAL42_R04_0_Pos)
#define LCD_PAL42_G04_0_Pos                                   5
#define LCD_PAL42_G04_0_Msk                                   (0x1fUL << LCD_PAL42_G04_0_Pos)
#define LCD_PAL42_B04_0_Pos                                   10
#define LCD_PAL42_B04_0_Msk                                   (0x1fUL << LCD_PAL42_B04_0_Pos)
#define LCD_PAL42_I0_Pos                                      15
#define LCD_PAL42_I0_Msk                                      (0x01UL << LCD_PAL42_I0_Pos)
#define LCD_PAL42_R14_0_Pos                                   16
#define LCD_PAL42_R14_0_Msk                                   (0x1fUL << LCD_PAL42_R14_0_Pos)
#define LCD_PAL42_G14_0_Pos                                   21
#define LCD_PAL42_G14_0_Msk                                   (0x1fUL << LCD_PAL42_G14_0_Pos)
#define LCD_PAL42_B14_0_Pos                                   26
#define LCD_PAL42_B14_0_Msk                                   (0x1fUL << LCD_PAL42_B14_0_Pos)
#define LCD_PAL42_I1_Pos                                      31
#define LCD_PAL42_I1_Msk                                      (0x01UL << LCD_PAL42_I1_Pos)

// ----------------------------------------  LCD_PAL43  -------------------------------------------
#define LCD_PAL43_R04_0_Pos                                   0
#define LCD_PAL43_R04_0_Msk                                   (0x1fUL << LCD_PAL43_R04_0_Pos)
#define LCD_PAL43_G04_0_Pos                                   5
#define LCD_PAL43_G04_0_Msk                                   (0x1fUL << LCD_PAL43_G04_0_Pos)
#define LCD_PAL43_B04_0_Pos                                   10
#define LCD_PAL43_B04_0_Msk                                   (0x1fUL << LCD_PAL43_B04_0_Pos)
#define LCD_PAL43_I0_Pos                                      15
#define LCD_PAL43_I0_Msk                                      (0x01UL << LCD_PAL43_I0_Pos)
#define LCD_PAL43_R14_0_Pos                                   16
#define LCD_PAL43_R14_0_Msk                                   (0x1fUL << LCD_PAL43_R14_0_Pos)
#define LCD_PAL43_G14_0_Pos                                   21
#define LCD_PAL43_G14_0_Msk                                   (0x1fUL << LCD_PAL43_G14_0_Pos)
#define LCD_PAL43_B14_0_Pos                                   26
#define LCD_PAL43_B14_0_Msk                                   (0x1fUL << LCD_PAL43_B14_0_Pos)
#define LCD_PAL43_I1_Pos                                      31
#define LCD_PAL43_I1_Msk                                      (0x01UL << LCD_PAL43_I1_Pos)

// ----------------------------------------  LCD_PAL44  -------------------------------------------
#define LCD_PAL44_R04_0_Pos                                   0
#define LCD_PAL44_R04_0_Msk                                   (0x1fUL << LCD_PAL44_R04_0_Pos)
#define LCD_PAL44_G04_0_Pos                                   5
#define LCD_PAL44_G04_0_Msk                                   (0x1fUL << LCD_PAL44_G04_0_Pos)
#define LCD_PAL44_B04_0_Pos                                   10
#define LCD_PAL44_B04_0_Msk                                   (0x1fUL << LCD_PAL44_B04_0_Pos)
#define LCD_PAL44_I0_Pos                                      15
#define LCD_PAL44_I0_Msk                                      (0x01UL << LCD_PAL44_I0_Pos)
#define LCD_PAL44_R14_0_Pos                                   16
#define LCD_PAL44_R14_0_Msk                                   (0x1fUL << LCD_PAL44_R14_0_Pos)
#define LCD_PAL44_G14_0_Pos                                   21
#define LCD_PAL44_G14_0_Msk                                   (0x1fUL << LCD_PAL44_G14_0_Pos)
#define LCD_PAL44_B14_0_Pos                                   26
#define LCD_PAL44_B14_0_Msk                                   (0x1fUL << LCD_PAL44_B14_0_Pos)
#define LCD_PAL44_I1_Pos                                      31
#define LCD_PAL44_I1_Msk                                      (0x01UL << LCD_PAL44_I1_Pos)

// ----------------------------------------  LCD_PAL45  -------------------------------------------
#define LCD_PAL45_R04_0_Pos                                   0
#define LCD_PAL45_R04_0_Msk                                   (0x1fUL << LCD_PAL45_R04_0_Pos)
#define LCD_PAL45_G04_0_Pos                                   5
#define LCD_PAL45_G04_0_Msk                                   (0x1fUL << LCD_PAL45_G04_0_Pos)
#define LCD_PAL45_B04_0_Pos                                   10
#define LCD_PAL45_B04_0_Msk                                   (0x1fUL << LCD_PAL45_B04_0_Pos)
#define LCD_PAL45_I0_Pos                                      15
#define LCD_PAL45_I0_Msk                                      (0x01UL << LCD_PAL45_I0_Pos)
#define LCD_PAL45_R14_0_Pos                                   16
#define LCD_PAL45_R14_0_Msk                                   (0x1fUL << LCD_PAL45_R14_0_Pos)
#define LCD_PAL45_G14_0_Pos                                   21
#define LCD_PAL45_G14_0_Msk                                   (0x1fUL << LCD_PAL45_G14_0_Pos)
#define LCD_PAL45_B14_0_Pos                                   26
#define LCD_PAL45_B14_0_Msk                                   (0x1fUL << LCD_PAL45_B14_0_Pos)
#define LCD_PAL45_I1_Pos                                      31
#define LCD_PAL45_I1_Msk                                      (0x01UL << LCD_PAL45_I1_Pos)

// ----------------------------------------  LCD_PAL46  -------------------------------------------
#define LCD_PAL46_R04_0_Pos                                   0
#define LCD_PAL46_R04_0_Msk                                   (0x1fUL << LCD_PAL46_R04_0_Pos)
#define LCD_PAL46_G04_0_Pos                                   5
#define LCD_PAL46_G04_0_Msk                                   (0x1fUL << LCD_PAL46_G04_0_Pos)
#define LCD_PAL46_B04_0_Pos                                   10
#define LCD_PAL46_B04_0_Msk                                   (0x1fUL << LCD_PAL46_B04_0_Pos)
#define LCD_PAL46_I0_Pos                                      15
#define LCD_PAL46_I0_Msk                                      (0x01UL << LCD_PAL46_I0_Pos)
#define LCD_PAL46_R14_0_Pos                                   16
#define LCD_PAL46_R14_0_Msk                                   (0x1fUL << LCD_PAL46_R14_0_Pos)
#define LCD_PAL46_G14_0_Pos                                   21
#define LCD_PAL46_G14_0_Msk                                   (0x1fUL << LCD_PAL46_G14_0_Pos)
#define LCD_PAL46_B14_0_Pos                                   26
#define LCD_PAL46_B14_0_Msk                                   (0x1fUL << LCD_PAL46_B14_0_Pos)
#define LCD_PAL46_I1_Pos                                      31
#define LCD_PAL46_I1_Msk                                      (0x01UL << LCD_PAL46_I1_Pos)

// ----------------------------------------  LCD_PAL47  -------------------------------------------
#define LCD_PAL47_R04_0_Pos                                   0
#define LCD_PAL47_R04_0_Msk                                   (0x1fUL << LCD_PAL47_R04_0_Pos)
#define LCD_PAL47_G04_0_Pos                                   5
#define LCD_PAL47_G04_0_Msk                                   (0x1fUL << LCD_PAL47_G04_0_Pos)
#define LCD_PAL47_B04_0_Pos                                   10
#define LCD_PAL47_B04_0_Msk                                   (0x1fUL << LCD_PAL47_B04_0_Pos)
#define LCD_PAL47_I0_Pos                                      15
#define LCD_PAL47_I0_Msk                                      (0x01UL << LCD_PAL47_I0_Pos)
#define LCD_PAL47_R14_0_Pos                                   16
#define LCD_PAL47_R14_0_Msk                                   (0x1fUL << LCD_PAL47_R14_0_Pos)
#define LCD_PAL47_G14_0_Pos                                   21
#define LCD_PAL47_G14_0_Msk                                   (0x1fUL << LCD_PAL47_G14_0_Pos)
#define LCD_PAL47_B14_0_Pos                                   26
#define LCD_PAL47_B14_0_Msk                                   (0x1fUL << LCD_PAL47_B14_0_Pos)
#define LCD_PAL47_I1_Pos                                      31
#define LCD_PAL47_I1_Msk                                      (0x01UL << LCD_PAL47_I1_Pos)

// ----------------------------------------  LCD_PAL48  -------------------------------------------
#define LCD_PAL48_R04_0_Pos                                   0
#define LCD_PAL48_R04_0_Msk                                   (0x1fUL << LCD_PAL48_R04_0_Pos)
#define LCD_PAL48_G04_0_Pos                                   5
#define LCD_PAL48_G04_0_Msk                                   (0x1fUL << LCD_PAL48_G04_0_Pos)
#define LCD_PAL48_B04_0_Pos                                   10
#define LCD_PAL48_B04_0_Msk                                   (0x1fUL << LCD_PAL48_B04_0_Pos)
#define LCD_PAL48_I0_Pos                                      15
#define LCD_PAL48_I0_Msk                                      (0x01UL << LCD_PAL48_I0_Pos)
#define LCD_PAL48_R14_0_Pos                                   16
#define LCD_PAL48_R14_0_Msk                                   (0x1fUL << LCD_PAL48_R14_0_Pos)
#define LCD_PAL48_G14_0_Pos                                   21
#define LCD_PAL48_G14_0_Msk                                   (0x1fUL << LCD_PAL48_G14_0_Pos)
#define LCD_PAL48_B14_0_Pos                                   26
#define LCD_PAL48_B14_0_Msk                                   (0x1fUL << LCD_PAL48_B14_0_Pos)
#define LCD_PAL48_I1_Pos                                      31
#define LCD_PAL48_I1_Msk                                      (0x01UL << LCD_PAL48_I1_Pos)

// ----------------------------------------  LCD_PAL49  -------------------------------------------
#define LCD_PAL49_R04_0_Pos                                   0
#define LCD_PAL49_R04_0_Msk                                   (0x1fUL << LCD_PAL49_R04_0_Pos)
#define LCD_PAL49_G04_0_Pos                                   5
#define LCD_PAL49_G04_0_Msk                                   (0x1fUL << LCD_PAL49_G04_0_Pos)
#define LCD_PAL49_B04_0_Pos                                   10
#define LCD_PAL49_B04_0_Msk                                   (0x1fUL << LCD_PAL49_B04_0_Pos)
#define LCD_PAL49_I0_Pos                                      15
#define LCD_PAL49_I0_Msk                                      (0x01UL << LCD_PAL49_I0_Pos)
#define LCD_PAL49_R14_0_Pos                                   16
#define LCD_PAL49_R14_0_Msk                                   (0x1fUL << LCD_PAL49_R14_0_Pos)
#define LCD_PAL49_G14_0_Pos                                   21
#define LCD_PAL49_G14_0_Msk                                   (0x1fUL << LCD_PAL49_G14_0_Pos)
#define LCD_PAL49_B14_0_Pos                                   26
#define LCD_PAL49_B14_0_Msk                                   (0x1fUL << LCD_PAL49_B14_0_Pos)
#define LCD_PAL49_I1_Pos                                      31
#define LCD_PAL49_I1_Msk                                      (0x01UL << LCD_PAL49_I1_Pos)

// ----------------------------------------  LCD_PAL50  -------------------------------------------
#define LCD_PAL50_R04_0_Pos                                   0
#define LCD_PAL50_R04_0_Msk                                   (0x1fUL << LCD_PAL50_R04_0_Pos)
#define LCD_PAL50_G04_0_Pos                                   5
#define LCD_PAL50_G04_0_Msk                                   (0x1fUL << LCD_PAL50_G04_0_Pos)
#define LCD_PAL50_B04_0_Pos                                   10
#define LCD_PAL50_B04_0_Msk                                   (0x1fUL << LCD_PAL50_B04_0_Pos)
#define LCD_PAL50_I0_Pos                                      15
#define LCD_PAL50_I0_Msk                                      (0x01UL << LCD_PAL50_I0_Pos)
#define LCD_PAL50_R14_0_Pos                                   16
#define LCD_PAL50_R14_0_Msk                                   (0x1fUL << LCD_PAL50_R14_0_Pos)
#define LCD_PAL50_G14_0_Pos                                   21
#define LCD_PAL50_G14_0_Msk                                   (0x1fUL << LCD_PAL50_G14_0_Pos)
#define LCD_PAL50_B14_0_Pos                                   26
#define LCD_PAL50_B14_0_Msk                                   (0x1fUL << LCD_PAL50_B14_0_Pos)
#define LCD_PAL50_I1_Pos                                      31
#define LCD_PAL50_I1_Msk                                      (0x01UL << LCD_PAL50_I1_Pos)

// ----------------------------------------  LCD_PAL51  -------------------------------------------
#define LCD_PAL51_R04_0_Pos                                   0
#define LCD_PAL51_R04_0_Msk                                   (0x1fUL << LCD_PAL51_R04_0_Pos)
#define LCD_PAL51_G04_0_Pos                                   5
#define LCD_PAL51_G04_0_Msk                                   (0x1fUL << LCD_PAL51_G04_0_Pos)
#define LCD_PAL51_B04_0_Pos                                   10
#define LCD_PAL51_B04_0_Msk                                   (0x1fUL << LCD_PAL51_B04_0_Pos)
#define LCD_PAL51_I0_Pos                                      15
#define LCD_PAL51_I0_Msk                                      (0x01UL << LCD_PAL51_I0_Pos)
#define LCD_PAL51_R14_0_Pos                                   16
#define LCD_PAL51_R14_0_Msk                                   (0x1fUL << LCD_PAL51_R14_0_Pos)
#define LCD_PAL51_G14_0_Pos                                   21
#define LCD_PAL51_G14_0_Msk                                   (0x1fUL << LCD_PAL51_G14_0_Pos)
#define LCD_PAL51_B14_0_Pos                                   26
#define LCD_PAL51_B14_0_Msk                                   (0x1fUL << LCD_PAL51_B14_0_Pos)
#define LCD_PAL51_I1_Pos                                      31
#define LCD_PAL51_I1_Msk                                      (0x01UL << LCD_PAL51_I1_Pos)

// ----------------------------------------  LCD_PAL52  -------------------------------------------
#define LCD_PAL52_R04_0_Pos                                   0
#define LCD_PAL52_R04_0_Msk                                   (0x1fUL << LCD_PAL52_R04_0_Pos)
#define LCD_PAL52_G04_0_Pos                                   5
#define LCD_PAL52_G04_0_Msk                                   (0x1fUL << LCD_PAL52_G04_0_Pos)
#define LCD_PAL52_B04_0_Pos                                   10
#define LCD_PAL52_B04_0_Msk                                   (0x1fUL << LCD_PAL52_B04_0_Pos)
#define LCD_PAL52_I0_Pos                                      15
#define LCD_PAL52_I0_Msk                                      (0x01UL << LCD_PAL52_I0_Pos)
#define LCD_PAL52_R14_0_Pos                                   16
#define LCD_PAL52_R14_0_Msk                                   (0x1fUL << LCD_PAL52_R14_0_Pos)
#define LCD_PAL52_G14_0_Pos                                   21
#define LCD_PAL52_G14_0_Msk                                   (0x1fUL << LCD_PAL52_G14_0_Pos)
#define LCD_PAL52_B14_0_Pos                                   26
#define LCD_PAL52_B14_0_Msk                                   (0x1fUL << LCD_PAL52_B14_0_Pos)
#define LCD_PAL52_I1_Pos                                      31
#define LCD_PAL52_I1_Msk                                      (0x01UL << LCD_PAL52_I1_Pos)

// ----------------------------------------  LCD_PAL53  -------------------------------------------
#define LCD_PAL53_R04_0_Pos                                   0
#define LCD_PAL53_R04_0_Msk                                   (0x1fUL << LCD_PAL53_R04_0_Pos)
#define LCD_PAL53_G04_0_Pos                                   5
#define LCD_PAL53_G04_0_Msk                                   (0x1fUL << LCD_PAL53_G04_0_Pos)
#define LCD_PAL53_B04_0_Pos                                   10
#define LCD_PAL53_B04_0_Msk                                   (0x1fUL << LCD_PAL53_B04_0_Pos)
#define LCD_PAL53_I0_Pos                                      15
#define LCD_PAL53_I0_Msk                                      (0x01UL << LCD_PAL53_I0_Pos)
#define LCD_PAL53_R14_0_Pos                                   16
#define LCD_PAL53_R14_0_Msk                                   (0x1fUL << LCD_PAL53_R14_0_Pos)
#define LCD_PAL53_G14_0_Pos                                   21
#define LCD_PAL53_G14_0_Msk                                   (0x1fUL << LCD_PAL53_G14_0_Pos)
#define LCD_PAL53_B14_0_Pos                                   26
#define LCD_PAL53_B14_0_Msk                                   (0x1fUL << LCD_PAL53_B14_0_Pos)
#define LCD_PAL53_I1_Pos                                      31
#define LCD_PAL53_I1_Msk                                      (0x01UL << LCD_PAL53_I1_Pos)

// ----------------------------------------  LCD_PAL54  -------------------------------------------
#define LCD_PAL54_R04_0_Pos                                   0
#define LCD_PAL54_R04_0_Msk                                   (0x1fUL << LCD_PAL54_R04_0_Pos)
#define LCD_PAL54_G04_0_Pos                                   5
#define LCD_PAL54_G04_0_Msk                                   (0x1fUL << LCD_PAL54_G04_0_Pos)
#define LCD_PAL54_B04_0_Pos                                   10
#define LCD_PAL54_B04_0_Msk                                   (0x1fUL << LCD_PAL54_B04_0_Pos)
#define LCD_PAL54_I0_Pos                                      15
#define LCD_PAL54_I0_Msk                                      (0x01UL << LCD_PAL54_I0_Pos)
#define LCD_PAL54_R14_0_Pos                                   16
#define LCD_PAL54_R14_0_Msk                                   (0x1fUL << LCD_PAL54_R14_0_Pos)
#define LCD_PAL54_G14_0_Pos                                   21
#define LCD_PAL54_G14_0_Msk                                   (0x1fUL << LCD_PAL54_G14_0_Pos)
#define LCD_PAL54_B14_0_Pos                                   26
#define LCD_PAL54_B14_0_Msk                                   (0x1fUL << LCD_PAL54_B14_0_Pos)
#define LCD_PAL54_I1_Pos                                      31
#define LCD_PAL54_I1_Msk                                      (0x01UL << LCD_PAL54_I1_Pos)

// ----------------------------------------  LCD_PAL55  -------------------------------------------
#define LCD_PAL55_R04_0_Pos                                   0
#define LCD_PAL55_R04_0_Msk                                   (0x1fUL << LCD_PAL55_R04_0_Pos)
#define LCD_PAL55_G04_0_Pos                                   5
#define LCD_PAL55_G04_0_Msk                                   (0x1fUL << LCD_PAL55_G04_0_Pos)
#define LCD_PAL55_B04_0_Pos                                   10
#define LCD_PAL55_B04_0_Msk                                   (0x1fUL << LCD_PAL55_B04_0_Pos)
#define LCD_PAL55_I0_Pos                                      15
#define LCD_PAL55_I0_Msk                                      (0x01UL << LCD_PAL55_I0_Pos)
#define LCD_PAL55_R14_0_Pos                                   16
#define LCD_PAL55_R14_0_Msk                                   (0x1fUL << LCD_PAL55_R14_0_Pos)
#define LCD_PAL55_G14_0_Pos                                   21
#define LCD_PAL55_G14_0_Msk                                   (0x1fUL << LCD_PAL55_G14_0_Pos)
#define LCD_PAL55_B14_0_Pos                                   26
#define LCD_PAL55_B14_0_Msk                                   (0x1fUL << LCD_PAL55_B14_0_Pos)
#define LCD_PAL55_I1_Pos                                      31
#define LCD_PAL55_I1_Msk                                      (0x01UL << LCD_PAL55_I1_Pos)

// ----------------------------------------  LCD_PAL56  -------------------------------------------
#define LCD_PAL56_R04_0_Pos                                   0
#define LCD_PAL56_R04_0_Msk                                   (0x1fUL << LCD_PAL56_R04_0_Pos)
#define LCD_PAL56_G04_0_Pos                                   5
#define LCD_PAL56_G04_0_Msk                                   (0x1fUL << LCD_PAL56_G04_0_Pos)
#define LCD_PAL56_B04_0_Pos                                   10
#define LCD_PAL56_B04_0_Msk                                   (0x1fUL << LCD_PAL56_B04_0_Pos)
#define LCD_PAL56_I0_Pos                                      15
#define LCD_PAL56_I0_Msk                                      (0x01UL << LCD_PAL56_I0_Pos)
#define LCD_PAL56_R14_0_Pos                                   16
#define LCD_PAL56_R14_0_Msk                                   (0x1fUL << LCD_PAL56_R14_0_Pos)
#define LCD_PAL56_G14_0_Pos                                   21
#define LCD_PAL56_G14_0_Msk                                   (0x1fUL << LCD_PAL56_G14_0_Pos)
#define LCD_PAL56_B14_0_Pos                                   26
#define LCD_PAL56_B14_0_Msk                                   (0x1fUL << LCD_PAL56_B14_0_Pos)
#define LCD_PAL56_I1_Pos                                      31
#define LCD_PAL56_I1_Msk                                      (0x01UL << LCD_PAL56_I1_Pos)

// ----------------------------------------  LCD_PAL57  -------------------------------------------
#define LCD_PAL57_R04_0_Pos                                   0
#define LCD_PAL57_R04_0_Msk                                   (0x1fUL << LCD_PAL57_R04_0_Pos)
#define LCD_PAL57_G04_0_Pos                                   5
#define LCD_PAL57_G04_0_Msk                                   (0x1fUL << LCD_PAL57_G04_0_Pos)
#define LCD_PAL57_B04_0_Pos                                   10
#define LCD_PAL57_B04_0_Msk                                   (0x1fUL << LCD_PAL57_B04_0_Pos)
#define LCD_PAL57_I0_Pos                                      15
#define LCD_PAL57_I0_Msk                                      (0x01UL << LCD_PAL57_I0_Pos)
#define LCD_PAL57_R14_0_Pos                                   16
#define LCD_PAL57_R14_0_Msk                                   (0x1fUL << LCD_PAL57_R14_0_Pos)
#define LCD_PAL57_G14_0_Pos                                   21
#define LCD_PAL57_G14_0_Msk                                   (0x1fUL << LCD_PAL57_G14_0_Pos)
#define LCD_PAL57_B14_0_Pos                                   26
#define LCD_PAL57_B14_0_Msk                                   (0x1fUL << LCD_PAL57_B14_0_Pos)
#define LCD_PAL57_I1_Pos                                      31
#define LCD_PAL57_I1_Msk                                      (0x01UL << LCD_PAL57_I1_Pos)

// ----------------------------------------  LCD_PAL58  -------------------------------------------
#define LCD_PAL58_R04_0_Pos                                   0
#define LCD_PAL58_R04_0_Msk                                   (0x1fUL << LCD_PAL58_R04_0_Pos)
#define LCD_PAL58_G04_0_Pos                                   5
#define LCD_PAL58_G04_0_Msk                                   (0x1fUL << LCD_PAL58_G04_0_Pos)
#define LCD_PAL58_B04_0_Pos                                   10
#define LCD_PAL58_B04_0_Msk                                   (0x1fUL << LCD_PAL58_B04_0_Pos)
#define LCD_PAL58_I0_Pos                                      15
#define LCD_PAL58_I0_Msk                                      (0x01UL << LCD_PAL58_I0_Pos)
#define LCD_PAL58_R14_0_Pos                                   16
#define LCD_PAL58_R14_0_Msk                                   (0x1fUL << LCD_PAL58_R14_0_Pos)
#define LCD_PAL58_G14_0_Pos                                   21
#define LCD_PAL58_G14_0_Msk                                   (0x1fUL << LCD_PAL58_G14_0_Pos)
#define LCD_PAL58_B14_0_Pos                                   26
#define LCD_PAL58_B14_0_Msk                                   (0x1fUL << LCD_PAL58_B14_0_Pos)
#define LCD_PAL58_I1_Pos                                      31
#define LCD_PAL58_I1_Msk                                      (0x01UL << LCD_PAL58_I1_Pos)

// ----------------------------------------  LCD_PAL59  -------------------------------------------
#define LCD_PAL59_R04_0_Pos                                   0
#define LCD_PAL59_R04_0_Msk                                   (0x1fUL << LCD_PAL59_R04_0_Pos)
#define LCD_PAL59_G04_0_Pos                                   5
#define LCD_PAL59_G04_0_Msk                                   (0x1fUL << LCD_PAL59_G04_0_Pos)
#define LCD_PAL59_B04_0_Pos                                   10
#define LCD_PAL59_B04_0_Msk                                   (0x1fUL << LCD_PAL59_B04_0_Pos)
#define LCD_PAL59_I0_Pos                                      15
#define LCD_PAL59_I0_Msk                                      (0x01UL << LCD_PAL59_I0_Pos)
#define LCD_PAL59_R14_0_Pos                                   16
#define LCD_PAL59_R14_0_Msk                                   (0x1fUL << LCD_PAL59_R14_0_Pos)
#define LCD_PAL59_G14_0_Pos                                   21
#define LCD_PAL59_G14_0_Msk                                   (0x1fUL << LCD_PAL59_G14_0_Pos)
#define LCD_PAL59_B14_0_Pos                                   26
#define LCD_PAL59_B14_0_Msk                                   (0x1fUL << LCD_PAL59_B14_0_Pos)
#define LCD_PAL59_I1_Pos                                      31
#define LCD_PAL59_I1_Msk                                      (0x01UL << LCD_PAL59_I1_Pos)

// ----------------------------------------  LCD_PAL60  -------------------------------------------
#define LCD_PAL60_R04_0_Pos                                   0
#define LCD_PAL60_R04_0_Msk                                   (0x1fUL << LCD_PAL60_R04_0_Pos)
#define LCD_PAL60_G04_0_Pos                                   5
#define LCD_PAL60_G04_0_Msk                                   (0x1fUL << LCD_PAL60_G04_0_Pos)
#define LCD_PAL60_B04_0_Pos                                   10
#define LCD_PAL60_B04_0_Msk                                   (0x1fUL << LCD_PAL60_B04_0_Pos)
#define LCD_PAL60_I0_Pos                                      15
#define LCD_PAL60_I0_Msk                                      (0x01UL << LCD_PAL60_I0_Pos)
#define LCD_PAL60_R14_0_Pos                                   16
#define LCD_PAL60_R14_0_Msk                                   (0x1fUL << LCD_PAL60_R14_0_Pos)
#define LCD_PAL60_G14_0_Pos                                   21
#define LCD_PAL60_G14_0_Msk                                   (0x1fUL << LCD_PAL60_G14_0_Pos)
#define LCD_PAL60_B14_0_Pos                                   26
#define LCD_PAL60_B14_0_Msk                                   (0x1fUL << LCD_PAL60_B14_0_Pos)
#define LCD_PAL60_I1_Pos                                      31
#define LCD_PAL60_I1_Msk                                      (0x01UL << LCD_PAL60_I1_Pos)

// ----------------------------------------  LCD_PAL61  -------------------------------------------
#define LCD_PAL61_R04_0_Pos                                   0
#define LCD_PAL61_R04_0_Msk                                   (0x1fUL << LCD_PAL61_R04_0_Pos)
#define LCD_PAL61_G04_0_Pos                                   5
#define LCD_PAL61_G04_0_Msk                                   (0x1fUL << LCD_PAL61_G04_0_Pos)
#define LCD_PAL61_B04_0_Pos                                   10
#define LCD_PAL61_B04_0_Msk                                   (0x1fUL << LCD_PAL61_B04_0_Pos)
#define LCD_PAL61_I0_Pos                                      15
#define LCD_PAL61_I0_Msk                                      (0x01UL << LCD_PAL61_I0_Pos)
#define LCD_PAL61_R14_0_Pos                                   16
#define LCD_PAL61_R14_0_Msk                                   (0x1fUL << LCD_PAL61_R14_0_Pos)
#define LCD_PAL61_G14_0_Pos                                   21
#define LCD_PAL61_G14_0_Msk                                   (0x1fUL << LCD_PAL61_G14_0_Pos)
#define LCD_PAL61_B14_0_Pos                                   26
#define LCD_PAL61_B14_0_Msk                                   (0x1fUL << LCD_PAL61_B14_0_Pos)
#define LCD_PAL61_I1_Pos                                      31
#define LCD_PAL61_I1_Msk                                      (0x01UL << LCD_PAL61_I1_Pos)

// ----------------------------------------  LCD_PAL62  -------------------------------------------
#define LCD_PAL62_R04_0_Pos                                   0
#define LCD_PAL62_R04_0_Msk                                   (0x1fUL << LCD_PAL62_R04_0_Pos)
#define LCD_PAL62_G04_0_Pos                                   5
#define LCD_PAL62_G04_0_Msk                                   (0x1fUL << LCD_PAL62_G04_0_Pos)
#define LCD_PAL62_B04_0_Pos                                   10
#define LCD_PAL62_B04_0_Msk                                   (0x1fUL << LCD_PAL62_B04_0_Pos)
#define LCD_PAL62_I0_Pos                                      15
#define LCD_PAL62_I0_Msk                                      (0x01UL << LCD_PAL62_I0_Pos)
#define LCD_PAL62_R14_0_Pos                                   16
#define LCD_PAL62_R14_0_Msk                                   (0x1fUL << LCD_PAL62_R14_0_Pos)
#define LCD_PAL62_G14_0_Pos                                   21
#define LCD_PAL62_G14_0_Msk                                   (0x1fUL << LCD_PAL62_G14_0_Pos)
#define LCD_PAL62_B14_0_Pos                                   26
#define LCD_PAL62_B14_0_Msk                                   (0x1fUL << LCD_PAL62_B14_0_Pos)
#define LCD_PAL62_I1_Pos                                      31
#define LCD_PAL62_I1_Msk                                      (0x01UL << LCD_PAL62_I1_Pos)

// ----------------------------------------  LCD_PAL63  -------------------------------------------
#define LCD_PAL63_R04_0_Pos                                   0
#define LCD_PAL63_R04_0_Msk                                   (0x1fUL << LCD_PAL63_R04_0_Pos)
#define LCD_PAL63_G04_0_Pos                                   5
#define LCD_PAL63_G04_0_Msk                                   (0x1fUL << LCD_PAL63_G04_0_Pos)
#define LCD_PAL63_B04_0_Pos                                   10
#define LCD_PAL63_B04_0_Msk                                   (0x1fUL << LCD_PAL63_B04_0_Pos)
#define LCD_PAL63_I0_Pos                                      15
#define LCD_PAL63_I0_Msk                                      (0x01UL << LCD_PAL63_I0_Pos)
#define LCD_PAL63_R14_0_Pos                                   16
#define LCD_PAL63_R14_0_Msk                                   (0x1fUL << LCD_PAL63_R14_0_Pos)
#define LCD_PAL63_G14_0_Pos                                   21
#define LCD_PAL63_G14_0_Msk                                   (0x1fUL << LCD_PAL63_G14_0_Pos)
#define LCD_PAL63_B14_0_Pos                                   26
#define LCD_PAL63_B14_0_Msk                                   (0x1fUL << LCD_PAL63_B14_0_Pos)
#define LCD_PAL63_I1_Pos                                      31
#define LCD_PAL63_I1_Msk                                      (0x01UL << LCD_PAL63_I1_Pos)

// ----------------------------------------  LCD_PAL64  -------------------------------------------
#define LCD_PAL64_R04_0_Pos                                   0
#define LCD_PAL64_R04_0_Msk                                   (0x1fUL << LCD_PAL64_R04_0_Pos)
#define LCD_PAL64_G04_0_Pos                                   5
#define LCD_PAL64_G04_0_Msk                                   (0x1fUL << LCD_PAL64_G04_0_Pos)
#define LCD_PAL64_B04_0_Pos                                   10
#define LCD_PAL64_B04_0_Msk                                   (0x1fUL << LCD_PAL64_B04_0_Pos)
#define LCD_PAL64_I0_Pos                                      15
#define LCD_PAL64_I0_Msk                                      (0x01UL << LCD_PAL64_I0_Pos)
#define LCD_PAL64_R14_0_Pos                                   16
#define LCD_PAL64_R14_0_Msk                                   (0x1fUL << LCD_PAL64_R14_0_Pos)
#define LCD_PAL64_G14_0_Pos                                   21
#define LCD_PAL64_G14_0_Msk                                   (0x1fUL << LCD_PAL64_G14_0_Pos)
#define LCD_PAL64_B14_0_Pos                                   26
#define LCD_PAL64_B14_0_Msk                                   (0x1fUL << LCD_PAL64_B14_0_Pos)
#define LCD_PAL64_I1_Pos                                      31
#define LCD_PAL64_I1_Msk                                      (0x01UL << LCD_PAL64_I1_Pos)

// ----------------------------------------  LCD_PAL65  -------------------------------------------
#define LCD_PAL65_R04_0_Pos                                   0
#define LCD_PAL65_R04_0_Msk                                   (0x1fUL << LCD_PAL65_R04_0_Pos)
#define LCD_PAL65_G04_0_Pos                                   5
#define LCD_PAL65_G04_0_Msk                                   (0x1fUL << LCD_PAL65_G04_0_Pos)
#define LCD_PAL65_B04_0_Pos                                   10
#define LCD_PAL65_B04_0_Msk                                   (0x1fUL << LCD_PAL65_B04_0_Pos)
#define LCD_PAL65_I0_Pos                                      15
#define LCD_PAL65_I0_Msk                                      (0x01UL << LCD_PAL65_I0_Pos)
#define LCD_PAL65_R14_0_Pos                                   16
#define LCD_PAL65_R14_0_Msk                                   (0x1fUL << LCD_PAL65_R14_0_Pos)
#define LCD_PAL65_G14_0_Pos                                   21
#define LCD_PAL65_G14_0_Msk                                   (0x1fUL << LCD_PAL65_G14_0_Pos)
#define LCD_PAL65_B14_0_Pos                                   26
#define LCD_PAL65_B14_0_Msk                                   (0x1fUL << LCD_PAL65_B14_0_Pos)
#define LCD_PAL65_I1_Pos                                      31
#define LCD_PAL65_I1_Msk                                      (0x01UL << LCD_PAL65_I1_Pos)

// ----------------------------------------  LCD_PAL66  -------------------------------------------
#define LCD_PAL66_R04_0_Pos                                   0
#define LCD_PAL66_R04_0_Msk                                   (0x1fUL << LCD_PAL66_R04_0_Pos)
#define LCD_PAL66_G04_0_Pos                                   5
#define LCD_PAL66_G04_0_Msk                                   (0x1fUL << LCD_PAL66_G04_0_Pos)
#define LCD_PAL66_B04_0_Pos                                   10
#define LCD_PAL66_B04_0_Msk                                   (0x1fUL << LCD_PAL66_B04_0_Pos)
#define LCD_PAL66_I0_Pos                                      15
#define LCD_PAL66_I0_Msk                                      (0x01UL << LCD_PAL66_I0_Pos)
#define LCD_PAL66_R14_0_Pos                                   16
#define LCD_PAL66_R14_0_Msk                                   (0x1fUL << LCD_PAL66_R14_0_Pos)
#define LCD_PAL66_G14_0_Pos                                   21
#define LCD_PAL66_G14_0_Msk                                   (0x1fUL << LCD_PAL66_G14_0_Pos)
#define LCD_PAL66_B14_0_Pos                                   26
#define LCD_PAL66_B14_0_Msk                                   (0x1fUL << LCD_PAL66_B14_0_Pos)
#define LCD_PAL66_I1_Pos                                      31
#define LCD_PAL66_I1_Msk                                      (0x01UL << LCD_PAL66_I1_Pos)

// ----------------------------------------  LCD_PAL67  -------------------------------------------
#define LCD_PAL67_R04_0_Pos                                   0
#define LCD_PAL67_R04_0_Msk                                   (0x1fUL << LCD_PAL67_R04_0_Pos)
#define LCD_PAL67_G04_0_Pos                                   5
#define LCD_PAL67_G04_0_Msk                                   (0x1fUL << LCD_PAL67_G04_0_Pos)
#define LCD_PAL67_B04_0_Pos                                   10
#define LCD_PAL67_B04_0_Msk                                   (0x1fUL << LCD_PAL67_B04_0_Pos)
#define LCD_PAL67_I0_Pos                                      15
#define LCD_PAL67_I0_Msk                                      (0x01UL << LCD_PAL67_I0_Pos)
#define LCD_PAL67_R14_0_Pos                                   16
#define LCD_PAL67_R14_0_Msk                                   (0x1fUL << LCD_PAL67_R14_0_Pos)
#define LCD_PAL67_G14_0_Pos                                   21
#define LCD_PAL67_G14_0_Msk                                   (0x1fUL << LCD_PAL67_G14_0_Pos)
#define LCD_PAL67_B14_0_Pos                                   26
#define LCD_PAL67_B14_0_Msk                                   (0x1fUL << LCD_PAL67_B14_0_Pos)
#define LCD_PAL67_I1_Pos                                      31
#define LCD_PAL67_I1_Msk                                      (0x01UL << LCD_PAL67_I1_Pos)

// ----------------------------------------  LCD_PAL68  -------------------------------------------
#define LCD_PAL68_R04_0_Pos                                   0
#define LCD_PAL68_R04_0_Msk                                   (0x1fUL << LCD_PAL68_R04_0_Pos)
#define LCD_PAL68_G04_0_Pos                                   5
#define LCD_PAL68_G04_0_Msk                                   (0x1fUL << LCD_PAL68_G04_0_Pos)
#define LCD_PAL68_B04_0_Pos                                   10
#define LCD_PAL68_B04_0_Msk                                   (0x1fUL << LCD_PAL68_B04_0_Pos)
#define LCD_PAL68_I0_Pos                                      15
#define LCD_PAL68_I0_Msk                                      (0x01UL << LCD_PAL68_I0_Pos)
#define LCD_PAL68_R14_0_Pos                                   16
#define LCD_PAL68_R14_0_Msk                                   (0x1fUL << LCD_PAL68_R14_0_Pos)
#define LCD_PAL68_G14_0_Pos                                   21
#define LCD_PAL68_G14_0_Msk                                   (0x1fUL << LCD_PAL68_G14_0_Pos)
#define LCD_PAL68_B14_0_Pos                                   26
#define LCD_PAL68_B14_0_Msk                                   (0x1fUL << LCD_PAL68_B14_0_Pos)
#define LCD_PAL68_I1_Pos                                      31
#define LCD_PAL68_I1_Msk                                      (0x01UL << LCD_PAL68_I1_Pos)

// ----------------------------------------  LCD_PAL69  -------------------------------------------
#define LCD_PAL69_R04_0_Pos                                   0
#define LCD_PAL69_R04_0_Msk                                   (0x1fUL << LCD_PAL69_R04_0_Pos)
#define LCD_PAL69_G04_0_Pos                                   5
#define LCD_PAL69_G04_0_Msk                                   (0x1fUL << LCD_PAL69_G04_0_Pos)
#define LCD_PAL69_B04_0_Pos                                   10
#define LCD_PAL69_B04_0_Msk                                   (0x1fUL << LCD_PAL69_B04_0_Pos)
#define LCD_PAL69_I0_Pos                                      15
#define LCD_PAL69_I0_Msk                                      (0x01UL << LCD_PAL69_I0_Pos)
#define LCD_PAL69_R14_0_Pos                                   16
#define LCD_PAL69_R14_0_Msk                                   (0x1fUL << LCD_PAL69_R14_0_Pos)
#define LCD_PAL69_G14_0_Pos                                   21
#define LCD_PAL69_G14_0_Msk                                   (0x1fUL << LCD_PAL69_G14_0_Pos)
#define LCD_PAL69_B14_0_Pos                                   26
#define LCD_PAL69_B14_0_Msk                                   (0x1fUL << LCD_PAL69_B14_0_Pos)
#define LCD_PAL69_I1_Pos                                      31
#define LCD_PAL69_I1_Msk                                      (0x01UL << LCD_PAL69_I1_Pos)

// ----------------------------------------  LCD_PAL70  -------------------------------------------
#define LCD_PAL70_R04_0_Pos                                   0
#define LCD_PAL70_R04_0_Msk                                   (0x1fUL << LCD_PAL70_R04_0_Pos)
#define LCD_PAL70_G04_0_Pos                                   5
#define LCD_PAL70_G04_0_Msk                                   (0x1fUL << LCD_PAL70_G04_0_Pos)
#define LCD_PAL70_B04_0_Pos                                   10
#define LCD_PAL70_B04_0_Msk                                   (0x1fUL << LCD_PAL70_B04_0_Pos)
#define LCD_PAL70_I0_Pos                                      15
#define LCD_PAL70_I0_Msk                                      (0x01UL << LCD_PAL70_I0_Pos)
#define LCD_PAL70_R14_0_Pos                                   16
#define LCD_PAL70_R14_0_Msk                                   (0x1fUL << LCD_PAL70_R14_0_Pos)
#define LCD_PAL70_G14_0_Pos                                   21
#define LCD_PAL70_G14_0_Msk                                   (0x1fUL << LCD_PAL70_G14_0_Pos)
#define LCD_PAL70_B14_0_Pos                                   26
#define LCD_PAL70_B14_0_Msk                                   (0x1fUL << LCD_PAL70_B14_0_Pos)
#define LCD_PAL70_I1_Pos                                      31
#define LCD_PAL70_I1_Msk                                      (0x01UL << LCD_PAL70_I1_Pos)

// ----------------------------------------  LCD_PAL71  -------------------------------------------
#define LCD_PAL71_R04_0_Pos                                   0
#define LCD_PAL71_R04_0_Msk                                   (0x1fUL << LCD_PAL71_R04_0_Pos)
#define LCD_PAL71_G04_0_Pos                                   5
#define LCD_PAL71_G04_0_Msk                                   (0x1fUL << LCD_PAL71_G04_0_Pos)
#define LCD_PAL71_B04_0_Pos                                   10
#define LCD_PAL71_B04_0_Msk                                   (0x1fUL << LCD_PAL71_B04_0_Pos)
#define LCD_PAL71_I0_Pos                                      15
#define LCD_PAL71_I0_Msk                                      (0x01UL << LCD_PAL71_I0_Pos)
#define LCD_PAL71_R14_0_Pos                                   16
#define LCD_PAL71_R14_0_Msk                                   (0x1fUL << LCD_PAL71_R14_0_Pos)
#define LCD_PAL71_G14_0_Pos                                   21
#define LCD_PAL71_G14_0_Msk                                   (0x1fUL << LCD_PAL71_G14_0_Pos)
#define LCD_PAL71_B14_0_Pos                                   26
#define LCD_PAL71_B14_0_Msk                                   (0x1fUL << LCD_PAL71_B14_0_Pos)
#define LCD_PAL71_I1_Pos                                      31
#define LCD_PAL71_I1_Msk                                      (0x01UL << LCD_PAL71_I1_Pos)

// ----------------------------------------  LCD_PAL72  -------------------------------------------
#define LCD_PAL72_R04_0_Pos                                   0
#define LCD_PAL72_R04_0_Msk                                   (0x1fUL << LCD_PAL72_R04_0_Pos)
#define LCD_PAL72_G04_0_Pos                                   5
#define LCD_PAL72_G04_0_Msk                                   (0x1fUL << LCD_PAL72_G04_0_Pos)
#define LCD_PAL72_B04_0_Pos                                   10
#define LCD_PAL72_B04_0_Msk                                   (0x1fUL << LCD_PAL72_B04_0_Pos)
#define LCD_PAL72_I0_Pos                                      15
#define LCD_PAL72_I0_Msk                                      (0x01UL << LCD_PAL72_I0_Pos)
#define LCD_PAL72_R14_0_Pos                                   16
#define LCD_PAL72_R14_0_Msk                                   (0x1fUL << LCD_PAL72_R14_0_Pos)
#define LCD_PAL72_G14_0_Pos                                   21
#define LCD_PAL72_G14_0_Msk                                   (0x1fUL << LCD_PAL72_G14_0_Pos)
#define LCD_PAL72_B14_0_Pos                                   26
#define LCD_PAL72_B14_0_Msk                                   (0x1fUL << LCD_PAL72_B14_0_Pos)
#define LCD_PAL72_I1_Pos                                      31
#define LCD_PAL72_I1_Msk                                      (0x01UL << LCD_PAL72_I1_Pos)

// ----------------------------------------  LCD_PAL73  -------------------------------------------
#define LCD_PAL73_R04_0_Pos                                   0
#define LCD_PAL73_R04_0_Msk                                   (0x1fUL << LCD_PAL73_R04_0_Pos)
#define LCD_PAL73_G04_0_Pos                                   5
#define LCD_PAL73_G04_0_Msk                                   (0x1fUL << LCD_PAL73_G04_0_Pos)
#define LCD_PAL73_B04_0_Pos                                   10
#define LCD_PAL73_B04_0_Msk                                   (0x1fUL << LCD_PAL73_B04_0_Pos)
#define LCD_PAL73_I0_Pos                                      15
#define LCD_PAL73_I0_Msk                                      (0x01UL << LCD_PAL73_I0_Pos)
#define LCD_PAL73_R14_0_Pos                                   16
#define LCD_PAL73_R14_0_Msk                                   (0x1fUL << LCD_PAL73_R14_0_Pos)
#define LCD_PAL73_G14_0_Pos                                   21
#define LCD_PAL73_G14_0_Msk                                   (0x1fUL << LCD_PAL73_G14_0_Pos)
#define LCD_PAL73_B14_0_Pos                                   26
#define LCD_PAL73_B14_0_Msk                                   (0x1fUL << LCD_PAL73_B14_0_Pos)
#define LCD_PAL73_I1_Pos                                      31
#define LCD_PAL73_I1_Msk                                      (0x01UL << LCD_PAL73_I1_Pos)

// ----------------------------------------  LCD_PAL74  -------------------------------------------
#define LCD_PAL74_R04_0_Pos                                   0
#define LCD_PAL74_R04_0_Msk                                   (0x1fUL << LCD_PAL74_R04_0_Pos)
#define LCD_PAL74_G04_0_Pos                                   5
#define LCD_PAL74_G04_0_Msk                                   (0x1fUL << LCD_PAL74_G04_0_Pos)
#define LCD_PAL74_B04_0_Pos                                   10
#define LCD_PAL74_B04_0_Msk                                   (0x1fUL << LCD_PAL74_B04_0_Pos)
#define LCD_PAL74_I0_Pos                                      15
#define LCD_PAL74_I0_Msk                                      (0x01UL << LCD_PAL74_I0_Pos)
#define LCD_PAL74_R14_0_Pos                                   16
#define LCD_PAL74_R14_0_Msk                                   (0x1fUL << LCD_PAL74_R14_0_Pos)
#define LCD_PAL74_G14_0_Pos                                   21
#define LCD_PAL74_G14_0_Msk                                   (0x1fUL << LCD_PAL74_G14_0_Pos)
#define LCD_PAL74_B14_0_Pos                                   26
#define LCD_PAL74_B14_0_Msk                                   (0x1fUL << LCD_PAL74_B14_0_Pos)
#define LCD_PAL74_I1_Pos                                      31
#define LCD_PAL74_I1_Msk                                      (0x01UL << LCD_PAL74_I1_Pos)

// ----------------------------------------  LCD_PAL75  -------------------------------------------
#define LCD_PAL75_R04_0_Pos                                   0
#define LCD_PAL75_R04_0_Msk                                   (0x1fUL << LCD_PAL75_R04_0_Pos)
#define LCD_PAL75_G04_0_Pos                                   5
#define LCD_PAL75_G04_0_Msk                                   (0x1fUL << LCD_PAL75_G04_0_Pos)
#define LCD_PAL75_B04_0_Pos                                   10
#define LCD_PAL75_B04_0_Msk                                   (0x1fUL << LCD_PAL75_B04_0_Pos)
#define LCD_PAL75_I0_Pos                                      15
#define LCD_PAL75_I0_Msk                                      (0x01UL << LCD_PAL75_I0_Pos)
#define LCD_PAL75_R14_0_Pos                                   16
#define LCD_PAL75_R14_0_Msk                                   (0x1fUL << LCD_PAL75_R14_0_Pos)
#define LCD_PAL75_G14_0_Pos                                   21
#define LCD_PAL75_G14_0_Msk                                   (0x1fUL << LCD_PAL75_G14_0_Pos)
#define LCD_PAL75_B14_0_Pos                                   26
#define LCD_PAL75_B14_0_Msk                                   (0x1fUL << LCD_PAL75_B14_0_Pos)
#define LCD_PAL75_I1_Pos                                      31
#define LCD_PAL75_I1_Msk                                      (0x01UL << LCD_PAL75_I1_Pos)

// ----------------------------------------  LCD_PAL76  -------------------------------------------
#define LCD_PAL76_R04_0_Pos                                   0
#define LCD_PAL76_R04_0_Msk                                   (0x1fUL << LCD_PAL76_R04_0_Pos)
#define LCD_PAL76_G04_0_Pos                                   5
#define LCD_PAL76_G04_0_Msk                                   (0x1fUL << LCD_PAL76_G04_0_Pos)
#define LCD_PAL76_B04_0_Pos                                   10
#define LCD_PAL76_B04_0_Msk                                   (0x1fUL << LCD_PAL76_B04_0_Pos)
#define LCD_PAL76_I0_Pos                                      15
#define LCD_PAL76_I0_Msk                                      (0x01UL << LCD_PAL76_I0_Pos)
#define LCD_PAL76_R14_0_Pos                                   16
#define LCD_PAL76_R14_0_Msk                                   (0x1fUL << LCD_PAL76_R14_0_Pos)
#define LCD_PAL76_G14_0_Pos                                   21
#define LCD_PAL76_G14_0_Msk                                   (0x1fUL << LCD_PAL76_G14_0_Pos)
#define LCD_PAL76_B14_0_Pos                                   26
#define LCD_PAL76_B14_0_Msk                                   (0x1fUL << LCD_PAL76_B14_0_Pos)
#define LCD_PAL76_I1_Pos                                      31
#define LCD_PAL76_I1_Msk                                      (0x01UL << LCD_PAL76_I1_Pos)

// ----------------------------------------  LCD_PAL77  -------------------------------------------
#define LCD_PAL77_R04_0_Pos                                   0
#define LCD_PAL77_R04_0_Msk                                   (0x1fUL << LCD_PAL77_R04_0_Pos)
#define LCD_PAL77_G04_0_Pos                                   5
#define LCD_PAL77_G04_0_Msk                                   (0x1fUL << LCD_PAL77_G04_0_Pos)
#define LCD_PAL77_B04_0_Pos                                   10
#define LCD_PAL77_B04_0_Msk                                   (0x1fUL << LCD_PAL77_B04_0_Pos)
#define LCD_PAL77_I0_Pos                                      15
#define LCD_PAL77_I0_Msk                                      (0x01UL << LCD_PAL77_I0_Pos)
#define LCD_PAL77_R14_0_Pos                                   16
#define LCD_PAL77_R14_0_Msk                                   (0x1fUL << LCD_PAL77_R14_0_Pos)
#define LCD_PAL77_G14_0_Pos                                   21
#define LCD_PAL77_G14_0_Msk                                   (0x1fUL << LCD_PAL77_G14_0_Pos)
#define LCD_PAL77_B14_0_Pos                                   26
#define LCD_PAL77_B14_0_Msk                                   (0x1fUL << LCD_PAL77_B14_0_Pos)
#define LCD_PAL77_I1_Pos                                      31
#define LCD_PAL77_I1_Msk                                      (0x01UL << LCD_PAL77_I1_Pos)

// ----------------------------------------  LCD_PAL78  -------------------------------------------
#define LCD_PAL78_R04_0_Pos                                   0
#define LCD_PAL78_R04_0_Msk                                   (0x1fUL << LCD_PAL78_R04_0_Pos)
#define LCD_PAL78_G04_0_Pos                                   5
#define LCD_PAL78_G04_0_Msk                                   (0x1fUL << LCD_PAL78_G04_0_Pos)
#define LCD_PAL78_B04_0_Pos                                   10
#define LCD_PAL78_B04_0_Msk                                   (0x1fUL << LCD_PAL78_B04_0_Pos)
#define LCD_PAL78_I0_Pos                                      15
#define LCD_PAL78_I0_Msk                                      (0x01UL << LCD_PAL78_I0_Pos)
#define LCD_PAL78_R14_0_Pos                                   16
#define LCD_PAL78_R14_0_Msk                                   (0x1fUL << LCD_PAL78_R14_0_Pos)
#define LCD_PAL78_G14_0_Pos                                   21
#define LCD_PAL78_G14_0_Msk                                   (0x1fUL << LCD_PAL78_G14_0_Pos)
#define LCD_PAL78_B14_0_Pos                                   26
#define LCD_PAL78_B14_0_Msk                                   (0x1fUL << LCD_PAL78_B14_0_Pos)
#define LCD_PAL78_I1_Pos                                      31
#define LCD_PAL78_I1_Msk                                      (0x01UL << LCD_PAL78_I1_Pos)

// ----------------------------------------  LCD_PAL79  -------------------------------------------
#define LCD_PAL79_R04_0_Pos                                   0
#define LCD_PAL79_R04_0_Msk                                   (0x1fUL << LCD_PAL79_R04_0_Pos)
#define LCD_PAL79_G04_0_Pos                                   5
#define LCD_PAL79_G04_0_Msk                                   (0x1fUL << LCD_PAL79_G04_0_Pos)
#define LCD_PAL79_B04_0_Pos                                   10
#define LCD_PAL79_B04_0_Msk                                   (0x1fUL << LCD_PAL79_B04_0_Pos)
#define LCD_PAL79_I0_Pos                                      15
#define LCD_PAL79_I0_Msk                                      (0x01UL << LCD_PAL79_I0_Pos)
#define LCD_PAL79_R14_0_Pos                                   16
#define LCD_PAL79_R14_0_Msk                                   (0x1fUL << LCD_PAL79_R14_0_Pos)
#define LCD_PAL79_G14_0_Pos                                   21
#define LCD_PAL79_G14_0_Msk                                   (0x1fUL << LCD_PAL79_G14_0_Pos)
#define LCD_PAL79_B14_0_Pos                                   26
#define LCD_PAL79_B14_0_Msk                                   (0x1fUL << LCD_PAL79_B14_0_Pos)
#define LCD_PAL79_I1_Pos                                      31
#define LCD_PAL79_I1_Msk                                      (0x01UL << LCD_PAL79_I1_Pos)

// ----------------------------------------  LCD_PAL80  -------------------------------------------
#define LCD_PAL80_R04_0_Pos                                   0
#define LCD_PAL80_R04_0_Msk                                   (0x1fUL << LCD_PAL80_R04_0_Pos)
#define LCD_PAL80_G04_0_Pos                                   5
#define LCD_PAL80_G04_0_Msk                                   (0x1fUL << LCD_PAL80_G04_0_Pos)
#define LCD_PAL80_B04_0_Pos                                   10
#define LCD_PAL80_B04_0_Msk                                   (0x1fUL << LCD_PAL80_B04_0_Pos)
#define LCD_PAL80_I0_Pos                                      15
#define LCD_PAL80_I0_Msk                                      (0x01UL << LCD_PAL80_I0_Pos)
#define LCD_PAL80_R14_0_Pos                                   16
#define LCD_PAL80_R14_0_Msk                                   (0x1fUL << LCD_PAL80_R14_0_Pos)
#define LCD_PAL80_G14_0_Pos                                   21
#define LCD_PAL80_G14_0_Msk                                   (0x1fUL << LCD_PAL80_G14_0_Pos)
#define LCD_PAL80_B14_0_Pos                                   26
#define LCD_PAL80_B14_0_Msk                                   (0x1fUL << LCD_PAL80_B14_0_Pos)
#define LCD_PAL80_I1_Pos                                      31
#define LCD_PAL80_I1_Msk                                      (0x01UL << LCD_PAL80_I1_Pos)

// ----------------------------------------  LCD_PAL81  -------------------------------------------
#define LCD_PAL81_R04_0_Pos                                   0
#define LCD_PAL81_R04_0_Msk                                   (0x1fUL << LCD_PAL81_R04_0_Pos)
#define LCD_PAL81_G04_0_Pos                                   5
#define LCD_PAL81_G04_0_Msk                                   (0x1fUL << LCD_PAL81_G04_0_Pos)
#define LCD_PAL81_B04_0_Pos                                   10
#define LCD_PAL81_B04_0_Msk                                   (0x1fUL << LCD_PAL81_B04_0_Pos)
#define LCD_PAL81_I0_Pos                                      15
#define LCD_PAL81_I0_Msk                                      (0x01UL << LCD_PAL81_I0_Pos)
#define LCD_PAL81_R14_0_Pos                                   16
#define LCD_PAL81_R14_0_Msk                                   (0x1fUL << LCD_PAL81_R14_0_Pos)
#define LCD_PAL81_G14_0_Pos                                   21
#define LCD_PAL81_G14_0_Msk                                   (0x1fUL << LCD_PAL81_G14_0_Pos)
#define LCD_PAL81_B14_0_Pos                                   26
#define LCD_PAL81_B14_0_Msk                                   (0x1fUL << LCD_PAL81_B14_0_Pos)
#define LCD_PAL81_I1_Pos                                      31
#define LCD_PAL81_I1_Msk                                      (0x01UL << LCD_PAL81_I1_Pos)

// ----------------------------------------  LCD_PAL82  -------------------------------------------
#define LCD_PAL82_R04_0_Pos                                   0
#define LCD_PAL82_R04_0_Msk                                   (0x1fUL << LCD_PAL82_R04_0_Pos)
#define LCD_PAL82_G04_0_Pos                                   5
#define LCD_PAL82_G04_0_Msk                                   (0x1fUL << LCD_PAL82_G04_0_Pos)
#define LCD_PAL82_B04_0_Pos                                   10
#define LCD_PAL82_B04_0_Msk                                   (0x1fUL << LCD_PAL82_B04_0_Pos)
#define LCD_PAL82_I0_Pos                                      15
#define LCD_PAL82_I0_Msk                                      (0x01UL << LCD_PAL82_I0_Pos)
#define LCD_PAL82_R14_0_Pos                                   16
#define LCD_PAL82_R14_0_Msk                                   (0x1fUL << LCD_PAL82_R14_0_Pos)
#define LCD_PAL82_G14_0_Pos                                   21
#define LCD_PAL82_G14_0_Msk                                   (0x1fUL << LCD_PAL82_G14_0_Pos)
#define LCD_PAL82_B14_0_Pos                                   26
#define LCD_PAL82_B14_0_Msk                                   (0x1fUL << LCD_PAL82_B14_0_Pos)
#define LCD_PAL82_I1_Pos                                      31
#define LCD_PAL82_I1_Msk                                      (0x01UL << LCD_PAL82_I1_Pos)

// ----------------------------------------  LCD_PAL83  -------------------------------------------
#define LCD_PAL83_R04_0_Pos                                   0
#define LCD_PAL83_R04_0_Msk                                   (0x1fUL << LCD_PAL83_R04_0_Pos)
#define LCD_PAL83_G04_0_Pos                                   5
#define LCD_PAL83_G04_0_Msk                                   (0x1fUL << LCD_PAL83_G04_0_Pos)
#define LCD_PAL83_B04_0_Pos                                   10
#define LCD_PAL83_B04_0_Msk                                   (0x1fUL << LCD_PAL83_B04_0_Pos)
#define LCD_PAL83_I0_Pos                                      15
#define LCD_PAL83_I0_Msk                                      (0x01UL << LCD_PAL83_I0_Pos)
#define LCD_PAL83_R14_0_Pos                                   16
#define LCD_PAL83_R14_0_Msk                                   (0x1fUL << LCD_PAL83_R14_0_Pos)
#define LCD_PAL83_G14_0_Pos                                   21
#define LCD_PAL83_G14_0_Msk                                   (0x1fUL << LCD_PAL83_G14_0_Pos)
#define LCD_PAL83_B14_0_Pos                                   26
#define LCD_PAL83_B14_0_Msk                                   (0x1fUL << LCD_PAL83_B14_0_Pos)
#define LCD_PAL83_I1_Pos                                      31
#define LCD_PAL83_I1_Msk                                      (0x01UL << LCD_PAL83_I1_Pos)

// ----------------------------------------  LCD_PAL84  -------------------------------------------
#define LCD_PAL84_R04_0_Pos                                   0
#define LCD_PAL84_R04_0_Msk                                   (0x1fUL << LCD_PAL84_R04_0_Pos)
#define LCD_PAL84_G04_0_Pos                                   5
#define LCD_PAL84_G04_0_Msk                                   (0x1fUL << LCD_PAL84_G04_0_Pos)
#define LCD_PAL84_B04_0_Pos                                   10
#define LCD_PAL84_B04_0_Msk                                   (0x1fUL << LCD_PAL84_B04_0_Pos)
#define LCD_PAL84_I0_Pos                                      15
#define LCD_PAL84_I0_Msk                                      (0x01UL << LCD_PAL84_I0_Pos)
#define LCD_PAL84_R14_0_Pos                                   16
#define LCD_PAL84_R14_0_Msk                                   (0x1fUL << LCD_PAL84_R14_0_Pos)
#define LCD_PAL84_G14_0_Pos                                   21
#define LCD_PAL84_G14_0_Msk                                   (0x1fUL << LCD_PAL84_G14_0_Pos)
#define LCD_PAL84_B14_0_Pos                                   26
#define LCD_PAL84_B14_0_Msk                                   (0x1fUL << LCD_PAL84_B14_0_Pos)
#define LCD_PAL84_I1_Pos                                      31
#define LCD_PAL84_I1_Msk                                      (0x01UL << LCD_PAL84_I1_Pos)

// ----------------------------------------  LCD_PAL85  -------------------------------------------
#define LCD_PAL85_R04_0_Pos                                   0
#define LCD_PAL85_R04_0_Msk                                   (0x1fUL << LCD_PAL85_R04_0_Pos)
#define LCD_PAL85_G04_0_Pos                                   5
#define LCD_PAL85_G04_0_Msk                                   (0x1fUL << LCD_PAL85_G04_0_Pos)
#define LCD_PAL85_B04_0_Pos                                   10
#define LCD_PAL85_B04_0_Msk                                   (0x1fUL << LCD_PAL85_B04_0_Pos)
#define LCD_PAL85_I0_Pos                                      15
#define LCD_PAL85_I0_Msk                                      (0x01UL << LCD_PAL85_I0_Pos)
#define LCD_PAL85_R14_0_Pos                                   16
#define LCD_PAL85_R14_0_Msk                                   (0x1fUL << LCD_PAL85_R14_0_Pos)
#define LCD_PAL85_G14_0_Pos                                   21
#define LCD_PAL85_G14_0_Msk                                   (0x1fUL << LCD_PAL85_G14_0_Pos)
#define LCD_PAL85_B14_0_Pos                                   26
#define LCD_PAL85_B14_0_Msk                                   (0x1fUL << LCD_PAL85_B14_0_Pos)
#define LCD_PAL85_I1_Pos                                      31
#define LCD_PAL85_I1_Msk                                      (0x01UL << LCD_PAL85_I1_Pos)

// ----------------------------------------  LCD_PAL86  -------------------------------------------
#define LCD_PAL86_R04_0_Pos                                   0
#define LCD_PAL86_R04_0_Msk                                   (0x1fUL << LCD_PAL86_R04_0_Pos)
#define LCD_PAL86_G04_0_Pos                                   5
#define LCD_PAL86_G04_0_Msk                                   (0x1fUL << LCD_PAL86_G04_0_Pos)
#define LCD_PAL86_B04_0_Pos                                   10
#define LCD_PAL86_B04_0_Msk                                   (0x1fUL << LCD_PAL86_B04_0_Pos)
#define LCD_PAL86_I0_Pos                                      15
#define LCD_PAL86_I0_Msk                                      (0x01UL << LCD_PAL86_I0_Pos)
#define LCD_PAL86_R14_0_Pos                                   16
#define LCD_PAL86_R14_0_Msk                                   (0x1fUL << LCD_PAL86_R14_0_Pos)
#define LCD_PAL86_G14_0_Pos                                   21
#define LCD_PAL86_G14_0_Msk                                   (0x1fUL << LCD_PAL86_G14_0_Pos)
#define LCD_PAL86_B14_0_Pos                                   26
#define LCD_PAL86_B14_0_Msk                                   (0x1fUL << LCD_PAL86_B14_0_Pos)
#define LCD_PAL86_I1_Pos                                      31
#define LCD_PAL86_I1_Msk                                      (0x01UL << LCD_PAL86_I1_Pos)

// ----------------------------------------  LCD_PAL87  -------------------------------------------
#define LCD_PAL87_R04_0_Pos                                   0
#define LCD_PAL87_R04_0_Msk                                   (0x1fUL << LCD_PAL87_R04_0_Pos)
#define LCD_PAL87_G04_0_Pos                                   5
#define LCD_PAL87_G04_0_Msk                                   (0x1fUL << LCD_PAL87_G04_0_Pos)
#define LCD_PAL87_B04_0_Pos                                   10
#define LCD_PAL87_B04_0_Msk                                   (0x1fUL << LCD_PAL87_B04_0_Pos)
#define LCD_PAL87_I0_Pos                                      15
#define LCD_PAL87_I0_Msk                                      (0x01UL << LCD_PAL87_I0_Pos)
#define LCD_PAL87_R14_0_Pos                                   16
#define LCD_PAL87_R14_0_Msk                                   (0x1fUL << LCD_PAL87_R14_0_Pos)
#define LCD_PAL87_G14_0_Pos                                   21
#define LCD_PAL87_G14_0_Msk                                   (0x1fUL << LCD_PAL87_G14_0_Pos)
#define LCD_PAL87_B14_0_Pos                                   26
#define LCD_PAL87_B14_0_Msk                                   (0x1fUL << LCD_PAL87_B14_0_Pos)
#define LCD_PAL87_I1_Pos                                      31
#define LCD_PAL87_I1_Msk                                      (0x01UL << LCD_PAL87_I1_Pos)

// ----------------------------------------  LCD_PAL88  -------------------------------------------
#define LCD_PAL88_R04_0_Pos                                   0
#define LCD_PAL88_R04_0_Msk                                   (0x1fUL << LCD_PAL88_R04_0_Pos)
#define LCD_PAL88_G04_0_Pos                                   5
#define LCD_PAL88_G04_0_Msk                                   (0x1fUL << LCD_PAL88_G04_0_Pos)
#define LCD_PAL88_B04_0_Pos                                   10
#define LCD_PAL88_B04_0_Msk                                   (0x1fUL << LCD_PAL88_B04_0_Pos)
#define LCD_PAL88_I0_Pos                                      15
#define LCD_PAL88_I0_Msk                                      (0x01UL << LCD_PAL88_I0_Pos)
#define LCD_PAL88_R14_0_Pos                                   16
#define LCD_PAL88_R14_0_Msk                                   (0x1fUL << LCD_PAL88_R14_0_Pos)
#define LCD_PAL88_G14_0_Pos                                   21
#define LCD_PAL88_G14_0_Msk                                   (0x1fUL << LCD_PAL88_G14_0_Pos)
#define LCD_PAL88_B14_0_Pos                                   26
#define LCD_PAL88_B14_0_Msk                                   (0x1fUL << LCD_PAL88_B14_0_Pos)
#define LCD_PAL88_I1_Pos                                      31
#define LCD_PAL88_I1_Msk                                      (0x01UL << LCD_PAL88_I1_Pos)

// ----------------------------------------  LCD_PAL89  -------------------------------------------
#define LCD_PAL89_R04_0_Pos                                   0
#define LCD_PAL89_R04_0_Msk                                   (0x1fUL << LCD_PAL89_R04_0_Pos)
#define LCD_PAL89_G04_0_Pos                                   5
#define LCD_PAL89_G04_0_Msk                                   (0x1fUL << LCD_PAL89_G04_0_Pos)
#define LCD_PAL89_B04_0_Pos                                   10
#define LCD_PAL89_B04_0_Msk                                   (0x1fUL << LCD_PAL89_B04_0_Pos)
#define LCD_PAL89_I0_Pos                                      15
#define LCD_PAL89_I0_Msk                                      (0x01UL << LCD_PAL89_I0_Pos)
#define LCD_PAL89_R14_0_Pos                                   16
#define LCD_PAL89_R14_0_Msk                                   (0x1fUL << LCD_PAL89_R14_0_Pos)
#define LCD_PAL89_G14_0_Pos                                   21
#define LCD_PAL89_G14_0_Msk                                   (0x1fUL << LCD_PAL89_G14_0_Pos)
#define LCD_PAL89_B14_0_Pos                                   26
#define LCD_PAL89_B14_0_Msk                                   (0x1fUL << LCD_PAL89_B14_0_Pos)
#define LCD_PAL89_I1_Pos                                      31
#define LCD_PAL89_I1_Msk                                      (0x01UL << LCD_PAL89_I1_Pos)

// ----------------------------------------  LCD_PAL90  -------------------------------------------
#define LCD_PAL90_R04_0_Pos                                   0
#define LCD_PAL90_R04_0_Msk                                   (0x1fUL << LCD_PAL90_R04_0_Pos)
#define LCD_PAL90_G04_0_Pos                                   5
#define LCD_PAL90_G04_0_Msk                                   (0x1fUL << LCD_PAL90_G04_0_Pos)
#define LCD_PAL90_B04_0_Pos                                   10
#define LCD_PAL90_B04_0_Msk                                   (0x1fUL << LCD_PAL90_B04_0_Pos)
#define LCD_PAL90_I0_Pos                                      15
#define LCD_PAL90_I0_Msk                                      (0x01UL << LCD_PAL90_I0_Pos)
#define LCD_PAL90_R14_0_Pos                                   16
#define LCD_PAL90_R14_0_Msk                                   (0x1fUL << LCD_PAL90_R14_0_Pos)
#define LCD_PAL90_G14_0_Pos                                   21
#define LCD_PAL90_G14_0_Msk                                   (0x1fUL << LCD_PAL90_G14_0_Pos)
#define LCD_PAL90_B14_0_Pos                                   26
#define LCD_PAL90_B14_0_Msk                                   (0x1fUL << LCD_PAL90_B14_0_Pos)
#define LCD_PAL90_I1_Pos                                      31
#define LCD_PAL90_I1_Msk                                      (0x01UL << LCD_PAL90_I1_Pos)

// ----------------------------------------  LCD_PAL91  -------------------------------------------
#define LCD_PAL91_R04_0_Pos                                   0
#define LCD_PAL91_R04_0_Msk                                   (0x1fUL << LCD_PAL91_R04_0_Pos)
#define LCD_PAL91_G04_0_Pos                                   5
#define LCD_PAL91_G04_0_Msk                                   (0x1fUL << LCD_PAL91_G04_0_Pos)
#define LCD_PAL91_B04_0_Pos                                   10
#define LCD_PAL91_B04_0_Msk                                   (0x1fUL << LCD_PAL91_B04_0_Pos)
#define LCD_PAL91_I0_Pos                                      15
#define LCD_PAL91_I0_Msk                                      (0x01UL << LCD_PAL91_I0_Pos)
#define LCD_PAL91_R14_0_Pos                                   16
#define LCD_PAL91_R14_0_Msk                                   (0x1fUL << LCD_PAL91_R14_0_Pos)
#define LCD_PAL91_G14_0_Pos                                   21
#define LCD_PAL91_G14_0_Msk                                   (0x1fUL << LCD_PAL91_G14_0_Pos)
#define LCD_PAL91_B14_0_Pos                                   26
#define LCD_PAL91_B14_0_Msk                                   (0x1fUL << LCD_PAL91_B14_0_Pos)
#define LCD_PAL91_I1_Pos                                      31
#define LCD_PAL91_I1_Msk                                      (0x01UL << LCD_PAL91_I1_Pos)

// ----------------------------------------  LCD_PAL92  -------------------------------------------
#define LCD_PAL92_R04_0_Pos                                   0
#define LCD_PAL92_R04_0_Msk                                   (0x1fUL << LCD_PAL92_R04_0_Pos)
#define LCD_PAL92_G04_0_Pos                                   5
#define LCD_PAL92_G04_0_Msk                                   (0x1fUL << LCD_PAL92_G04_0_Pos)
#define LCD_PAL92_B04_0_Pos                                   10
#define LCD_PAL92_B04_0_Msk                                   (0x1fUL << LCD_PAL92_B04_0_Pos)
#define LCD_PAL92_I0_Pos                                      15
#define LCD_PAL92_I0_Msk                                      (0x01UL << LCD_PAL92_I0_Pos)
#define LCD_PAL92_R14_0_Pos                                   16
#define LCD_PAL92_R14_0_Msk                                   (0x1fUL << LCD_PAL92_R14_0_Pos)
#define LCD_PAL92_G14_0_Pos                                   21
#define LCD_PAL92_G14_0_Msk                                   (0x1fUL << LCD_PAL92_G14_0_Pos)
#define LCD_PAL92_B14_0_Pos                                   26
#define LCD_PAL92_B14_0_Msk                                   (0x1fUL << LCD_PAL92_B14_0_Pos)
#define LCD_PAL92_I1_Pos                                      31
#define LCD_PAL92_I1_Msk                                      (0x01UL << LCD_PAL92_I1_Pos)

// ----------------------------------------  LCD_PAL93  -------------------------------------------
#define LCD_PAL93_R04_0_Pos                                   0
#define LCD_PAL93_R04_0_Msk                                   (0x1fUL << LCD_PAL93_R04_0_Pos)
#define LCD_PAL93_G04_0_Pos                                   5
#define LCD_PAL93_G04_0_Msk                                   (0x1fUL << LCD_PAL93_G04_0_Pos)
#define LCD_PAL93_B04_0_Pos                                   10
#define LCD_PAL93_B04_0_Msk                                   (0x1fUL << LCD_PAL93_B04_0_Pos)
#define LCD_PAL93_I0_Pos                                      15
#define LCD_PAL93_I0_Msk                                      (0x01UL << LCD_PAL93_I0_Pos)
#define LCD_PAL93_R14_0_Pos                                   16
#define LCD_PAL93_R14_0_Msk                                   (0x1fUL << LCD_PAL93_R14_0_Pos)
#define LCD_PAL93_G14_0_Pos                                   21
#define LCD_PAL93_G14_0_Msk                                   (0x1fUL << LCD_PAL93_G14_0_Pos)
#define LCD_PAL93_B14_0_Pos                                   26
#define LCD_PAL93_B14_0_Msk                                   (0x1fUL << LCD_PAL93_B14_0_Pos)
#define LCD_PAL93_I1_Pos                                      31
#define LCD_PAL93_I1_Msk                                      (0x01UL << LCD_PAL93_I1_Pos)

// ----------------------------------------  LCD_PAL94  -------------------------------------------
#define LCD_PAL94_R04_0_Pos                                   0
#define LCD_PAL94_R04_0_Msk                                   (0x1fUL << LCD_PAL94_R04_0_Pos)
#define LCD_PAL94_G04_0_Pos                                   5
#define LCD_PAL94_G04_0_Msk                                   (0x1fUL << LCD_PAL94_G04_0_Pos)
#define LCD_PAL94_B04_0_Pos                                   10
#define LCD_PAL94_B04_0_Msk                                   (0x1fUL << LCD_PAL94_B04_0_Pos)
#define LCD_PAL94_I0_Pos                                      15
#define LCD_PAL94_I0_Msk                                      (0x01UL << LCD_PAL94_I0_Pos)
#define LCD_PAL94_R14_0_Pos                                   16
#define LCD_PAL94_R14_0_Msk                                   (0x1fUL << LCD_PAL94_R14_0_Pos)
#define LCD_PAL94_G14_0_Pos                                   21
#define LCD_PAL94_G14_0_Msk                                   (0x1fUL << LCD_PAL94_G14_0_Pos)
#define LCD_PAL94_B14_0_Pos                                   26
#define LCD_PAL94_B14_0_Msk                                   (0x1fUL << LCD_PAL94_B14_0_Pos)
#define LCD_PAL94_I1_Pos                                      31
#define LCD_PAL94_I1_Msk                                      (0x01UL << LCD_PAL94_I1_Pos)

// ----------------------------------------  LCD_PAL95  -------------------------------------------
#define LCD_PAL95_R04_0_Pos                                   0
#define LCD_PAL95_R04_0_Msk                                   (0x1fUL << LCD_PAL95_R04_0_Pos)
#define LCD_PAL95_G04_0_Pos                                   5
#define LCD_PAL95_G04_0_Msk                                   (0x1fUL << LCD_PAL95_G04_0_Pos)
#define LCD_PAL95_B04_0_Pos                                   10
#define LCD_PAL95_B04_0_Msk                                   (0x1fUL << LCD_PAL95_B04_0_Pos)
#define LCD_PAL95_I0_Pos                                      15
#define LCD_PAL95_I0_Msk                                      (0x01UL << LCD_PAL95_I0_Pos)
#define LCD_PAL95_R14_0_Pos                                   16
#define LCD_PAL95_R14_0_Msk                                   (0x1fUL << LCD_PAL95_R14_0_Pos)
#define LCD_PAL95_G14_0_Pos                                   21
#define LCD_PAL95_G14_0_Msk                                   (0x1fUL << LCD_PAL95_G14_0_Pos)
#define LCD_PAL95_B14_0_Pos                                   26
#define LCD_PAL95_B14_0_Msk                                   (0x1fUL << LCD_PAL95_B14_0_Pos)
#define LCD_PAL95_I1_Pos                                      31
#define LCD_PAL95_I1_Msk                                      (0x01UL << LCD_PAL95_I1_Pos)

// ----------------------------------------  LCD_PAL96  -------------------------------------------
#define LCD_PAL96_R04_0_Pos                                   0
#define LCD_PAL96_R04_0_Msk                                   (0x1fUL << LCD_PAL96_R04_0_Pos)
#define LCD_PAL96_G04_0_Pos                                   5
#define LCD_PAL96_G04_0_Msk                                   (0x1fUL << LCD_PAL96_G04_0_Pos)
#define LCD_PAL96_B04_0_Pos                                   10
#define LCD_PAL96_B04_0_Msk                                   (0x1fUL << LCD_PAL96_B04_0_Pos)
#define LCD_PAL96_I0_Pos                                      15
#define LCD_PAL96_I0_Msk                                      (0x01UL << LCD_PAL96_I0_Pos)
#define LCD_PAL96_R14_0_Pos                                   16
#define LCD_PAL96_R14_0_Msk                                   (0x1fUL << LCD_PAL96_R14_0_Pos)
#define LCD_PAL96_G14_0_Pos                                   21
#define LCD_PAL96_G14_0_Msk                                   (0x1fUL << LCD_PAL96_G14_0_Pos)
#define LCD_PAL96_B14_0_Pos                                   26
#define LCD_PAL96_B14_0_Msk                                   (0x1fUL << LCD_PAL96_B14_0_Pos)
#define LCD_PAL96_I1_Pos                                      31
#define LCD_PAL96_I1_Msk                                      (0x01UL << LCD_PAL96_I1_Pos)

// ----------------------------------------  LCD_PAL97  -------------------------------------------
#define LCD_PAL97_R04_0_Pos                                   0
#define LCD_PAL97_R04_0_Msk                                   (0x1fUL << LCD_PAL97_R04_0_Pos)
#define LCD_PAL97_G04_0_Pos                                   5
#define LCD_PAL97_G04_0_Msk                                   (0x1fUL << LCD_PAL97_G04_0_Pos)
#define LCD_PAL97_B04_0_Pos                                   10
#define LCD_PAL97_B04_0_Msk                                   (0x1fUL << LCD_PAL97_B04_0_Pos)
#define LCD_PAL97_I0_Pos                                      15
#define LCD_PAL97_I0_Msk                                      (0x01UL << LCD_PAL97_I0_Pos)
#define LCD_PAL97_R14_0_Pos                                   16
#define LCD_PAL97_R14_0_Msk                                   (0x1fUL << LCD_PAL97_R14_0_Pos)
#define LCD_PAL97_G14_0_Pos                                   21
#define LCD_PAL97_G14_0_Msk                                   (0x1fUL << LCD_PAL97_G14_0_Pos)
#define LCD_PAL97_B14_0_Pos                                   26
#define LCD_PAL97_B14_0_Msk                                   (0x1fUL << LCD_PAL97_B14_0_Pos)
#define LCD_PAL97_I1_Pos                                      31
#define LCD_PAL97_I1_Msk                                      (0x01UL << LCD_PAL97_I1_Pos)

// ----------------------------------------  LCD_PAL98  -------------------------------------------
#define LCD_PAL98_R04_0_Pos                                   0
#define LCD_PAL98_R04_0_Msk                                   (0x1fUL << LCD_PAL98_R04_0_Pos)
#define LCD_PAL98_G04_0_Pos                                   5
#define LCD_PAL98_G04_0_Msk                                   (0x1fUL << LCD_PAL98_G04_0_Pos)
#define LCD_PAL98_B04_0_Pos                                   10
#define LCD_PAL98_B04_0_Msk                                   (0x1fUL << LCD_PAL98_B04_0_Pos)
#define LCD_PAL98_I0_Pos                                      15
#define LCD_PAL98_I0_Msk                                      (0x01UL << LCD_PAL98_I0_Pos)
#define LCD_PAL98_R14_0_Pos                                   16
#define LCD_PAL98_R14_0_Msk                                   (0x1fUL << LCD_PAL98_R14_0_Pos)
#define LCD_PAL98_G14_0_Pos                                   21
#define LCD_PAL98_G14_0_Msk                                   (0x1fUL << LCD_PAL98_G14_0_Pos)
#define LCD_PAL98_B14_0_Pos                                   26
#define LCD_PAL98_B14_0_Msk                                   (0x1fUL << LCD_PAL98_B14_0_Pos)
#define LCD_PAL98_I1_Pos                                      31
#define LCD_PAL98_I1_Msk                                      (0x01UL << LCD_PAL98_I1_Pos)

// ----------------------------------------  LCD_PAL99  -------------------------------------------
#define LCD_PAL99_R04_0_Pos                                   0
#define LCD_PAL99_R04_0_Msk                                   (0x1fUL << LCD_PAL99_R04_0_Pos)
#define LCD_PAL99_G04_0_Pos                                   5
#define LCD_PAL99_G04_0_Msk                                   (0x1fUL << LCD_PAL99_G04_0_Pos)
#define LCD_PAL99_B04_0_Pos                                   10
#define LCD_PAL99_B04_0_Msk                                   (0x1fUL << LCD_PAL99_B04_0_Pos)
#define LCD_PAL99_I0_Pos                                      15
#define LCD_PAL99_I0_Msk                                      (0x01UL << LCD_PAL99_I0_Pos)
#define LCD_PAL99_R14_0_Pos                                   16
#define LCD_PAL99_R14_0_Msk                                   (0x1fUL << LCD_PAL99_R14_0_Pos)
#define LCD_PAL99_G14_0_Pos                                   21
#define LCD_PAL99_G14_0_Msk                                   (0x1fUL << LCD_PAL99_G14_0_Pos)
#define LCD_PAL99_B14_0_Pos                                   26
#define LCD_PAL99_B14_0_Msk                                   (0x1fUL << LCD_PAL99_B14_0_Pos)
#define LCD_PAL99_I1_Pos                                      31
#define LCD_PAL99_I1_Msk                                      (0x01UL << LCD_PAL99_I1_Pos)

// ---------------------------------------  LCD_PAL100  -------------------------------------------
#define LCD_PAL100_R04_0_Pos                                  0
#define LCD_PAL100_R04_0_Msk                                  (0x1fUL << LCD_PAL100_R04_0_Pos)
#define LCD_PAL100_G04_0_Pos                                  5
#define LCD_PAL100_G04_0_Msk                                  (0x1fUL << LCD_PAL100_G04_0_Pos)
#define LCD_PAL100_B04_0_Pos                                  10
#define LCD_PAL100_B04_0_Msk                                  (0x1fUL << LCD_PAL100_B04_0_Pos)
#define LCD_PAL100_I0_Pos                                     15
#define LCD_PAL100_I0_Msk                                     (0x01UL << LCD_PAL100_I0_Pos)
#define LCD_PAL100_R14_0_Pos                                  16
#define LCD_PAL100_R14_0_Msk                                  (0x1fUL << LCD_PAL100_R14_0_Pos)
#define LCD_PAL100_G14_0_Pos                                  21
#define LCD_PAL100_G14_0_Msk                                  (0x1fUL << LCD_PAL100_G14_0_Pos)
#define LCD_PAL100_B14_0_Pos                                  26
#define LCD_PAL100_B14_0_Msk                                  (0x1fUL << LCD_PAL100_B14_0_Pos)
#define LCD_PAL100_I1_Pos                                     31
#define LCD_PAL100_I1_Msk                                     (0x01UL << LCD_PAL100_I1_Pos)

// ---------------------------------------  LCD_PAL101  -------------------------------------------
#define LCD_PAL101_R04_0_Pos                                  0
#define LCD_PAL101_R04_0_Msk                                  (0x1fUL << LCD_PAL101_R04_0_Pos)
#define LCD_PAL101_G04_0_Pos                                  5
#define LCD_PAL101_G04_0_Msk                                  (0x1fUL << LCD_PAL101_G04_0_Pos)
#define LCD_PAL101_B04_0_Pos                                  10
#define LCD_PAL101_B04_0_Msk                                  (0x1fUL << LCD_PAL101_B04_0_Pos)
#define LCD_PAL101_I0_Pos                                     15
#define LCD_PAL101_I0_Msk                                     (0x01UL << LCD_PAL101_I0_Pos)
#define LCD_PAL101_R14_0_Pos                                  16
#define LCD_PAL101_R14_0_Msk                                  (0x1fUL << LCD_PAL101_R14_0_Pos)
#define LCD_PAL101_G14_0_Pos                                  21
#define LCD_PAL101_G14_0_Msk                                  (0x1fUL << LCD_PAL101_G14_0_Pos)
#define LCD_PAL101_B14_0_Pos                                  26
#define LCD_PAL101_B14_0_Msk                                  (0x1fUL << LCD_PAL101_B14_0_Pos)
#define LCD_PAL101_I1_Pos                                     31
#define LCD_PAL101_I1_Msk                                     (0x01UL << LCD_PAL101_I1_Pos)

// ---------------------------------------  LCD_PAL102  -------------------------------------------
#define LCD_PAL102_R04_0_Pos                                  0
#define LCD_PAL102_R04_0_Msk                                  (0x1fUL << LCD_PAL102_R04_0_Pos)
#define LCD_PAL102_G04_0_Pos                                  5
#define LCD_PAL102_G04_0_Msk                                  (0x1fUL << LCD_PAL102_G04_0_Pos)
#define LCD_PAL102_B04_0_Pos                                  10
#define LCD_PAL102_B04_0_Msk                                  (0x1fUL << LCD_PAL102_B04_0_Pos)
#define LCD_PAL102_I0_Pos                                     15
#define LCD_PAL102_I0_Msk                                     (0x01UL << LCD_PAL102_I0_Pos)
#define LCD_PAL102_R14_0_Pos                                  16
#define LCD_PAL102_R14_0_Msk                                  (0x1fUL << LCD_PAL102_R14_0_Pos)
#define LCD_PAL102_G14_0_Pos                                  21
#define LCD_PAL102_G14_0_Msk                                  (0x1fUL << LCD_PAL102_G14_0_Pos)
#define LCD_PAL102_B14_0_Pos                                  26
#define LCD_PAL102_B14_0_Msk                                  (0x1fUL << LCD_PAL102_B14_0_Pos)
#define LCD_PAL102_I1_Pos                                     31
#define LCD_PAL102_I1_Msk                                     (0x01UL << LCD_PAL102_I1_Pos)

// ---------------------------------------  LCD_PAL103  -------------------------------------------
#define LCD_PAL103_R04_0_Pos                                  0
#define LCD_PAL103_R04_0_Msk                                  (0x1fUL << LCD_PAL103_R04_0_Pos)
#define LCD_PAL103_G04_0_Pos                                  5
#define LCD_PAL103_G04_0_Msk                                  (0x1fUL << LCD_PAL103_G04_0_Pos)
#define LCD_PAL103_B04_0_Pos                                  10
#define LCD_PAL103_B04_0_Msk                                  (0x1fUL << LCD_PAL103_B04_0_Pos)
#define LCD_PAL103_I0_Pos                                     15
#define LCD_PAL103_I0_Msk                                     (0x01UL << LCD_PAL103_I0_Pos)
#define LCD_PAL103_R14_0_Pos                                  16
#define LCD_PAL103_R14_0_Msk                                  (0x1fUL << LCD_PAL103_R14_0_Pos)
#define LCD_PAL103_G14_0_Pos                                  21
#define LCD_PAL103_G14_0_Msk                                  (0x1fUL << LCD_PAL103_G14_0_Pos)
#define LCD_PAL103_B14_0_Pos                                  26
#define LCD_PAL103_B14_0_Msk                                  (0x1fUL << LCD_PAL103_B14_0_Pos)
#define LCD_PAL103_I1_Pos                                     31
#define LCD_PAL103_I1_Msk                                     (0x01UL << LCD_PAL103_I1_Pos)

// ---------------------------------------  LCD_PAL104  -------------------------------------------
#define LCD_PAL104_R04_0_Pos                                  0
#define LCD_PAL104_R04_0_Msk                                  (0x1fUL << LCD_PAL104_R04_0_Pos)
#define LCD_PAL104_G04_0_Pos                                  5
#define LCD_PAL104_G04_0_Msk                                  (0x1fUL << LCD_PAL104_G04_0_Pos)
#define LCD_PAL104_B04_0_Pos                                  10
#define LCD_PAL104_B04_0_Msk                                  (0x1fUL << LCD_PAL104_B04_0_Pos)
#define LCD_PAL104_I0_Pos                                     15
#define LCD_PAL104_I0_Msk                                     (0x01UL << LCD_PAL104_I0_Pos)
#define LCD_PAL104_R14_0_Pos                                  16
#define LCD_PAL104_R14_0_Msk                                  (0x1fUL << LCD_PAL104_R14_0_Pos)
#define LCD_PAL104_G14_0_Pos                                  21
#define LCD_PAL104_G14_0_Msk                                  (0x1fUL << LCD_PAL104_G14_0_Pos)
#define LCD_PAL104_B14_0_Pos                                  26
#define LCD_PAL104_B14_0_Msk                                  (0x1fUL << LCD_PAL104_B14_0_Pos)
#define LCD_PAL104_I1_Pos                                     31
#define LCD_PAL104_I1_Msk                                     (0x01UL << LCD_PAL104_I1_Pos)

// ---------------------------------------  LCD_PAL105  -------------------------------------------
#define LCD_PAL105_R04_0_Pos                                  0
#define LCD_PAL105_R04_0_Msk                                  (0x1fUL << LCD_PAL105_R04_0_Pos)
#define LCD_PAL105_G04_0_Pos                                  5
#define LCD_PAL105_G04_0_Msk                                  (0x1fUL << LCD_PAL105_G04_0_Pos)
#define LCD_PAL105_B04_0_Pos                                  10
#define LCD_PAL105_B04_0_Msk                                  (0x1fUL << LCD_PAL105_B04_0_Pos)
#define LCD_PAL105_I0_Pos                                     15
#define LCD_PAL105_I0_Msk                                     (0x01UL << LCD_PAL105_I0_Pos)
#define LCD_PAL105_R14_0_Pos                                  16
#define LCD_PAL105_R14_0_Msk                                  (0x1fUL << LCD_PAL105_R14_0_Pos)
#define LCD_PAL105_G14_0_Pos                                  21
#define LCD_PAL105_G14_0_Msk                                  (0x1fUL << LCD_PAL105_G14_0_Pos)
#define LCD_PAL105_B14_0_Pos                                  26
#define LCD_PAL105_B14_0_Msk                                  (0x1fUL << LCD_PAL105_B14_0_Pos)
#define LCD_PAL105_I1_Pos                                     31
#define LCD_PAL105_I1_Msk                                     (0x01UL << LCD_PAL105_I1_Pos)

// ---------------------------------------  LCD_PAL106  -------------------------------------------
#define LCD_PAL106_R04_0_Pos                                  0
#define LCD_PAL106_R04_0_Msk                                  (0x1fUL << LCD_PAL106_R04_0_Pos)
#define LCD_PAL106_G04_0_Pos                                  5
#define LCD_PAL106_G04_0_Msk                                  (0x1fUL << LCD_PAL106_G04_0_Pos)
#define LCD_PAL106_B04_0_Pos                                  10
#define LCD_PAL106_B04_0_Msk                                  (0x1fUL << LCD_PAL106_B04_0_Pos)
#define LCD_PAL106_I0_Pos                                     15
#define LCD_PAL106_I0_Msk                                     (0x01UL << LCD_PAL106_I0_Pos)
#define LCD_PAL106_R14_0_Pos                                  16
#define LCD_PAL106_R14_0_Msk                                  (0x1fUL << LCD_PAL106_R14_0_Pos)
#define LCD_PAL106_G14_0_Pos                                  21
#define LCD_PAL106_G14_0_Msk                                  (0x1fUL << LCD_PAL106_G14_0_Pos)
#define LCD_PAL106_B14_0_Pos                                  26
#define LCD_PAL106_B14_0_Msk                                  (0x1fUL << LCD_PAL106_B14_0_Pos)
#define LCD_PAL106_I1_Pos                                     31
#define LCD_PAL106_I1_Msk                                     (0x01UL << LCD_PAL106_I1_Pos)

// ---------------------------------------  LCD_PAL107  -------------------------------------------
#define LCD_PAL107_R04_0_Pos                                  0
#define LCD_PAL107_R04_0_Msk                                  (0x1fUL << LCD_PAL107_R04_0_Pos)
#define LCD_PAL107_G04_0_Pos                                  5
#define LCD_PAL107_G04_0_Msk                                  (0x1fUL << LCD_PAL107_G04_0_Pos)
#define LCD_PAL107_B04_0_Pos                                  10
#define LCD_PAL107_B04_0_Msk                                  (0x1fUL << LCD_PAL107_B04_0_Pos)
#define LCD_PAL107_I0_Pos                                     15
#define LCD_PAL107_I0_Msk                                     (0x01UL << LCD_PAL107_I0_Pos)
#define LCD_PAL107_R14_0_Pos                                  16
#define LCD_PAL107_R14_0_Msk                                  (0x1fUL << LCD_PAL107_R14_0_Pos)
#define LCD_PAL107_G14_0_Pos                                  21
#define LCD_PAL107_G14_0_Msk                                  (0x1fUL << LCD_PAL107_G14_0_Pos)
#define LCD_PAL107_B14_0_Pos                                  26
#define LCD_PAL107_B14_0_Msk                                  (0x1fUL << LCD_PAL107_B14_0_Pos)
#define LCD_PAL107_I1_Pos                                     31
#define LCD_PAL107_I1_Msk                                     (0x01UL << LCD_PAL107_I1_Pos)

// ---------------------------------------  LCD_PAL108  -------------------------------------------
#define LCD_PAL108_R04_0_Pos                                  0
#define LCD_PAL108_R04_0_Msk                                  (0x1fUL << LCD_PAL108_R04_0_Pos)
#define LCD_PAL108_G04_0_Pos                                  5
#define LCD_PAL108_G04_0_Msk                                  (0x1fUL << LCD_PAL108_G04_0_Pos)
#define LCD_PAL108_B04_0_Pos                                  10
#define LCD_PAL108_B04_0_Msk                                  (0x1fUL << LCD_PAL108_B04_0_Pos)
#define LCD_PAL108_I0_Pos                                     15
#define LCD_PAL108_I0_Msk                                     (0x01UL << LCD_PAL108_I0_Pos)
#define LCD_PAL108_R14_0_Pos                                  16
#define LCD_PAL108_R14_0_Msk                                  (0x1fUL << LCD_PAL108_R14_0_Pos)
#define LCD_PAL108_G14_0_Pos                                  21
#define LCD_PAL108_G14_0_Msk                                  (0x1fUL << LCD_PAL108_G14_0_Pos)
#define LCD_PAL108_B14_0_Pos                                  26
#define LCD_PAL108_B14_0_Msk                                  (0x1fUL << LCD_PAL108_B14_0_Pos)
#define LCD_PAL108_I1_Pos                                     31
#define LCD_PAL108_I1_Msk                                     (0x01UL << LCD_PAL108_I1_Pos)

// ---------------------------------------  LCD_PAL109  -------------------------------------------
#define LCD_PAL109_R04_0_Pos                                  0
#define LCD_PAL109_R04_0_Msk                                  (0x1fUL << LCD_PAL109_R04_0_Pos)
#define LCD_PAL109_G04_0_Pos                                  5
#define LCD_PAL109_G04_0_Msk                                  (0x1fUL << LCD_PAL109_G04_0_Pos)
#define LCD_PAL109_B04_0_Pos                                  10
#define LCD_PAL109_B04_0_Msk                                  (0x1fUL << LCD_PAL109_B04_0_Pos)
#define LCD_PAL109_I0_Pos                                     15
#define LCD_PAL109_I0_Msk                                     (0x01UL << LCD_PAL109_I0_Pos)
#define LCD_PAL109_R14_0_Pos                                  16
#define LCD_PAL109_R14_0_Msk                                  (0x1fUL << LCD_PAL109_R14_0_Pos)
#define LCD_PAL109_G14_0_Pos                                  21
#define LCD_PAL109_G14_0_Msk                                  (0x1fUL << LCD_PAL109_G14_0_Pos)
#define LCD_PAL109_B14_0_Pos                                  26
#define LCD_PAL109_B14_0_Msk                                  (0x1fUL << LCD_PAL109_B14_0_Pos)
#define LCD_PAL109_I1_Pos                                     31
#define LCD_PAL109_I1_Msk                                     (0x01UL << LCD_PAL109_I1_Pos)

// ---------------------------------------  LCD_PAL110  -------------------------------------------
#define LCD_PAL110_R04_0_Pos                                  0
#define LCD_PAL110_R04_0_Msk                                  (0x1fUL << LCD_PAL110_R04_0_Pos)
#define LCD_PAL110_G04_0_Pos                                  5
#define LCD_PAL110_G04_0_Msk                                  (0x1fUL << LCD_PAL110_G04_0_Pos)
#define LCD_PAL110_B04_0_Pos                                  10
#define LCD_PAL110_B04_0_Msk                                  (0x1fUL << LCD_PAL110_B04_0_Pos)
#define LCD_PAL110_I0_Pos                                     15
#define LCD_PAL110_I0_Msk                                     (0x01UL << LCD_PAL110_I0_Pos)
#define LCD_PAL110_R14_0_Pos                                  16
#define LCD_PAL110_R14_0_Msk                                  (0x1fUL << LCD_PAL110_R14_0_Pos)
#define LCD_PAL110_G14_0_Pos                                  21
#define LCD_PAL110_G14_0_Msk                                  (0x1fUL << LCD_PAL110_G14_0_Pos)
#define LCD_PAL110_B14_0_Pos                                  26
#define LCD_PAL110_B14_0_Msk                                  (0x1fUL << LCD_PAL110_B14_0_Pos)
#define LCD_PAL110_I1_Pos                                     31
#define LCD_PAL110_I1_Msk                                     (0x01UL << LCD_PAL110_I1_Pos)

// ---------------------------------------  LCD_PAL111  -------------------------------------------
#define LCD_PAL111_R04_0_Pos                                  0
#define LCD_PAL111_R04_0_Msk                                  (0x1fUL << LCD_PAL111_R04_0_Pos)
#define LCD_PAL111_G04_0_Pos                                  5
#define LCD_PAL111_G04_0_Msk                                  (0x1fUL << LCD_PAL111_G04_0_Pos)
#define LCD_PAL111_B04_0_Pos                                  10
#define LCD_PAL111_B04_0_Msk                                  (0x1fUL << LCD_PAL111_B04_0_Pos)
#define LCD_PAL111_I0_Pos                                     15
#define LCD_PAL111_I0_Msk                                     (0x01UL << LCD_PAL111_I0_Pos)
#define LCD_PAL111_R14_0_Pos                                  16
#define LCD_PAL111_R14_0_Msk                                  (0x1fUL << LCD_PAL111_R14_0_Pos)
#define LCD_PAL111_G14_0_Pos                                  21
#define LCD_PAL111_G14_0_Msk                                  (0x1fUL << LCD_PAL111_G14_0_Pos)
#define LCD_PAL111_B14_0_Pos                                  26
#define LCD_PAL111_B14_0_Msk                                  (0x1fUL << LCD_PAL111_B14_0_Pos)
#define LCD_PAL111_I1_Pos                                     31
#define LCD_PAL111_I1_Msk                                     (0x01UL << LCD_PAL111_I1_Pos)

// ---------------------------------------  LCD_PAL112  -------------------------------------------
#define LCD_PAL112_R04_0_Pos                                  0
#define LCD_PAL112_R04_0_Msk                                  (0x1fUL << LCD_PAL112_R04_0_Pos)
#define LCD_PAL112_G04_0_Pos                                  5
#define LCD_PAL112_G04_0_Msk                                  (0x1fUL << LCD_PAL112_G04_0_Pos)
#define LCD_PAL112_B04_0_Pos                                  10
#define LCD_PAL112_B04_0_Msk                                  (0x1fUL << LCD_PAL112_B04_0_Pos)
#define LCD_PAL112_I0_Pos                                     15
#define LCD_PAL112_I0_Msk                                     (0x01UL << LCD_PAL112_I0_Pos)
#define LCD_PAL112_R14_0_Pos                                  16
#define LCD_PAL112_R14_0_Msk                                  (0x1fUL << LCD_PAL112_R14_0_Pos)
#define LCD_PAL112_G14_0_Pos                                  21
#define LCD_PAL112_G14_0_Msk                                  (0x1fUL << LCD_PAL112_G14_0_Pos)
#define LCD_PAL112_B14_0_Pos                                  26
#define LCD_PAL112_B14_0_Msk                                  (0x1fUL << LCD_PAL112_B14_0_Pos)
#define LCD_PAL112_I1_Pos                                     31
#define LCD_PAL112_I1_Msk                                     (0x01UL << LCD_PAL112_I1_Pos)

// ---------------------------------------  LCD_PAL113  -------------------------------------------
#define LCD_PAL113_R04_0_Pos                                  0
#define LCD_PAL113_R04_0_Msk                                  (0x1fUL << LCD_PAL113_R04_0_Pos)
#define LCD_PAL113_G04_0_Pos                                  5
#define LCD_PAL113_G04_0_Msk                                  (0x1fUL << LCD_PAL113_G04_0_Pos)
#define LCD_PAL113_B04_0_Pos                                  10
#define LCD_PAL113_B04_0_Msk                                  (0x1fUL << LCD_PAL113_B04_0_Pos)
#define LCD_PAL113_I0_Pos                                     15
#define LCD_PAL113_I0_Msk                                     (0x01UL << LCD_PAL113_I0_Pos)
#define LCD_PAL113_R14_0_Pos                                  16
#define LCD_PAL113_R14_0_Msk                                  (0x1fUL << LCD_PAL113_R14_0_Pos)
#define LCD_PAL113_G14_0_Pos                                  21
#define LCD_PAL113_G14_0_Msk                                  (0x1fUL << LCD_PAL113_G14_0_Pos)
#define LCD_PAL113_B14_0_Pos                                  26
#define LCD_PAL113_B14_0_Msk                                  (0x1fUL << LCD_PAL113_B14_0_Pos)
#define LCD_PAL113_I1_Pos                                     31
#define LCD_PAL113_I1_Msk                                     (0x01UL << LCD_PAL113_I1_Pos)

// ---------------------------------------  LCD_PAL114  -------------------------------------------
#define LCD_PAL114_R04_0_Pos                                  0
#define LCD_PAL114_R04_0_Msk                                  (0x1fUL << LCD_PAL114_R04_0_Pos)
#define LCD_PAL114_G04_0_Pos                                  5
#define LCD_PAL114_G04_0_Msk                                  (0x1fUL << LCD_PAL114_G04_0_Pos)
#define LCD_PAL114_B04_0_Pos                                  10
#define LCD_PAL114_B04_0_Msk                                  (0x1fUL << LCD_PAL114_B04_0_Pos)
#define LCD_PAL114_I0_Pos                                     15
#define LCD_PAL114_I0_Msk                                     (0x01UL << LCD_PAL114_I0_Pos)
#define LCD_PAL114_R14_0_Pos                                  16
#define LCD_PAL114_R14_0_Msk                                  (0x1fUL << LCD_PAL114_R14_0_Pos)
#define LCD_PAL114_G14_0_Pos                                  21
#define LCD_PAL114_G14_0_Msk                                  (0x1fUL << LCD_PAL114_G14_0_Pos)
#define LCD_PAL114_B14_0_Pos                                  26
#define LCD_PAL114_B14_0_Msk                                  (0x1fUL << LCD_PAL114_B14_0_Pos)
#define LCD_PAL114_I1_Pos                                     31
#define LCD_PAL114_I1_Msk                                     (0x01UL << LCD_PAL114_I1_Pos)

// ---------------------------------------  LCD_PAL115  -------------------------------------------
#define LCD_PAL115_R04_0_Pos                                  0
#define LCD_PAL115_R04_0_Msk                                  (0x1fUL << LCD_PAL115_R04_0_Pos)
#define LCD_PAL115_G04_0_Pos                                  5
#define LCD_PAL115_G04_0_Msk                                  (0x1fUL << LCD_PAL115_G04_0_Pos)
#define LCD_PAL115_B04_0_Pos                                  10
#define LCD_PAL115_B04_0_Msk                                  (0x1fUL << LCD_PAL115_B04_0_Pos)
#define LCD_PAL115_I0_Pos                                     15
#define LCD_PAL115_I0_Msk                                     (0x01UL << LCD_PAL115_I0_Pos)
#define LCD_PAL115_R14_0_Pos                                  16
#define LCD_PAL115_R14_0_Msk                                  (0x1fUL << LCD_PAL115_R14_0_Pos)
#define LCD_PAL115_G14_0_Pos                                  21
#define LCD_PAL115_G14_0_Msk                                  (0x1fUL << LCD_PAL115_G14_0_Pos)
#define LCD_PAL115_B14_0_Pos                                  26
#define LCD_PAL115_B14_0_Msk                                  (0x1fUL << LCD_PAL115_B14_0_Pos)
#define LCD_PAL115_I1_Pos                                     31
#define LCD_PAL115_I1_Msk                                     (0x01UL << LCD_PAL115_I1_Pos)

// ---------------------------------------  LCD_PAL116  -------------------------------------------
#define LCD_PAL116_R04_0_Pos                                  0
#define LCD_PAL116_R04_0_Msk                                  (0x1fUL << LCD_PAL116_R04_0_Pos)
#define LCD_PAL116_G04_0_Pos                                  5
#define LCD_PAL116_G04_0_Msk                                  (0x1fUL << LCD_PAL116_G04_0_Pos)
#define LCD_PAL116_B04_0_Pos                                  10
#define LCD_PAL116_B04_0_Msk                                  (0x1fUL << LCD_PAL116_B04_0_Pos)
#define LCD_PAL116_I0_Pos                                     15
#define LCD_PAL116_I0_Msk                                     (0x01UL << LCD_PAL116_I0_Pos)
#define LCD_PAL116_R14_0_Pos                                  16
#define LCD_PAL116_R14_0_Msk                                  (0x1fUL << LCD_PAL116_R14_0_Pos)
#define LCD_PAL116_G14_0_Pos                                  21
#define LCD_PAL116_G14_0_Msk                                  (0x1fUL << LCD_PAL116_G14_0_Pos)
#define LCD_PAL116_B14_0_Pos                                  26
#define LCD_PAL116_B14_0_Msk                                  (0x1fUL << LCD_PAL116_B14_0_Pos)
#define LCD_PAL116_I1_Pos                                     31
#define LCD_PAL116_I1_Msk                                     (0x01UL << LCD_PAL116_I1_Pos)

// ---------------------------------------  LCD_PAL117  -------------------------------------------
#define LCD_PAL117_R04_0_Pos                                  0
#define LCD_PAL117_R04_0_Msk                                  (0x1fUL << LCD_PAL117_R04_0_Pos)
#define LCD_PAL117_G04_0_Pos                                  5
#define LCD_PAL117_G04_0_Msk                                  (0x1fUL << LCD_PAL117_G04_0_Pos)
#define LCD_PAL117_B04_0_Pos                                  10
#define LCD_PAL117_B04_0_Msk                                  (0x1fUL << LCD_PAL117_B04_0_Pos)
#define LCD_PAL117_I0_Pos                                     15
#define LCD_PAL117_I0_Msk                                     (0x01UL << LCD_PAL117_I0_Pos)
#define LCD_PAL117_R14_0_Pos                                  16
#define LCD_PAL117_R14_0_Msk                                  (0x1fUL << LCD_PAL117_R14_0_Pos)
#define LCD_PAL117_G14_0_Pos                                  21
#define LCD_PAL117_G14_0_Msk                                  (0x1fUL << LCD_PAL117_G14_0_Pos)
#define LCD_PAL117_B14_0_Pos                                  26
#define LCD_PAL117_B14_0_Msk                                  (0x1fUL << LCD_PAL117_B14_0_Pos)
#define LCD_PAL117_I1_Pos                                     31
#define LCD_PAL117_I1_Msk                                     (0x01UL << LCD_PAL117_I1_Pos)

// ---------------------------------------  LCD_PAL118  -------------------------------------------
#define LCD_PAL118_R04_0_Pos                                  0
#define LCD_PAL118_R04_0_Msk                                  (0x1fUL << LCD_PAL118_R04_0_Pos)
#define LCD_PAL118_G04_0_Pos                                  5
#define LCD_PAL118_G04_0_Msk                                  (0x1fUL << LCD_PAL118_G04_0_Pos)
#define LCD_PAL118_B04_0_Pos                                  10
#define LCD_PAL118_B04_0_Msk                                  (0x1fUL << LCD_PAL118_B04_0_Pos)
#define LCD_PAL118_I0_Pos                                     15
#define LCD_PAL118_I0_Msk                                     (0x01UL << LCD_PAL118_I0_Pos)
#define LCD_PAL118_R14_0_Pos                                  16
#define LCD_PAL118_R14_0_Msk                                  (0x1fUL << LCD_PAL118_R14_0_Pos)
#define LCD_PAL118_G14_0_Pos                                  21
#define LCD_PAL118_G14_0_Msk                                  (0x1fUL << LCD_PAL118_G14_0_Pos)
#define LCD_PAL118_B14_0_Pos                                  26
#define LCD_PAL118_B14_0_Msk                                  (0x1fUL << LCD_PAL118_B14_0_Pos)
#define LCD_PAL118_I1_Pos                                     31
#define LCD_PAL118_I1_Msk                                     (0x01UL << LCD_PAL118_I1_Pos)

// ---------------------------------------  LCD_PAL119  -------------------------------------------
#define LCD_PAL119_R04_0_Pos                                  0
#define LCD_PAL119_R04_0_Msk                                  (0x1fUL << LCD_PAL119_R04_0_Pos)
#define LCD_PAL119_G04_0_Pos                                  5
#define LCD_PAL119_G04_0_Msk                                  (0x1fUL << LCD_PAL119_G04_0_Pos)
#define LCD_PAL119_B04_0_Pos                                  10
#define LCD_PAL119_B04_0_Msk                                  (0x1fUL << LCD_PAL119_B04_0_Pos)
#define LCD_PAL119_I0_Pos                                     15
#define LCD_PAL119_I0_Msk                                     (0x01UL << LCD_PAL119_I0_Pos)
#define LCD_PAL119_R14_0_Pos                                  16
#define LCD_PAL119_R14_0_Msk                                  (0x1fUL << LCD_PAL119_R14_0_Pos)
#define LCD_PAL119_G14_0_Pos                                  21
#define LCD_PAL119_G14_0_Msk                                  (0x1fUL << LCD_PAL119_G14_0_Pos)
#define LCD_PAL119_B14_0_Pos                                  26
#define LCD_PAL119_B14_0_Msk                                  (0x1fUL << LCD_PAL119_B14_0_Pos)
#define LCD_PAL119_I1_Pos                                     31
#define LCD_PAL119_I1_Msk                                     (0x01UL << LCD_PAL119_I1_Pos)

// ---------------------------------------  LCD_PAL120  -------------------------------------------
#define LCD_PAL120_R04_0_Pos                                  0
#define LCD_PAL120_R04_0_Msk                                  (0x1fUL << LCD_PAL120_R04_0_Pos)
#define LCD_PAL120_G04_0_Pos                                  5
#define LCD_PAL120_G04_0_Msk                                  (0x1fUL << LCD_PAL120_G04_0_Pos)
#define LCD_PAL120_B04_0_Pos                                  10
#define LCD_PAL120_B04_0_Msk                                  (0x1fUL << LCD_PAL120_B04_0_Pos)
#define LCD_PAL120_I0_Pos                                     15
#define LCD_PAL120_I0_Msk                                     (0x01UL << LCD_PAL120_I0_Pos)
#define LCD_PAL120_R14_0_Pos                                  16
#define LCD_PAL120_R14_0_Msk                                  (0x1fUL << LCD_PAL120_R14_0_Pos)
#define LCD_PAL120_G14_0_Pos                                  21
#define LCD_PAL120_G14_0_Msk                                  (0x1fUL << LCD_PAL120_G14_0_Pos)
#define LCD_PAL120_B14_0_Pos                                  26
#define LCD_PAL120_B14_0_Msk                                  (0x1fUL << LCD_PAL120_B14_0_Pos)
#define LCD_PAL120_I1_Pos                                     31
#define LCD_PAL120_I1_Msk                                     (0x01UL << LCD_PAL120_I1_Pos)

// ---------------------------------------  LCD_PAL121  -------------------------------------------
#define LCD_PAL121_R04_0_Pos                                  0
#define LCD_PAL121_R04_0_Msk                                  (0x1fUL << LCD_PAL121_R04_0_Pos)
#define LCD_PAL121_G04_0_Pos                                  5
#define LCD_PAL121_G04_0_Msk                                  (0x1fUL << LCD_PAL121_G04_0_Pos)
#define LCD_PAL121_B04_0_Pos                                  10
#define LCD_PAL121_B04_0_Msk                                  (0x1fUL << LCD_PAL121_B04_0_Pos)
#define LCD_PAL121_I0_Pos                                     15
#define LCD_PAL121_I0_Msk                                     (0x01UL << LCD_PAL121_I0_Pos)
#define LCD_PAL121_R14_0_Pos                                  16
#define LCD_PAL121_R14_0_Msk                                  (0x1fUL << LCD_PAL121_R14_0_Pos)
#define LCD_PAL121_G14_0_Pos                                  21
#define LCD_PAL121_G14_0_Msk                                  (0x1fUL << LCD_PAL121_G14_0_Pos)
#define LCD_PAL121_B14_0_Pos                                  26
#define LCD_PAL121_B14_0_Msk                                  (0x1fUL << LCD_PAL121_B14_0_Pos)
#define LCD_PAL121_I1_Pos                                     31
#define LCD_PAL121_I1_Msk                                     (0x01UL << LCD_PAL121_I1_Pos)

// ---------------------------------------  LCD_PAL122  -------------------------------------------
#define LCD_PAL122_R04_0_Pos                                  0
#define LCD_PAL122_R04_0_Msk                                  (0x1fUL << LCD_PAL122_R04_0_Pos)
#define LCD_PAL122_G04_0_Pos                                  5
#define LCD_PAL122_G04_0_Msk                                  (0x1fUL << LCD_PAL122_G04_0_Pos)
#define LCD_PAL122_B04_0_Pos                                  10
#define LCD_PAL122_B04_0_Msk                                  (0x1fUL << LCD_PAL122_B04_0_Pos)
#define LCD_PAL122_I0_Pos                                     15
#define LCD_PAL122_I0_Msk                                     (0x01UL << LCD_PAL122_I0_Pos)
#define LCD_PAL122_R14_0_Pos                                  16
#define LCD_PAL122_R14_0_Msk                                  (0x1fUL << LCD_PAL122_R14_0_Pos)
#define LCD_PAL122_G14_0_Pos                                  21
#define LCD_PAL122_G14_0_Msk                                  (0x1fUL << LCD_PAL122_G14_0_Pos)
#define LCD_PAL122_B14_0_Pos                                  26
#define LCD_PAL122_B14_0_Msk                                  (0x1fUL << LCD_PAL122_B14_0_Pos)
#define LCD_PAL122_I1_Pos                                     31
#define LCD_PAL122_I1_Msk                                     (0x01UL << LCD_PAL122_I1_Pos)

// ---------------------------------------  LCD_PAL123  -------------------------------------------
#define LCD_PAL123_R04_0_Pos                                  0
#define LCD_PAL123_R04_0_Msk                                  (0x1fUL << LCD_PAL123_R04_0_Pos)
#define LCD_PAL123_G04_0_Pos                                  5
#define LCD_PAL123_G04_0_Msk                                  (0x1fUL << LCD_PAL123_G04_0_Pos)
#define LCD_PAL123_B04_0_Pos                                  10
#define LCD_PAL123_B04_0_Msk                                  (0x1fUL << LCD_PAL123_B04_0_Pos)
#define LCD_PAL123_I0_Pos                                     15
#define LCD_PAL123_I0_Msk                                     (0x01UL << LCD_PAL123_I0_Pos)
#define LCD_PAL123_R14_0_Pos                                  16
#define LCD_PAL123_R14_0_Msk                                  (0x1fUL << LCD_PAL123_R14_0_Pos)
#define LCD_PAL123_G14_0_Pos                                  21
#define LCD_PAL123_G14_0_Msk                                  (0x1fUL << LCD_PAL123_G14_0_Pos)
#define LCD_PAL123_B14_0_Pos                                  26
#define LCD_PAL123_B14_0_Msk                                  (0x1fUL << LCD_PAL123_B14_0_Pos)
#define LCD_PAL123_I1_Pos                                     31
#define LCD_PAL123_I1_Msk                                     (0x01UL << LCD_PAL123_I1_Pos)

// ---------------------------------------  LCD_PAL124  -------------------------------------------
#define LCD_PAL124_R04_0_Pos                                  0
#define LCD_PAL124_R04_0_Msk                                  (0x1fUL << LCD_PAL124_R04_0_Pos)
#define LCD_PAL124_G04_0_Pos                                  5
#define LCD_PAL124_G04_0_Msk                                  (0x1fUL << LCD_PAL124_G04_0_Pos)
#define LCD_PAL124_B04_0_Pos                                  10
#define LCD_PAL124_B04_0_Msk                                  (0x1fUL << LCD_PAL124_B04_0_Pos)
#define LCD_PAL124_I0_Pos                                     15
#define LCD_PAL124_I0_Msk                                     (0x01UL << LCD_PAL124_I0_Pos)
#define LCD_PAL124_R14_0_Pos                                  16
#define LCD_PAL124_R14_0_Msk                                  (0x1fUL << LCD_PAL124_R14_0_Pos)
#define LCD_PAL124_G14_0_Pos                                  21
#define LCD_PAL124_G14_0_Msk                                  (0x1fUL << LCD_PAL124_G14_0_Pos)
#define LCD_PAL124_B14_0_Pos                                  26
#define LCD_PAL124_B14_0_Msk                                  (0x1fUL << LCD_PAL124_B14_0_Pos)
#define LCD_PAL124_I1_Pos                                     31
#define LCD_PAL124_I1_Msk                                     (0x01UL << LCD_PAL124_I1_Pos)

// ---------------------------------------  LCD_PAL125  -------------------------------------------
#define LCD_PAL125_R04_0_Pos                                  0
#define LCD_PAL125_R04_0_Msk                                  (0x1fUL << LCD_PAL125_R04_0_Pos)
#define LCD_PAL125_G04_0_Pos                                  5
#define LCD_PAL125_G04_0_Msk                                  (0x1fUL << LCD_PAL125_G04_0_Pos)
#define LCD_PAL125_B04_0_Pos                                  10
#define LCD_PAL125_B04_0_Msk                                  (0x1fUL << LCD_PAL125_B04_0_Pos)
#define LCD_PAL125_I0_Pos                                     15
#define LCD_PAL125_I0_Msk                                     (0x01UL << LCD_PAL125_I0_Pos)
#define LCD_PAL125_R14_0_Pos                                  16
#define LCD_PAL125_R14_0_Msk                                  (0x1fUL << LCD_PAL125_R14_0_Pos)
#define LCD_PAL125_G14_0_Pos                                  21
#define LCD_PAL125_G14_0_Msk                                  (0x1fUL << LCD_PAL125_G14_0_Pos)
#define LCD_PAL125_B14_0_Pos                                  26
#define LCD_PAL125_B14_0_Msk                                  (0x1fUL << LCD_PAL125_B14_0_Pos)
#define LCD_PAL125_I1_Pos                                     31
#define LCD_PAL125_I1_Msk                                     (0x01UL << LCD_PAL125_I1_Pos)

// ---------------------------------------  LCD_PAL126  -------------------------------------------
#define LCD_PAL126_R04_0_Pos                                  0
#define LCD_PAL126_R04_0_Msk                                  (0x1fUL << LCD_PAL126_R04_0_Pos)
#define LCD_PAL126_G04_0_Pos                                  5
#define LCD_PAL126_G04_0_Msk                                  (0x1fUL << LCD_PAL126_G04_0_Pos)
#define LCD_PAL126_B04_0_Pos                                  10
#define LCD_PAL126_B04_0_Msk                                  (0x1fUL << LCD_PAL126_B04_0_Pos)
#define LCD_PAL126_I0_Pos                                     15
#define LCD_PAL126_I0_Msk                                     (0x01UL << LCD_PAL126_I0_Pos)
#define LCD_PAL126_R14_0_Pos                                  16
#define LCD_PAL126_R14_0_Msk                                  (0x1fUL << LCD_PAL126_R14_0_Pos)
#define LCD_PAL126_G14_0_Pos                                  21
#define LCD_PAL126_G14_0_Msk                                  (0x1fUL << LCD_PAL126_G14_0_Pos)
#define LCD_PAL126_B14_0_Pos                                  26
#define LCD_PAL126_B14_0_Msk                                  (0x1fUL << LCD_PAL126_B14_0_Pos)
#define LCD_PAL126_I1_Pos                                     31
#define LCD_PAL126_I1_Msk                                     (0x01UL << LCD_PAL126_I1_Pos)

// ---------------------------------------  LCD_PAL127  -------------------------------------------
#define LCD_PAL127_R04_0_Pos                                  0
#define LCD_PAL127_R04_0_Msk                                  (0x1fUL << LCD_PAL127_R04_0_Pos)
#define LCD_PAL127_G04_0_Pos                                  5
#define LCD_PAL127_G04_0_Msk                                  (0x1fUL << LCD_PAL127_G04_0_Pos)
#define LCD_PAL127_B04_0_Pos                                  10
#define LCD_PAL127_B04_0_Msk                                  (0x1fUL << LCD_PAL127_B04_0_Pos)
#define LCD_PAL127_I0_Pos                                     15
#define LCD_PAL127_I0_Msk                                     (0x01UL << LCD_PAL127_I0_Pos)
#define LCD_PAL127_R14_0_Pos                                  16
#define LCD_PAL127_R14_0_Msk                                  (0x1fUL << LCD_PAL127_R14_0_Pos)
#define LCD_PAL127_G14_0_Pos                                  21
#define LCD_PAL127_G14_0_Msk                                  (0x1fUL << LCD_PAL127_G14_0_Pos)
#define LCD_PAL127_B14_0_Pos                                  26
#define LCD_PAL127_B14_0_Msk                                  (0x1fUL << LCD_PAL127_B14_0_Pos)
#define LCD_PAL127_I1_Pos                                     31
#define LCD_PAL127_I1_Msk                                     (0x01UL << LCD_PAL127_I1_Pos)

// ---------------------------------------  LCD_PAL128  -------------------------------------------
#define LCD_PAL128_R04_0_Pos                                  0
#define LCD_PAL128_R04_0_Msk                                  (0x1fUL << LCD_PAL128_R04_0_Pos)
#define LCD_PAL128_G04_0_Pos                                  5
#define LCD_PAL128_G04_0_Msk                                  (0x1fUL << LCD_PAL128_G04_0_Pos)
#define LCD_PAL128_B04_0_Pos                                  10
#define LCD_PAL128_B04_0_Msk                                  (0x1fUL << LCD_PAL128_B04_0_Pos)
#define LCD_PAL128_I0_Pos                                     15
#define LCD_PAL128_I0_Msk                                     (0x01UL << LCD_PAL128_I0_Pos)
#define LCD_PAL128_R14_0_Pos                                  16
#define LCD_PAL128_R14_0_Msk                                  (0x1fUL << LCD_PAL128_R14_0_Pos)
#define LCD_PAL128_G14_0_Pos                                  21
#define LCD_PAL128_G14_0_Msk                                  (0x1fUL << LCD_PAL128_G14_0_Pos)
#define LCD_PAL128_B14_0_Pos                                  26
#define LCD_PAL128_B14_0_Msk                                  (0x1fUL << LCD_PAL128_B14_0_Pos)
#define LCD_PAL128_I1_Pos                                     31
#define LCD_PAL128_I1_Msk                                     (0x01UL << LCD_PAL128_I1_Pos)

// ---------------------------------------  LCD_PAL129  -------------------------------------------
#define LCD_PAL129_R04_0_Pos                                  0
#define LCD_PAL129_R04_0_Msk                                  (0x1fUL << LCD_PAL129_R04_0_Pos)
#define LCD_PAL129_G04_0_Pos                                  5
#define LCD_PAL129_G04_0_Msk                                  (0x1fUL << LCD_PAL129_G04_0_Pos)
#define LCD_PAL129_B04_0_Pos                                  10
#define LCD_PAL129_B04_0_Msk                                  (0x1fUL << LCD_PAL129_B04_0_Pos)
#define LCD_PAL129_I0_Pos                                     15
#define LCD_PAL129_I0_Msk                                     (0x01UL << LCD_PAL129_I0_Pos)
#define LCD_PAL129_R14_0_Pos                                  16
#define LCD_PAL129_R14_0_Msk                                  (0x1fUL << LCD_PAL129_R14_0_Pos)
#define LCD_PAL129_G14_0_Pos                                  21
#define LCD_PAL129_G14_0_Msk                                  (0x1fUL << LCD_PAL129_G14_0_Pos)
#define LCD_PAL129_B14_0_Pos                                  26
#define LCD_PAL129_B14_0_Msk                                  (0x1fUL << LCD_PAL129_B14_0_Pos)
#define LCD_PAL129_I1_Pos                                     31
#define LCD_PAL129_I1_Msk                                     (0x01UL << LCD_PAL129_I1_Pos)

// ---------------------------------------  LCD_PAL130  -------------------------------------------
#define LCD_PAL130_R04_0_Pos                                  0
#define LCD_PAL130_R04_0_Msk                                  (0x1fUL << LCD_PAL130_R04_0_Pos)
#define LCD_PAL130_G04_0_Pos                                  5
#define LCD_PAL130_G04_0_Msk                                  (0x1fUL << LCD_PAL130_G04_0_Pos)
#define LCD_PAL130_B04_0_Pos                                  10
#define LCD_PAL130_B04_0_Msk                                  (0x1fUL << LCD_PAL130_B04_0_Pos)
#define LCD_PAL130_I0_Pos                                     15
#define LCD_PAL130_I0_Msk                                     (0x01UL << LCD_PAL130_I0_Pos)
#define LCD_PAL130_R14_0_Pos                                  16
#define LCD_PAL130_R14_0_Msk                                  (0x1fUL << LCD_PAL130_R14_0_Pos)
#define LCD_PAL130_G14_0_Pos                                  21
#define LCD_PAL130_G14_0_Msk                                  (0x1fUL << LCD_PAL130_G14_0_Pos)
#define LCD_PAL130_B14_0_Pos                                  26
#define LCD_PAL130_B14_0_Msk                                  (0x1fUL << LCD_PAL130_B14_0_Pos)
#define LCD_PAL130_I1_Pos                                     31
#define LCD_PAL130_I1_Msk                                     (0x01UL << LCD_PAL130_I1_Pos)

// ---------------------------------------  LCD_PAL131  -------------------------------------------
#define LCD_PAL131_R04_0_Pos                                  0
#define LCD_PAL131_R04_0_Msk                                  (0x1fUL << LCD_PAL131_R04_0_Pos)
#define LCD_PAL131_G04_0_Pos                                  5
#define LCD_PAL131_G04_0_Msk                                  (0x1fUL << LCD_PAL131_G04_0_Pos)
#define LCD_PAL131_B04_0_Pos                                  10
#define LCD_PAL131_B04_0_Msk                                  (0x1fUL << LCD_PAL131_B04_0_Pos)
#define LCD_PAL131_I0_Pos                                     15
#define LCD_PAL131_I0_Msk                                     (0x01UL << LCD_PAL131_I0_Pos)
#define LCD_PAL131_R14_0_Pos                                  16
#define LCD_PAL131_R14_0_Msk                                  (0x1fUL << LCD_PAL131_R14_0_Pos)
#define LCD_PAL131_G14_0_Pos                                  21
#define LCD_PAL131_G14_0_Msk                                  (0x1fUL << LCD_PAL131_G14_0_Pos)
#define LCD_PAL131_B14_0_Pos                                  26
#define LCD_PAL131_B14_0_Msk                                  (0x1fUL << LCD_PAL131_B14_0_Pos)
#define LCD_PAL131_I1_Pos                                     31
#define LCD_PAL131_I1_Msk                                     (0x01UL << LCD_PAL131_I1_Pos)

// ---------------------------------------  LCD_PAL132  -------------------------------------------
#define LCD_PAL132_R04_0_Pos                                  0
#define LCD_PAL132_R04_0_Msk                                  (0x1fUL << LCD_PAL132_R04_0_Pos)
#define LCD_PAL132_G04_0_Pos                                  5
#define LCD_PAL132_G04_0_Msk                                  (0x1fUL << LCD_PAL132_G04_0_Pos)
#define LCD_PAL132_B04_0_Pos                                  10
#define LCD_PAL132_B04_0_Msk                                  (0x1fUL << LCD_PAL132_B04_0_Pos)
#define LCD_PAL132_I0_Pos                                     15
#define LCD_PAL132_I0_Msk                                     (0x01UL << LCD_PAL132_I0_Pos)
#define LCD_PAL132_R14_0_Pos                                  16
#define LCD_PAL132_R14_0_Msk                                  (0x1fUL << LCD_PAL132_R14_0_Pos)
#define LCD_PAL132_G14_0_Pos                                  21
#define LCD_PAL132_G14_0_Msk                                  (0x1fUL << LCD_PAL132_G14_0_Pos)
#define LCD_PAL132_B14_0_Pos                                  26
#define LCD_PAL132_B14_0_Msk                                  (0x1fUL << LCD_PAL132_B14_0_Pos)
#define LCD_PAL132_I1_Pos                                     31
#define LCD_PAL132_I1_Msk                                     (0x01UL << LCD_PAL132_I1_Pos)

// ---------------------------------------  LCD_PAL133  -------------------------------------------
#define LCD_PAL133_R04_0_Pos                                  0
#define LCD_PAL133_R04_0_Msk                                  (0x1fUL << LCD_PAL133_R04_0_Pos)
#define LCD_PAL133_G04_0_Pos                                  5
#define LCD_PAL133_G04_0_Msk                                  (0x1fUL << LCD_PAL133_G04_0_Pos)
#define LCD_PAL133_B04_0_Pos                                  10
#define LCD_PAL133_B04_0_Msk                                  (0x1fUL << LCD_PAL133_B04_0_Pos)
#define LCD_PAL133_I0_Pos                                     15
#define LCD_PAL133_I0_Msk                                     (0x01UL << LCD_PAL133_I0_Pos)
#define LCD_PAL133_R14_0_Pos                                  16
#define LCD_PAL133_R14_0_Msk                                  (0x1fUL << LCD_PAL133_R14_0_Pos)
#define LCD_PAL133_G14_0_Pos                                  21
#define LCD_PAL133_G14_0_Msk                                  (0x1fUL << LCD_PAL133_G14_0_Pos)
#define LCD_PAL133_B14_0_Pos                                  26
#define LCD_PAL133_B14_0_Msk                                  (0x1fUL << LCD_PAL133_B14_0_Pos)
#define LCD_PAL133_I1_Pos                                     31
#define LCD_PAL133_I1_Msk                                     (0x01UL << LCD_PAL133_I1_Pos)

// ---------------------------------------  LCD_PAL134  -------------------------------------------
#define LCD_PAL134_R04_0_Pos                                  0
#define LCD_PAL134_R04_0_Msk                                  (0x1fUL << LCD_PAL134_R04_0_Pos)
#define LCD_PAL134_G04_0_Pos                                  5
#define LCD_PAL134_G04_0_Msk                                  (0x1fUL << LCD_PAL134_G04_0_Pos)
#define LCD_PAL134_B04_0_Pos                                  10
#define LCD_PAL134_B04_0_Msk                                  (0x1fUL << LCD_PAL134_B04_0_Pos)
#define LCD_PAL134_I0_Pos                                     15
#define LCD_PAL134_I0_Msk                                     (0x01UL << LCD_PAL134_I0_Pos)
#define LCD_PAL134_R14_0_Pos                                  16
#define LCD_PAL134_R14_0_Msk                                  (0x1fUL << LCD_PAL134_R14_0_Pos)
#define LCD_PAL134_G14_0_Pos                                  21
#define LCD_PAL134_G14_0_Msk                                  (0x1fUL << LCD_PAL134_G14_0_Pos)
#define LCD_PAL134_B14_0_Pos                                  26
#define LCD_PAL134_B14_0_Msk                                  (0x1fUL << LCD_PAL134_B14_0_Pos)
#define LCD_PAL134_I1_Pos                                     31
#define LCD_PAL134_I1_Msk                                     (0x01UL << LCD_PAL134_I1_Pos)

// ---------------------------------------  LCD_PAL135  -------------------------------------------
#define LCD_PAL135_R04_0_Pos                                  0
#define LCD_PAL135_R04_0_Msk                                  (0x1fUL << LCD_PAL135_R04_0_Pos)
#define LCD_PAL135_G04_0_Pos                                  5
#define LCD_PAL135_G04_0_Msk                                  (0x1fUL << LCD_PAL135_G04_0_Pos)
#define LCD_PAL135_B04_0_Pos                                  10
#define LCD_PAL135_B04_0_Msk                                  (0x1fUL << LCD_PAL135_B04_0_Pos)
#define LCD_PAL135_I0_Pos                                     15
#define LCD_PAL135_I0_Msk                                     (0x01UL << LCD_PAL135_I0_Pos)
#define LCD_PAL135_R14_0_Pos                                  16
#define LCD_PAL135_R14_0_Msk                                  (0x1fUL << LCD_PAL135_R14_0_Pos)
#define LCD_PAL135_G14_0_Pos                                  21
#define LCD_PAL135_G14_0_Msk                                  (0x1fUL << LCD_PAL135_G14_0_Pos)
#define LCD_PAL135_B14_0_Pos                                  26
#define LCD_PAL135_B14_0_Msk                                  (0x1fUL << LCD_PAL135_B14_0_Pos)
#define LCD_PAL135_I1_Pos                                     31
#define LCD_PAL135_I1_Msk                                     (0x01UL << LCD_PAL135_I1_Pos)

// ---------------------------------------  LCD_PAL136  -------------------------------------------
#define LCD_PAL136_R04_0_Pos                                  0
#define LCD_PAL136_R04_0_Msk                                  (0x1fUL << LCD_PAL136_R04_0_Pos)
#define LCD_PAL136_G04_0_Pos                                  5
#define LCD_PAL136_G04_0_Msk                                  (0x1fUL << LCD_PAL136_G04_0_Pos)
#define LCD_PAL136_B04_0_Pos                                  10
#define LCD_PAL136_B04_0_Msk                                  (0x1fUL << LCD_PAL136_B04_0_Pos)
#define LCD_PAL136_I0_Pos                                     15
#define LCD_PAL136_I0_Msk                                     (0x01UL << LCD_PAL136_I0_Pos)
#define LCD_PAL136_R14_0_Pos                                  16
#define LCD_PAL136_R14_0_Msk                                  (0x1fUL << LCD_PAL136_R14_0_Pos)
#define LCD_PAL136_G14_0_Pos                                  21
#define LCD_PAL136_G14_0_Msk                                  (0x1fUL << LCD_PAL136_G14_0_Pos)
#define LCD_PAL136_B14_0_Pos                                  26
#define LCD_PAL136_B14_0_Msk                                  (0x1fUL << LCD_PAL136_B14_0_Pos)
#define LCD_PAL136_I1_Pos                                     31
#define LCD_PAL136_I1_Msk                                     (0x01UL << LCD_PAL136_I1_Pos)

// ---------------------------------------  LCD_PAL137  -------------------------------------------
#define LCD_PAL137_R04_0_Pos                                  0
#define LCD_PAL137_R04_0_Msk                                  (0x1fUL << LCD_PAL137_R04_0_Pos)
#define LCD_PAL137_G04_0_Pos                                  5
#define LCD_PAL137_G04_0_Msk                                  (0x1fUL << LCD_PAL137_G04_0_Pos)
#define LCD_PAL137_B04_0_Pos                                  10
#define LCD_PAL137_B04_0_Msk                                  (0x1fUL << LCD_PAL137_B04_0_Pos)
#define LCD_PAL137_I0_Pos                                     15
#define LCD_PAL137_I0_Msk                                     (0x01UL << LCD_PAL137_I0_Pos)
#define LCD_PAL137_R14_0_Pos                                  16
#define LCD_PAL137_R14_0_Msk                                  (0x1fUL << LCD_PAL137_R14_0_Pos)
#define LCD_PAL137_G14_0_Pos                                  21
#define LCD_PAL137_G14_0_Msk                                  (0x1fUL << LCD_PAL137_G14_0_Pos)
#define LCD_PAL137_B14_0_Pos                                  26
#define LCD_PAL137_B14_0_Msk                                  (0x1fUL << LCD_PAL137_B14_0_Pos)
#define LCD_PAL137_I1_Pos                                     31
#define LCD_PAL137_I1_Msk                                     (0x01UL << LCD_PAL137_I1_Pos)

// ---------------------------------------  LCD_PAL138  -------------------------------------------
#define LCD_PAL138_R04_0_Pos                                  0
#define LCD_PAL138_R04_0_Msk                                  (0x1fUL << LCD_PAL138_R04_0_Pos)
#define LCD_PAL138_G04_0_Pos                                  5
#define LCD_PAL138_G04_0_Msk                                  (0x1fUL << LCD_PAL138_G04_0_Pos)
#define LCD_PAL138_B04_0_Pos                                  10
#define LCD_PAL138_B04_0_Msk                                  (0x1fUL << LCD_PAL138_B04_0_Pos)
#define LCD_PAL138_I0_Pos                                     15
#define LCD_PAL138_I0_Msk                                     (0x01UL << LCD_PAL138_I0_Pos)
#define LCD_PAL138_R14_0_Pos                                  16
#define LCD_PAL138_R14_0_Msk                                  (0x1fUL << LCD_PAL138_R14_0_Pos)
#define LCD_PAL138_G14_0_Pos                                  21
#define LCD_PAL138_G14_0_Msk                                  (0x1fUL << LCD_PAL138_G14_0_Pos)
#define LCD_PAL138_B14_0_Pos                                  26
#define LCD_PAL138_B14_0_Msk                                  (0x1fUL << LCD_PAL138_B14_0_Pos)
#define LCD_PAL138_I1_Pos                                     31
#define LCD_PAL138_I1_Msk                                     (0x01UL << LCD_PAL138_I1_Pos)

// ---------------------------------------  LCD_PAL139  -------------------------------------------
#define LCD_PAL139_R04_0_Pos                                  0
#define LCD_PAL139_R04_0_Msk                                  (0x1fUL << LCD_PAL139_R04_0_Pos)
#define LCD_PAL139_G04_0_Pos                                  5
#define LCD_PAL139_G04_0_Msk                                  (0x1fUL << LCD_PAL139_G04_0_Pos)
#define LCD_PAL139_B04_0_Pos                                  10
#define LCD_PAL139_B04_0_Msk                                  (0x1fUL << LCD_PAL139_B04_0_Pos)
#define LCD_PAL139_I0_Pos                                     15
#define LCD_PAL139_I0_Msk                                     (0x01UL << LCD_PAL139_I0_Pos)
#define LCD_PAL139_R14_0_Pos                                  16
#define LCD_PAL139_R14_0_Msk                                  (0x1fUL << LCD_PAL139_R14_0_Pos)
#define LCD_PAL139_G14_0_Pos                                  21
#define LCD_PAL139_G14_0_Msk                                  (0x1fUL << LCD_PAL139_G14_0_Pos)
#define LCD_PAL139_B14_0_Pos                                  26
#define LCD_PAL139_B14_0_Msk                                  (0x1fUL << LCD_PAL139_B14_0_Pos)
#define LCD_PAL139_I1_Pos                                     31
#define LCD_PAL139_I1_Msk                                     (0x01UL << LCD_PAL139_I1_Pos)

// ---------------------------------------  LCD_PAL140  -------------------------------------------
#define LCD_PAL140_R04_0_Pos                                  0
#define LCD_PAL140_R04_0_Msk                                  (0x1fUL << LCD_PAL140_R04_0_Pos)
#define LCD_PAL140_G04_0_Pos                                  5
#define LCD_PAL140_G04_0_Msk                                  (0x1fUL << LCD_PAL140_G04_0_Pos)
#define LCD_PAL140_B04_0_Pos                                  10
#define LCD_PAL140_B04_0_Msk                                  (0x1fUL << LCD_PAL140_B04_0_Pos)
#define LCD_PAL140_I0_Pos                                     15
#define LCD_PAL140_I0_Msk                                     (0x01UL << LCD_PAL140_I0_Pos)
#define LCD_PAL140_R14_0_Pos                                  16
#define LCD_PAL140_R14_0_Msk                                  (0x1fUL << LCD_PAL140_R14_0_Pos)
#define LCD_PAL140_G14_0_Pos                                  21
#define LCD_PAL140_G14_0_Msk                                  (0x1fUL << LCD_PAL140_G14_0_Pos)
#define LCD_PAL140_B14_0_Pos                                  26
#define LCD_PAL140_B14_0_Msk                                  (0x1fUL << LCD_PAL140_B14_0_Pos)
#define LCD_PAL140_I1_Pos                                     31
#define LCD_PAL140_I1_Msk                                     (0x01UL << LCD_PAL140_I1_Pos)

// ---------------------------------------  LCD_PAL141  -------------------------------------------
#define LCD_PAL141_R04_0_Pos                                  0
#define LCD_PAL141_R04_0_Msk                                  (0x1fUL << LCD_PAL141_R04_0_Pos)
#define LCD_PAL141_G04_0_Pos                                  5
#define LCD_PAL141_G04_0_Msk                                  (0x1fUL << LCD_PAL141_G04_0_Pos)
#define LCD_PAL141_B04_0_Pos                                  10
#define LCD_PAL141_B04_0_Msk                                  (0x1fUL << LCD_PAL141_B04_0_Pos)
#define LCD_PAL141_I0_Pos                                     15
#define LCD_PAL141_I0_Msk                                     (0x01UL << LCD_PAL141_I0_Pos)
#define LCD_PAL141_R14_0_Pos                                  16
#define LCD_PAL141_R14_0_Msk                                  (0x1fUL << LCD_PAL141_R14_0_Pos)
#define LCD_PAL141_G14_0_Pos                                  21
#define LCD_PAL141_G14_0_Msk                                  (0x1fUL << LCD_PAL141_G14_0_Pos)
#define LCD_PAL141_B14_0_Pos                                  26
#define LCD_PAL141_B14_0_Msk                                  (0x1fUL << LCD_PAL141_B14_0_Pos)
#define LCD_PAL141_I1_Pos                                     31
#define LCD_PAL141_I1_Msk                                     (0x01UL << LCD_PAL141_I1_Pos)

// ---------------------------------------  LCD_PAL142  -------------------------------------------
#define LCD_PAL142_R04_0_Pos                                  0
#define LCD_PAL142_R04_0_Msk                                  (0x1fUL << LCD_PAL142_R04_0_Pos)
#define LCD_PAL142_G04_0_Pos                                  5
#define LCD_PAL142_G04_0_Msk                                  (0x1fUL << LCD_PAL142_G04_0_Pos)
#define LCD_PAL142_B04_0_Pos                                  10
#define LCD_PAL142_B04_0_Msk                                  (0x1fUL << LCD_PAL142_B04_0_Pos)
#define LCD_PAL142_I0_Pos                                     15
#define LCD_PAL142_I0_Msk                                     (0x01UL << LCD_PAL142_I0_Pos)
#define LCD_PAL142_R14_0_Pos                                  16
#define LCD_PAL142_R14_0_Msk                                  (0x1fUL << LCD_PAL142_R14_0_Pos)
#define LCD_PAL142_G14_0_Pos                                  21
#define LCD_PAL142_G14_0_Msk                                  (0x1fUL << LCD_PAL142_G14_0_Pos)
#define LCD_PAL142_B14_0_Pos                                  26
#define LCD_PAL142_B14_0_Msk                                  (0x1fUL << LCD_PAL142_B14_0_Pos)
#define LCD_PAL142_I1_Pos                                     31
#define LCD_PAL142_I1_Msk                                     (0x01UL << LCD_PAL142_I1_Pos)

// ---------------------------------------  LCD_PAL143  -------------------------------------------
#define LCD_PAL143_R04_0_Pos                                  0
#define LCD_PAL143_R04_0_Msk                                  (0x1fUL << LCD_PAL143_R04_0_Pos)
#define LCD_PAL143_G04_0_Pos                                  5
#define LCD_PAL143_G04_0_Msk                                  (0x1fUL << LCD_PAL143_G04_0_Pos)
#define LCD_PAL143_B04_0_Pos                                  10
#define LCD_PAL143_B04_0_Msk                                  (0x1fUL << LCD_PAL143_B04_0_Pos)
#define LCD_PAL143_I0_Pos                                     15
#define LCD_PAL143_I0_Msk                                     (0x01UL << LCD_PAL143_I0_Pos)
#define LCD_PAL143_R14_0_Pos                                  16
#define LCD_PAL143_R14_0_Msk                                  (0x1fUL << LCD_PAL143_R14_0_Pos)
#define LCD_PAL143_G14_0_Pos                                  21
#define LCD_PAL143_G14_0_Msk                                  (0x1fUL << LCD_PAL143_G14_0_Pos)
#define LCD_PAL143_B14_0_Pos                                  26
#define LCD_PAL143_B14_0_Msk                                  (0x1fUL << LCD_PAL143_B14_0_Pos)
#define LCD_PAL143_I1_Pos                                     31
#define LCD_PAL143_I1_Msk                                     (0x01UL << LCD_PAL143_I1_Pos)

// ---------------------------------------  LCD_PAL144  -------------------------------------------
#define LCD_PAL144_R04_0_Pos                                  0
#define LCD_PAL144_R04_0_Msk                                  (0x1fUL << LCD_PAL144_R04_0_Pos)
#define LCD_PAL144_G04_0_Pos                                  5
#define LCD_PAL144_G04_0_Msk                                  (0x1fUL << LCD_PAL144_G04_0_Pos)
#define LCD_PAL144_B04_0_Pos                                  10
#define LCD_PAL144_B04_0_Msk                                  (0x1fUL << LCD_PAL144_B04_0_Pos)
#define LCD_PAL144_I0_Pos                                     15
#define LCD_PAL144_I0_Msk                                     (0x01UL << LCD_PAL144_I0_Pos)
#define LCD_PAL144_R14_0_Pos                                  16
#define LCD_PAL144_R14_0_Msk                                  (0x1fUL << LCD_PAL144_R14_0_Pos)
#define LCD_PAL144_G14_0_Pos                                  21
#define LCD_PAL144_G14_0_Msk                                  (0x1fUL << LCD_PAL144_G14_0_Pos)
#define LCD_PAL144_B14_0_Pos                                  26
#define LCD_PAL144_B14_0_Msk                                  (0x1fUL << LCD_PAL144_B14_0_Pos)
#define LCD_PAL144_I1_Pos                                     31
#define LCD_PAL144_I1_Msk                                     (0x01UL << LCD_PAL144_I1_Pos)

// ---------------------------------------  LCD_PAL145  -------------------------------------------
#define LCD_PAL145_R04_0_Pos                                  0
#define LCD_PAL145_R04_0_Msk                                  (0x1fUL << LCD_PAL145_R04_0_Pos)
#define LCD_PAL145_G04_0_Pos                                  5
#define LCD_PAL145_G04_0_Msk                                  (0x1fUL << LCD_PAL145_G04_0_Pos)
#define LCD_PAL145_B04_0_Pos                                  10
#define LCD_PAL145_B04_0_Msk                                  (0x1fUL << LCD_PAL145_B04_0_Pos)
#define LCD_PAL145_I0_Pos                                     15
#define LCD_PAL145_I0_Msk                                     (0x01UL << LCD_PAL145_I0_Pos)
#define LCD_PAL145_R14_0_Pos                                  16
#define LCD_PAL145_R14_0_Msk                                  (0x1fUL << LCD_PAL145_R14_0_Pos)
#define LCD_PAL145_G14_0_Pos                                  21
#define LCD_PAL145_G14_0_Msk                                  (0x1fUL << LCD_PAL145_G14_0_Pos)
#define LCD_PAL145_B14_0_Pos                                  26
#define LCD_PAL145_B14_0_Msk                                  (0x1fUL << LCD_PAL145_B14_0_Pos)
#define LCD_PAL145_I1_Pos                                     31
#define LCD_PAL145_I1_Msk                                     (0x01UL << LCD_PAL145_I1_Pos)

// ---------------------------------------  LCD_PAL146  -------------------------------------------
#define LCD_PAL146_R04_0_Pos                                  0
#define LCD_PAL146_R04_0_Msk                                  (0x1fUL << LCD_PAL146_R04_0_Pos)
#define LCD_PAL146_G04_0_Pos                                  5
#define LCD_PAL146_G04_0_Msk                                  (0x1fUL << LCD_PAL146_G04_0_Pos)
#define LCD_PAL146_B04_0_Pos                                  10
#define LCD_PAL146_B04_0_Msk                                  (0x1fUL << LCD_PAL146_B04_0_Pos)
#define LCD_PAL146_I0_Pos                                     15
#define LCD_PAL146_I0_Msk                                     (0x01UL << LCD_PAL146_I0_Pos)
#define LCD_PAL146_R14_0_Pos                                  16
#define LCD_PAL146_R14_0_Msk                                  (0x1fUL << LCD_PAL146_R14_0_Pos)
#define LCD_PAL146_G14_0_Pos                                  21
#define LCD_PAL146_G14_0_Msk                                  (0x1fUL << LCD_PAL146_G14_0_Pos)
#define LCD_PAL146_B14_0_Pos                                  26
#define LCD_PAL146_B14_0_Msk                                  (0x1fUL << LCD_PAL146_B14_0_Pos)
#define LCD_PAL146_I1_Pos                                     31
#define LCD_PAL146_I1_Msk                                     (0x01UL << LCD_PAL146_I1_Pos)

// ---------------------------------------  LCD_PAL147  -------------------------------------------
#define LCD_PAL147_R04_0_Pos                                  0
#define LCD_PAL147_R04_0_Msk                                  (0x1fUL << LCD_PAL147_R04_0_Pos)
#define LCD_PAL147_G04_0_Pos                                  5
#define LCD_PAL147_G04_0_Msk                                  (0x1fUL << LCD_PAL147_G04_0_Pos)
#define LCD_PAL147_B04_0_Pos                                  10
#define LCD_PAL147_B04_0_Msk                                  (0x1fUL << LCD_PAL147_B04_0_Pos)
#define LCD_PAL147_I0_Pos                                     15
#define LCD_PAL147_I0_Msk                                     (0x01UL << LCD_PAL147_I0_Pos)
#define LCD_PAL147_R14_0_Pos                                  16
#define LCD_PAL147_R14_0_Msk                                  (0x1fUL << LCD_PAL147_R14_0_Pos)
#define LCD_PAL147_G14_0_Pos                                  21
#define LCD_PAL147_G14_0_Msk                                  (0x1fUL << LCD_PAL147_G14_0_Pos)
#define LCD_PAL147_B14_0_Pos                                  26
#define LCD_PAL147_B14_0_Msk                                  (0x1fUL << LCD_PAL147_B14_0_Pos)
#define LCD_PAL147_I1_Pos                                     31
#define LCD_PAL147_I1_Msk                                     (0x01UL << LCD_PAL147_I1_Pos)

// ---------------------------------------  LCD_PAL148  -------------------------------------------
#define LCD_PAL148_R04_0_Pos                                  0
#define LCD_PAL148_R04_0_Msk                                  (0x1fUL << LCD_PAL148_R04_0_Pos)
#define LCD_PAL148_G04_0_Pos                                  5
#define LCD_PAL148_G04_0_Msk                                  (0x1fUL << LCD_PAL148_G04_0_Pos)
#define LCD_PAL148_B04_0_Pos                                  10
#define LCD_PAL148_B04_0_Msk                                  (0x1fUL << LCD_PAL148_B04_0_Pos)
#define LCD_PAL148_I0_Pos                                     15
#define LCD_PAL148_I0_Msk                                     (0x01UL << LCD_PAL148_I0_Pos)
#define LCD_PAL148_R14_0_Pos                                  16
#define LCD_PAL148_R14_0_Msk                                  (0x1fUL << LCD_PAL148_R14_0_Pos)
#define LCD_PAL148_G14_0_Pos                                  21
#define LCD_PAL148_G14_0_Msk                                  (0x1fUL << LCD_PAL148_G14_0_Pos)
#define LCD_PAL148_B14_0_Pos                                  26
#define LCD_PAL148_B14_0_Msk                                  (0x1fUL << LCD_PAL148_B14_0_Pos)
#define LCD_PAL148_I1_Pos                                     31
#define LCD_PAL148_I1_Msk                                     (0x01UL << LCD_PAL148_I1_Pos)

// ---------------------------------------  LCD_PAL149  -------------------------------------------
#define LCD_PAL149_R04_0_Pos                                  0
#define LCD_PAL149_R04_0_Msk                                  (0x1fUL << LCD_PAL149_R04_0_Pos)
#define LCD_PAL149_G04_0_Pos                                  5
#define LCD_PAL149_G04_0_Msk                                  (0x1fUL << LCD_PAL149_G04_0_Pos)
#define LCD_PAL149_B04_0_Pos                                  10
#define LCD_PAL149_B04_0_Msk                                  (0x1fUL << LCD_PAL149_B04_0_Pos)
#define LCD_PAL149_I0_Pos                                     15
#define LCD_PAL149_I0_Msk                                     (0x01UL << LCD_PAL149_I0_Pos)
#define LCD_PAL149_R14_0_Pos                                  16
#define LCD_PAL149_R14_0_Msk                                  (0x1fUL << LCD_PAL149_R14_0_Pos)
#define LCD_PAL149_G14_0_Pos                                  21
#define LCD_PAL149_G14_0_Msk                                  (0x1fUL << LCD_PAL149_G14_0_Pos)
#define LCD_PAL149_B14_0_Pos                                  26
#define LCD_PAL149_B14_0_Msk                                  (0x1fUL << LCD_PAL149_B14_0_Pos)
#define LCD_PAL149_I1_Pos                                     31
#define LCD_PAL149_I1_Msk                                     (0x01UL << LCD_PAL149_I1_Pos)

// ---------------------------------------  LCD_PAL150  -------------------------------------------
#define LCD_PAL150_R04_0_Pos                                  0
#define LCD_PAL150_R04_0_Msk                                  (0x1fUL << LCD_PAL150_R04_0_Pos)
#define LCD_PAL150_G04_0_Pos                                  5
#define LCD_PAL150_G04_0_Msk                                  (0x1fUL << LCD_PAL150_G04_0_Pos)
#define LCD_PAL150_B04_0_Pos                                  10
#define LCD_PAL150_B04_0_Msk                                  (0x1fUL << LCD_PAL150_B04_0_Pos)
#define LCD_PAL150_I0_Pos                                     15
#define LCD_PAL150_I0_Msk                                     (0x01UL << LCD_PAL150_I0_Pos)
#define LCD_PAL150_R14_0_Pos                                  16
#define LCD_PAL150_R14_0_Msk                                  (0x1fUL << LCD_PAL150_R14_0_Pos)
#define LCD_PAL150_G14_0_Pos                                  21
#define LCD_PAL150_G14_0_Msk                                  (0x1fUL << LCD_PAL150_G14_0_Pos)
#define LCD_PAL150_B14_0_Pos                                  26
#define LCD_PAL150_B14_0_Msk                                  (0x1fUL << LCD_PAL150_B14_0_Pos)
#define LCD_PAL150_I1_Pos                                     31
#define LCD_PAL150_I1_Msk                                     (0x01UL << LCD_PAL150_I1_Pos)

// ---------------------------------------  LCD_PAL151  -------------------------------------------
#define LCD_PAL151_R04_0_Pos                                  0
#define LCD_PAL151_R04_0_Msk                                  (0x1fUL << LCD_PAL151_R04_0_Pos)
#define LCD_PAL151_G04_0_Pos                                  5
#define LCD_PAL151_G04_0_Msk                                  (0x1fUL << LCD_PAL151_G04_0_Pos)
#define LCD_PAL151_B04_0_Pos                                  10
#define LCD_PAL151_B04_0_Msk                                  (0x1fUL << LCD_PAL151_B04_0_Pos)
#define LCD_PAL151_I0_Pos                                     15
#define LCD_PAL151_I0_Msk                                     (0x01UL << LCD_PAL151_I0_Pos)
#define LCD_PAL151_R14_0_Pos                                  16
#define LCD_PAL151_R14_0_Msk                                  (0x1fUL << LCD_PAL151_R14_0_Pos)
#define LCD_PAL151_G14_0_Pos                                  21
#define LCD_PAL151_G14_0_Msk                                  (0x1fUL << LCD_PAL151_G14_0_Pos)
#define LCD_PAL151_B14_0_Pos                                  26
#define LCD_PAL151_B14_0_Msk                                  (0x1fUL << LCD_PAL151_B14_0_Pos)
#define LCD_PAL151_I1_Pos                                     31
#define LCD_PAL151_I1_Msk                                     (0x01UL << LCD_PAL151_I1_Pos)

// ---------------------------------------  LCD_PAL152  -------------------------------------------
#define LCD_PAL152_R04_0_Pos                                  0
#define LCD_PAL152_R04_0_Msk                                  (0x1fUL << LCD_PAL152_R04_0_Pos)
#define LCD_PAL152_G04_0_Pos                                  5
#define LCD_PAL152_G04_0_Msk                                  (0x1fUL << LCD_PAL152_G04_0_Pos)
#define LCD_PAL152_B04_0_Pos                                  10
#define LCD_PAL152_B04_0_Msk                                  (0x1fUL << LCD_PAL152_B04_0_Pos)
#define LCD_PAL152_I0_Pos                                     15
#define LCD_PAL152_I0_Msk                                     (0x01UL << LCD_PAL152_I0_Pos)
#define LCD_PAL152_R14_0_Pos                                  16
#define LCD_PAL152_R14_0_Msk                                  (0x1fUL << LCD_PAL152_R14_0_Pos)
#define LCD_PAL152_G14_0_Pos                                  21
#define LCD_PAL152_G14_0_Msk                                  (0x1fUL << LCD_PAL152_G14_0_Pos)
#define LCD_PAL152_B14_0_Pos                                  26
#define LCD_PAL152_B14_0_Msk                                  (0x1fUL << LCD_PAL152_B14_0_Pos)
#define LCD_PAL152_I1_Pos                                     31
#define LCD_PAL152_I1_Msk                                     (0x01UL << LCD_PAL152_I1_Pos)

// ---------------------------------------  LCD_PAL153  -------------------------------------------
#define LCD_PAL153_R04_0_Pos                                  0
#define LCD_PAL153_R04_0_Msk                                  (0x1fUL << LCD_PAL153_R04_0_Pos)
#define LCD_PAL153_G04_0_Pos                                  5
#define LCD_PAL153_G04_0_Msk                                  (0x1fUL << LCD_PAL153_G04_0_Pos)
#define LCD_PAL153_B04_0_Pos                                  10
#define LCD_PAL153_B04_0_Msk                                  (0x1fUL << LCD_PAL153_B04_0_Pos)
#define LCD_PAL153_I0_Pos                                     15
#define LCD_PAL153_I0_Msk                                     (0x01UL << LCD_PAL153_I0_Pos)
#define LCD_PAL153_R14_0_Pos                                  16
#define LCD_PAL153_R14_0_Msk                                  (0x1fUL << LCD_PAL153_R14_0_Pos)
#define LCD_PAL153_G14_0_Pos                                  21
#define LCD_PAL153_G14_0_Msk                                  (0x1fUL << LCD_PAL153_G14_0_Pos)
#define LCD_PAL153_B14_0_Pos                                  26
#define LCD_PAL153_B14_0_Msk                                  (0x1fUL << LCD_PAL153_B14_0_Pos)
#define LCD_PAL153_I1_Pos                                     31
#define LCD_PAL153_I1_Msk                                     (0x01UL << LCD_PAL153_I1_Pos)

// ---------------------------------------  LCD_PAL154  -------------------------------------------
#define LCD_PAL154_R04_0_Pos                                  0
#define LCD_PAL154_R04_0_Msk                                  (0x1fUL << LCD_PAL154_R04_0_Pos)
#define LCD_PAL154_G04_0_Pos                                  5
#define LCD_PAL154_G04_0_Msk                                  (0x1fUL << LCD_PAL154_G04_0_Pos)
#define LCD_PAL154_B04_0_Pos                                  10
#define LCD_PAL154_B04_0_Msk                                  (0x1fUL << LCD_PAL154_B04_0_Pos)
#define LCD_PAL154_I0_Pos                                     15
#define LCD_PAL154_I0_Msk                                     (0x01UL << LCD_PAL154_I0_Pos)
#define LCD_PAL154_R14_0_Pos                                  16
#define LCD_PAL154_R14_0_Msk                                  (0x1fUL << LCD_PAL154_R14_0_Pos)
#define LCD_PAL154_G14_0_Pos                                  21
#define LCD_PAL154_G14_0_Msk                                  (0x1fUL << LCD_PAL154_G14_0_Pos)
#define LCD_PAL154_B14_0_Pos                                  26
#define LCD_PAL154_B14_0_Msk                                  (0x1fUL << LCD_PAL154_B14_0_Pos)
#define LCD_PAL154_I1_Pos                                     31
#define LCD_PAL154_I1_Msk                                     (0x01UL << LCD_PAL154_I1_Pos)

// ---------------------------------------  LCD_PAL155  -------------------------------------------
#define LCD_PAL155_R04_0_Pos                                  0
#define LCD_PAL155_R04_0_Msk                                  (0x1fUL << LCD_PAL155_R04_0_Pos)
#define LCD_PAL155_G04_0_Pos                                  5
#define LCD_PAL155_G04_0_Msk                                  (0x1fUL << LCD_PAL155_G04_0_Pos)
#define LCD_PAL155_B04_0_Pos                                  10
#define LCD_PAL155_B04_0_Msk                                  (0x1fUL << LCD_PAL155_B04_0_Pos)
#define LCD_PAL155_I0_Pos                                     15
#define LCD_PAL155_I0_Msk                                     (0x01UL << LCD_PAL155_I0_Pos)
#define LCD_PAL155_R14_0_Pos                                  16
#define LCD_PAL155_R14_0_Msk                                  (0x1fUL << LCD_PAL155_R14_0_Pos)
#define LCD_PAL155_G14_0_Pos                                  21
#define LCD_PAL155_G14_0_Msk                                  (0x1fUL << LCD_PAL155_G14_0_Pos)
#define LCD_PAL155_B14_0_Pos                                  26
#define LCD_PAL155_B14_0_Msk                                  (0x1fUL << LCD_PAL155_B14_0_Pos)
#define LCD_PAL155_I1_Pos                                     31
#define LCD_PAL155_I1_Msk                                     (0x01UL << LCD_PAL155_I1_Pos)

// ---------------------------------------  LCD_PAL156  -------------------------------------------
#define LCD_PAL156_R04_0_Pos                                  0
#define LCD_PAL156_R04_0_Msk                                  (0x1fUL << LCD_PAL156_R04_0_Pos)
#define LCD_PAL156_G04_0_Pos                                  5
#define LCD_PAL156_G04_0_Msk                                  (0x1fUL << LCD_PAL156_G04_0_Pos)
#define LCD_PAL156_B04_0_Pos                                  10
#define LCD_PAL156_B04_0_Msk                                  (0x1fUL << LCD_PAL156_B04_0_Pos)
#define LCD_PAL156_I0_Pos                                     15
#define LCD_PAL156_I0_Msk                                     (0x01UL << LCD_PAL156_I0_Pos)
#define LCD_PAL156_R14_0_Pos                                  16
#define LCD_PAL156_R14_0_Msk                                  (0x1fUL << LCD_PAL156_R14_0_Pos)
#define LCD_PAL156_G14_0_Pos                                  21
#define LCD_PAL156_G14_0_Msk                                  (0x1fUL << LCD_PAL156_G14_0_Pos)
#define LCD_PAL156_B14_0_Pos                                  26
#define LCD_PAL156_B14_0_Msk                                  (0x1fUL << LCD_PAL156_B14_0_Pos)
#define LCD_PAL156_I1_Pos                                     31
#define LCD_PAL156_I1_Msk                                     (0x01UL << LCD_PAL156_I1_Pos)

// ---------------------------------------  LCD_PAL157  -------------------------------------------
#define LCD_PAL157_R04_0_Pos                                  0
#define LCD_PAL157_R04_0_Msk                                  (0x1fUL << LCD_PAL157_R04_0_Pos)
#define LCD_PAL157_G04_0_Pos                                  5
#define LCD_PAL157_G04_0_Msk                                  (0x1fUL << LCD_PAL157_G04_0_Pos)
#define LCD_PAL157_B04_0_Pos                                  10
#define LCD_PAL157_B04_0_Msk                                  (0x1fUL << LCD_PAL157_B04_0_Pos)
#define LCD_PAL157_I0_Pos                                     15
#define LCD_PAL157_I0_Msk                                     (0x01UL << LCD_PAL157_I0_Pos)
#define LCD_PAL157_R14_0_Pos                                  16
#define LCD_PAL157_R14_0_Msk                                  (0x1fUL << LCD_PAL157_R14_0_Pos)
#define LCD_PAL157_G14_0_Pos                                  21
#define LCD_PAL157_G14_0_Msk                                  (0x1fUL << LCD_PAL157_G14_0_Pos)
#define LCD_PAL157_B14_0_Pos                                  26
#define LCD_PAL157_B14_0_Msk                                  (0x1fUL << LCD_PAL157_B14_0_Pos)
#define LCD_PAL157_I1_Pos                                     31
#define LCD_PAL157_I1_Msk                                     (0x01UL << LCD_PAL157_I1_Pos)

// ---------------------------------------  LCD_PAL158  -------------------------------------------
#define LCD_PAL158_R04_0_Pos                                  0
#define LCD_PAL158_R04_0_Msk                                  (0x1fUL << LCD_PAL158_R04_0_Pos)
#define LCD_PAL158_G04_0_Pos                                  5
#define LCD_PAL158_G04_0_Msk                                  (0x1fUL << LCD_PAL158_G04_0_Pos)
#define LCD_PAL158_B04_0_Pos                                  10
#define LCD_PAL158_B04_0_Msk                                  (0x1fUL << LCD_PAL158_B04_0_Pos)
#define LCD_PAL158_I0_Pos                                     15
#define LCD_PAL158_I0_Msk                                     (0x01UL << LCD_PAL158_I0_Pos)
#define LCD_PAL158_R14_0_Pos                                  16
#define LCD_PAL158_R14_0_Msk                                  (0x1fUL << LCD_PAL158_R14_0_Pos)
#define LCD_PAL158_G14_0_Pos                                  21
#define LCD_PAL158_G14_0_Msk                                  (0x1fUL << LCD_PAL158_G14_0_Pos)
#define LCD_PAL158_B14_0_Pos                                  26
#define LCD_PAL158_B14_0_Msk                                  (0x1fUL << LCD_PAL158_B14_0_Pos)
#define LCD_PAL158_I1_Pos                                     31
#define LCD_PAL158_I1_Msk                                     (0x01UL << LCD_PAL158_I1_Pos)

// ---------------------------------------  LCD_PAL159  -------------------------------------------
#define LCD_PAL159_R04_0_Pos                                  0
#define LCD_PAL159_R04_0_Msk                                  (0x1fUL << LCD_PAL159_R04_0_Pos)
#define LCD_PAL159_G04_0_Pos                                  5
#define LCD_PAL159_G04_0_Msk                                  (0x1fUL << LCD_PAL159_G04_0_Pos)
#define LCD_PAL159_B04_0_Pos                                  10
#define LCD_PAL159_B04_0_Msk                                  (0x1fUL << LCD_PAL159_B04_0_Pos)
#define LCD_PAL159_I0_Pos                                     15
#define LCD_PAL159_I0_Msk                                     (0x01UL << LCD_PAL159_I0_Pos)
#define LCD_PAL159_R14_0_Pos                                  16
#define LCD_PAL159_R14_0_Msk                                  (0x1fUL << LCD_PAL159_R14_0_Pos)
#define LCD_PAL159_G14_0_Pos                                  21
#define LCD_PAL159_G14_0_Msk                                  (0x1fUL << LCD_PAL159_G14_0_Pos)
#define LCD_PAL159_B14_0_Pos                                  26
#define LCD_PAL159_B14_0_Msk                                  (0x1fUL << LCD_PAL159_B14_0_Pos)
#define LCD_PAL159_I1_Pos                                     31
#define LCD_PAL159_I1_Msk                                     (0x01UL << LCD_PAL159_I1_Pos)

// ---------------------------------------  LCD_PAL160  -------------------------------------------
#define LCD_PAL160_R04_0_Pos                                  0
#define LCD_PAL160_R04_0_Msk                                  (0x1fUL << LCD_PAL160_R04_0_Pos)
#define LCD_PAL160_G04_0_Pos                                  5
#define LCD_PAL160_G04_0_Msk                                  (0x1fUL << LCD_PAL160_G04_0_Pos)
#define LCD_PAL160_B04_0_Pos                                  10
#define LCD_PAL160_B04_0_Msk                                  (0x1fUL << LCD_PAL160_B04_0_Pos)
#define LCD_PAL160_I0_Pos                                     15
#define LCD_PAL160_I0_Msk                                     (0x01UL << LCD_PAL160_I0_Pos)
#define LCD_PAL160_R14_0_Pos                                  16
#define LCD_PAL160_R14_0_Msk                                  (0x1fUL << LCD_PAL160_R14_0_Pos)
#define LCD_PAL160_G14_0_Pos                                  21
#define LCD_PAL160_G14_0_Msk                                  (0x1fUL << LCD_PAL160_G14_0_Pos)
#define LCD_PAL160_B14_0_Pos                                  26
#define LCD_PAL160_B14_0_Msk                                  (0x1fUL << LCD_PAL160_B14_0_Pos)
#define LCD_PAL160_I1_Pos                                     31
#define LCD_PAL160_I1_Msk                                     (0x01UL << LCD_PAL160_I1_Pos)

// ---------------------------------------  LCD_PAL161  -------------------------------------------
#define LCD_PAL161_R04_0_Pos                                  0
#define LCD_PAL161_R04_0_Msk                                  (0x1fUL << LCD_PAL161_R04_0_Pos)
#define LCD_PAL161_G04_0_Pos                                  5
#define LCD_PAL161_G04_0_Msk                                  (0x1fUL << LCD_PAL161_G04_0_Pos)
#define LCD_PAL161_B04_0_Pos                                  10
#define LCD_PAL161_B04_0_Msk                                  (0x1fUL << LCD_PAL161_B04_0_Pos)
#define LCD_PAL161_I0_Pos                                     15
#define LCD_PAL161_I0_Msk                                     (0x01UL << LCD_PAL161_I0_Pos)
#define LCD_PAL161_R14_0_Pos                                  16
#define LCD_PAL161_R14_0_Msk                                  (0x1fUL << LCD_PAL161_R14_0_Pos)
#define LCD_PAL161_G14_0_Pos                                  21
#define LCD_PAL161_G14_0_Msk                                  (0x1fUL << LCD_PAL161_G14_0_Pos)
#define LCD_PAL161_B14_0_Pos                                  26
#define LCD_PAL161_B14_0_Msk                                  (0x1fUL << LCD_PAL161_B14_0_Pos)
#define LCD_PAL161_I1_Pos                                     31
#define LCD_PAL161_I1_Msk                                     (0x01UL << LCD_PAL161_I1_Pos)

// ---------------------------------------  LCD_PAL162  -------------------------------------------
#define LCD_PAL162_R04_0_Pos                                  0
#define LCD_PAL162_R04_0_Msk                                  (0x1fUL << LCD_PAL162_R04_0_Pos)
#define LCD_PAL162_G04_0_Pos                                  5
#define LCD_PAL162_G04_0_Msk                                  (0x1fUL << LCD_PAL162_G04_0_Pos)
#define LCD_PAL162_B04_0_Pos                                  10
#define LCD_PAL162_B04_0_Msk                                  (0x1fUL << LCD_PAL162_B04_0_Pos)
#define LCD_PAL162_I0_Pos                                     15
#define LCD_PAL162_I0_Msk                                     (0x01UL << LCD_PAL162_I0_Pos)
#define LCD_PAL162_R14_0_Pos                                  16
#define LCD_PAL162_R14_0_Msk                                  (0x1fUL << LCD_PAL162_R14_0_Pos)
#define LCD_PAL162_G14_0_Pos                                  21
#define LCD_PAL162_G14_0_Msk                                  (0x1fUL << LCD_PAL162_G14_0_Pos)
#define LCD_PAL162_B14_0_Pos                                  26
#define LCD_PAL162_B14_0_Msk                                  (0x1fUL << LCD_PAL162_B14_0_Pos)
#define LCD_PAL162_I1_Pos                                     31
#define LCD_PAL162_I1_Msk                                     (0x01UL << LCD_PAL162_I1_Pos)

// ---------------------------------------  LCD_PAL163  -------------------------------------------
#define LCD_PAL163_R04_0_Pos                                  0
#define LCD_PAL163_R04_0_Msk                                  (0x1fUL << LCD_PAL163_R04_0_Pos)
#define LCD_PAL163_G04_0_Pos                                  5
#define LCD_PAL163_G04_0_Msk                                  (0x1fUL << LCD_PAL163_G04_0_Pos)
#define LCD_PAL163_B04_0_Pos                                  10
#define LCD_PAL163_B04_0_Msk                                  (0x1fUL << LCD_PAL163_B04_0_Pos)
#define LCD_PAL163_I0_Pos                                     15
#define LCD_PAL163_I0_Msk                                     (0x01UL << LCD_PAL163_I0_Pos)
#define LCD_PAL163_R14_0_Pos                                  16
#define LCD_PAL163_R14_0_Msk                                  (0x1fUL << LCD_PAL163_R14_0_Pos)
#define LCD_PAL163_G14_0_Pos                                  21
#define LCD_PAL163_G14_0_Msk                                  (0x1fUL << LCD_PAL163_G14_0_Pos)
#define LCD_PAL163_B14_0_Pos                                  26
#define LCD_PAL163_B14_0_Msk                                  (0x1fUL << LCD_PAL163_B14_0_Pos)
#define LCD_PAL163_I1_Pos                                     31
#define LCD_PAL163_I1_Msk                                     (0x01UL << LCD_PAL163_I1_Pos)

// ---------------------------------------  LCD_PAL164  -------------------------------------------
#define LCD_PAL164_R04_0_Pos                                  0
#define LCD_PAL164_R04_0_Msk                                  (0x1fUL << LCD_PAL164_R04_0_Pos)
#define LCD_PAL164_G04_0_Pos                                  5
#define LCD_PAL164_G04_0_Msk                                  (0x1fUL << LCD_PAL164_G04_0_Pos)
#define LCD_PAL164_B04_0_Pos                                  10
#define LCD_PAL164_B04_0_Msk                                  (0x1fUL << LCD_PAL164_B04_0_Pos)
#define LCD_PAL164_I0_Pos                                     15
#define LCD_PAL164_I0_Msk                                     (0x01UL << LCD_PAL164_I0_Pos)
#define LCD_PAL164_R14_0_Pos                                  16
#define LCD_PAL164_R14_0_Msk                                  (0x1fUL << LCD_PAL164_R14_0_Pos)
#define LCD_PAL164_G14_0_Pos                                  21
#define LCD_PAL164_G14_0_Msk                                  (0x1fUL << LCD_PAL164_G14_0_Pos)
#define LCD_PAL164_B14_0_Pos                                  26
#define LCD_PAL164_B14_0_Msk                                  (0x1fUL << LCD_PAL164_B14_0_Pos)
#define LCD_PAL164_I1_Pos                                     31
#define LCD_PAL164_I1_Msk                                     (0x01UL << LCD_PAL164_I1_Pos)

// ---------------------------------------  LCD_PAL165  -------------------------------------------
#define LCD_PAL165_R04_0_Pos                                  0
#define LCD_PAL165_R04_0_Msk                                  (0x1fUL << LCD_PAL165_R04_0_Pos)
#define LCD_PAL165_G04_0_Pos                                  5
#define LCD_PAL165_G04_0_Msk                                  (0x1fUL << LCD_PAL165_G04_0_Pos)
#define LCD_PAL165_B04_0_Pos                                  10
#define LCD_PAL165_B04_0_Msk                                  (0x1fUL << LCD_PAL165_B04_0_Pos)
#define LCD_PAL165_I0_Pos                                     15
#define LCD_PAL165_I0_Msk                                     (0x01UL << LCD_PAL165_I0_Pos)
#define LCD_PAL165_R14_0_Pos                                  16
#define LCD_PAL165_R14_0_Msk                                  (0x1fUL << LCD_PAL165_R14_0_Pos)
#define LCD_PAL165_G14_0_Pos                                  21
#define LCD_PAL165_G14_0_Msk                                  (0x1fUL << LCD_PAL165_G14_0_Pos)
#define LCD_PAL165_B14_0_Pos                                  26
#define LCD_PAL165_B14_0_Msk                                  (0x1fUL << LCD_PAL165_B14_0_Pos)
#define LCD_PAL165_I1_Pos                                     31
#define LCD_PAL165_I1_Msk                                     (0x01UL << LCD_PAL165_I1_Pos)

// ---------------------------------------  LCD_PAL166  -------------------------------------------
#define LCD_PAL166_R04_0_Pos                                  0
#define LCD_PAL166_R04_0_Msk                                  (0x1fUL << LCD_PAL166_R04_0_Pos)
#define LCD_PAL166_G04_0_Pos                                  5
#define LCD_PAL166_G04_0_Msk                                  (0x1fUL << LCD_PAL166_G04_0_Pos)
#define LCD_PAL166_B04_0_Pos                                  10
#define LCD_PAL166_B04_0_Msk                                  (0x1fUL << LCD_PAL166_B04_0_Pos)
#define LCD_PAL166_I0_Pos                                     15
#define LCD_PAL166_I0_Msk                                     (0x01UL << LCD_PAL166_I0_Pos)
#define LCD_PAL166_R14_0_Pos                                  16
#define LCD_PAL166_R14_0_Msk                                  (0x1fUL << LCD_PAL166_R14_0_Pos)
#define LCD_PAL166_G14_0_Pos                                  21
#define LCD_PAL166_G14_0_Msk                                  (0x1fUL << LCD_PAL166_G14_0_Pos)
#define LCD_PAL166_B14_0_Pos                                  26
#define LCD_PAL166_B14_0_Msk                                  (0x1fUL << LCD_PAL166_B14_0_Pos)
#define LCD_PAL166_I1_Pos                                     31
#define LCD_PAL166_I1_Msk                                     (0x01UL << LCD_PAL166_I1_Pos)

// ---------------------------------------  LCD_PAL167  -------------------------------------------
#define LCD_PAL167_R04_0_Pos                                  0
#define LCD_PAL167_R04_0_Msk                                  (0x1fUL << LCD_PAL167_R04_0_Pos)
#define LCD_PAL167_G04_0_Pos                                  5
#define LCD_PAL167_G04_0_Msk                                  (0x1fUL << LCD_PAL167_G04_0_Pos)
#define LCD_PAL167_B04_0_Pos                                  10
#define LCD_PAL167_B04_0_Msk                                  (0x1fUL << LCD_PAL167_B04_0_Pos)
#define LCD_PAL167_I0_Pos                                     15
#define LCD_PAL167_I0_Msk                                     (0x01UL << LCD_PAL167_I0_Pos)
#define LCD_PAL167_R14_0_Pos                                  16
#define LCD_PAL167_R14_0_Msk                                  (0x1fUL << LCD_PAL167_R14_0_Pos)
#define LCD_PAL167_G14_0_Pos                                  21
#define LCD_PAL167_G14_0_Msk                                  (0x1fUL << LCD_PAL167_G14_0_Pos)
#define LCD_PAL167_B14_0_Pos                                  26
#define LCD_PAL167_B14_0_Msk                                  (0x1fUL << LCD_PAL167_B14_0_Pos)
#define LCD_PAL167_I1_Pos                                     31
#define LCD_PAL167_I1_Msk                                     (0x01UL << LCD_PAL167_I1_Pos)

// ---------------------------------------  LCD_PAL168  -------------------------------------------
#define LCD_PAL168_R04_0_Pos                                  0
#define LCD_PAL168_R04_0_Msk                                  (0x1fUL << LCD_PAL168_R04_0_Pos)
#define LCD_PAL168_G04_0_Pos                                  5
#define LCD_PAL168_G04_0_Msk                                  (0x1fUL << LCD_PAL168_G04_0_Pos)
#define LCD_PAL168_B04_0_Pos                                  10
#define LCD_PAL168_B04_0_Msk                                  (0x1fUL << LCD_PAL168_B04_0_Pos)
#define LCD_PAL168_I0_Pos                                     15
#define LCD_PAL168_I0_Msk                                     (0x01UL << LCD_PAL168_I0_Pos)
#define LCD_PAL168_R14_0_Pos                                  16
#define LCD_PAL168_R14_0_Msk                                  (0x1fUL << LCD_PAL168_R14_0_Pos)
#define LCD_PAL168_G14_0_Pos                                  21
#define LCD_PAL168_G14_0_Msk                                  (0x1fUL << LCD_PAL168_G14_0_Pos)
#define LCD_PAL168_B14_0_Pos                                  26
#define LCD_PAL168_B14_0_Msk                                  (0x1fUL << LCD_PAL168_B14_0_Pos)
#define LCD_PAL168_I1_Pos                                     31
#define LCD_PAL168_I1_Msk                                     (0x01UL << LCD_PAL168_I1_Pos)

// ---------------------------------------  LCD_PAL169  -------------------------------------------
#define LCD_PAL169_R04_0_Pos                                  0
#define LCD_PAL169_R04_0_Msk                                  (0x1fUL << LCD_PAL169_R04_0_Pos)
#define LCD_PAL169_G04_0_Pos                                  5
#define LCD_PAL169_G04_0_Msk                                  (0x1fUL << LCD_PAL169_G04_0_Pos)
#define LCD_PAL169_B04_0_Pos                                  10
#define LCD_PAL169_B04_0_Msk                                  (0x1fUL << LCD_PAL169_B04_0_Pos)
#define LCD_PAL169_I0_Pos                                     15
#define LCD_PAL169_I0_Msk                                     (0x01UL << LCD_PAL169_I0_Pos)
#define LCD_PAL169_R14_0_Pos                                  16
#define LCD_PAL169_R14_0_Msk                                  (0x1fUL << LCD_PAL169_R14_0_Pos)
#define LCD_PAL169_G14_0_Pos                                  21
#define LCD_PAL169_G14_0_Msk                                  (0x1fUL << LCD_PAL169_G14_0_Pos)
#define LCD_PAL169_B14_0_Pos                                  26
#define LCD_PAL169_B14_0_Msk                                  (0x1fUL << LCD_PAL169_B14_0_Pos)
#define LCD_PAL169_I1_Pos                                     31
#define LCD_PAL169_I1_Msk                                     (0x01UL << LCD_PAL169_I1_Pos)

// ---------------------------------------  LCD_PAL170  -------------------------------------------
#define LCD_PAL170_R04_0_Pos                                  0
#define LCD_PAL170_R04_0_Msk                                  (0x1fUL << LCD_PAL170_R04_0_Pos)
#define LCD_PAL170_G04_0_Pos                                  5
#define LCD_PAL170_G04_0_Msk                                  (0x1fUL << LCD_PAL170_G04_0_Pos)
#define LCD_PAL170_B04_0_Pos                                  10
#define LCD_PAL170_B04_0_Msk                                  (0x1fUL << LCD_PAL170_B04_0_Pos)
#define LCD_PAL170_I0_Pos                                     15
#define LCD_PAL170_I0_Msk                                     (0x01UL << LCD_PAL170_I0_Pos)
#define LCD_PAL170_R14_0_Pos                                  16
#define LCD_PAL170_R14_0_Msk                                  (0x1fUL << LCD_PAL170_R14_0_Pos)
#define LCD_PAL170_G14_0_Pos                                  21
#define LCD_PAL170_G14_0_Msk                                  (0x1fUL << LCD_PAL170_G14_0_Pos)
#define LCD_PAL170_B14_0_Pos                                  26
#define LCD_PAL170_B14_0_Msk                                  (0x1fUL << LCD_PAL170_B14_0_Pos)
#define LCD_PAL170_I1_Pos                                     31
#define LCD_PAL170_I1_Msk                                     (0x01UL << LCD_PAL170_I1_Pos)

// ---------------------------------------  LCD_PAL171  -------------------------------------------
#define LCD_PAL171_R04_0_Pos                                  0
#define LCD_PAL171_R04_0_Msk                                  (0x1fUL << LCD_PAL171_R04_0_Pos)
#define LCD_PAL171_G04_0_Pos                                  5
#define LCD_PAL171_G04_0_Msk                                  (0x1fUL << LCD_PAL171_G04_0_Pos)
#define LCD_PAL171_B04_0_Pos                                  10
#define LCD_PAL171_B04_0_Msk                                  (0x1fUL << LCD_PAL171_B04_0_Pos)
#define LCD_PAL171_I0_Pos                                     15
#define LCD_PAL171_I0_Msk                                     (0x01UL << LCD_PAL171_I0_Pos)
#define LCD_PAL171_R14_0_Pos                                  16
#define LCD_PAL171_R14_0_Msk                                  (0x1fUL << LCD_PAL171_R14_0_Pos)
#define LCD_PAL171_G14_0_Pos                                  21
#define LCD_PAL171_G14_0_Msk                                  (0x1fUL << LCD_PAL171_G14_0_Pos)
#define LCD_PAL171_B14_0_Pos                                  26
#define LCD_PAL171_B14_0_Msk                                  (0x1fUL << LCD_PAL171_B14_0_Pos)
#define LCD_PAL171_I1_Pos                                     31
#define LCD_PAL171_I1_Msk                                     (0x01UL << LCD_PAL171_I1_Pos)

// ---------------------------------------  LCD_PAL172  -------------------------------------------
#define LCD_PAL172_R04_0_Pos                                  0
#define LCD_PAL172_R04_0_Msk                                  (0x1fUL << LCD_PAL172_R04_0_Pos)
#define LCD_PAL172_G04_0_Pos                                  5
#define LCD_PAL172_G04_0_Msk                                  (0x1fUL << LCD_PAL172_G04_0_Pos)
#define LCD_PAL172_B04_0_Pos                                  10
#define LCD_PAL172_B04_0_Msk                                  (0x1fUL << LCD_PAL172_B04_0_Pos)
#define LCD_PAL172_I0_Pos                                     15
#define LCD_PAL172_I0_Msk                                     (0x01UL << LCD_PAL172_I0_Pos)
#define LCD_PAL172_R14_0_Pos                                  16
#define LCD_PAL172_R14_0_Msk                                  (0x1fUL << LCD_PAL172_R14_0_Pos)
#define LCD_PAL172_G14_0_Pos                                  21
#define LCD_PAL172_G14_0_Msk                                  (0x1fUL << LCD_PAL172_G14_0_Pos)
#define LCD_PAL172_B14_0_Pos                                  26
#define LCD_PAL172_B14_0_Msk                                  (0x1fUL << LCD_PAL172_B14_0_Pos)
#define LCD_PAL172_I1_Pos                                     31
#define LCD_PAL172_I1_Msk                                     (0x01UL << LCD_PAL172_I1_Pos)

// ---------------------------------------  LCD_PAL173  -------------------------------------------
#define LCD_PAL173_R04_0_Pos                                  0
#define LCD_PAL173_R04_0_Msk                                  (0x1fUL << LCD_PAL173_R04_0_Pos)
#define LCD_PAL173_G04_0_Pos                                  5
#define LCD_PAL173_G04_0_Msk                                  (0x1fUL << LCD_PAL173_G04_0_Pos)
#define LCD_PAL173_B04_0_Pos                                  10
#define LCD_PAL173_B04_0_Msk                                  (0x1fUL << LCD_PAL173_B04_0_Pos)
#define LCD_PAL173_I0_Pos                                     15
#define LCD_PAL173_I0_Msk                                     (0x01UL << LCD_PAL173_I0_Pos)
#define LCD_PAL173_R14_0_Pos                                  16
#define LCD_PAL173_R14_0_Msk                                  (0x1fUL << LCD_PAL173_R14_0_Pos)
#define LCD_PAL173_G14_0_Pos                                  21
#define LCD_PAL173_G14_0_Msk                                  (0x1fUL << LCD_PAL173_G14_0_Pos)
#define LCD_PAL173_B14_0_Pos                                  26
#define LCD_PAL173_B14_0_Msk                                  (0x1fUL << LCD_PAL173_B14_0_Pos)
#define LCD_PAL173_I1_Pos                                     31
#define LCD_PAL173_I1_Msk                                     (0x01UL << LCD_PAL173_I1_Pos)

// ---------------------------------------  LCD_PAL174  -------------------------------------------
#define LCD_PAL174_R04_0_Pos                                  0
#define LCD_PAL174_R04_0_Msk                                  (0x1fUL << LCD_PAL174_R04_0_Pos)
#define LCD_PAL174_G04_0_Pos                                  5
#define LCD_PAL174_G04_0_Msk                                  (0x1fUL << LCD_PAL174_G04_0_Pos)
#define LCD_PAL174_B04_0_Pos                                  10
#define LCD_PAL174_B04_0_Msk                                  (0x1fUL << LCD_PAL174_B04_0_Pos)
#define LCD_PAL174_I0_Pos                                     15
#define LCD_PAL174_I0_Msk                                     (0x01UL << LCD_PAL174_I0_Pos)
#define LCD_PAL174_R14_0_Pos                                  16
#define LCD_PAL174_R14_0_Msk                                  (0x1fUL << LCD_PAL174_R14_0_Pos)
#define LCD_PAL174_G14_0_Pos                                  21
#define LCD_PAL174_G14_0_Msk                                  (0x1fUL << LCD_PAL174_G14_0_Pos)
#define LCD_PAL174_B14_0_Pos                                  26
#define LCD_PAL174_B14_0_Msk                                  (0x1fUL << LCD_PAL174_B14_0_Pos)
#define LCD_PAL174_I1_Pos                                     31
#define LCD_PAL174_I1_Msk                                     (0x01UL << LCD_PAL174_I1_Pos)

// ---------------------------------------  LCD_PAL175  -------------------------------------------
#define LCD_PAL175_R04_0_Pos                                  0
#define LCD_PAL175_R04_0_Msk                                  (0x1fUL << LCD_PAL175_R04_0_Pos)
#define LCD_PAL175_G04_0_Pos                                  5
#define LCD_PAL175_G04_0_Msk                                  (0x1fUL << LCD_PAL175_G04_0_Pos)
#define LCD_PAL175_B04_0_Pos                                  10
#define LCD_PAL175_B04_0_Msk                                  (0x1fUL << LCD_PAL175_B04_0_Pos)
#define LCD_PAL175_I0_Pos                                     15
#define LCD_PAL175_I0_Msk                                     (0x01UL << LCD_PAL175_I0_Pos)
#define LCD_PAL175_R14_0_Pos                                  16
#define LCD_PAL175_R14_0_Msk                                  (0x1fUL << LCD_PAL175_R14_0_Pos)
#define LCD_PAL175_G14_0_Pos                                  21
#define LCD_PAL175_G14_0_Msk                                  (0x1fUL << LCD_PAL175_G14_0_Pos)
#define LCD_PAL175_B14_0_Pos                                  26
#define LCD_PAL175_B14_0_Msk                                  (0x1fUL << LCD_PAL175_B14_0_Pos)
#define LCD_PAL175_I1_Pos                                     31
#define LCD_PAL175_I1_Msk                                     (0x01UL << LCD_PAL175_I1_Pos)

// ---------------------------------------  LCD_PAL176  -------------------------------------------
#define LCD_PAL176_R04_0_Pos                                  0
#define LCD_PAL176_R04_0_Msk                                  (0x1fUL << LCD_PAL176_R04_0_Pos)
#define LCD_PAL176_G04_0_Pos                                  5
#define LCD_PAL176_G04_0_Msk                                  (0x1fUL << LCD_PAL176_G04_0_Pos)
#define LCD_PAL176_B04_0_Pos                                  10
#define LCD_PAL176_B04_0_Msk                                  (0x1fUL << LCD_PAL176_B04_0_Pos)
#define LCD_PAL176_I0_Pos                                     15
#define LCD_PAL176_I0_Msk                                     (0x01UL << LCD_PAL176_I0_Pos)
#define LCD_PAL176_R14_0_Pos                                  16
#define LCD_PAL176_R14_0_Msk                                  (0x1fUL << LCD_PAL176_R14_0_Pos)
#define LCD_PAL176_G14_0_Pos                                  21
#define LCD_PAL176_G14_0_Msk                                  (0x1fUL << LCD_PAL176_G14_0_Pos)
#define LCD_PAL176_B14_0_Pos                                  26
#define LCD_PAL176_B14_0_Msk                                  (0x1fUL << LCD_PAL176_B14_0_Pos)
#define LCD_PAL176_I1_Pos                                     31
#define LCD_PAL176_I1_Msk                                     (0x01UL << LCD_PAL176_I1_Pos)

// ---------------------------------------  LCD_PAL177  -------------------------------------------
#define LCD_PAL177_R04_0_Pos                                  0
#define LCD_PAL177_R04_0_Msk                                  (0x1fUL << LCD_PAL177_R04_0_Pos)
#define LCD_PAL177_G04_0_Pos                                  5
#define LCD_PAL177_G04_0_Msk                                  (0x1fUL << LCD_PAL177_G04_0_Pos)
#define LCD_PAL177_B04_0_Pos                                  10
#define LCD_PAL177_B04_0_Msk                                  (0x1fUL << LCD_PAL177_B04_0_Pos)
#define LCD_PAL177_I0_Pos                                     15
#define LCD_PAL177_I0_Msk                                     (0x01UL << LCD_PAL177_I0_Pos)
#define LCD_PAL177_R14_0_Pos                                  16
#define LCD_PAL177_R14_0_Msk                                  (0x1fUL << LCD_PAL177_R14_0_Pos)
#define LCD_PAL177_G14_0_Pos                                  21
#define LCD_PAL177_G14_0_Msk                                  (0x1fUL << LCD_PAL177_G14_0_Pos)
#define LCD_PAL177_B14_0_Pos                                  26
#define LCD_PAL177_B14_0_Msk                                  (0x1fUL << LCD_PAL177_B14_0_Pos)
#define LCD_PAL177_I1_Pos                                     31
#define LCD_PAL177_I1_Msk                                     (0x01UL << LCD_PAL177_I1_Pos)

// ---------------------------------------  LCD_PAL178  -------------------------------------------
#define LCD_PAL178_R04_0_Pos                                  0
#define LCD_PAL178_R04_0_Msk                                  (0x1fUL << LCD_PAL178_R04_0_Pos)
#define LCD_PAL178_G04_0_Pos                                  5
#define LCD_PAL178_G04_0_Msk                                  (0x1fUL << LCD_PAL178_G04_0_Pos)
#define LCD_PAL178_B04_0_Pos                                  10
#define LCD_PAL178_B04_0_Msk                                  (0x1fUL << LCD_PAL178_B04_0_Pos)
#define LCD_PAL178_I0_Pos                                     15
#define LCD_PAL178_I0_Msk                                     (0x01UL << LCD_PAL178_I0_Pos)
#define LCD_PAL178_R14_0_Pos                                  16
#define LCD_PAL178_R14_0_Msk                                  (0x1fUL << LCD_PAL178_R14_0_Pos)
#define LCD_PAL178_G14_0_Pos                                  21
#define LCD_PAL178_G14_0_Msk                                  (0x1fUL << LCD_PAL178_G14_0_Pos)
#define LCD_PAL178_B14_0_Pos                                  26
#define LCD_PAL178_B14_0_Msk                                  (0x1fUL << LCD_PAL178_B14_0_Pos)
#define LCD_PAL178_I1_Pos                                     31
#define LCD_PAL178_I1_Msk                                     (0x01UL << LCD_PAL178_I1_Pos)

// ---------------------------------------  LCD_PAL179  -------------------------------------------
#define LCD_PAL179_R04_0_Pos                                  0
#define LCD_PAL179_R04_0_Msk                                  (0x1fUL << LCD_PAL179_R04_0_Pos)
#define LCD_PAL179_G04_0_Pos                                  5
#define LCD_PAL179_G04_0_Msk                                  (0x1fUL << LCD_PAL179_G04_0_Pos)
#define LCD_PAL179_B04_0_Pos                                  10
#define LCD_PAL179_B04_0_Msk                                  (0x1fUL << LCD_PAL179_B04_0_Pos)
#define LCD_PAL179_I0_Pos                                     15
#define LCD_PAL179_I0_Msk                                     (0x01UL << LCD_PAL179_I0_Pos)
#define LCD_PAL179_R14_0_Pos                                  16
#define LCD_PAL179_R14_0_Msk                                  (0x1fUL << LCD_PAL179_R14_0_Pos)
#define LCD_PAL179_G14_0_Pos                                  21
#define LCD_PAL179_G14_0_Msk                                  (0x1fUL << LCD_PAL179_G14_0_Pos)
#define LCD_PAL179_B14_0_Pos                                  26
#define LCD_PAL179_B14_0_Msk                                  (0x1fUL << LCD_PAL179_B14_0_Pos)
#define LCD_PAL179_I1_Pos                                     31
#define LCD_PAL179_I1_Msk                                     (0x01UL << LCD_PAL179_I1_Pos)

// ---------------------------------------  LCD_PAL180  -------------------------------------------
#define LCD_PAL180_R04_0_Pos                                  0
#define LCD_PAL180_R04_0_Msk                                  (0x1fUL << LCD_PAL180_R04_0_Pos)
#define LCD_PAL180_G04_0_Pos                                  5
#define LCD_PAL180_G04_0_Msk                                  (0x1fUL << LCD_PAL180_G04_0_Pos)
#define LCD_PAL180_B04_0_Pos                                  10
#define LCD_PAL180_B04_0_Msk                                  (0x1fUL << LCD_PAL180_B04_0_Pos)
#define LCD_PAL180_I0_Pos                                     15
#define LCD_PAL180_I0_Msk                                     (0x01UL << LCD_PAL180_I0_Pos)
#define LCD_PAL180_R14_0_Pos                                  16
#define LCD_PAL180_R14_0_Msk                                  (0x1fUL << LCD_PAL180_R14_0_Pos)
#define LCD_PAL180_G14_0_Pos                                  21
#define LCD_PAL180_G14_0_Msk                                  (0x1fUL << LCD_PAL180_G14_0_Pos)
#define LCD_PAL180_B14_0_Pos                                  26
#define LCD_PAL180_B14_0_Msk                                  (0x1fUL << LCD_PAL180_B14_0_Pos)
#define LCD_PAL180_I1_Pos                                     31
#define LCD_PAL180_I1_Msk                                     (0x01UL << LCD_PAL180_I1_Pos)

// ---------------------------------------  LCD_PAL181  -------------------------------------------
#define LCD_PAL181_R04_0_Pos                                  0
#define LCD_PAL181_R04_0_Msk                                  (0x1fUL << LCD_PAL181_R04_0_Pos)
#define LCD_PAL181_G04_0_Pos                                  5
#define LCD_PAL181_G04_0_Msk                                  (0x1fUL << LCD_PAL181_G04_0_Pos)
#define LCD_PAL181_B04_0_Pos                                  10
#define LCD_PAL181_B04_0_Msk                                  (0x1fUL << LCD_PAL181_B04_0_Pos)
#define LCD_PAL181_I0_Pos                                     15
#define LCD_PAL181_I0_Msk                                     (0x01UL << LCD_PAL181_I0_Pos)
#define LCD_PAL181_R14_0_Pos                                  16
#define LCD_PAL181_R14_0_Msk                                  (0x1fUL << LCD_PAL181_R14_0_Pos)
#define LCD_PAL181_G14_0_Pos                                  21
#define LCD_PAL181_G14_0_Msk                                  (0x1fUL << LCD_PAL181_G14_0_Pos)
#define LCD_PAL181_B14_0_Pos                                  26
#define LCD_PAL181_B14_0_Msk                                  (0x1fUL << LCD_PAL181_B14_0_Pos)
#define LCD_PAL181_I1_Pos                                     31
#define LCD_PAL181_I1_Msk                                     (0x01UL << LCD_PAL181_I1_Pos)

// ---------------------------------------  LCD_PAL182  -------------------------------------------
#define LCD_PAL182_R04_0_Pos                                  0
#define LCD_PAL182_R04_0_Msk                                  (0x1fUL << LCD_PAL182_R04_0_Pos)
#define LCD_PAL182_G04_0_Pos                                  5
#define LCD_PAL182_G04_0_Msk                                  (0x1fUL << LCD_PAL182_G04_0_Pos)
#define LCD_PAL182_B04_0_Pos                                  10
#define LCD_PAL182_B04_0_Msk                                  (0x1fUL << LCD_PAL182_B04_0_Pos)
#define LCD_PAL182_I0_Pos                                     15
#define LCD_PAL182_I0_Msk                                     (0x01UL << LCD_PAL182_I0_Pos)
#define LCD_PAL182_R14_0_Pos                                  16
#define LCD_PAL182_R14_0_Msk                                  (0x1fUL << LCD_PAL182_R14_0_Pos)
#define LCD_PAL182_G14_0_Pos                                  21
#define LCD_PAL182_G14_0_Msk                                  (0x1fUL << LCD_PAL182_G14_0_Pos)
#define LCD_PAL182_B14_0_Pos                                  26
#define LCD_PAL182_B14_0_Msk                                  (0x1fUL << LCD_PAL182_B14_0_Pos)
#define LCD_PAL182_I1_Pos                                     31
#define LCD_PAL182_I1_Msk                                     (0x01UL << LCD_PAL182_I1_Pos)

// ---------------------------------------  LCD_PAL183  -------------------------------------------
#define LCD_PAL183_R04_0_Pos                                  0
#define LCD_PAL183_R04_0_Msk                                  (0x1fUL << LCD_PAL183_R04_0_Pos)
#define LCD_PAL183_G04_0_Pos                                  5
#define LCD_PAL183_G04_0_Msk                                  (0x1fUL << LCD_PAL183_G04_0_Pos)
#define LCD_PAL183_B04_0_Pos                                  10
#define LCD_PAL183_B04_0_Msk                                  (0x1fUL << LCD_PAL183_B04_0_Pos)
#define LCD_PAL183_I0_Pos                                     15
#define LCD_PAL183_I0_Msk                                     (0x01UL << LCD_PAL183_I0_Pos)
#define LCD_PAL183_R14_0_Pos                                  16
#define LCD_PAL183_R14_0_Msk                                  (0x1fUL << LCD_PAL183_R14_0_Pos)
#define LCD_PAL183_G14_0_Pos                                  21
#define LCD_PAL183_G14_0_Msk                                  (0x1fUL << LCD_PAL183_G14_0_Pos)
#define LCD_PAL183_B14_0_Pos                                  26
#define LCD_PAL183_B14_0_Msk                                  (0x1fUL << LCD_PAL183_B14_0_Pos)
#define LCD_PAL183_I1_Pos                                     31
#define LCD_PAL183_I1_Msk                                     (0x01UL << LCD_PAL183_I1_Pos)

// ---------------------------------------  LCD_PAL184  -------------------------------------------
#define LCD_PAL184_R04_0_Pos                                  0
#define LCD_PAL184_R04_0_Msk                                  (0x1fUL << LCD_PAL184_R04_0_Pos)
#define LCD_PAL184_G04_0_Pos                                  5
#define LCD_PAL184_G04_0_Msk                                  (0x1fUL << LCD_PAL184_G04_0_Pos)
#define LCD_PAL184_B04_0_Pos                                  10
#define LCD_PAL184_B04_0_Msk                                  (0x1fUL << LCD_PAL184_B04_0_Pos)
#define LCD_PAL184_I0_Pos                                     15
#define LCD_PAL184_I0_Msk                                     (0x01UL << LCD_PAL184_I0_Pos)
#define LCD_PAL184_R14_0_Pos                                  16
#define LCD_PAL184_R14_0_Msk                                  (0x1fUL << LCD_PAL184_R14_0_Pos)
#define LCD_PAL184_G14_0_Pos                                  21
#define LCD_PAL184_G14_0_Msk                                  (0x1fUL << LCD_PAL184_G14_0_Pos)
#define LCD_PAL184_B14_0_Pos                                  26
#define LCD_PAL184_B14_0_Msk                                  (0x1fUL << LCD_PAL184_B14_0_Pos)
#define LCD_PAL184_I1_Pos                                     31
#define LCD_PAL184_I1_Msk                                     (0x01UL << LCD_PAL184_I1_Pos)

// ---------------------------------------  LCD_PAL185  -------------------------------------------
#define LCD_PAL185_R04_0_Pos                                  0
#define LCD_PAL185_R04_0_Msk                                  (0x1fUL << LCD_PAL185_R04_0_Pos)
#define LCD_PAL185_G04_0_Pos                                  5
#define LCD_PAL185_G04_0_Msk                                  (0x1fUL << LCD_PAL185_G04_0_Pos)
#define LCD_PAL185_B04_0_Pos                                  10
#define LCD_PAL185_B04_0_Msk                                  (0x1fUL << LCD_PAL185_B04_0_Pos)
#define LCD_PAL185_I0_Pos                                     15
#define LCD_PAL185_I0_Msk                                     (0x01UL << LCD_PAL185_I0_Pos)
#define LCD_PAL185_R14_0_Pos                                  16
#define LCD_PAL185_R14_0_Msk                                  (0x1fUL << LCD_PAL185_R14_0_Pos)
#define LCD_PAL185_G14_0_Pos                                  21
#define LCD_PAL185_G14_0_Msk                                  (0x1fUL << LCD_PAL185_G14_0_Pos)
#define LCD_PAL185_B14_0_Pos                                  26
#define LCD_PAL185_B14_0_Msk                                  (0x1fUL << LCD_PAL185_B14_0_Pos)
#define LCD_PAL185_I1_Pos                                     31
#define LCD_PAL185_I1_Msk                                     (0x01UL << LCD_PAL185_I1_Pos)

// ---------------------------------------  LCD_PAL186  -------------------------------------------
#define LCD_PAL186_R04_0_Pos                                  0
#define LCD_PAL186_R04_0_Msk                                  (0x1fUL << LCD_PAL186_R04_0_Pos)
#define LCD_PAL186_G04_0_Pos                                  5
#define LCD_PAL186_G04_0_Msk                                  (0x1fUL << LCD_PAL186_G04_0_Pos)
#define LCD_PAL186_B04_0_Pos                                  10
#define LCD_PAL186_B04_0_Msk                                  (0x1fUL << LCD_PAL186_B04_0_Pos)
#define LCD_PAL186_I0_Pos                                     15
#define LCD_PAL186_I0_Msk                                     (0x01UL << LCD_PAL186_I0_Pos)
#define LCD_PAL186_R14_0_Pos                                  16
#define LCD_PAL186_R14_0_Msk                                  (0x1fUL << LCD_PAL186_R14_0_Pos)
#define LCD_PAL186_G14_0_Pos                                  21
#define LCD_PAL186_G14_0_Msk                                  (0x1fUL << LCD_PAL186_G14_0_Pos)
#define LCD_PAL186_B14_0_Pos                                  26
#define LCD_PAL186_B14_0_Msk                                  (0x1fUL << LCD_PAL186_B14_0_Pos)
#define LCD_PAL186_I1_Pos                                     31
#define LCD_PAL186_I1_Msk                                     (0x01UL << LCD_PAL186_I1_Pos)

// ---------------------------------------  LCD_PAL187  -------------------------------------------
#define LCD_PAL187_R04_0_Pos                                  0
#define LCD_PAL187_R04_0_Msk                                  (0x1fUL << LCD_PAL187_R04_0_Pos)
#define LCD_PAL187_G04_0_Pos                                  5
#define LCD_PAL187_G04_0_Msk                                  (0x1fUL << LCD_PAL187_G04_0_Pos)
#define LCD_PAL187_B04_0_Pos                                  10
#define LCD_PAL187_B04_0_Msk                                  (0x1fUL << LCD_PAL187_B04_0_Pos)
#define LCD_PAL187_I0_Pos                                     15
#define LCD_PAL187_I0_Msk                                     (0x01UL << LCD_PAL187_I0_Pos)
#define LCD_PAL187_R14_0_Pos                                  16
#define LCD_PAL187_R14_0_Msk                                  (0x1fUL << LCD_PAL187_R14_0_Pos)
#define LCD_PAL187_G14_0_Pos                                  21
#define LCD_PAL187_G14_0_Msk                                  (0x1fUL << LCD_PAL187_G14_0_Pos)
#define LCD_PAL187_B14_0_Pos                                  26
#define LCD_PAL187_B14_0_Msk                                  (0x1fUL << LCD_PAL187_B14_0_Pos)
#define LCD_PAL187_I1_Pos                                     31
#define LCD_PAL187_I1_Msk                                     (0x01UL << LCD_PAL187_I1_Pos)

// ---------------------------------------  LCD_PAL188  -------------------------------------------
#define LCD_PAL188_R04_0_Pos                                  0
#define LCD_PAL188_R04_0_Msk                                  (0x1fUL << LCD_PAL188_R04_0_Pos)
#define LCD_PAL188_G04_0_Pos                                  5
#define LCD_PAL188_G04_0_Msk                                  (0x1fUL << LCD_PAL188_G04_0_Pos)
#define LCD_PAL188_B04_0_Pos                                  10
#define LCD_PAL188_B04_0_Msk                                  (0x1fUL << LCD_PAL188_B04_0_Pos)
#define LCD_PAL188_I0_Pos                                     15
#define LCD_PAL188_I0_Msk                                     (0x01UL << LCD_PAL188_I0_Pos)
#define LCD_PAL188_R14_0_Pos                                  16
#define LCD_PAL188_R14_0_Msk                                  (0x1fUL << LCD_PAL188_R14_0_Pos)
#define LCD_PAL188_G14_0_Pos                                  21
#define LCD_PAL188_G14_0_Msk                                  (0x1fUL << LCD_PAL188_G14_0_Pos)
#define LCD_PAL188_B14_0_Pos                                  26
#define LCD_PAL188_B14_0_Msk                                  (0x1fUL << LCD_PAL188_B14_0_Pos)
#define LCD_PAL188_I1_Pos                                     31
#define LCD_PAL188_I1_Msk                                     (0x01UL << LCD_PAL188_I1_Pos)

// ---------------------------------------  LCD_PAL189  -------------------------------------------
#define LCD_PAL189_R04_0_Pos                                  0
#define LCD_PAL189_R04_0_Msk                                  (0x1fUL << LCD_PAL189_R04_0_Pos)
#define LCD_PAL189_G04_0_Pos                                  5
#define LCD_PAL189_G04_0_Msk                                  (0x1fUL << LCD_PAL189_G04_0_Pos)
#define LCD_PAL189_B04_0_Pos                                  10
#define LCD_PAL189_B04_0_Msk                                  (0x1fUL << LCD_PAL189_B04_0_Pos)
#define LCD_PAL189_I0_Pos                                     15
#define LCD_PAL189_I0_Msk                                     (0x01UL << LCD_PAL189_I0_Pos)
#define LCD_PAL189_R14_0_Pos                                  16
#define LCD_PAL189_R14_0_Msk                                  (0x1fUL << LCD_PAL189_R14_0_Pos)
#define LCD_PAL189_G14_0_Pos                                  21
#define LCD_PAL189_G14_0_Msk                                  (0x1fUL << LCD_PAL189_G14_0_Pos)
#define LCD_PAL189_B14_0_Pos                                  26
#define LCD_PAL189_B14_0_Msk                                  (0x1fUL << LCD_PAL189_B14_0_Pos)
#define LCD_PAL189_I1_Pos                                     31
#define LCD_PAL189_I1_Msk                                     (0x01UL << LCD_PAL189_I1_Pos)

// ---------------------------------------  LCD_PAL190  -------------------------------------------
#define LCD_PAL190_R04_0_Pos                                  0
#define LCD_PAL190_R04_0_Msk                                  (0x1fUL << LCD_PAL190_R04_0_Pos)
#define LCD_PAL190_G04_0_Pos                                  5
#define LCD_PAL190_G04_0_Msk                                  (0x1fUL << LCD_PAL190_G04_0_Pos)
#define LCD_PAL190_B04_0_Pos                                  10
#define LCD_PAL190_B04_0_Msk                                  (0x1fUL << LCD_PAL190_B04_0_Pos)
#define LCD_PAL190_I0_Pos                                     15
#define LCD_PAL190_I0_Msk                                     (0x01UL << LCD_PAL190_I0_Pos)
#define LCD_PAL190_R14_0_Pos                                  16
#define LCD_PAL190_R14_0_Msk                                  (0x1fUL << LCD_PAL190_R14_0_Pos)
#define LCD_PAL190_G14_0_Pos                                  21
#define LCD_PAL190_G14_0_Msk                                  (0x1fUL << LCD_PAL190_G14_0_Pos)
#define LCD_PAL190_B14_0_Pos                                  26
#define LCD_PAL190_B14_0_Msk                                  (0x1fUL << LCD_PAL190_B14_0_Pos)
#define LCD_PAL190_I1_Pos                                     31
#define LCD_PAL190_I1_Msk                                     (0x01UL << LCD_PAL190_I1_Pos)

// ---------------------------------------  LCD_PAL191  -------------------------------------------
#define LCD_PAL191_R04_0_Pos                                  0
#define LCD_PAL191_R04_0_Msk                                  (0x1fUL << LCD_PAL191_R04_0_Pos)
#define LCD_PAL191_G04_0_Pos                                  5
#define LCD_PAL191_G04_0_Msk                                  (0x1fUL << LCD_PAL191_G04_0_Pos)
#define LCD_PAL191_B04_0_Pos                                  10
#define LCD_PAL191_B04_0_Msk                                  (0x1fUL << LCD_PAL191_B04_0_Pos)
#define LCD_PAL191_I0_Pos                                     15
#define LCD_PAL191_I0_Msk                                     (0x01UL << LCD_PAL191_I0_Pos)
#define LCD_PAL191_R14_0_Pos                                  16
#define LCD_PAL191_R14_0_Msk                                  (0x1fUL << LCD_PAL191_R14_0_Pos)
#define LCD_PAL191_G14_0_Pos                                  21
#define LCD_PAL191_G14_0_Msk                                  (0x1fUL << LCD_PAL191_G14_0_Pos)
#define LCD_PAL191_B14_0_Pos                                  26
#define LCD_PAL191_B14_0_Msk                                  (0x1fUL << LCD_PAL191_B14_0_Pos)
#define LCD_PAL191_I1_Pos                                     31
#define LCD_PAL191_I1_Msk                                     (0x01UL << LCD_PAL191_I1_Pos)

// ---------------------------------------  LCD_PAL192  -------------------------------------------
#define LCD_PAL192_R04_0_Pos                                  0
#define LCD_PAL192_R04_0_Msk                                  (0x1fUL << LCD_PAL192_R04_0_Pos)
#define LCD_PAL192_G04_0_Pos                                  5
#define LCD_PAL192_G04_0_Msk                                  (0x1fUL << LCD_PAL192_G04_0_Pos)
#define LCD_PAL192_B04_0_Pos                                  10
#define LCD_PAL192_B04_0_Msk                                  (0x1fUL << LCD_PAL192_B04_0_Pos)
#define LCD_PAL192_I0_Pos                                     15
#define LCD_PAL192_I0_Msk                                     (0x01UL << LCD_PAL192_I0_Pos)
#define LCD_PAL192_R14_0_Pos                                  16
#define LCD_PAL192_R14_0_Msk                                  (0x1fUL << LCD_PAL192_R14_0_Pos)
#define LCD_PAL192_G14_0_Pos                                  21
#define LCD_PAL192_G14_0_Msk                                  (0x1fUL << LCD_PAL192_G14_0_Pos)
#define LCD_PAL192_B14_0_Pos                                  26
#define LCD_PAL192_B14_0_Msk                                  (0x1fUL << LCD_PAL192_B14_0_Pos)
#define LCD_PAL192_I1_Pos                                     31
#define LCD_PAL192_I1_Msk                                     (0x01UL << LCD_PAL192_I1_Pos)

// ---------------------------------------  LCD_PAL193  -------------------------------------------
#define LCD_PAL193_R04_0_Pos                                  0
#define LCD_PAL193_R04_0_Msk                                  (0x1fUL << LCD_PAL193_R04_0_Pos)
#define LCD_PAL193_G04_0_Pos                                  5
#define LCD_PAL193_G04_0_Msk                                  (0x1fUL << LCD_PAL193_G04_0_Pos)
#define LCD_PAL193_B04_0_Pos                                  10
#define LCD_PAL193_B04_0_Msk                                  (0x1fUL << LCD_PAL193_B04_0_Pos)
#define LCD_PAL193_I0_Pos                                     15
#define LCD_PAL193_I0_Msk                                     (0x01UL << LCD_PAL193_I0_Pos)
#define LCD_PAL193_R14_0_Pos                                  16
#define LCD_PAL193_R14_0_Msk                                  (0x1fUL << LCD_PAL193_R14_0_Pos)
#define LCD_PAL193_G14_0_Pos                                  21
#define LCD_PAL193_G14_0_Msk                                  (0x1fUL << LCD_PAL193_G14_0_Pos)
#define LCD_PAL193_B14_0_Pos                                  26
#define LCD_PAL193_B14_0_Msk                                  (0x1fUL << LCD_PAL193_B14_0_Pos)
#define LCD_PAL193_I1_Pos                                     31
#define LCD_PAL193_I1_Msk                                     (0x01UL << LCD_PAL193_I1_Pos)

// ---------------------------------------  LCD_PAL194  -------------------------------------------
#define LCD_PAL194_R04_0_Pos                                  0
#define LCD_PAL194_R04_0_Msk                                  (0x1fUL << LCD_PAL194_R04_0_Pos)
#define LCD_PAL194_G04_0_Pos                                  5
#define LCD_PAL194_G04_0_Msk                                  (0x1fUL << LCD_PAL194_G04_0_Pos)
#define LCD_PAL194_B04_0_Pos                                  10
#define LCD_PAL194_B04_0_Msk                                  (0x1fUL << LCD_PAL194_B04_0_Pos)
#define LCD_PAL194_I0_Pos                                     15
#define LCD_PAL194_I0_Msk                                     (0x01UL << LCD_PAL194_I0_Pos)
#define LCD_PAL194_R14_0_Pos                                  16
#define LCD_PAL194_R14_0_Msk                                  (0x1fUL << LCD_PAL194_R14_0_Pos)
#define LCD_PAL194_G14_0_Pos                                  21
#define LCD_PAL194_G14_0_Msk                                  (0x1fUL << LCD_PAL194_G14_0_Pos)
#define LCD_PAL194_B14_0_Pos                                  26
#define LCD_PAL194_B14_0_Msk                                  (0x1fUL << LCD_PAL194_B14_0_Pos)
#define LCD_PAL194_I1_Pos                                     31
#define LCD_PAL194_I1_Msk                                     (0x01UL << LCD_PAL194_I1_Pos)

// ---------------------------------------  LCD_PAL195  -------------------------------------------
#define LCD_PAL195_R04_0_Pos                                  0
#define LCD_PAL195_R04_0_Msk                                  (0x1fUL << LCD_PAL195_R04_0_Pos)
#define LCD_PAL195_G04_0_Pos                                  5
#define LCD_PAL195_G04_0_Msk                                  (0x1fUL << LCD_PAL195_G04_0_Pos)
#define LCD_PAL195_B04_0_Pos                                  10
#define LCD_PAL195_B04_0_Msk                                  (0x1fUL << LCD_PAL195_B04_0_Pos)
#define LCD_PAL195_I0_Pos                                     15
#define LCD_PAL195_I0_Msk                                     (0x01UL << LCD_PAL195_I0_Pos)
#define LCD_PAL195_R14_0_Pos                                  16
#define LCD_PAL195_R14_0_Msk                                  (0x1fUL << LCD_PAL195_R14_0_Pos)
#define LCD_PAL195_G14_0_Pos                                  21
#define LCD_PAL195_G14_0_Msk                                  (0x1fUL << LCD_PAL195_G14_0_Pos)
#define LCD_PAL195_B14_0_Pos                                  26
#define LCD_PAL195_B14_0_Msk                                  (0x1fUL << LCD_PAL195_B14_0_Pos)
#define LCD_PAL195_I1_Pos                                     31
#define LCD_PAL195_I1_Msk                                     (0x01UL << LCD_PAL195_I1_Pos)

// ---------------------------------------  LCD_PAL196  -------------------------------------------
#define LCD_PAL196_R04_0_Pos                                  0
#define LCD_PAL196_R04_0_Msk                                  (0x1fUL << LCD_PAL196_R04_0_Pos)
#define LCD_PAL196_G04_0_Pos                                  5
#define LCD_PAL196_G04_0_Msk                                  (0x1fUL << LCD_PAL196_G04_0_Pos)
#define LCD_PAL196_B04_0_Pos                                  10
#define LCD_PAL196_B04_0_Msk                                  (0x1fUL << LCD_PAL196_B04_0_Pos)
#define LCD_PAL196_I0_Pos                                     15
#define LCD_PAL196_I0_Msk                                     (0x01UL << LCD_PAL196_I0_Pos)
#define LCD_PAL196_R14_0_Pos                                  16
#define LCD_PAL196_R14_0_Msk                                  (0x1fUL << LCD_PAL196_R14_0_Pos)
#define LCD_PAL196_G14_0_Pos                                  21
#define LCD_PAL196_G14_0_Msk                                  (0x1fUL << LCD_PAL196_G14_0_Pos)
#define LCD_PAL196_B14_0_Pos                                  26
#define LCD_PAL196_B14_0_Msk                                  (0x1fUL << LCD_PAL196_B14_0_Pos)
#define LCD_PAL196_I1_Pos                                     31
#define LCD_PAL196_I1_Msk                                     (0x01UL << LCD_PAL196_I1_Pos)

// ---------------------------------------  LCD_PAL197  -------------------------------------------
#define LCD_PAL197_R04_0_Pos                                  0
#define LCD_PAL197_R04_0_Msk                                  (0x1fUL << LCD_PAL197_R04_0_Pos)
#define LCD_PAL197_G04_0_Pos                                  5
#define LCD_PAL197_G04_0_Msk                                  (0x1fUL << LCD_PAL197_G04_0_Pos)
#define LCD_PAL197_B04_0_Pos                                  10
#define LCD_PAL197_B04_0_Msk                                  (0x1fUL << LCD_PAL197_B04_0_Pos)
#define LCD_PAL197_I0_Pos                                     15
#define LCD_PAL197_I0_Msk                                     (0x01UL << LCD_PAL197_I0_Pos)
#define LCD_PAL197_R14_0_Pos                                  16
#define LCD_PAL197_R14_0_Msk                                  (0x1fUL << LCD_PAL197_R14_0_Pos)
#define LCD_PAL197_G14_0_Pos                                  21
#define LCD_PAL197_G14_0_Msk                                  (0x1fUL << LCD_PAL197_G14_0_Pos)
#define LCD_PAL197_B14_0_Pos                                  26
#define LCD_PAL197_B14_0_Msk                                  (0x1fUL << LCD_PAL197_B14_0_Pos)
#define LCD_PAL197_I1_Pos                                     31
#define LCD_PAL197_I1_Msk                                     (0x01UL << LCD_PAL197_I1_Pos)

// ---------------------------------------  LCD_PAL198  -------------------------------------------
#define LCD_PAL198_R04_0_Pos                                  0
#define LCD_PAL198_R04_0_Msk                                  (0x1fUL << LCD_PAL198_R04_0_Pos)
#define LCD_PAL198_G04_0_Pos                                  5
#define LCD_PAL198_G04_0_Msk                                  (0x1fUL << LCD_PAL198_G04_0_Pos)
#define LCD_PAL198_B04_0_Pos                                  10
#define LCD_PAL198_B04_0_Msk                                  (0x1fUL << LCD_PAL198_B04_0_Pos)
#define LCD_PAL198_I0_Pos                                     15
#define LCD_PAL198_I0_Msk                                     (0x01UL << LCD_PAL198_I0_Pos)
#define LCD_PAL198_R14_0_Pos                                  16
#define LCD_PAL198_R14_0_Msk                                  (0x1fUL << LCD_PAL198_R14_0_Pos)
#define LCD_PAL198_G14_0_Pos                                  21
#define LCD_PAL198_G14_0_Msk                                  (0x1fUL << LCD_PAL198_G14_0_Pos)
#define LCD_PAL198_B14_0_Pos                                  26
#define LCD_PAL198_B14_0_Msk                                  (0x1fUL << LCD_PAL198_B14_0_Pos)
#define LCD_PAL198_I1_Pos                                     31
#define LCD_PAL198_I1_Msk                                     (0x01UL << LCD_PAL198_I1_Pos)

// ---------------------------------------  LCD_PAL199  -------------------------------------------
#define LCD_PAL199_R04_0_Pos                                  0
#define LCD_PAL199_R04_0_Msk                                  (0x1fUL << LCD_PAL199_R04_0_Pos)
#define LCD_PAL199_G04_0_Pos                                  5
#define LCD_PAL199_G04_0_Msk                                  (0x1fUL << LCD_PAL199_G04_0_Pos)
#define LCD_PAL199_B04_0_Pos                                  10
#define LCD_PAL199_B04_0_Msk                                  (0x1fUL << LCD_PAL199_B04_0_Pos)
#define LCD_PAL199_I0_Pos                                     15
#define LCD_PAL199_I0_Msk                                     (0x01UL << LCD_PAL199_I0_Pos)
#define LCD_PAL199_R14_0_Pos                                  16
#define LCD_PAL199_R14_0_Msk                                  (0x1fUL << LCD_PAL199_R14_0_Pos)
#define LCD_PAL199_G14_0_Pos                                  21
#define LCD_PAL199_G14_0_Msk                                  (0x1fUL << LCD_PAL199_G14_0_Pos)
#define LCD_PAL199_B14_0_Pos                                  26
#define LCD_PAL199_B14_0_Msk                                  (0x1fUL << LCD_PAL199_B14_0_Pos)
#define LCD_PAL199_I1_Pos                                     31
#define LCD_PAL199_I1_Msk                                     (0x01UL << LCD_PAL199_I1_Pos)

// ---------------------------------------  LCD_PAL200  -------------------------------------------
#define LCD_PAL200_R04_0_Pos                                  0
#define LCD_PAL200_R04_0_Msk                                  (0x1fUL << LCD_PAL200_R04_0_Pos)
#define LCD_PAL200_G04_0_Pos                                  5
#define LCD_PAL200_G04_0_Msk                                  (0x1fUL << LCD_PAL200_G04_0_Pos)
#define LCD_PAL200_B04_0_Pos                                  10
#define LCD_PAL200_B04_0_Msk                                  (0x1fUL << LCD_PAL200_B04_0_Pos)
#define LCD_PAL200_I0_Pos                                     15
#define LCD_PAL200_I0_Msk                                     (0x01UL << LCD_PAL200_I0_Pos)
#define LCD_PAL200_R14_0_Pos                                  16
#define LCD_PAL200_R14_0_Msk                                  (0x1fUL << LCD_PAL200_R14_0_Pos)
#define LCD_PAL200_G14_0_Pos                                  21
#define LCD_PAL200_G14_0_Msk                                  (0x1fUL << LCD_PAL200_G14_0_Pos)
#define LCD_PAL200_B14_0_Pos                                  26
#define LCD_PAL200_B14_0_Msk                                  (0x1fUL << LCD_PAL200_B14_0_Pos)
#define LCD_PAL200_I1_Pos                                     31
#define LCD_PAL200_I1_Msk                                     (0x01UL << LCD_PAL200_I1_Pos)

// ---------------------------------------  LCD_PAL201  -------------------------------------------
#define LCD_PAL201_R04_0_Pos                                  0
#define LCD_PAL201_R04_0_Msk                                  (0x1fUL << LCD_PAL201_R04_0_Pos)
#define LCD_PAL201_G04_0_Pos                                  5
#define LCD_PAL201_G04_0_Msk                                  (0x1fUL << LCD_PAL201_G04_0_Pos)
#define LCD_PAL201_B04_0_Pos                                  10
#define LCD_PAL201_B04_0_Msk                                  (0x1fUL << LCD_PAL201_B04_0_Pos)
#define LCD_PAL201_I0_Pos                                     15
#define LCD_PAL201_I0_Msk                                     (0x01UL << LCD_PAL201_I0_Pos)
#define LCD_PAL201_R14_0_Pos                                  16
#define LCD_PAL201_R14_0_Msk                                  (0x1fUL << LCD_PAL201_R14_0_Pos)
#define LCD_PAL201_G14_0_Pos                                  21
#define LCD_PAL201_G14_0_Msk                                  (0x1fUL << LCD_PAL201_G14_0_Pos)
#define LCD_PAL201_B14_0_Pos                                  26
#define LCD_PAL201_B14_0_Msk                                  (0x1fUL << LCD_PAL201_B14_0_Pos)
#define LCD_PAL201_I1_Pos                                     31
#define LCD_PAL201_I1_Msk                                     (0x01UL << LCD_PAL201_I1_Pos)

// ---------------------------------------  LCD_PAL202  -------------------------------------------
#define LCD_PAL202_R04_0_Pos                                  0
#define LCD_PAL202_R04_0_Msk                                  (0x1fUL << LCD_PAL202_R04_0_Pos)
#define LCD_PAL202_G04_0_Pos                                  5
#define LCD_PAL202_G04_0_Msk                                  (0x1fUL << LCD_PAL202_G04_0_Pos)
#define LCD_PAL202_B04_0_Pos                                  10
#define LCD_PAL202_B04_0_Msk                                  (0x1fUL << LCD_PAL202_B04_0_Pos)
#define LCD_PAL202_I0_Pos                                     15
#define LCD_PAL202_I0_Msk                                     (0x01UL << LCD_PAL202_I0_Pos)
#define LCD_PAL202_R14_0_Pos                                  16
#define LCD_PAL202_R14_0_Msk                                  (0x1fUL << LCD_PAL202_R14_0_Pos)
#define LCD_PAL202_G14_0_Pos                                  21
#define LCD_PAL202_G14_0_Msk                                  (0x1fUL << LCD_PAL202_G14_0_Pos)
#define LCD_PAL202_B14_0_Pos                                  26
#define LCD_PAL202_B14_0_Msk                                  (0x1fUL << LCD_PAL202_B14_0_Pos)
#define LCD_PAL202_I1_Pos                                     31
#define LCD_PAL202_I1_Msk                                     (0x01UL << LCD_PAL202_I1_Pos)

// ---------------------------------------  LCD_PAL203  -------------------------------------------
#define LCD_PAL203_R04_0_Pos                                  0
#define LCD_PAL203_R04_0_Msk                                  (0x1fUL << LCD_PAL203_R04_0_Pos)
#define LCD_PAL203_G04_0_Pos                                  5
#define LCD_PAL203_G04_0_Msk                                  (0x1fUL << LCD_PAL203_G04_0_Pos)
#define LCD_PAL203_B04_0_Pos                                  10
#define LCD_PAL203_B04_0_Msk                                  (0x1fUL << LCD_PAL203_B04_0_Pos)
#define LCD_PAL203_I0_Pos                                     15
#define LCD_PAL203_I0_Msk                                     (0x01UL << LCD_PAL203_I0_Pos)
#define LCD_PAL203_R14_0_Pos                                  16
#define LCD_PAL203_R14_0_Msk                                  (0x1fUL << LCD_PAL203_R14_0_Pos)
#define LCD_PAL203_G14_0_Pos                                  21
#define LCD_PAL203_G14_0_Msk                                  (0x1fUL << LCD_PAL203_G14_0_Pos)
#define LCD_PAL203_B14_0_Pos                                  26
#define LCD_PAL203_B14_0_Msk                                  (0x1fUL << LCD_PAL203_B14_0_Pos)
#define LCD_PAL203_I1_Pos                                     31
#define LCD_PAL203_I1_Msk                                     (0x01UL << LCD_PAL203_I1_Pos)

// ---------------------------------------  LCD_PAL204  -------------------------------------------
#define LCD_PAL204_R04_0_Pos                                  0
#define LCD_PAL204_R04_0_Msk                                  (0x1fUL << LCD_PAL204_R04_0_Pos)
#define LCD_PAL204_G04_0_Pos                                  5
#define LCD_PAL204_G04_0_Msk                                  (0x1fUL << LCD_PAL204_G04_0_Pos)
#define LCD_PAL204_B04_0_Pos                                  10
#define LCD_PAL204_B04_0_Msk                                  (0x1fUL << LCD_PAL204_B04_0_Pos)
#define LCD_PAL204_I0_Pos                                     15
#define LCD_PAL204_I0_Msk                                     (0x01UL << LCD_PAL204_I0_Pos)
#define LCD_PAL204_R14_0_Pos                                  16
#define LCD_PAL204_R14_0_Msk                                  (0x1fUL << LCD_PAL204_R14_0_Pos)
#define LCD_PAL204_G14_0_Pos                                  21
#define LCD_PAL204_G14_0_Msk                                  (0x1fUL << LCD_PAL204_G14_0_Pos)
#define LCD_PAL204_B14_0_Pos                                  26
#define LCD_PAL204_B14_0_Msk                                  (0x1fUL << LCD_PAL204_B14_0_Pos)
#define LCD_PAL204_I1_Pos                                     31
#define LCD_PAL204_I1_Msk                                     (0x01UL << LCD_PAL204_I1_Pos)

// ---------------------------------------  LCD_PAL205  -------------------------------------------
#define LCD_PAL205_R04_0_Pos                                  0
#define LCD_PAL205_R04_0_Msk                                  (0x1fUL << LCD_PAL205_R04_0_Pos)
#define LCD_PAL205_G04_0_Pos                                  5
#define LCD_PAL205_G04_0_Msk                                  (0x1fUL << LCD_PAL205_G04_0_Pos)
#define LCD_PAL205_B04_0_Pos                                  10
#define LCD_PAL205_B04_0_Msk                                  (0x1fUL << LCD_PAL205_B04_0_Pos)
#define LCD_PAL205_I0_Pos                                     15
#define LCD_PAL205_I0_Msk                                     (0x01UL << LCD_PAL205_I0_Pos)
#define LCD_PAL205_R14_0_Pos                                  16
#define LCD_PAL205_R14_0_Msk                                  (0x1fUL << LCD_PAL205_R14_0_Pos)
#define LCD_PAL205_G14_0_Pos                                  21
#define LCD_PAL205_G14_0_Msk                                  (0x1fUL << LCD_PAL205_G14_0_Pos)
#define LCD_PAL205_B14_0_Pos                                  26
#define LCD_PAL205_B14_0_Msk                                  (0x1fUL << LCD_PAL205_B14_0_Pos)
#define LCD_PAL205_I1_Pos                                     31
#define LCD_PAL205_I1_Msk                                     (0x01UL << LCD_PAL205_I1_Pos)

// ---------------------------------------  LCD_PAL206  -------------------------------------------
#define LCD_PAL206_R04_0_Pos                                  0
#define LCD_PAL206_R04_0_Msk                                  (0x1fUL << LCD_PAL206_R04_0_Pos)
#define LCD_PAL206_G04_0_Pos                                  5
#define LCD_PAL206_G04_0_Msk                                  (0x1fUL << LCD_PAL206_G04_0_Pos)
#define LCD_PAL206_B04_0_Pos                                  10
#define LCD_PAL206_B04_0_Msk                                  (0x1fUL << LCD_PAL206_B04_0_Pos)
#define LCD_PAL206_I0_Pos                                     15
#define LCD_PAL206_I0_Msk                                     (0x01UL << LCD_PAL206_I0_Pos)
#define LCD_PAL206_R14_0_Pos                                  16
#define LCD_PAL206_R14_0_Msk                                  (0x1fUL << LCD_PAL206_R14_0_Pos)
#define LCD_PAL206_G14_0_Pos                                  21
#define LCD_PAL206_G14_0_Msk                                  (0x1fUL << LCD_PAL206_G14_0_Pos)
#define LCD_PAL206_B14_0_Pos                                  26
#define LCD_PAL206_B14_0_Msk                                  (0x1fUL << LCD_PAL206_B14_0_Pos)
#define LCD_PAL206_I1_Pos                                     31
#define LCD_PAL206_I1_Msk                                     (0x01UL << LCD_PAL206_I1_Pos)

// ---------------------------------------  LCD_PAL207  -------------------------------------------
#define LCD_PAL207_R04_0_Pos                                  0
#define LCD_PAL207_R04_0_Msk                                  (0x1fUL << LCD_PAL207_R04_0_Pos)
#define LCD_PAL207_G04_0_Pos                                  5
#define LCD_PAL207_G04_0_Msk                                  (0x1fUL << LCD_PAL207_G04_0_Pos)
#define LCD_PAL207_B04_0_Pos                                  10
#define LCD_PAL207_B04_0_Msk                                  (0x1fUL << LCD_PAL207_B04_0_Pos)
#define LCD_PAL207_I0_Pos                                     15
#define LCD_PAL207_I0_Msk                                     (0x01UL << LCD_PAL207_I0_Pos)
#define LCD_PAL207_R14_0_Pos                                  16
#define LCD_PAL207_R14_0_Msk                                  (0x1fUL << LCD_PAL207_R14_0_Pos)
#define LCD_PAL207_G14_0_Pos                                  21
#define LCD_PAL207_G14_0_Msk                                  (0x1fUL << LCD_PAL207_G14_0_Pos)
#define LCD_PAL207_B14_0_Pos                                  26
#define LCD_PAL207_B14_0_Msk                                  (0x1fUL << LCD_PAL207_B14_0_Pos)
#define LCD_PAL207_I1_Pos                                     31
#define LCD_PAL207_I1_Msk                                     (0x01UL << LCD_PAL207_I1_Pos)

// ---------------------------------------  LCD_PAL208  -------------------------------------------
#define LCD_PAL208_R04_0_Pos                                  0
#define LCD_PAL208_R04_0_Msk                                  (0x1fUL << LCD_PAL208_R04_0_Pos)
#define LCD_PAL208_G04_0_Pos                                  5
#define LCD_PAL208_G04_0_Msk                                  (0x1fUL << LCD_PAL208_G04_0_Pos)
#define LCD_PAL208_B04_0_Pos                                  10
#define LCD_PAL208_B04_0_Msk                                  (0x1fUL << LCD_PAL208_B04_0_Pos)
#define LCD_PAL208_I0_Pos                                     15
#define LCD_PAL208_I0_Msk                                     (0x01UL << LCD_PAL208_I0_Pos)
#define LCD_PAL208_R14_0_Pos                                  16
#define LCD_PAL208_R14_0_Msk                                  (0x1fUL << LCD_PAL208_R14_0_Pos)
#define LCD_PAL208_G14_0_Pos                                  21
#define LCD_PAL208_G14_0_Msk                                  (0x1fUL << LCD_PAL208_G14_0_Pos)
#define LCD_PAL208_B14_0_Pos                                  26
#define LCD_PAL208_B14_0_Msk                                  (0x1fUL << LCD_PAL208_B14_0_Pos)
#define LCD_PAL208_I1_Pos                                     31
#define LCD_PAL208_I1_Msk                                     (0x01UL << LCD_PAL208_I1_Pos)

// ---------------------------------------  LCD_PAL209  -------------------------------------------
#define LCD_PAL209_R04_0_Pos                                  0
#define LCD_PAL209_R04_0_Msk                                  (0x1fUL << LCD_PAL209_R04_0_Pos)
#define LCD_PAL209_G04_0_Pos                                  5
#define LCD_PAL209_G04_0_Msk                                  (0x1fUL << LCD_PAL209_G04_0_Pos)
#define LCD_PAL209_B04_0_Pos                                  10
#define LCD_PAL209_B04_0_Msk                                  (0x1fUL << LCD_PAL209_B04_0_Pos)
#define LCD_PAL209_I0_Pos                                     15
#define LCD_PAL209_I0_Msk                                     (0x01UL << LCD_PAL209_I0_Pos)
#define LCD_PAL209_R14_0_Pos                                  16
#define LCD_PAL209_R14_0_Msk                                  (0x1fUL << LCD_PAL209_R14_0_Pos)
#define LCD_PAL209_G14_0_Pos                                  21
#define LCD_PAL209_G14_0_Msk                                  (0x1fUL << LCD_PAL209_G14_0_Pos)
#define LCD_PAL209_B14_0_Pos                                  26
#define LCD_PAL209_B14_0_Msk                                  (0x1fUL << LCD_PAL209_B14_0_Pos)
#define LCD_PAL209_I1_Pos                                     31
#define LCD_PAL209_I1_Msk                                     (0x01UL << LCD_PAL209_I1_Pos)

// ---------------------------------------  LCD_PAL210  -------------------------------------------
#define LCD_PAL210_R04_0_Pos                                  0
#define LCD_PAL210_R04_0_Msk                                  (0x1fUL << LCD_PAL210_R04_0_Pos)
#define LCD_PAL210_G04_0_Pos                                  5
#define LCD_PAL210_G04_0_Msk                                  (0x1fUL << LCD_PAL210_G04_0_Pos)
#define LCD_PAL210_B04_0_Pos                                  10
#define LCD_PAL210_B04_0_Msk                                  (0x1fUL << LCD_PAL210_B04_0_Pos)
#define LCD_PAL210_I0_Pos                                     15
#define LCD_PAL210_I0_Msk                                     (0x01UL << LCD_PAL210_I0_Pos)
#define LCD_PAL210_R14_0_Pos                                  16
#define LCD_PAL210_R14_0_Msk                                  (0x1fUL << LCD_PAL210_R14_0_Pos)
#define LCD_PAL210_G14_0_Pos                                  21
#define LCD_PAL210_G14_0_Msk                                  (0x1fUL << LCD_PAL210_G14_0_Pos)
#define LCD_PAL210_B14_0_Pos                                  26
#define LCD_PAL210_B14_0_Msk                                  (0x1fUL << LCD_PAL210_B14_0_Pos)
#define LCD_PAL210_I1_Pos                                     31
#define LCD_PAL210_I1_Msk                                     (0x01UL << LCD_PAL210_I1_Pos)

// ---------------------------------------  LCD_PAL211  -------------------------------------------
#define LCD_PAL211_R04_0_Pos                                  0
#define LCD_PAL211_R04_0_Msk                                  (0x1fUL << LCD_PAL211_R04_0_Pos)
#define LCD_PAL211_G04_0_Pos                                  5
#define LCD_PAL211_G04_0_Msk                                  (0x1fUL << LCD_PAL211_G04_0_Pos)
#define LCD_PAL211_B04_0_Pos                                  10
#define LCD_PAL211_B04_0_Msk                                  (0x1fUL << LCD_PAL211_B04_0_Pos)
#define LCD_PAL211_I0_Pos                                     15
#define LCD_PAL211_I0_Msk                                     (0x01UL << LCD_PAL211_I0_Pos)
#define LCD_PAL211_R14_0_Pos                                  16
#define LCD_PAL211_R14_0_Msk                                  (0x1fUL << LCD_PAL211_R14_0_Pos)
#define LCD_PAL211_G14_0_Pos                                  21
#define LCD_PAL211_G14_0_Msk                                  (0x1fUL << LCD_PAL211_G14_0_Pos)
#define LCD_PAL211_B14_0_Pos                                  26
#define LCD_PAL211_B14_0_Msk                                  (0x1fUL << LCD_PAL211_B14_0_Pos)
#define LCD_PAL211_I1_Pos                                     31
#define LCD_PAL211_I1_Msk                                     (0x01UL << LCD_PAL211_I1_Pos)

// ---------------------------------------  LCD_PAL212  -------------------------------------------
#define LCD_PAL212_R04_0_Pos                                  0
#define LCD_PAL212_R04_0_Msk                                  (0x1fUL << LCD_PAL212_R04_0_Pos)
#define LCD_PAL212_G04_0_Pos                                  5
#define LCD_PAL212_G04_0_Msk                                  (0x1fUL << LCD_PAL212_G04_0_Pos)
#define LCD_PAL212_B04_0_Pos                                  10
#define LCD_PAL212_B04_0_Msk                                  (0x1fUL << LCD_PAL212_B04_0_Pos)
#define LCD_PAL212_I0_Pos                                     15
#define LCD_PAL212_I0_Msk                                     (0x01UL << LCD_PAL212_I0_Pos)
#define LCD_PAL212_R14_0_Pos                                  16
#define LCD_PAL212_R14_0_Msk                                  (0x1fUL << LCD_PAL212_R14_0_Pos)
#define LCD_PAL212_G14_0_Pos                                  21
#define LCD_PAL212_G14_0_Msk                                  (0x1fUL << LCD_PAL212_G14_0_Pos)
#define LCD_PAL212_B14_0_Pos                                  26
#define LCD_PAL212_B14_0_Msk                                  (0x1fUL << LCD_PAL212_B14_0_Pos)
#define LCD_PAL212_I1_Pos                                     31
#define LCD_PAL212_I1_Msk                                     (0x01UL << LCD_PAL212_I1_Pos)

// ---------------------------------------  LCD_PAL213  -------------------------------------------
#define LCD_PAL213_R04_0_Pos                                  0
#define LCD_PAL213_R04_0_Msk                                  (0x1fUL << LCD_PAL213_R04_0_Pos)
#define LCD_PAL213_G04_0_Pos                                  5
#define LCD_PAL213_G04_0_Msk                                  (0x1fUL << LCD_PAL213_G04_0_Pos)
#define LCD_PAL213_B04_0_Pos                                  10
#define LCD_PAL213_B04_0_Msk                                  (0x1fUL << LCD_PAL213_B04_0_Pos)
#define LCD_PAL213_I0_Pos                                     15
#define LCD_PAL213_I0_Msk                                     (0x01UL << LCD_PAL213_I0_Pos)
#define LCD_PAL213_R14_0_Pos                                  16
#define LCD_PAL213_R14_0_Msk                                  (0x1fUL << LCD_PAL213_R14_0_Pos)
#define LCD_PAL213_G14_0_Pos                                  21
#define LCD_PAL213_G14_0_Msk                                  (0x1fUL << LCD_PAL213_G14_0_Pos)
#define LCD_PAL213_B14_0_Pos                                  26
#define LCD_PAL213_B14_0_Msk                                  (0x1fUL << LCD_PAL213_B14_0_Pos)
#define LCD_PAL213_I1_Pos                                     31
#define LCD_PAL213_I1_Msk                                     (0x01UL << LCD_PAL213_I1_Pos)

// ---------------------------------------  LCD_PAL214  -------------------------------------------
#define LCD_PAL214_R04_0_Pos                                  0
#define LCD_PAL214_R04_0_Msk                                  (0x1fUL << LCD_PAL214_R04_0_Pos)
#define LCD_PAL214_G04_0_Pos                                  5
#define LCD_PAL214_G04_0_Msk                                  (0x1fUL << LCD_PAL214_G04_0_Pos)
#define LCD_PAL214_B04_0_Pos                                  10
#define LCD_PAL214_B04_0_Msk                                  (0x1fUL << LCD_PAL214_B04_0_Pos)
#define LCD_PAL214_I0_Pos                                     15
#define LCD_PAL214_I0_Msk                                     (0x01UL << LCD_PAL214_I0_Pos)
#define LCD_PAL214_R14_0_Pos                                  16
#define LCD_PAL214_R14_0_Msk                                  (0x1fUL << LCD_PAL214_R14_0_Pos)
#define LCD_PAL214_G14_0_Pos                                  21
#define LCD_PAL214_G14_0_Msk                                  (0x1fUL << LCD_PAL214_G14_0_Pos)
#define LCD_PAL214_B14_0_Pos                                  26
#define LCD_PAL214_B14_0_Msk                                  (0x1fUL << LCD_PAL214_B14_0_Pos)
#define LCD_PAL214_I1_Pos                                     31
#define LCD_PAL214_I1_Msk                                     (0x01UL << LCD_PAL214_I1_Pos)

// ---------------------------------------  LCD_PAL215  -------------------------------------------
#define LCD_PAL215_R04_0_Pos                                  0
#define LCD_PAL215_R04_0_Msk                                  (0x1fUL << LCD_PAL215_R04_0_Pos)
#define LCD_PAL215_G04_0_Pos                                  5
#define LCD_PAL215_G04_0_Msk                                  (0x1fUL << LCD_PAL215_G04_0_Pos)
#define LCD_PAL215_B04_0_Pos                                  10
#define LCD_PAL215_B04_0_Msk                                  (0x1fUL << LCD_PAL215_B04_0_Pos)
#define LCD_PAL215_I0_Pos                                     15
#define LCD_PAL215_I0_Msk                                     (0x01UL << LCD_PAL215_I0_Pos)
#define LCD_PAL215_R14_0_Pos                                  16
#define LCD_PAL215_R14_0_Msk                                  (0x1fUL << LCD_PAL215_R14_0_Pos)
#define LCD_PAL215_G14_0_Pos                                  21
#define LCD_PAL215_G14_0_Msk                                  (0x1fUL << LCD_PAL215_G14_0_Pos)
#define LCD_PAL215_B14_0_Pos                                  26
#define LCD_PAL215_B14_0_Msk                                  (0x1fUL << LCD_PAL215_B14_0_Pos)
#define LCD_PAL215_I1_Pos                                     31
#define LCD_PAL215_I1_Msk                                     (0x01UL << LCD_PAL215_I1_Pos)

// ---------------------------------------  LCD_PAL216  -------------------------------------------
#define LCD_PAL216_R04_0_Pos                                  0
#define LCD_PAL216_R04_0_Msk                                  (0x1fUL << LCD_PAL216_R04_0_Pos)
#define LCD_PAL216_G04_0_Pos                                  5
#define LCD_PAL216_G04_0_Msk                                  (0x1fUL << LCD_PAL216_G04_0_Pos)
#define LCD_PAL216_B04_0_Pos                                  10
#define LCD_PAL216_B04_0_Msk                                  (0x1fUL << LCD_PAL216_B04_0_Pos)
#define LCD_PAL216_I0_Pos                                     15
#define LCD_PAL216_I0_Msk                                     (0x01UL << LCD_PAL216_I0_Pos)
#define LCD_PAL216_R14_0_Pos                                  16
#define LCD_PAL216_R14_0_Msk                                  (0x1fUL << LCD_PAL216_R14_0_Pos)
#define LCD_PAL216_G14_0_Pos                                  21
#define LCD_PAL216_G14_0_Msk                                  (0x1fUL << LCD_PAL216_G14_0_Pos)
#define LCD_PAL216_B14_0_Pos                                  26
#define LCD_PAL216_B14_0_Msk                                  (0x1fUL << LCD_PAL216_B14_0_Pos)
#define LCD_PAL216_I1_Pos                                     31
#define LCD_PAL216_I1_Msk                                     (0x01UL << LCD_PAL216_I1_Pos)

// ---------------------------------------  LCD_PAL217  -------------------------------------------
#define LCD_PAL217_R04_0_Pos                                  0
#define LCD_PAL217_R04_0_Msk                                  (0x1fUL << LCD_PAL217_R04_0_Pos)
#define LCD_PAL217_G04_0_Pos                                  5
#define LCD_PAL217_G04_0_Msk                                  (0x1fUL << LCD_PAL217_G04_0_Pos)
#define LCD_PAL217_B04_0_Pos                                  10
#define LCD_PAL217_B04_0_Msk                                  (0x1fUL << LCD_PAL217_B04_0_Pos)
#define LCD_PAL217_I0_Pos                                     15
#define LCD_PAL217_I0_Msk                                     (0x01UL << LCD_PAL217_I0_Pos)
#define LCD_PAL217_R14_0_Pos                                  16
#define LCD_PAL217_R14_0_Msk                                  (0x1fUL << LCD_PAL217_R14_0_Pos)
#define LCD_PAL217_G14_0_Pos                                  21
#define LCD_PAL217_G14_0_Msk                                  (0x1fUL << LCD_PAL217_G14_0_Pos)
#define LCD_PAL217_B14_0_Pos                                  26
#define LCD_PAL217_B14_0_Msk                                  (0x1fUL << LCD_PAL217_B14_0_Pos)
#define LCD_PAL217_I1_Pos                                     31
#define LCD_PAL217_I1_Msk                                     (0x01UL << LCD_PAL217_I1_Pos)

// ---------------------------------------  LCD_PAL218  -------------------------------------------
#define LCD_PAL218_R04_0_Pos                                  0
#define LCD_PAL218_R04_0_Msk                                  (0x1fUL << LCD_PAL218_R04_0_Pos)
#define LCD_PAL218_G04_0_Pos                                  5
#define LCD_PAL218_G04_0_Msk                                  (0x1fUL << LCD_PAL218_G04_0_Pos)
#define LCD_PAL218_B04_0_Pos                                  10
#define LCD_PAL218_B04_0_Msk                                  (0x1fUL << LCD_PAL218_B04_0_Pos)
#define LCD_PAL218_I0_Pos                                     15
#define LCD_PAL218_I0_Msk                                     (0x01UL << LCD_PAL218_I0_Pos)
#define LCD_PAL218_R14_0_Pos                                  16
#define LCD_PAL218_R14_0_Msk                                  (0x1fUL << LCD_PAL218_R14_0_Pos)
#define LCD_PAL218_G14_0_Pos                                  21
#define LCD_PAL218_G14_0_Msk                                  (0x1fUL << LCD_PAL218_G14_0_Pos)
#define LCD_PAL218_B14_0_Pos                                  26
#define LCD_PAL218_B14_0_Msk                                  (0x1fUL << LCD_PAL218_B14_0_Pos)
#define LCD_PAL218_I1_Pos                                     31
#define LCD_PAL218_I1_Msk                                     (0x01UL << LCD_PAL218_I1_Pos)

// ---------------------------------------  LCD_PAL219  -------------------------------------------
#define LCD_PAL219_R04_0_Pos                                  0
#define LCD_PAL219_R04_0_Msk                                  (0x1fUL << LCD_PAL219_R04_0_Pos)
#define LCD_PAL219_G04_0_Pos                                  5
#define LCD_PAL219_G04_0_Msk                                  (0x1fUL << LCD_PAL219_G04_0_Pos)
#define LCD_PAL219_B04_0_Pos                                  10
#define LCD_PAL219_B04_0_Msk                                  (0x1fUL << LCD_PAL219_B04_0_Pos)
#define LCD_PAL219_I0_Pos                                     15
#define LCD_PAL219_I0_Msk                                     (0x01UL << LCD_PAL219_I0_Pos)
#define LCD_PAL219_R14_0_Pos                                  16
#define LCD_PAL219_R14_0_Msk                                  (0x1fUL << LCD_PAL219_R14_0_Pos)
#define LCD_PAL219_G14_0_Pos                                  21
#define LCD_PAL219_G14_0_Msk                                  (0x1fUL << LCD_PAL219_G14_0_Pos)
#define LCD_PAL219_B14_0_Pos                                  26
#define LCD_PAL219_B14_0_Msk                                  (0x1fUL << LCD_PAL219_B14_0_Pos)
#define LCD_PAL219_I1_Pos                                     31
#define LCD_PAL219_I1_Msk                                     (0x01UL << LCD_PAL219_I1_Pos)

// ---------------------------------------  LCD_PAL220  -------------------------------------------
#define LCD_PAL220_R04_0_Pos                                  0
#define LCD_PAL220_R04_0_Msk                                  (0x1fUL << LCD_PAL220_R04_0_Pos)
#define LCD_PAL220_G04_0_Pos                                  5
#define LCD_PAL220_G04_0_Msk                                  (0x1fUL << LCD_PAL220_G04_0_Pos)
#define LCD_PAL220_B04_0_Pos                                  10
#define LCD_PAL220_B04_0_Msk                                  (0x1fUL << LCD_PAL220_B04_0_Pos)
#define LCD_PAL220_I0_Pos                                     15
#define LCD_PAL220_I0_Msk                                     (0x01UL << LCD_PAL220_I0_Pos)
#define LCD_PAL220_R14_0_Pos                                  16
#define LCD_PAL220_R14_0_Msk                                  (0x1fUL << LCD_PAL220_R14_0_Pos)
#define LCD_PAL220_G14_0_Pos                                  21
#define LCD_PAL220_G14_0_Msk                                  (0x1fUL << LCD_PAL220_G14_0_Pos)
#define LCD_PAL220_B14_0_Pos                                  26
#define LCD_PAL220_B14_0_Msk                                  (0x1fUL << LCD_PAL220_B14_0_Pos)
#define LCD_PAL220_I1_Pos                                     31
#define LCD_PAL220_I1_Msk                                     (0x01UL << LCD_PAL220_I1_Pos)

// ---------------------------------------  LCD_PAL221  -------------------------------------------
#define LCD_PAL221_R04_0_Pos                                  0
#define LCD_PAL221_R04_0_Msk                                  (0x1fUL << LCD_PAL221_R04_0_Pos)
#define LCD_PAL221_G04_0_Pos                                  5
#define LCD_PAL221_G04_0_Msk                                  (0x1fUL << LCD_PAL221_G04_0_Pos)
#define LCD_PAL221_B04_0_Pos                                  10
#define LCD_PAL221_B04_0_Msk                                  (0x1fUL << LCD_PAL221_B04_0_Pos)
#define LCD_PAL221_I0_Pos                                     15
#define LCD_PAL221_I0_Msk                                     (0x01UL << LCD_PAL221_I0_Pos)
#define LCD_PAL221_R14_0_Pos                                  16
#define LCD_PAL221_R14_0_Msk                                  (0x1fUL << LCD_PAL221_R14_0_Pos)
#define LCD_PAL221_G14_0_Pos                                  21
#define LCD_PAL221_G14_0_Msk                                  (0x1fUL << LCD_PAL221_G14_0_Pos)
#define LCD_PAL221_B14_0_Pos                                  26
#define LCD_PAL221_B14_0_Msk                                  (0x1fUL << LCD_PAL221_B14_0_Pos)
#define LCD_PAL221_I1_Pos                                     31
#define LCD_PAL221_I1_Msk                                     (0x01UL << LCD_PAL221_I1_Pos)

// ---------------------------------------  LCD_PAL222  -------------------------------------------
#define LCD_PAL222_R04_0_Pos                                  0
#define LCD_PAL222_R04_0_Msk                                  (0x1fUL << LCD_PAL222_R04_0_Pos)
#define LCD_PAL222_G04_0_Pos                                  5
#define LCD_PAL222_G04_0_Msk                                  (0x1fUL << LCD_PAL222_G04_0_Pos)
#define LCD_PAL222_B04_0_Pos                                  10
#define LCD_PAL222_B04_0_Msk                                  (0x1fUL << LCD_PAL222_B04_0_Pos)
#define LCD_PAL222_I0_Pos                                     15
#define LCD_PAL222_I0_Msk                                     (0x01UL << LCD_PAL222_I0_Pos)
#define LCD_PAL222_R14_0_Pos                                  16
#define LCD_PAL222_R14_0_Msk                                  (0x1fUL << LCD_PAL222_R14_0_Pos)
#define LCD_PAL222_G14_0_Pos                                  21
#define LCD_PAL222_G14_0_Msk                                  (0x1fUL << LCD_PAL222_G14_0_Pos)
#define LCD_PAL222_B14_0_Pos                                  26
#define LCD_PAL222_B14_0_Msk                                  (0x1fUL << LCD_PAL222_B14_0_Pos)
#define LCD_PAL222_I1_Pos                                     31
#define LCD_PAL222_I1_Msk                                     (0x01UL << LCD_PAL222_I1_Pos)

// ---------------------------------------  LCD_PAL223  -------------------------------------------
#define LCD_PAL223_R04_0_Pos                                  0
#define LCD_PAL223_R04_0_Msk                                  (0x1fUL << LCD_PAL223_R04_0_Pos)
#define LCD_PAL223_G04_0_Pos                                  5
#define LCD_PAL223_G04_0_Msk                                  (0x1fUL << LCD_PAL223_G04_0_Pos)
#define LCD_PAL223_B04_0_Pos                                  10
#define LCD_PAL223_B04_0_Msk                                  (0x1fUL << LCD_PAL223_B04_0_Pos)
#define LCD_PAL223_I0_Pos                                     15
#define LCD_PAL223_I0_Msk                                     (0x01UL << LCD_PAL223_I0_Pos)
#define LCD_PAL223_R14_0_Pos                                  16
#define LCD_PAL223_R14_0_Msk                                  (0x1fUL << LCD_PAL223_R14_0_Pos)
#define LCD_PAL223_G14_0_Pos                                  21
#define LCD_PAL223_G14_0_Msk                                  (0x1fUL << LCD_PAL223_G14_0_Pos)
#define LCD_PAL223_B14_0_Pos                                  26
#define LCD_PAL223_B14_0_Msk                                  (0x1fUL << LCD_PAL223_B14_0_Pos)
#define LCD_PAL223_I1_Pos                                     31
#define LCD_PAL223_I1_Msk                                     (0x01UL << LCD_PAL223_I1_Pos)

// ---------------------------------------  LCD_PAL224  -------------------------------------------
#define LCD_PAL224_R04_0_Pos                                  0
#define LCD_PAL224_R04_0_Msk                                  (0x1fUL << LCD_PAL224_R04_0_Pos)
#define LCD_PAL224_G04_0_Pos                                  5
#define LCD_PAL224_G04_0_Msk                                  (0x1fUL << LCD_PAL224_G04_0_Pos)
#define LCD_PAL224_B04_0_Pos                                  10
#define LCD_PAL224_B04_0_Msk                                  (0x1fUL << LCD_PAL224_B04_0_Pos)
#define LCD_PAL224_I0_Pos                                     15
#define LCD_PAL224_I0_Msk                                     (0x01UL << LCD_PAL224_I0_Pos)
#define LCD_PAL224_R14_0_Pos                                  16
#define LCD_PAL224_R14_0_Msk                                  (0x1fUL << LCD_PAL224_R14_0_Pos)
#define LCD_PAL224_G14_0_Pos                                  21
#define LCD_PAL224_G14_0_Msk                                  (0x1fUL << LCD_PAL224_G14_0_Pos)
#define LCD_PAL224_B14_0_Pos                                  26
#define LCD_PAL224_B14_0_Msk                                  (0x1fUL << LCD_PAL224_B14_0_Pos)
#define LCD_PAL224_I1_Pos                                     31
#define LCD_PAL224_I1_Msk                                     (0x01UL << LCD_PAL224_I1_Pos)

// ---------------------------------------  LCD_PAL225  -------------------------------------------
#define LCD_PAL225_R04_0_Pos                                  0
#define LCD_PAL225_R04_0_Msk                                  (0x1fUL << LCD_PAL225_R04_0_Pos)
#define LCD_PAL225_G04_0_Pos                                  5
#define LCD_PAL225_G04_0_Msk                                  (0x1fUL << LCD_PAL225_G04_0_Pos)
#define LCD_PAL225_B04_0_Pos                                  10
#define LCD_PAL225_B04_0_Msk                                  (0x1fUL << LCD_PAL225_B04_0_Pos)
#define LCD_PAL225_I0_Pos                                     15
#define LCD_PAL225_I0_Msk                                     (0x01UL << LCD_PAL225_I0_Pos)
#define LCD_PAL225_R14_0_Pos                                  16
#define LCD_PAL225_R14_0_Msk                                  (0x1fUL << LCD_PAL225_R14_0_Pos)
#define LCD_PAL225_G14_0_Pos                                  21
#define LCD_PAL225_G14_0_Msk                                  (0x1fUL << LCD_PAL225_G14_0_Pos)
#define LCD_PAL225_B14_0_Pos                                  26
#define LCD_PAL225_B14_0_Msk                                  (0x1fUL << LCD_PAL225_B14_0_Pos)
#define LCD_PAL225_I1_Pos                                     31
#define LCD_PAL225_I1_Msk                                     (0x01UL << LCD_PAL225_I1_Pos)

// ---------------------------------------  LCD_PAL226  -------------------------------------------
#define LCD_PAL226_R04_0_Pos                                  0
#define LCD_PAL226_R04_0_Msk                                  (0x1fUL << LCD_PAL226_R04_0_Pos)
#define LCD_PAL226_G04_0_Pos                                  5
#define LCD_PAL226_G04_0_Msk                                  (0x1fUL << LCD_PAL226_G04_0_Pos)
#define LCD_PAL226_B04_0_Pos                                  10
#define LCD_PAL226_B04_0_Msk                                  (0x1fUL << LCD_PAL226_B04_0_Pos)
#define LCD_PAL226_I0_Pos                                     15
#define LCD_PAL226_I0_Msk                                     (0x01UL << LCD_PAL226_I0_Pos)
#define LCD_PAL226_R14_0_Pos                                  16
#define LCD_PAL226_R14_0_Msk                                  (0x1fUL << LCD_PAL226_R14_0_Pos)
#define LCD_PAL226_G14_0_Pos                                  21
#define LCD_PAL226_G14_0_Msk                                  (0x1fUL << LCD_PAL226_G14_0_Pos)
#define LCD_PAL226_B14_0_Pos                                  26
#define LCD_PAL226_B14_0_Msk                                  (0x1fUL << LCD_PAL226_B14_0_Pos)
#define LCD_PAL226_I1_Pos                                     31
#define LCD_PAL226_I1_Msk                                     (0x01UL << LCD_PAL226_I1_Pos)

// ---------------------------------------  LCD_PAL227  -------------------------------------------
#define LCD_PAL227_R04_0_Pos                                  0
#define LCD_PAL227_R04_0_Msk                                  (0x1fUL << LCD_PAL227_R04_0_Pos)
#define LCD_PAL227_G04_0_Pos                                  5
#define LCD_PAL227_G04_0_Msk                                  (0x1fUL << LCD_PAL227_G04_0_Pos)
#define LCD_PAL227_B04_0_Pos                                  10
#define LCD_PAL227_B04_0_Msk                                  (0x1fUL << LCD_PAL227_B04_0_Pos)
#define LCD_PAL227_I0_Pos                                     15
#define LCD_PAL227_I0_Msk                                     (0x01UL << LCD_PAL227_I0_Pos)
#define LCD_PAL227_R14_0_Pos                                  16
#define LCD_PAL227_R14_0_Msk                                  (0x1fUL << LCD_PAL227_R14_0_Pos)
#define LCD_PAL227_G14_0_Pos                                  21
#define LCD_PAL227_G14_0_Msk                                  (0x1fUL << LCD_PAL227_G14_0_Pos)
#define LCD_PAL227_B14_0_Pos                                  26
#define LCD_PAL227_B14_0_Msk                                  (0x1fUL << LCD_PAL227_B14_0_Pos)
#define LCD_PAL227_I1_Pos                                     31
#define LCD_PAL227_I1_Msk                                     (0x01UL << LCD_PAL227_I1_Pos)

// ---------------------------------------  LCD_PAL228  -------------------------------------------
#define LCD_PAL228_R04_0_Pos                                  0
#define LCD_PAL228_R04_0_Msk                                  (0x1fUL << LCD_PAL228_R04_0_Pos)
#define LCD_PAL228_G04_0_Pos                                  5
#define LCD_PAL228_G04_0_Msk                                  (0x1fUL << LCD_PAL228_G04_0_Pos)
#define LCD_PAL228_B04_0_Pos                                  10
#define LCD_PAL228_B04_0_Msk                                  (0x1fUL << LCD_PAL228_B04_0_Pos)
#define LCD_PAL228_I0_Pos                                     15
#define LCD_PAL228_I0_Msk                                     (0x01UL << LCD_PAL228_I0_Pos)
#define LCD_PAL228_R14_0_Pos                                  16
#define LCD_PAL228_R14_0_Msk                                  (0x1fUL << LCD_PAL228_R14_0_Pos)
#define LCD_PAL228_G14_0_Pos                                  21
#define LCD_PAL228_G14_0_Msk                                  (0x1fUL << LCD_PAL228_G14_0_Pos)
#define LCD_PAL228_B14_0_Pos                                  26
#define LCD_PAL228_B14_0_Msk                                  (0x1fUL << LCD_PAL228_B14_0_Pos)
#define LCD_PAL228_I1_Pos                                     31
#define LCD_PAL228_I1_Msk                                     (0x01UL << LCD_PAL228_I1_Pos)

// ---------------------------------------  LCD_PAL229  -------------------------------------------
#define LCD_PAL229_R04_0_Pos                                  0
#define LCD_PAL229_R04_0_Msk                                  (0x1fUL << LCD_PAL229_R04_0_Pos)
#define LCD_PAL229_G04_0_Pos                                  5
#define LCD_PAL229_G04_0_Msk                                  (0x1fUL << LCD_PAL229_G04_0_Pos)
#define LCD_PAL229_B04_0_Pos                                  10
#define LCD_PAL229_B04_0_Msk                                  (0x1fUL << LCD_PAL229_B04_0_Pos)
#define LCD_PAL229_I0_Pos                                     15
#define LCD_PAL229_I0_Msk                                     (0x01UL << LCD_PAL229_I0_Pos)
#define LCD_PAL229_R14_0_Pos                                  16
#define LCD_PAL229_R14_0_Msk                                  (0x1fUL << LCD_PAL229_R14_0_Pos)
#define LCD_PAL229_G14_0_Pos                                  21
#define LCD_PAL229_G14_0_Msk                                  (0x1fUL << LCD_PAL229_G14_0_Pos)
#define LCD_PAL229_B14_0_Pos                                  26
#define LCD_PAL229_B14_0_Msk                                  (0x1fUL << LCD_PAL229_B14_0_Pos)
#define LCD_PAL229_I1_Pos                                     31
#define LCD_PAL229_I1_Msk                                     (0x01UL << LCD_PAL229_I1_Pos)

// ---------------------------------------  LCD_PAL230  -------------------------------------------
#define LCD_PAL230_R04_0_Pos                                  0
#define LCD_PAL230_R04_0_Msk                                  (0x1fUL << LCD_PAL230_R04_0_Pos)
#define LCD_PAL230_G04_0_Pos                                  5
#define LCD_PAL230_G04_0_Msk                                  (0x1fUL << LCD_PAL230_G04_0_Pos)
#define LCD_PAL230_B04_0_Pos                                  10
#define LCD_PAL230_B04_0_Msk                                  (0x1fUL << LCD_PAL230_B04_0_Pos)
#define LCD_PAL230_I0_Pos                                     15
#define LCD_PAL230_I0_Msk                                     (0x01UL << LCD_PAL230_I0_Pos)
#define LCD_PAL230_R14_0_Pos                                  16
#define LCD_PAL230_R14_0_Msk                                  (0x1fUL << LCD_PAL230_R14_0_Pos)
#define LCD_PAL230_G14_0_Pos                                  21
#define LCD_PAL230_G14_0_Msk                                  (0x1fUL << LCD_PAL230_G14_0_Pos)
#define LCD_PAL230_B14_0_Pos                                  26
#define LCD_PAL230_B14_0_Msk                                  (0x1fUL << LCD_PAL230_B14_0_Pos)
#define LCD_PAL230_I1_Pos                                     31
#define LCD_PAL230_I1_Msk                                     (0x01UL << LCD_PAL230_I1_Pos)

// ---------------------------------------  LCD_PAL231  -------------------------------------------
#define LCD_PAL231_R04_0_Pos                                  0
#define LCD_PAL231_R04_0_Msk                                  (0x1fUL << LCD_PAL231_R04_0_Pos)
#define LCD_PAL231_G04_0_Pos                                  5
#define LCD_PAL231_G04_0_Msk                                  (0x1fUL << LCD_PAL231_G04_0_Pos)
#define LCD_PAL231_B04_0_Pos                                  10
#define LCD_PAL231_B04_0_Msk                                  (0x1fUL << LCD_PAL231_B04_0_Pos)
#define LCD_PAL231_I0_Pos                                     15
#define LCD_PAL231_I0_Msk                                     (0x01UL << LCD_PAL231_I0_Pos)
#define LCD_PAL231_R14_0_Pos                                  16
#define LCD_PAL231_R14_0_Msk                                  (0x1fUL << LCD_PAL231_R14_0_Pos)
#define LCD_PAL231_G14_0_Pos                                  21
#define LCD_PAL231_G14_0_Msk                                  (0x1fUL << LCD_PAL231_G14_0_Pos)
#define LCD_PAL231_B14_0_Pos                                  26
#define LCD_PAL231_B14_0_Msk                                  (0x1fUL << LCD_PAL231_B14_0_Pos)
#define LCD_PAL231_I1_Pos                                     31
#define LCD_PAL231_I1_Msk                                     (0x01UL << LCD_PAL231_I1_Pos)

// ---------------------------------------  LCD_PAL232  -------------------------------------------
#define LCD_PAL232_R04_0_Pos                                  0
#define LCD_PAL232_R04_0_Msk                                  (0x1fUL << LCD_PAL232_R04_0_Pos)
#define LCD_PAL232_G04_0_Pos                                  5
#define LCD_PAL232_G04_0_Msk                                  (0x1fUL << LCD_PAL232_G04_0_Pos)
#define LCD_PAL232_B04_0_Pos                                  10
#define LCD_PAL232_B04_0_Msk                                  (0x1fUL << LCD_PAL232_B04_0_Pos)
#define LCD_PAL232_I0_Pos                                     15
#define LCD_PAL232_I0_Msk                                     (0x01UL << LCD_PAL232_I0_Pos)
#define LCD_PAL232_R14_0_Pos                                  16
#define LCD_PAL232_R14_0_Msk                                  (0x1fUL << LCD_PAL232_R14_0_Pos)
#define LCD_PAL232_G14_0_Pos                                  21
#define LCD_PAL232_G14_0_Msk                                  (0x1fUL << LCD_PAL232_G14_0_Pos)
#define LCD_PAL232_B14_0_Pos                                  26
#define LCD_PAL232_B14_0_Msk                                  (0x1fUL << LCD_PAL232_B14_0_Pos)
#define LCD_PAL232_I1_Pos                                     31
#define LCD_PAL232_I1_Msk                                     (0x01UL << LCD_PAL232_I1_Pos)

// ---------------------------------------  LCD_PAL233  -------------------------------------------
#define LCD_PAL233_R04_0_Pos                                  0
#define LCD_PAL233_R04_0_Msk                                  (0x1fUL << LCD_PAL233_R04_0_Pos)
#define LCD_PAL233_G04_0_Pos                                  5
#define LCD_PAL233_G04_0_Msk                                  (0x1fUL << LCD_PAL233_G04_0_Pos)
#define LCD_PAL233_B04_0_Pos                                  10
#define LCD_PAL233_B04_0_Msk                                  (0x1fUL << LCD_PAL233_B04_0_Pos)
#define LCD_PAL233_I0_Pos                                     15
#define LCD_PAL233_I0_Msk                                     (0x01UL << LCD_PAL233_I0_Pos)
#define LCD_PAL233_R14_0_Pos                                  16
#define LCD_PAL233_R14_0_Msk                                  (0x1fUL << LCD_PAL233_R14_0_Pos)
#define LCD_PAL233_G14_0_Pos                                  21
#define LCD_PAL233_G14_0_Msk                                  (0x1fUL << LCD_PAL233_G14_0_Pos)
#define LCD_PAL233_B14_0_Pos                                  26
#define LCD_PAL233_B14_0_Msk                                  (0x1fUL << LCD_PAL233_B14_0_Pos)
#define LCD_PAL233_I1_Pos                                     31
#define LCD_PAL233_I1_Msk                                     (0x01UL << LCD_PAL233_I1_Pos)

// ---------------------------------------  LCD_PAL234  -------------------------------------------
#define LCD_PAL234_R04_0_Pos                                  0
#define LCD_PAL234_R04_0_Msk                                  (0x1fUL << LCD_PAL234_R04_0_Pos)
#define LCD_PAL234_G04_0_Pos                                  5
#define LCD_PAL234_G04_0_Msk                                  (0x1fUL << LCD_PAL234_G04_0_Pos)
#define LCD_PAL234_B04_0_Pos                                  10
#define LCD_PAL234_B04_0_Msk                                  (0x1fUL << LCD_PAL234_B04_0_Pos)
#define LCD_PAL234_I0_Pos                                     15
#define LCD_PAL234_I0_Msk                                     (0x01UL << LCD_PAL234_I0_Pos)
#define LCD_PAL234_R14_0_Pos                                  16
#define LCD_PAL234_R14_0_Msk                                  (0x1fUL << LCD_PAL234_R14_0_Pos)
#define LCD_PAL234_G14_0_Pos                                  21
#define LCD_PAL234_G14_0_Msk                                  (0x1fUL << LCD_PAL234_G14_0_Pos)
#define LCD_PAL234_B14_0_Pos                                  26
#define LCD_PAL234_B14_0_Msk                                  (0x1fUL << LCD_PAL234_B14_0_Pos)
#define LCD_PAL234_I1_Pos                                     31
#define LCD_PAL234_I1_Msk                                     (0x01UL << LCD_PAL234_I1_Pos)

// ---------------------------------------  LCD_PAL235  -------------------------------------------
#define LCD_PAL235_R04_0_Pos                                  0
#define LCD_PAL235_R04_0_Msk                                  (0x1fUL << LCD_PAL235_R04_0_Pos)
#define LCD_PAL235_G04_0_Pos                                  5
#define LCD_PAL235_G04_0_Msk                                  (0x1fUL << LCD_PAL235_G04_0_Pos)
#define LCD_PAL235_B04_0_Pos                                  10
#define LCD_PAL235_B04_0_Msk                                  (0x1fUL << LCD_PAL235_B04_0_Pos)
#define LCD_PAL235_I0_Pos                                     15
#define LCD_PAL235_I0_Msk                                     (0x01UL << LCD_PAL235_I0_Pos)
#define LCD_PAL235_R14_0_Pos                                  16
#define LCD_PAL235_R14_0_Msk                                  (0x1fUL << LCD_PAL235_R14_0_Pos)
#define LCD_PAL235_G14_0_Pos                                  21
#define LCD_PAL235_G14_0_Msk                                  (0x1fUL << LCD_PAL235_G14_0_Pos)
#define LCD_PAL235_B14_0_Pos                                  26
#define LCD_PAL235_B14_0_Msk                                  (0x1fUL << LCD_PAL235_B14_0_Pos)
#define LCD_PAL235_I1_Pos                                     31
#define LCD_PAL235_I1_Msk                                     (0x01UL << LCD_PAL235_I1_Pos)

// ---------------------------------------  LCD_PAL236  -------------------------------------------
#define LCD_PAL236_R04_0_Pos                                  0
#define LCD_PAL236_R04_0_Msk                                  (0x1fUL << LCD_PAL236_R04_0_Pos)
#define LCD_PAL236_G04_0_Pos                                  5
#define LCD_PAL236_G04_0_Msk                                  (0x1fUL << LCD_PAL236_G04_0_Pos)
#define LCD_PAL236_B04_0_Pos                                  10
#define LCD_PAL236_B04_0_Msk                                  (0x1fUL << LCD_PAL236_B04_0_Pos)
#define LCD_PAL236_I0_Pos                                     15
#define LCD_PAL236_I0_Msk                                     (0x01UL << LCD_PAL236_I0_Pos)
#define LCD_PAL236_R14_0_Pos                                  16
#define LCD_PAL236_R14_0_Msk                                  (0x1fUL << LCD_PAL236_R14_0_Pos)
#define LCD_PAL236_G14_0_Pos                                  21
#define LCD_PAL236_G14_0_Msk                                  (0x1fUL << LCD_PAL236_G14_0_Pos)
#define LCD_PAL236_B14_0_Pos                                  26
#define LCD_PAL236_B14_0_Msk                                  (0x1fUL << LCD_PAL236_B14_0_Pos)
#define LCD_PAL236_I1_Pos                                     31
#define LCD_PAL236_I1_Msk                                     (0x01UL << LCD_PAL236_I1_Pos)

// ---------------------------------------  LCD_PAL237  -------------------------------------------
#define LCD_PAL237_R04_0_Pos                                  0
#define LCD_PAL237_R04_0_Msk                                  (0x1fUL << LCD_PAL237_R04_0_Pos)
#define LCD_PAL237_G04_0_Pos                                  5
#define LCD_PAL237_G04_0_Msk                                  (0x1fUL << LCD_PAL237_G04_0_Pos)
#define LCD_PAL237_B04_0_Pos                                  10
#define LCD_PAL237_B04_0_Msk                                  (0x1fUL << LCD_PAL237_B04_0_Pos)
#define LCD_PAL237_I0_Pos                                     15
#define LCD_PAL237_I0_Msk                                     (0x01UL << LCD_PAL237_I0_Pos)
#define LCD_PAL237_R14_0_Pos                                  16
#define LCD_PAL237_R14_0_Msk                                  (0x1fUL << LCD_PAL237_R14_0_Pos)
#define LCD_PAL237_G14_0_Pos                                  21
#define LCD_PAL237_G14_0_Msk                                  (0x1fUL << LCD_PAL237_G14_0_Pos)
#define LCD_PAL237_B14_0_Pos                                  26
#define LCD_PAL237_B14_0_Msk                                  (0x1fUL << LCD_PAL237_B14_0_Pos)
#define LCD_PAL237_I1_Pos                                     31
#define LCD_PAL237_I1_Msk                                     (0x01UL << LCD_PAL237_I1_Pos)

// ---------------------------------------  LCD_PAL238  -------------------------------------------
#define LCD_PAL238_R04_0_Pos                                  0
#define LCD_PAL238_R04_0_Msk                                  (0x1fUL << LCD_PAL238_R04_0_Pos)
#define LCD_PAL238_G04_0_Pos                                  5
#define LCD_PAL238_G04_0_Msk                                  (0x1fUL << LCD_PAL238_G04_0_Pos)
#define LCD_PAL238_B04_0_Pos                                  10
#define LCD_PAL238_B04_0_Msk                                  (0x1fUL << LCD_PAL238_B04_0_Pos)
#define LCD_PAL238_I0_Pos                                     15
#define LCD_PAL238_I0_Msk                                     (0x01UL << LCD_PAL238_I0_Pos)
#define LCD_PAL238_R14_0_Pos                                  16
#define LCD_PAL238_R14_0_Msk                                  (0x1fUL << LCD_PAL238_R14_0_Pos)
#define LCD_PAL238_G14_0_Pos                                  21
#define LCD_PAL238_G14_0_Msk                                  (0x1fUL << LCD_PAL238_G14_0_Pos)
#define LCD_PAL238_B14_0_Pos                                  26
#define LCD_PAL238_B14_0_Msk                                  (0x1fUL << LCD_PAL238_B14_0_Pos)
#define LCD_PAL238_I1_Pos                                     31
#define LCD_PAL238_I1_Msk                                     (0x01UL << LCD_PAL238_I1_Pos)

// ---------------------------------------  LCD_PAL239  -------------------------------------------
#define LCD_PAL239_R04_0_Pos                                  0
#define LCD_PAL239_R04_0_Msk                                  (0x1fUL << LCD_PAL239_R04_0_Pos)
#define LCD_PAL239_G04_0_Pos                                  5
#define LCD_PAL239_G04_0_Msk                                  (0x1fUL << LCD_PAL239_G04_0_Pos)
#define LCD_PAL239_B04_0_Pos                                  10
#define LCD_PAL239_B04_0_Msk                                  (0x1fUL << LCD_PAL239_B04_0_Pos)
#define LCD_PAL239_I0_Pos                                     15
#define LCD_PAL239_I0_Msk                                     (0x01UL << LCD_PAL239_I0_Pos)
#define LCD_PAL239_R14_0_Pos                                  16
#define LCD_PAL239_R14_0_Msk                                  (0x1fUL << LCD_PAL239_R14_0_Pos)
#define LCD_PAL239_G14_0_Pos                                  21
#define LCD_PAL239_G14_0_Msk                                  (0x1fUL << LCD_PAL239_G14_0_Pos)
#define LCD_PAL239_B14_0_Pos                                  26
#define LCD_PAL239_B14_0_Msk                                  (0x1fUL << LCD_PAL239_B14_0_Pos)
#define LCD_PAL239_I1_Pos                                     31
#define LCD_PAL239_I1_Msk                                     (0x01UL << LCD_PAL239_I1_Pos)

// ---------------------------------------  LCD_PAL240  -------------------------------------------
#define LCD_PAL240_R04_0_Pos                                  0
#define LCD_PAL240_R04_0_Msk                                  (0x1fUL << LCD_PAL240_R04_0_Pos)
#define LCD_PAL240_G04_0_Pos                                  5
#define LCD_PAL240_G04_0_Msk                                  (0x1fUL << LCD_PAL240_G04_0_Pos)
#define LCD_PAL240_B04_0_Pos                                  10
#define LCD_PAL240_B04_0_Msk                                  (0x1fUL << LCD_PAL240_B04_0_Pos)
#define LCD_PAL240_I0_Pos                                     15
#define LCD_PAL240_I0_Msk                                     (0x01UL << LCD_PAL240_I0_Pos)
#define LCD_PAL240_R14_0_Pos                                  16
#define LCD_PAL240_R14_0_Msk                                  (0x1fUL << LCD_PAL240_R14_0_Pos)
#define LCD_PAL240_G14_0_Pos                                  21
#define LCD_PAL240_G14_0_Msk                                  (0x1fUL << LCD_PAL240_G14_0_Pos)
#define LCD_PAL240_B14_0_Pos                                  26
#define LCD_PAL240_B14_0_Msk                                  (0x1fUL << LCD_PAL240_B14_0_Pos)
#define LCD_PAL240_I1_Pos                                     31
#define LCD_PAL240_I1_Msk                                     (0x01UL << LCD_PAL240_I1_Pos)

// ---------------------------------------  LCD_PAL241  -------------------------------------------
#define LCD_PAL241_R04_0_Pos                                  0
#define LCD_PAL241_R04_0_Msk                                  (0x1fUL << LCD_PAL241_R04_0_Pos)
#define LCD_PAL241_G04_0_Pos                                  5
#define LCD_PAL241_G04_0_Msk                                  (0x1fUL << LCD_PAL241_G04_0_Pos)
#define LCD_PAL241_B04_0_Pos                                  10
#define LCD_PAL241_B04_0_Msk                                  (0x1fUL << LCD_PAL241_B04_0_Pos)
#define LCD_PAL241_I0_Pos                                     15
#define LCD_PAL241_I0_Msk                                     (0x01UL << LCD_PAL241_I0_Pos)
#define LCD_PAL241_R14_0_Pos                                  16
#define LCD_PAL241_R14_0_Msk                                  (0x1fUL << LCD_PAL241_R14_0_Pos)
#define LCD_PAL241_G14_0_Pos                                  21
#define LCD_PAL241_G14_0_Msk                                  (0x1fUL << LCD_PAL241_G14_0_Pos)
#define LCD_PAL241_B14_0_Pos                                  26
#define LCD_PAL241_B14_0_Msk                                  (0x1fUL << LCD_PAL241_B14_0_Pos)
#define LCD_PAL241_I1_Pos                                     31
#define LCD_PAL241_I1_Msk                                     (0x01UL << LCD_PAL241_I1_Pos)

// ---------------------------------------  LCD_PAL242  -------------------------------------------
#define LCD_PAL242_R04_0_Pos                                  0
#define LCD_PAL242_R04_0_Msk                                  (0x1fUL << LCD_PAL242_R04_0_Pos)
#define LCD_PAL242_G04_0_Pos                                  5
#define LCD_PAL242_G04_0_Msk                                  (0x1fUL << LCD_PAL242_G04_0_Pos)
#define LCD_PAL242_B04_0_Pos                                  10
#define LCD_PAL242_B04_0_Msk                                  (0x1fUL << LCD_PAL242_B04_0_Pos)
#define LCD_PAL242_I0_Pos                                     15
#define LCD_PAL242_I0_Msk                                     (0x01UL << LCD_PAL242_I0_Pos)
#define LCD_PAL242_R14_0_Pos                                  16
#define LCD_PAL242_R14_0_Msk                                  (0x1fUL << LCD_PAL242_R14_0_Pos)
#define LCD_PAL242_G14_0_Pos                                  21
#define LCD_PAL242_G14_0_Msk                                  (0x1fUL << LCD_PAL242_G14_0_Pos)
#define LCD_PAL242_B14_0_Pos                                  26
#define LCD_PAL242_B14_0_Msk                                  (0x1fUL << LCD_PAL242_B14_0_Pos)
#define LCD_PAL242_I1_Pos                                     31
#define LCD_PAL242_I1_Msk                                     (0x01UL << LCD_PAL242_I1_Pos)

// ---------------------------------------  LCD_PAL243  -------------------------------------------
#define LCD_PAL243_R04_0_Pos                                  0
#define LCD_PAL243_R04_0_Msk                                  (0x1fUL << LCD_PAL243_R04_0_Pos)
#define LCD_PAL243_G04_0_Pos                                  5
#define LCD_PAL243_G04_0_Msk                                  (0x1fUL << LCD_PAL243_G04_0_Pos)
#define LCD_PAL243_B04_0_Pos                                  10
#define LCD_PAL243_B04_0_Msk                                  (0x1fUL << LCD_PAL243_B04_0_Pos)
#define LCD_PAL243_I0_Pos                                     15
#define LCD_PAL243_I0_Msk                                     (0x01UL << LCD_PAL243_I0_Pos)
#define LCD_PAL243_R14_0_Pos                                  16
#define LCD_PAL243_R14_0_Msk                                  (0x1fUL << LCD_PAL243_R14_0_Pos)
#define LCD_PAL243_G14_0_Pos                                  21
#define LCD_PAL243_G14_0_Msk                                  (0x1fUL << LCD_PAL243_G14_0_Pos)
#define LCD_PAL243_B14_0_Pos                                  26
#define LCD_PAL243_B14_0_Msk                                  (0x1fUL << LCD_PAL243_B14_0_Pos)
#define LCD_PAL243_I1_Pos                                     31
#define LCD_PAL243_I1_Msk                                     (0x01UL << LCD_PAL243_I1_Pos)

// ---------------------------------------  LCD_PAL244  -------------------------------------------
#define LCD_PAL244_R04_0_Pos                                  0
#define LCD_PAL244_R04_0_Msk                                  (0x1fUL << LCD_PAL244_R04_0_Pos)
#define LCD_PAL244_G04_0_Pos                                  5
#define LCD_PAL244_G04_0_Msk                                  (0x1fUL << LCD_PAL244_G04_0_Pos)
#define LCD_PAL244_B04_0_Pos                                  10
#define LCD_PAL244_B04_0_Msk                                  (0x1fUL << LCD_PAL244_B04_0_Pos)
#define LCD_PAL244_I0_Pos                                     15
#define LCD_PAL244_I0_Msk                                     (0x01UL << LCD_PAL244_I0_Pos)
#define LCD_PAL244_R14_0_Pos                                  16
#define LCD_PAL244_R14_0_Msk                                  (0x1fUL << LCD_PAL244_R14_0_Pos)
#define LCD_PAL244_G14_0_Pos                                  21
#define LCD_PAL244_G14_0_Msk                                  (0x1fUL << LCD_PAL244_G14_0_Pos)
#define LCD_PAL244_B14_0_Pos                                  26
#define LCD_PAL244_B14_0_Msk                                  (0x1fUL << LCD_PAL244_B14_0_Pos)
#define LCD_PAL244_I1_Pos                                     31
#define LCD_PAL244_I1_Msk                                     (0x01UL << LCD_PAL244_I1_Pos)

// ---------------------------------------  LCD_PAL245  -------------------------------------------
#define LCD_PAL245_R04_0_Pos                                  0
#define LCD_PAL245_R04_0_Msk                                  (0x1fUL << LCD_PAL245_R04_0_Pos)
#define LCD_PAL245_G04_0_Pos                                  5
#define LCD_PAL245_G04_0_Msk                                  (0x1fUL << LCD_PAL245_G04_0_Pos)
#define LCD_PAL245_B04_0_Pos                                  10
#define LCD_PAL245_B04_0_Msk                                  (0x1fUL << LCD_PAL245_B04_0_Pos)
#define LCD_PAL245_I0_Pos                                     15
#define LCD_PAL245_I0_Msk                                     (0x01UL << LCD_PAL245_I0_Pos)
#define LCD_PAL245_R14_0_Pos                                  16
#define LCD_PAL245_R14_0_Msk                                  (0x1fUL << LCD_PAL245_R14_0_Pos)
#define LCD_PAL245_G14_0_Pos                                  21
#define LCD_PAL245_G14_0_Msk                                  (0x1fUL << LCD_PAL245_G14_0_Pos)
#define LCD_PAL245_B14_0_Pos                                  26
#define LCD_PAL245_B14_0_Msk                                  (0x1fUL << LCD_PAL245_B14_0_Pos)
#define LCD_PAL245_I1_Pos                                     31
#define LCD_PAL245_I1_Msk                                     (0x01UL << LCD_PAL245_I1_Pos)

// ---------------------------------------  LCD_PAL246  -------------------------------------------
#define LCD_PAL246_R04_0_Pos                                  0
#define LCD_PAL246_R04_0_Msk                                  (0x1fUL << LCD_PAL246_R04_0_Pos)
#define LCD_PAL246_G04_0_Pos                                  5
#define LCD_PAL246_G04_0_Msk                                  (0x1fUL << LCD_PAL246_G04_0_Pos)
#define LCD_PAL246_B04_0_Pos                                  10
#define LCD_PAL246_B04_0_Msk                                  (0x1fUL << LCD_PAL246_B04_0_Pos)
#define LCD_PAL246_I0_Pos                                     15
#define LCD_PAL246_I0_Msk                                     (0x01UL << LCD_PAL246_I0_Pos)
#define LCD_PAL246_R14_0_Pos                                  16
#define LCD_PAL246_R14_0_Msk                                  (0x1fUL << LCD_PAL246_R14_0_Pos)
#define LCD_PAL246_G14_0_Pos                                  21
#define LCD_PAL246_G14_0_Msk                                  (0x1fUL << LCD_PAL246_G14_0_Pos)
#define LCD_PAL246_B14_0_Pos                                  26
#define LCD_PAL246_B14_0_Msk                                  (0x1fUL << LCD_PAL246_B14_0_Pos)
#define LCD_PAL246_I1_Pos                                     31
#define LCD_PAL246_I1_Msk                                     (0x01UL << LCD_PAL246_I1_Pos)

// ---------------------------------------  LCD_PAL247  -------------------------------------------
#define LCD_PAL247_R04_0_Pos                                  0
#define LCD_PAL247_R04_0_Msk                                  (0x1fUL << LCD_PAL247_R04_0_Pos)
#define LCD_PAL247_G04_0_Pos                                  5
#define LCD_PAL247_G04_0_Msk                                  (0x1fUL << LCD_PAL247_G04_0_Pos)
#define LCD_PAL247_B04_0_Pos                                  10
#define LCD_PAL247_B04_0_Msk                                  (0x1fUL << LCD_PAL247_B04_0_Pos)
#define LCD_PAL247_I0_Pos                                     15
#define LCD_PAL247_I0_Msk                                     (0x01UL << LCD_PAL247_I0_Pos)
#define LCD_PAL247_R14_0_Pos                                  16
#define LCD_PAL247_R14_0_Msk                                  (0x1fUL << LCD_PAL247_R14_0_Pos)
#define LCD_PAL247_G14_0_Pos                                  21
#define LCD_PAL247_G14_0_Msk                                  (0x1fUL << LCD_PAL247_G14_0_Pos)
#define LCD_PAL247_B14_0_Pos                                  26
#define LCD_PAL247_B14_0_Msk                                  (0x1fUL << LCD_PAL247_B14_0_Pos)
#define LCD_PAL247_I1_Pos                                     31
#define LCD_PAL247_I1_Msk                                     (0x01UL << LCD_PAL247_I1_Pos)

// ---------------------------------------  LCD_PAL248  -------------------------------------------
#define LCD_PAL248_R04_0_Pos                                  0
#define LCD_PAL248_R04_0_Msk                                  (0x1fUL << LCD_PAL248_R04_0_Pos)
#define LCD_PAL248_G04_0_Pos                                  5
#define LCD_PAL248_G04_0_Msk                                  (0x1fUL << LCD_PAL248_G04_0_Pos)
#define LCD_PAL248_B04_0_Pos                                  10
#define LCD_PAL248_B04_0_Msk                                  (0x1fUL << LCD_PAL248_B04_0_Pos)
#define LCD_PAL248_I0_Pos                                     15
#define LCD_PAL248_I0_Msk                                     (0x01UL << LCD_PAL248_I0_Pos)
#define LCD_PAL248_R14_0_Pos                                  16
#define LCD_PAL248_R14_0_Msk                                  (0x1fUL << LCD_PAL248_R14_0_Pos)
#define LCD_PAL248_G14_0_Pos                                  21
#define LCD_PAL248_G14_0_Msk                                  (0x1fUL << LCD_PAL248_G14_0_Pos)
#define LCD_PAL248_B14_0_Pos                                  26
#define LCD_PAL248_B14_0_Msk                                  (0x1fUL << LCD_PAL248_B14_0_Pos)
#define LCD_PAL248_I1_Pos                                     31
#define LCD_PAL248_I1_Msk                                     (0x01UL << LCD_PAL248_I1_Pos)

// ---------------------------------------  LCD_PAL249  -------------------------------------------
#define LCD_PAL249_R04_0_Pos                                  0
#define LCD_PAL249_R04_0_Msk                                  (0x1fUL << LCD_PAL249_R04_0_Pos)
#define LCD_PAL249_G04_0_Pos                                  5
#define LCD_PAL249_G04_0_Msk                                  (0x1fUL << LCD_PAL249_G04_0_Pos)
#define LCD_PAL249_B04_0_Pos                                  10
#define LCD_PAL249_B04_0_Msk                                  (0x1fUL << LCD_PAL249_B04_0_Pos)
#define LCD_PAL249_I0_Pos                                     15
#define LCD_PAL249_I0_Msk                                     (0x01UL << LCD_PAL249_I0_Pos)
#define LCD_PAL249_R14_0_Pos                                  16
#define LCD_PAL249_R14_0_Msk                                  (0x1fUL << LCD_PAL249_R14_0_Pos)
#define LCD_PAL249_G14_0_Pos                                  21
#define LCD_PAL249_G14_0_Msk                                  (0x1fUL << LCD_PAL249_G14_0_Pos)
#define LCD_PAL249_B14_0_Pos                                  26
#define LCD_PAL249_B14_0_Msk                                  (0x1fUL << LCD_PAL249_B14_0_Pos)
#define LCD_PAL249_I1_Pos                                     31
#define LCD_PAL249_I1_Msk                                     (0x01UL << LCD_PAL249_I1_Pos)

// ---------------------------------------  LCD_PAL250  -------------------------------------------
#define LCD_PAL250_R04_0_Pos                                  0
#define LCD_PAL250_R04_0_Msk                                  (0x1fUL << LCD_PAL250_R04_0_Pos)
#define LCD_PAL250_G04_0_Pos                                  5
#define LCD_PAL250_G04_0_Msk                                  (0x1fUL << LCD_PAL250_G04_0_Pos)
#define LCD_PAL250_B04_0_Pos                                  10
#define LCD_PAL250_B04_0_Msk                                  (0x1fUL << LCD_PAL250_B04_0_Pos)
#define LCD_PAL250_I0_Pos                                     15
#define LCD_PAL250_I0_Msk                                     (0x01UL << LCD_PAL250_I0_Pos)
#define LCD_PAL250_R14_0_Pos                                  16
#define LCD_PAL250_R14_0_Msk                                  (0x1fUL << LCD_PAL250_R14_0_Pos)
#define LCD_PAL250_G14_0_Pos                                  21
#define LCD_PAL250_G14_0_Msk                                  (0x1fUL << LCD_PAL250_G14_0_Pos)
#define LCD_PAL250_B14_0_Pos                                  26
#define LCD_PAL250_B14_0_Msk                                  (0x1fUL << LCD_PAL250_B14_0_Pos)
#define LCD_PAL250_I1_Pos                                     31
#define LCD_PAL250_I1_Msk                                     (0x01UL << LCD_PAL250_I1_Pos)

// ---------------------------------------  LCD_PAL251  -------------------------------------------
#define LCD_PAL251_R04_0_Pos                                  0
#define LCD_PAL251_R04_0_Msk                                  (0x1fUL << LCD_PAL251_R04_0_Pos)
#define LCD_PAL251_G04_0_Pos                                  5
#define LCD_PAL251_G04_0_Msk                                  (0x1fUL << LCD_PAL251_G04_0_Pos)
#define LCD_PAL251_B04_0_Pos                                  10
#define LCD_PAL251_B04_0_Msk                                  (0x1fUL << LCD_PAL251_B04_0_Pos)
#define LCD_PAL251_I0_Pos                                     15
#define LCD_PAL251_I0_Msk                                     (0x01UL << LCD_PAL251_I0_Pos)
#define LCD_PAL251_R14_0_Pos                                  16
#define LCD_PAL251_R14_0_Msk                                  (0x1fUL << LCD_PAL251_R14_0_Pos)
#define LCD_PAL251_G14_0_Pos                                  21
#define LCD_PAL251_G14_0_Msk                                  (0x1fUL << LCD_PAL251_G14_0_Pos)
#define LCD_PAL251_B14_0_Pos                                  26
#define LCD_PAL251_B14_0_Msk                                  (0x1fUL << LCD_PAL251_B14_0_Pos)
#define LCD_PAL251_I1_Pos                                     31
#define LCD_PAL251_I1_Msk                                     (0x01UL << LCD_PAL251_I1_Pos)

// ---------------------------------------  LCD_PAL252  -------------------------------------------
#define LCD_PAL252_R04_0_Pos                                  0
#define LCD_PAL252_R04_0_Msk                                  (0x1fUL << LCD_PAL252_R04_0_Pos)
#define LCD_PAL252_G04_0_Pos                                  5
#define LCD_PAL252_G04_0_Msk                                  (0x1fUL << LCD_PAL252_G04_0_Pos)
#define LCD_PAL252_B04_0_Pos                                  10
#define LCD_PAL252_B04_0_Msk                                  (0x1fUL << LCD_PAL252_B04_0_Pos)
#define LCD_PAL252_I0_Pos                                     15
#define LCD_PAL252_I0_Msk                                     (0x01UL << LCD_PAL252_I0_Pos)
#define LCD_PAL252_R14_0_Pos                                  16
#define LCD_PAL252_R14_0_Msk                                  (0x1fUL << LCD_PAL252_R14_0_Pos)
#define LCD_PAL252_G14_0_Pos                                  21
#define LCD_PAL252_G14_0_Msk                                  (0x1fUL << LCD_PAL252_G14_0_Pos)
#define LCD_PAL252_B14_0_Pos                                  26
#define LCD_PAL252_B14_0_Msk                                  (0x1fUL << LCD_PAL252_B14_0_Pos)
#define LCD_PAL252_I1_Pos                                     31
#define LCD_PAL252_I1_Msk                                     (0x01UL << LCD_PAL252_I1_Pos)

// ---------------------------------------  LCD_PAL253  -------------------------------------------
#define LCD_PAL253_R04_0_Pos                                  0
#define LCD_PAL253_R04_0_Msk                                  (0x1fUL << LCD_PAL253_R04_0_Pos)
#define LCD_PAL253_G04_0_Pos                                  5
#define LCD_PAL253_G04_0_Msk                                  (0x1fUL << LCD_PAL253_G04_0_Pos)
#define LCD_PAL253_B04_0_Pos                                  10
#define LCD_PAL253_B04_0_Msk                                  (0x1fUL << LCD_PAL253_B04_0_Pos)
#define LCD_PAL253_I0_Pos                                     15
#define LCD_PAL253_I0_Msk                                     (0x01UL << LCD_PAL253_I0_Pos)
#define LCD_PAL253_R14_0_Pos                                  16
#define LCD_PAL253_R14_0_Msk                                  (0x1fUL << LCD_PAL253_R14_0_Pos)
#define LCD_PAL253_G14_0_Pos                                  21
#define LCD_PAL253_G14_0_Msk                                  (0x1fUL << LCD_PAL253_G14_0_Pos)
#define LCD_PAL253_B14_0_Pos                                  26
#define LCD_PAL253_B14_0_Msk                                  (0x1fUL << LCD_PAL253_B14_0_Pos)
#define LCD_PAL253_I1_Pos                                     31
#define LCD_PAL253_I1_Msk                                     (0x01UL << LCD_PAL253_I1_Pos)

// ---------------------------------------  LCD_PAL254  -------------------------------------------
#define LCD_PAL254_R04_0_Pos                                  0
#define LCD_PAL254_R04_0_Msk                                  (0x1fUL << LCD_PAL254_R04_0_Pos)
#define LCD_PAL254_G04_0_Pos                                  5
#define LCD_PAL254_G04_0_Msk                                  (0x1fUL << LCD_PAL254_G04_0_Pos)
#define LCD_PAL254_B04_0_Pos                                  10
#define LCD_PAL254_B04_0_Msk                                  (0x1fUL << LCD_PAL254_B04_0_Pos)
#define LCD_PAL254_I0_Pos                                     15
#define LCD_PAL254_I0_Msk                                     (0x01UL << LCD_PAL254_I0_Pos)
#define LCD_PAL254_R14_0_Pos                                  16
#define LCD_PAL254_R14_0_Msk                                  (0x1fUL << LCD_PAL254_R14_0_Pos)
#define LCD_PAL254_G14_0_Pos                                  21
#define LCD_PAL254_G14_0_Msk                                  (0x1fUL << LCD_PAL254_G14_0_Pos)
#define LCD_PAL254_B14_0_Pos                                  26
#define LCD_PAL254_B14_0_Msk                                  (0x1fUL << LCD_PAL254_B14_0_Pos)
#define LCD_PAL254_I1_Pos                                     31
#define LCD_PAL254_I1_Msk                                     (0x01UL << LCD_PAL254_I1_Pos)

// ---------------------------------------  LCD_PAL255  -------------------------------------------
#define LCD_PAL255_R04_0_Pos                                  0
#define LCD_PAL255_R04_0_Msk                                  (0x1fUL << LCD_PAL255_R04_0_Pos)
#define LCD_PAL255_G04_0_Pos                                  5
#define LCD_PAL255_G04_0_Msk                                  (0x1fUL << LCD_PAL255_G04_0_Pos)
#define LCD_PAL255_B04_0_Pos                                  10
#define LCD_PAL255_B04_0_Msk                                  (0x1fUL << LCD_PAL255_B04_0_Pos)
#define LCD_PAL255_I0_Pos                                     15
#define LCD_PAL255_I0_Msk                                     (0x01UL << LCD_PAL255_I0_Pos)
#define LCD_PAL255_R14_0_Pos                                  16
#define LCD_PAL255_R14_0_Msk                                  (0x1fUL << LCD_PAL255_R14_0_Pos)
#define LCD_PAL255_G14_0_Pos                                  21
#define LCD_PAL255_G14_0_Msk                                  (0x1fUL << LCD_PAL255_G14_0_Pos)
#define LCD_PAL255_B14_0_Pos                                  26
#define LCD_PAL255_B14_0_Msk                                  (0x1fUL << LCD_PAL255_B14_0_Pos)
#define LCD_PAL255_I1_Pos                                     31
#define LCD_PAL255_I1_Msk                                     (0x01UL << LCD_PAL255_I1_Pos)

// --------------------------------------  LCD_CRSR_IMG0  -----------------------------------------
#define LCD_CRSR_IMG0_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG0_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG1  -----------------------------------------
#define LCD_CRSR_IMG1_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG1_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG2  -----------------------------------------
#define LCD_CRSR_IMG2_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG2_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG3  -----------------------------------------
#define LCD_CRSR_IMG3_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG3_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG4  -----------------------------------------
#define LCD_CRSR_IMG4_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG4_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG5  -----------------------------------------
#define LCD_CRSR_IMG5_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG5_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG6  -----------------------------------------
#define LCD_CRSR_IMG6_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG6_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG7  -----------------------------------------
#define LCD_CRSR_IMG7_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG7_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG8  -----------------------------------------
#define LCD_CRSR_IMG8_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG8_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_IMG9  -----------------------------------------
#define LCD_CRSR_IMG9_CRSR_IMG_Pos                            0
#define LCD_CRSR_IMG9_CRSR_IMG_Msk                            (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG10  -----------------------------------------
#define LCD_CRSR_IMG10_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG10_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG11  -----------------------------------------
#define LCD_CRSR_IMG11_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG11_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG12  -----------------------------------------
#define LCD_CRSR_IMG12_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG12_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG13  -----------------------------------------
#define LCD_CRSR_IMG13_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG13_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG14  -----------------------------------------
#define LCD_CRSR_IMG14_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG14_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG15  -----------------------------------------
#define LCD_CRSR_IMG15_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG15_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG16  -----------------------------------------
#define LCD_CRSR_IMG16_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG16_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG17  -----------------------------------------
#define LCD_CRSR_IMG17_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG17_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG18  -----------------------------------------
#define LCD_CRSR_IMG18_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG18_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG19  -----------------------------------------
#define LCD_CRSR_IMG19_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG19_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG20  -----------------------------------------
#define LCD_CRSR_IMG20_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG20_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG21  -----------------------------------------
#define LCD_CRSR_IMG21_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG21_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG22  -----------------------------------------
#define LCD_CRSR_IMG22_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG22_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG23  -----------------------------------------
#define LCD_CRSR_IMG23_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG23_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG24  -----------------------------------------
#define LCD_CRSR_IMG24_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG24_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG25  -----------------------------------------
#define LCD_CRSR_IMG25_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG25_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG26  -----------------------------------------
#define LCD_CRSR_IMG26_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG26_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG27  -----------------------------------------
#define LCD_CRSR_IMG27_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG27_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG28  -----------------------------------------
#define LCD_CRSR_IMG28_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG28_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG29  -----------------------------------------
#define LCD_CRSR_IMG29_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG29_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG30  -----------------------------------------
#define LCD_CRSR_IMG30_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG30_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG31  -----------------------------------------
#define LCD_CRSR_IMG31_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG31_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG32  -----------------------------------------
#define LCD_CRSR_IMG32_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG32_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG33  -----------------------------------------
#define LCD_CRSR_IMG33_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG33_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG34  -----------------------------------------
#define LCD_CRSR_IMG34_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG34_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG35  -----------------------------------------
#define LCD_CRSR_IMG35_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG35_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG36  -----------------------------------------
#define LCD_CRSR_IMG36_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG36_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG37  -----------------------------------------
#define LCD_CRSR_IMG37_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG37_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG38  -----------------------------------------
#define LCD_CRSR_IMG38_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG38_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG39  -----------------------------------------
#define LCD_CRSR_IMG39_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG39_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG40  -----------------------------------------
#define LCD_CRSR_IMG40_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG40_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG41  -----------------------------------------
#define LCD_CRSR_IMG41_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG41_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG42  -----------------------------------------
#define LCD_CRSR_IMG42_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG42_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG43  -----------------------------------------
#define LCD_CRSR_IMG43_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG43_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG44  -----------------------------------------
#define LCD_CRSR_IMG44_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG44_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG45  -----------------------------------------
#define LCD_CRSR_IMG45_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG45_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG46  -----------------------------------------
#define LCD_CRSR_IMG46_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG46_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG47  -----------------------------------------
#define LCD_CRSR_IMG47_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG47_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG48  -----------------------------------------
#define LCD_CRSR_IMG48_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG48_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG49  -----------------------------------------
#define LCD_CRSR_IMG49_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG49_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG50  -----------------------------------------
#define LCD_CRSR_IMG50_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG50_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG51  -----------------------------------------
#define LCD_CRSR_IMG51_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG51_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG52  -----------------------------------------
#define LCD_CRSR_IMG52_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG52_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG53  -----------------------------------------
#define LCD_CRSR_IMG53_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG53_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG54  -----------------------------------------
#define LCD_CRSR_IMG54_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG54_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG55  -----------------------------------------
#define LCD_CRSR_IMG55_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG55_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG56  -----------------------------------------
#define LCD_CRSR_IMG56_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG56_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG57  -----------------------------------------
#define LCD_CRSR_IMG57_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG57_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG58  -----------------------------------------
#define LCD_CRSR_IMG58_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG58_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG59  -----------------------------------------
#define LCD_CRSR_IMG59_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG59_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG60  -----------------------------------------
#define LCD_CRSR_IMG60_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG60_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG61  -----------------------------------------
#define LCD_CRSR_IMG61_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG61_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG62  -----------------------------------------
#define LCD_CRSR_IMG62_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG62_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG63  -----------------------------------------
#define LCD_CRSR_IMG63_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG63_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG64  -----------------------------------------
#define LCD_CRSR_IMG64_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG64_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG65  -----------------------------------------
#define LCD_CRSR_IMG65_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG65_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG66  -----------------------------------------
#define LCD_CRSR_IMG66_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG66_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG67  -----------------------------------------
#define LCD_CRSR_IMG67_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG67_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG68  -----------------------------------------
#define LCD_CRSR_IMG68_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG68_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG69  -----------------------------------------
#define LCD_CRSR_IMG69_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG69_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG70  -----------------------------------------
#define LCD_CRSR_IMG70_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG70_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG71  -----------------------------------------
#define LCD_CRSR_IMG71_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG71_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG72  -----------------------------------------
#define LCD_CRSR_IMG72_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG72_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG73  -----------------------------------------
#define LCD_CRSR_IMG73_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG73_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG74  -----------------------------------------
#define LCD_CRSR_IMG74_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG74_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG75  -----------------------------------------
#define LCD_CRSR_IMG75_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG75_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG76  -----------------------------------------
#define LCD_CRSR_IMG76_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG76_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG77  -----------------------------------------
#define LCD_CRSR_IMG77_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG77_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG78  -----------------------------------------
#define LCD_CRSR_IMG78_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG78_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG79  -----------------------------------------
#define LCD_CRSR_IMG79_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG79_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG80  -----------------------------------------
#define LCD_CRSR_IMG80_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG80_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG81  -----------------------------------------
#define LCD_CRSR_IMG81_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG81_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG82  -----------------------------------------
#define LCD_CRSR_IMG82_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG82_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG83  -----------------------------------------
#define LCD_CRSR_IMG83_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG83_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG84  -----------------------------------------
#define LCD_CRSR_IMG84_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG84_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG85  -----------------------------------------
#define LCD_CRSR_IMG85_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG85_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG86  -----------------------------------------
#define LCD_CRSR_IMG86_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG86_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG87  -----------------------------------------
#define LCD_CRSR_IMG87_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG87_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG88  -----------------------------------------
#define LCD_CRSR_IMG88_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG88_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG89  -----------------------------------------
#define LCD_CRSR_IMG89_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG89_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG90  -----------------------------------------
#define LCD_CRSR_IMG90_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG90_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG91  -----------------------------------------
#define LCD_CRSR_IMG91_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG91_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG92  -----------------------------------------
#define LCD_CRSR_IMG92_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG92_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG93  -----------------------------------------
#define LCD_CRSR_IMG93_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG93_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG94  -----------------------------------------
#define LCD_CRSR_IMG94_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG94_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG95  -----------------------------------------
#define LCD_CRSR_IMG95_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG95_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG96  -----------------------------------------
#define LCD_CRSR_IMG96_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG96_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG97  -----------------------------------------
#define LCD_CRSR_IMG97_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG97_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG98  -----------------------------------------
#define LCD_CRSR_IMG98_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG98_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG99  -----------------------------------------
#define LCD_CRSR_IMG99_CRSR_IMG_Pos                           0
#define LCD_CRSR_IMG99_CRSR_IMG_Msk                           (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG100  ----------------------------------------
#define LCD_CRSR_IMG100_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG100_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG101  ----------------------------------------
#define LCD_CRSR_IMG101_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG101_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG102  ----------------------------------------
#define LCD_CRSR_IMG102_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG102_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG103  ----------------------------------------
#define LCD_CRSR_IMG103_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG103_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG104  ----------------------------------------
#define LCD_CRSR_IMG104_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG104_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG105  ----------------------------------------
#define LCD_CRSR_IMG105_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG105_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG106  ----------------------------------------
#define LCD_CRSR_IMG106_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG106_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG107  ----------------------------------------
#define LCD_CRSR_IMG107_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG107_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG108  ----------------------------------------
#define LCD_CRSR_IMG108_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG108_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG109  ----------------------------------------
#define LCD_CRSR_IMG109_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG109_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG110  ----------------------------------------
#define LCD_CRSR_IMG110_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG110_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG111  ----------------------------------------
#define LCD_CRSR_IMG111_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG111_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG112  ----------------------------------------
#define LCD_CRSR_IMG112_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG112_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG113  ----------------------------------------
#define LCD_CRSR_IMG113_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG113_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG114  ----------------------------------------
#define LCD_CRSR_IMG114_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG114_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG115  ----------------------------------------
#define LCD_CRSR_IMG115_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG115_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG116  ----------------------------------------
#define LCD_CRSR_IMG116_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG116_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG117  ----------------------------------------
#define LCD_CRSR_IMG117_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG117_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG118  ----------------------------------------
#define LCD_CRSR_IMG118_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG118_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG119  ----------------------------------------
#define LCD_CRSR_IMG119_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG119_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG120  ----------------------------------------
#define LCD_CRSR_IMG120_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG120_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG121  ----------------------------------------
#define LCD_CRSR_IMG121_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG121_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG122  ----------------------------------------
#define LCD_CRSR_IMG122_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG122_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG123  ----------------------------------------
#define LCD_CRSR_IMG123_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG123_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG124  ----------------------------------------
#define LCD_CRSR_IMG124_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG124_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG125  ----------------------------------------
#define LCD_CRSR_IMG125_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG125_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG126  ----------------------------------------
#define LCD_CRSR_IMG126_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG126_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG127  ----------------------------------------
#define LCD_CRSR_IMG127_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG127_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG128  ----------------------------------------
#define LCD_CRSR_IMG128_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG128_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG129  ----------------------------------------
#define LCD_CRSR_IMG129_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG129_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG130  ----------------------------------------
#define LCD_CRSR_IMG130_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG130_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG131  ----------------------------------------
#define LCD_CRSR_IMG131_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG131_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG132  ----------------------------------------
#define LCD_CRSR_IMG132_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG132_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG133  ----------------------------------------
#define LCD_CRSR_IMG133_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG133_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG134  ----------------------------------------
#define LCD_CRSR_IMG134_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG134_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG135  ----------------------------------------
#define LCD_CRSR_IMG135_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG135_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG136  ----------------------------------------
#define LCD_CRSR_IMG136_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG136_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG137  ----------------------------------------
#define LCD_CRSR_IMG137_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG137_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG138  ----------------------------------------
#define LCD_CRSR_IMG138_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG138_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG139  ----------------------------------------
#define LCD_CRSR_IMG139_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG139_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG140  ----------------------------------------
#define LCD_CRSR_IMG140_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG140_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG141  ----------------------------------------
#define LCD_CRSR_IMG141_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG141_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG142  ----------------------------------------
#define LCD_CRSR_IMG142_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG142_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG143  ----------------------------------------
#define LCD_CRSR_IMG143_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG143_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG144  ----------------------------------------
#define LCD_CRSR_IMG144_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG144_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG145  ----------------------------------------
#define LCD_CRSR_IMG145_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG145_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG146  ----------------------------------------
#define LCD_CRSR_IMG146_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG146_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG147  ----------------------------------------
#define LCD_CRSR_IMG147_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG147_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG148  ----------------------------------------
#define LCD_CRSR_IMG148_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG148_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG149  ----------------------------------------
#define LCD_CRSR_IMG149_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG149_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG150  ----------------------------------------
#define LCD_CRSR_IMG150_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG150_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG151  ----------------------------------------
#define LCD_CRSR_IMG151_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG151_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG152  ----------------------------------------
#define LCD_CRSR_IMG152_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG152_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG153  ----------------------------------------
#define LCD_CRSR_IMG153_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG153_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG154  ----------------------------------------
#define LCD_CRSR_IMG154_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG154_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG155  ----------------------------------------
#define LCD_CRSR_IMG155_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG155_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG156  ----------------------------------------
#define LCD_CRSR_IMG156_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG156_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG157  ----------------------------------------
#define LCD_CRSR_IMG157_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG157_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG158  ----------------------------------------
#define LCD_CRSR_IMG158_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG158_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG159  ----------------------------------------
#define LCD_CRSR_IMG159_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG159_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG160  ----------------------------------------
#define LCD_CRSR_IMG160_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG160_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG161  ----------------------------------------
#define LCD_CRSR_IMG161_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG161_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG162  ----------------------------------------
#define LCD_CRSR_IMG162_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG162_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG163  ----------------------------------------
#define LCD_CRSR_IMG163_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG163_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG164  ----------------------------------------
#define LCD_CRSR_IMG164_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG164_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG165  ----------------------------------------
#define LCD_CRSR_IMG165_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG165_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG166  ----------------------------------------
#define LCD_CRSR_IMG166_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG166_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG167  ----------------------------------------
#define LCD_CRSR_IMG167_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG167_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG168  ----------------------------------------
#define LCD_CRSR_IMG168_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG168_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG169  ----------------------------------------
#define LCD_CRSR_IMG169_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG169_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG170  ----------------------------------------
#define LCD_CRSR_IMG170_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG170_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG171  ----------------------------------------
#define LCD_CRSR_IMG171_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG171_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG172  ----------------------------------------
#define LCD_CRSR_IMG172_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG172_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG173  ----------------------------------------
#define LCD_CRSR_IMG173_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG173_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG174  ----------------------------------------
#define LCD_CRSR_IMG174_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG174_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG175  ----------------------------------------
#define LCD_CRSR_IMG175_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG175_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG176  ----------------------------------------
#define LCD_CRSR_IMG176_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG176_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG177  ----------------------------------------
#define LCD_CRSR_IMG177_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG177_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG178  ----------------------------------------
#define LCD_CRSR_IMG178_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG178_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG179  ----------------------------------------
#define LCD_CRSR_IMG179_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG179_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG180  ----------------------------------------
#define LCD_CRSR_IMG180_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG180_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG181  ----------------------------------------
#define LCD_CRSR_IMG181_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG181_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG182  ----------------------------------------
#define LCD_CRSR_IMG182_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG182_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG183  ----------------------------------------
#define LCD_CRSR_IMG183_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG183_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG184  ----------------------------------------
#define LCD_CRSR_IMG184_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG184_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG185  ----------------------------------------
#define LCD_CRSR_IMG185_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG185_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG186  ----------------------------------------
#define LCD_CRSR_IMG186_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG186_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG187  ----------------------------------------
#define LCD_CRSR_IMG187_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG187_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG188  ----------------------------------------
#define LCD_CRSR_IMG188_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG188_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG189  ----------------------------------------
#define LCD_CRSR_IMG189_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG189_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG190  ----------------------------------------
#define LCD_CRSR_IMG190_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG190_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG191  ----------------------------------------
#define LCD_CRSR_IMG191_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG191_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG192  ----------------------------------------
#define LCD_CRSR_IMG192_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG192_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG193  ----------------------------------------
#define LCD_CRSR_IMG193_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG193_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG194  ----------------------------------------
#define LCD_CRSR_IMG194_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG194_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG195  ----------------------------------------
#define LCD_CRSR_IMG195_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG195_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG196  ----------------------------------------
#define LCD_CRSR_IMG196_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG196_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG197  ----------------------------------------
#define LCD_CRSR_IMG197_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG197_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG198  ----------------------------------------
#define LCD_CRSR_IMG198_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG198_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG199  ----------------------------------------
#define LCD_CRSR_IMG199_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG199_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG200  ----------------------------------------
#define LCD_CRSR_IMG200_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG200_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG201  ----------------------------------------
#define LCD_CRSR_IMG201_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG201_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG202  ----------------------------------------
#define LCD_CRSR_IMG202_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG202_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG203  ----------------------------------------
#define LCD_CRSR_IMG203_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG203_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG204  ----------------------------------------
#define LCD_CRSR_IMG204_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG204_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG205  ----------------------------------------
#define LCD_CRSR_IMG205_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG205_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG206  ----------------------------------------
#define LCD_CRSR_IMG206_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG206_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG207  ----------------------------------------
#define LCD_CRSR_IMG207_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG207_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG208  ----------------------------------------
#define LCD_CRSR_IMG208_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG208_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG209  ----------------------------------------
#define LCD_CRSR_IMG209_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG209_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG210  ----------------------------------------
#define LCD_CRSR_IMG210_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG210_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG211  ----------------------------------------
#define LCD_CRSR_IMG211_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG211_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG212  ----------------------------------------
#define LCD_CRSR_IMG212_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG212_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG213  ----------------------------------------
#define LCD_CRSR_IMG213_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG213_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG214  ----------------------------------------
#define LCD_CRSR_IMG214_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG214_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG215  ----------------------------------------
#define LCD_CRSR_IMG215_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG215_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG216  ----------------------------------------
#define LCD_CRSR_IMG216_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG216_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG217  ----------------------------------------
#define LCD_CRSR_IMG217_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG217_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG218  ----------------------------------------
#define LCD_CRSR_IMG218_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG218_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG219  ----------------------------------------
#define LCD_CRSR_IMG219_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG219_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG220  ----------------------------------------
#define LCD_CRSR_IMG220_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG220_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG221  ----------------------------------------
#define LCD_CRSR_IMG221_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG221_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG222  ----------------------------------------
#define LCD_CRSR_IMG222_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG222_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG223  ----------------------------------------
#define LCD_CRSR_IMG223_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG223_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG224  ----------------------------------------
#define LCD_CRSR_IMG224_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG224_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG225  ----------------------------------------
#define LCD_CRSR_IMG225_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG225_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG226  ----------------------------------------
#define LCD_CRSR_IMG226_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG226_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG227  ----------------------------------------
#define LCD_CRSR_IMG227_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG227_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG228  ----------------------------------------
#define LCD_CRSR_IMG228_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG228_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG229  ----------------------------------------
#define LCD_CRSR_IMG229_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG229_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG230  ----------------------------------------
#define LCD_CRSR_IMG230_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG230_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG231  ----------------------------------------
#define LCD_CRSR_IMG231_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG231_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG232  ----------------------------------------
#define LCD_CRSR_IMG232_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG232_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG233  ----------------------------------------
#define LCD_CRSR_IMG233_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG233_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG234  ----------------------------------------
#define LCD_CRSR_IMG234_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG234_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG235  ----------------------------------------
#define LCD_CRSR_IMG235_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG235_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG236  ----------------------------------------
#define LCD_CRSR_IMG236_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG236_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG237  ----------------------------------------
#define LCD_CRSR_IMG237_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG237_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG238  ----------------------------------------
#define LCD_CRSR_IMG238_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG238_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG239  ----------------------------------------
#define LCD_CRSR_IMG239_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG239_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG240  ----------------------------------------
#define LCD_CRSR_IMG240_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG240_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG241  ----------------------------------------
#define LCD_CRSR_IMG241_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG241_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG242  ----------------------------------------
#define LCD_CRSR_IMG242_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG242_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG243  ----------------------------------------
#define LCD_CRSR_IMG243_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG243_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG244  ----------------------------------------
#define LCD_CRSR_IMG244_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG244_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG245  ----------------------------------------
#define LCD_CRSR_IMG245_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG245_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG246  ----------------------------------------
#define LCD_CRSR_IMG246_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG246_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG247  ----------------------------------------
#define LCD_CRSR_IMG247_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG247_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG248  ----------------------------------------
#define LCD_CRSR_IMG248_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG248_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG249  ----------------------------------------
#define LCD_CRSR_IMG249_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG249_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG250  ----------------------------------------
#define LCD_CRSR_IMG250_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG250_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG251  ----------------------------------------
#define LCD_CRSR_IMG251_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG251_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG252  ----------------------------------------
#define LCD_CRSR_IMG252_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG252_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG253  ----------------------------------------
#define LCD_CRSR_IMG253_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG253_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG254  ----------------------------------------
#define LCD_CRSR_IMG254_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG254_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos)

// -------------------------------------  LCD_CRSR_IMG255  ----------------------------------------
#define LCD_CRSR_IMG255_CRSR_IMG_Pos                          0
#define LCD_CRSR_IMG255_CRSR_IMG_Msk                          (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos)

// --------------------------------------  LCD_CRSR_CTRL  -----------------------------------------
#define LCD_CRSR_CTRL_CrsrOn_Pos                              0
#define LCD_CRSR_CTRL_CrsrOn_Msk                              (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos)
#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos                          4
#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk                          (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos)

// --------------------------------------  LCD_CRSR_CFG  ------------------------------------------
#define LCD_CRSR_CFG_CrsrSize_Pos                             0
#define LCD_CRSR_CFG_CrsrSize_Msk                             (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos)
#define LCD_CRSR_CFG_FRAMESYNC_Pos                            1
#define LCD_CRSR_CFG_FRAMESYNC_Msk                            (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos)

// --------------------------------------  LCD_CRSR_PAL0  -----------------------------------------
#define LCD_CRSR_PAL0_RED_Pos                                 0
#define LCD_CRSR_PAL0_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos)
#define LCD_CRSR_PAL0_GREEN_Pos                               8
#define LCD_CRSR_PAL0_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos)
#define LCD_CRSR_PAL0_BLUE_Pos                                16
#define LCD_CRSR_PAL0_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos)

// --------------------------------------  LCD_CRSR_PAL1  -----------------------------------------
#define LCD_CRSR_PAL1_RED_Pos                                 0
#define LCD_CRSR_PAL1_RED_Msk                                 (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos)
#define LCD_CRSR_PAL1_GREEN_Pos                               8
#define LCD_CRSR_PAL1_GREEN_Msk                               (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos)
#define LCD_CRSR_PAL1_BLUE_Pos                                16
#define LCD_CRSR_PAL1_BLUE_Msk                                (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos)

// ---------------------------------------  LCD_CRSR_XY  ------------------------------------------
#define LCD_CRSR_XY_CRSRX_Pos                                 0
#define LCD_CRSR_XY_CRSRX_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos)
#define LCD_CRSR_XY_CRSRY_Pos                                 16
#define LCD_CRSR_XY_CRSRY_Msk                                 (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos)

// --------------------------------------  LCD_CRSR_CLIP  -----------------------------------------
#define LCD_CRSR_CLIP_CRSRCLIPX_Pos                           0
#define LCD_CRSR_CLIP_CRSRCLIPX_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos)
#define LCD_CRSR_CLIP_CRSRCLIPY_Pos                           8
#define LCD_CRSR_CLIP_CRSRCLIPY_Msk                           (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos)

// -------------------------------------  LCD_CRSR_INTMSK  ----------------------------------------
#define LCD_CRSR_INTMSK_CRSRIM_Pos                            0
#define LCD_CRSR_INTMSK_CRSRIM_Msk                            (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos)

// -------------------------------------  LCD_CRSR_INTCLR  ----------------------------------------
#define LCD_CRSR_INTCLR_CRSRIC_Pos                            0
#define LCD_CRSR_INTCLR_CRSRIC_Msk                            (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos)

// -------------------------------------  LCD_CRSR_INTRAW  ----------------------------------------
#define LCD_CRSR_INTRAW_CRSRRIS_Pos                           0
#define LCD_CRSR_INTRAW_CRSRRIS_Msk                           (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos)

// ------------------------------------  LCD_CRSR_INTSTAT  ----------------------------------------
#define LCD_CRSR_INTSTAT_CRSRMIS_Pos                          0
#define LCD_CRSR_INTSTAT_CRSRMIS_Msk                          (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos)


// ------------------------------------------------------------------------------------------------
// -----                               ETHERNET Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  ETHERNET_MAC_CONFIG  --------------------------------------
#define ETHERNET_MAC_CONFIG_RE_Pos                            2
#define ETHERNET_MAC_CONFIG_RE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos)
#define ETHERNET_MAC_CONFIG_TE_Pos                            3
#define ETHERNET_MAC_CONFIG_TE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos)
#define ETHERNET_MAC_CONFIG_DF_Pos                            4
#define ETHERNET_MAC_CONFIG_DF_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos)
#define ETHERNET_MAC_CONFIG_BL_Pos                            5
#define ETHERNET_MAC_CONFIG_BL_Msk                            (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos)
#define ETHERNET_MAC_CONFIG_ACS_Pos                           7
#define ETHERNET_MAC_CONFIG_ACS_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos)
#define ETHERNET_MAC_CONFIG_DR_Pos                            9
#define ETHERNET_MAC_CONFIG_DR_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos)
#define ETHERNET_MAC_CONFIG_IPC_Pos                           10
#define ETHERNET_MAC_CONFIG_IPC_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos)
#define ETHERNET_MAC_CONFIG_DM_Pos                            11
#define ETHERNET_MAC_CONFIG_DM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos)
#define ETHERNET_MAC_CONFIG_LM_Pos                            12
#define ETHERNET_MAC_CONFIG_LM_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos)
#define ETHERNET_MAC_CONFIG_DO_Pos                            13
#define ETHERNET_MAC_CONFIG_DO_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos)
#define ETHERNET_MAC_CONFIG_FES_Pos                           14
#define ETHERNET_MAC_CONFIG_FES_Msk                           (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos)
#define ETHERNET_MAC_CONFIG_PS_Pos                            15
#define ETHERNET_MAC_CONFIG_PS_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos)
#define ETHERNET_MAC_CONFIG_DCRS_Pos                          16
#define ETHERNET_MAC_CONFIG_DCRS_Msk                          (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos)
#define ETHERNET_MAC_CONFIG_IFG_Pos                           17
#define ETHERNET_MAC_CONFIG_IFG_Msk                           (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos)
#define ETHERNET_MAC_CONFIG_JE_Pos                            20
#define ETHERNET_MAC_CONFIG_JE_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos)
#define ETHERNET_MAC_CONFIG_JD_Pos                            22
#define ETHERNET_MAC_CONFIG_JD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos)
#define ETHERNET_MAC_CONFIG_WD_Pos                            23
#define ETHERNET_MAC_CONFIG_WD_Msk                            (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos)

// --------------------------------  ETHERNET_MAC_FRAME_FILTER  -----------------------------------
#define ETHERNET_MAC_FRAME_FILTER_PR_Pos                      0
#define ETHERNET_MAC_FRAME_FILTER_PR_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos)
#define ETHERNET_MAC_FRAME_FILTER_HUC_Pos                     1
#define ETHERNET_MAC_FRAME_FILTER_HUC_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_HUC_Pos)
#define ETHERNET_MAC_FRAME_FILTER_HMC_Pos                     2
#define ETHERNET_MAC_FRAME_FILTER_HMC_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_HMC_Pos)
#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos                    3
#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_PM_Pos                      4
#define ETHERNET_MAC_FRAME_FILTER_PM_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos)
#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos                     5
#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos                     6
#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk                     (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos                    8
#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk                    (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos                     9
#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_HPF_Pos                     10
#define ETHERNET_MAC_FRAME_FILTER_HPF_Msk                     (0x01UL << ETHERNET_MAC_FRAME_FILTER_HPF_Pos)
#define ETHERNET_MAC_FRAME_FILTER_RA_Pos                      31
#define ETHERNET_MAC_FRAME_FILTER_RA_Msk                      (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos)

// -------------------------------  ETHERNET_MAC_HASHTABLE_HIGH  ----------------------------------
#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos                   0
#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk                   (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos)

// -------------------------------  ETHERNET_MAC_HASHTABLE_LOW  -----------------------------------
#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos                    0
#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk                    (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos)

// ----------------------------------  ETHERNET_MAC_MII_ADDR  -------------------------------------
#define ETHERNET_MAC_MII_ADDR_GB_Pos                          0
#define ETHERNET_MAC_MII_ADDR_GB_Msk                          (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos)
#define ETHERNET_MAC_MII_ADDR_W_Pos                           1
#define ETHERNET_MAC_MII_ADDR_W_Msk                           (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos)
#define ETHERNET_MAC_MII_ADDR_CR_Pos                          2
#define ETHERNET_MAC_MII_ADDR_CR_Msk                          (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos)
#define ETHERNET_MAC_MII_ADDR_GR_Pos                          6
#define ETHERNET_MAC_MII_ADDR_GR_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos)
#define ETHERNET_MAC_MII_ADDR_PA_Pos                          11
#define ETHERNET_MAC_MII_ADDR_PA_Msk                          (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos)

// ----------------------------------  ETHERNET_MAC_MII_DATA  -------------------------------------
#define ETHERNET_MAC_MII_DATA_GD_Pos                          0
#define ETHERNET_MAC_MII_DATA_GD_Msk                          (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos)

// ---------------------------------  ETHERNET_MAC_FLOW_CTRL  -------------------------------------
#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos                        0
#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos)
#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos                        1
#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos)
#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos                        2
#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk                        (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos)
#define ETHERNET_MAC_FLOW_CTRL_UP_Pos                         3
#define ETHERNET_MAC_FLOW_CTRL_UP_Msk                         (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos)
#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos                        4
#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk                        (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos)
#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos                       7
#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk                       (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos)
#define ETHERNET_MAC_FLOW_CTRL_PT_Pos                         16
#define ETHERNET_MAC_FLOW_CTRL_PT_Msk                         (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos)

// ----------------------------------  ETHERNET_MAC_VLAN_TAG  -------------------------------------
#define ETHERNET_MAC_VLAN_TAG_VL_Pos                          0
#define ETHERNET_MAC_VLAN_TAG_VL_Msk                          (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos)
#define ETHERNET_MAC_VLAN_TAG_ETV_Pos                         16
#define ETHERNET_MAC_VLAN_TAG_ETV_Msk                         (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos)

// -----------------------------------  ETHERNET_MAC_DEBUG  ---------------------------------------
#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos                     0
#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos)
#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos                      1
#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos)
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos                    4
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos)
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos                     5
#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos)
#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos                      8
#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk                      (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos)
#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos                     16
#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos)
#define ETHERNET_MAC_DEBUG_TXSTAT_Pos                         17
#define ETHERNET_MAC_DEBUG_TXSTAT_Msk                         (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos)
#define ETHERNET_MAC_DEBUG_PAUSE_Pos                          19
#define ETHERNET_MAC_DEBUG_PAUSE_Msk                          (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos)
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos                     20
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk                     (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos)
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos                    22
#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk                    (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos)
#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos                      24
#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk                      (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos)
#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos                     25
#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk                     (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos)

// --------------------------------  ETHERNET_MAC_RWAKE_FRFLT  ------------------------------------
#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos                     0
#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk                     (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos)

// -------------------------------  ETHERNET_MAC_PMT_CTRL_STAT  -----------------------------------
#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos                     0
#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos                    1
#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos                    2
#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos                    5
#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos                    6
#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk                    (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos                     9
#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk                     (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos)
#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos                 31
#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk                 (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos)

// ---------------------------------  ETHERNET_MAC_INTR_MASK  -------------------------------------
#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos                     3
#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk                     (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos)

// ---------------------------------  ETHERNET_MAC_ADDR0_HIGH  ------------------------------------
#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos                    0
#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk                    (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos)
#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos                        31
#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk                        (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos)

// ---------------------------------  ETHERNET_MAC_ADDR0_LOW  -------------------------------------
#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos                      0
#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk                      (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos)

// --------------------------------  ETHERNET_MAC_TIMESTP_CTRL  -----------------------------------
#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos                   0
#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk                   (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos                1
#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos                  2
#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos                  3
#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos                  4
#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk                  (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos                5
#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk                (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos                 8
#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos               9
#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos               10
#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos                 11
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk                 (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos               12
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos               13
#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos               14
#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos               15
#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk               (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos               16
#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk               (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos)
#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos             18
#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk             (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)

// ---------------------------------  ETHERNET_SUBSECOND_INCR  ------------------------------------
#define ETHERNET_SUBSECOND_INCR_SSINC_Pos                     0
#define ETHERNET_SUBSECOND_INCR_SSINC_Msk                     (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos)

// ------------------------------------  ETHERNET_SECONDS  ----------------------------------------
#define ETHERNET_SECONDS_TSS_Pos                              0
#define ETHERNET_SECONDS_TSS_Msk                              (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos)

// ----------------------------------  ETHERNET_NANOSECONDS  --------------------------------------
#define ETHERNET_NANOSECONDS_TSSS_Pos                         0
#define ETHERNET_NANOSECONDS_TSSS_Msk                         (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos)
#define ETHERNET_NANOSECONDS_PSNT_Pos                         31
#define ETHERNET_NANOSECONDS_PSNT_Msk                         (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos)

// ---------------------------------  ETHERNET_SECONDSUPDATE  -------------------------------------
#define ETHERNET_SECONDSUPDATE_TSS_Pos                        0
#define ETHERNET_SECONDSUPDATE_TSS_Msk                        (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos)

// -------------------------------  ETHERNET_NANOSECONDSUPDATE  -----------------------------------
#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos                   0
#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk                   (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos)
#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos                 31
#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk                 (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos)

// -------------------------------------  ETHERNET_ADDEND  ----------------------------------------
#define ETHERNET_ADDEND_TSAR_Pos                              0
#define ETHERNET_ADDEND_TSAR_Msk                              (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos)

// ---------------------------------  ETHERNET_TARGETSECONDS  -------------------------------------
#define ETHERNET_TARGETSECONDS_TSTR_Pos                       0
#define ETHERNET_TARGETSECONDS_TSTR_Msk                       (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos)

// -------------------------------  ETHERNET_TARGETNANOSECONDS  -----------------------------------
#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos                   0
#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk                   (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos)

// ------------------------------------  ETHERNET_HIGHWORD  ---------------------------------------
#define ETHERNET_HIGHWORD_TSHWR_Pos                           0
#define ETHERNET_HIGHWORD_TSHWR_Msk                           (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos)

// ---------------------------------  ETHERNET_TIMESTAMPSTAT  -------------------------------------
#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos                     0
#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos)
#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos                    1
#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk                    (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos)
#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos                      2
#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk                      (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos)
#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos                     24
#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk                     (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos)
#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos                      25
#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk                      (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos)

// ------------------------------------  ETHERNET_PPSCTRL  ----------------------------------------
#define ETHERNET_PPSCTRL_PPSCTRL_Pos                          0
#define ETHERNET_PPSCTRL_PPSCTRL_Msk                          (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos)

// ---------------------------------  ETHERNET_AUXNANOSECONDS  ------------------------------------
#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos                     0
#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk                     (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos)

// -----------------------------------  ETHERNET_AUXSECONDS  --------------------------------------
#define ETHERNET_AUXSECONDS_AUXS_Pos                          0
#define ETHERNET_AUXSECONDS_AUXS_Msk                          (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos)

// ----------------------------------  ETHERNET_DMA_BUS_MODE  -------------------------------------
#define ETHERNET_DMA_BUS_MODE_SWR_Pos                         0
#define ETHERNET_DMA_BUS_MODE_SWR_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos)
#define ETHERNET_DMA_BUS_MODE_DA_Pos                          1
#define ETHERNET_DMA_BUS_MODE_DA_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos)
#define ETHERNET_DMA_BUS_MODE_DSL_Pos                         2
#define ETHERNET_DMA_BUS_MODE_DSL_Msk                         (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos)
#define ETHERNET_DMA_BUS_MODE_ATDS_Pos                        7
#define ETHERNET_DMA_BUS_MODE_ATDS_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos)
#define ETHERNET_DMA_BUS_MODE_PBL_Pos                         8
#define ETHERNET_DMA_BUS_MODE_PBL_Msk                         (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos)
#define ETHERNET_DMA_BUS_MODE_PR_Pos                          14
#define ETHERNET_DMA_BUS_MODE_PR_Msk                          (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos)
#define ETHERNET_DMA_BUS_MODE_FB_Pos                          16
#define ETHERNET_DMA_BUS_MODE_FB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos)
#define ETHERNET_DMA_BUS_MODE_RPBL_Pos                        17
#define ETHERNET_DMA_BUS_MODE_RPBL_Msk                        (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
#define ETHERNET_DMA_BUS_MODE_USP_Pos                         23
#define ETHERNET_DMA_BUS_MODE_USP_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos)
#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos                       24
#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk                       (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos)
#define ETHERNET_DMA_BUS_MODE_AAL_Pos                         25
#define ETHERNET_DMA_BUS_MODE_AAL_Msk                         (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos)
#define ETHERNET_DMA_BUS_MODE_MB_Pos                          26
#define ETHERNET_DMA_BUS_MODE_MB_Msk                          (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos)
#define ETHERNET_DMA_BUS_MODE_TXPR_Pos                        27
#define ETHERNET_DMA_BUS_MODE_TXPR_Msk                        (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos)

// -----------------------------  ETHERNET_DMA_TRANS_POLL_DEMAND  ---------------------------------
#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos                0
#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk                (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)

// ------------------------------  ETHERNET_DMA_REC_POLL_DEMAND  ----------------------------------
#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos                  0
#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk                  (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos)

// --------------------------------  ETHERNET_DMA_REC_DES_ADDR  -----------------------------------
#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos                     0
#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk                     (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos)

// -------------------------------  ETHERNET_DMA_TRANS_DES_ADDR  ----------------------------------
#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos                   0
#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk                   (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos)

// ------------------------------------  ETHERNET_DMA_STAT  ---------------------------------------
#define ETHERNET_DMA_STAT_TI_Pos                              0
#define ETHERNET_DMA_STAT_TI_Msk                              (0x01UL << ETHERNET_DMA_STAT_TI_Pos)
#define ETHERNET_DMA_STAT_TPS_Pos                             1
#define ETHERNET_DMA_STAT_TPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_TPS_Pos)
#define ETHERNET_DMA_STAT_TU_Pos                              2
#define ETHERNET_DMA_STAT_TU_Msk                              (0x01UL << ETHERNET_DMA_STAT_TU_Pos)
#define ETHERNET_DMA_STAT_TJT_Pos                             3
#define ETHERNET_DMA_STAT_TJT_Msk                             (0x01UL << ETHERNET_DMA_STAT_TJT_Pos)
#define ETHERNET_DMA_STAT_OVF_Pos                             4
#define ETHERNET_DMA_STAT_OVF_Msk                             (0x01UL << ETHERNET_DMA_STAT_OVF_Pos)
#define ETHERNET_DMA_STAT_UNF_Pos                             5
#define ETHERNET_DMA_STAT_UNF_Msk                             (0x01UL << ETHERNET_DMA_STAT_UNF_Pos)
#define ETHERNET_DMA_STAT_RI_Pos                              6
#define ETHERNET_DMA_STAT_RI_Msk                              (0x01UL << ETHERNET_DMA_STAT_RI_Pos)
#define ETHERNET_DMA_STAT_RU_Pos                              7
#define ETHERNET_DMA_STAT_RU_Msk                              (0x01UL << ETHERNET_DMA_STAT_RU_Pos)
#define ETHERNET_DMA_STAT_RPS_Pos                             8
#define ETHERNET_DMA_STAT_RPS_Msk                             (0x01UL << ETHERNET_DMA_STAT_RPS_Pos)
#define ETHERNET_DMA_STAT_RWT_Pos                             9
#define ETHERNET_DMA_STAT_RWT_Msk                             (0x01UL << ETHERNET_DMA_STAT_RWT_Pos)
#define ETHERNET_DMA_STAT_ETI_Pos                             10
#define ETHERNET_DMA_STAT_ETI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ETI_Pos)
#define ETHERNET_DMA_STAT_FBI_Pos                             13
#define ETHERNET_DMA_STAT_FBI_Msk                             (0x01UL << ETHERNET_DMA_STAT_FBI_Pos)
#define ETHERNET_DMA_STAT_ERI_Pos                             14
#define ETHERNET_DMA_STAT_ERI_Msk                             (0x01UL << ETHERNET_DMA_STAT_ERI_Pos)
#define ETHERNET_DMA_STAT_AIE_Pos                             15
#define ETHERNET_DMA_STAT_AIE_Msk                             (0x01UL << ETHERNET_DMA_STAT_AIE_Pos)
#define ETHERNET_DMA_STAT_NIS_Pos                             16
#define ETHERNET_DMA_STAT_NIS_Msk                             (0x01UL << ETHERNET_DMA_STAT_NIS_Pos)

// ----------------------------------  ETHERNET_DMA_OP_MODE  --------------------------------------
#define ETHERNET_DMA_OP_MODE_SR_Pos                           1
#define ETHERNET_DMA_OP_MODE_SR_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos)
#define ETHERNET_DMA_OP_MODE_OSF_Pos                          2
#define ETHERNET_DMA_OP_MODE_OSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos)
#define ETHERNET_DMA_OP_MODE_RTC_Pos                          3
#define ETHERNET_DMA_OP_MODE_RTC_Msk                          (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos)
#define ETHERNET_DMA_OP_MODE_FUF_Pos                          6
#define ETHERNET_DMA_OP_MODE_FUF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos)
#define ETHERNET_DMA_OP_MODE_FEF_Pos                          7
#define ETHERNET_DMA_OP_MODE_FEF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos)
#define ETHERNET_DMA_OP_MODE_ST_Pos                           13
#define ETHERNET_DMA_OP_MODE_ST_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos)
#define ETHERNET_DMA_OP_MODE_TTC_Pos                          14
#define ETHERNET_DMA_OP_MODE_TTC_Msk                          (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos)
#define ETHERNET_DMA_OP_MODE_FTF_Pos                          20
#define ETHERNET_DMA_OP_MODE_FTF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos)
#define ETHERNET_DMA_OP_MODE_TSF_Pos                          21
#define ETHERNET_DMA_OP_MODE_TSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos)
#define ETHERNET_DMA_OP_MODE_DFF_Pos                          24
#define ETHERNET_DMA_OP_MODE_DFF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos)
#define ETHERNET_DMA_OP_MODE_RSF_Pos                          25
#define ETHERNET_DMA_OP_MODE_RSF_Msk                          (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos)
#define ETHERNET_DMA_OP_MODE_DT_Pos                           26
#define ETHERNET_DMA_OP_MODE_DT_Msk                           (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos)

// -----------------------------------  ETHERNET_DMA_INT_EN  --------------------------------------
#define ETHERNET_DMA_INT_EN_TIE_Pos                           0
#define ETHERNET_DMA_INT_EN_TIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos)
#define ETHERNET_DMA_INT_EN_TSE_Pos                           1
#define ETHERNET_DMA_INT_EN_TSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos)
#define ETHERNET_DMA_INT_EN_TUE_Pos                           2
#define ETHERNET_DMA_INT_EN_TUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos)
#define ETHERNET_DMA_INT_EN_TJE_Pos                           3
#define ETHERNET_DMA_INT_EN_TJE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos)
#define ETHERNET_DMA_INT_EN_OVE_Pos                           4
#define ETHERNET_DMA_INT_EN_OVE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos)
#define ETHERNET_DMA_INT_EN_UNE_Pos                           5
#define ETHERNET_DMA_INT_EN_UNE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos)
#define ETHERNET_DMA_INT_EN_RIE_Pos                           6
#define ETHERNET_DMA_INT_EN_RIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos)
#define ETHERNET_DMA_INT_EN_RUE_Pos                           7
#define ETHERNET_DMA_INT_EN_RUE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos)
#define ETHERNET_DMA_INT_EN_RSE_Pos                           8
#define ETHERNET_DMA_INT_EN_RSE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos)
#define ETHERNET_DMA_INT_EN_RWE_Pos                           9
#define ETHERNET_DMA_INT_EN_RWE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos)
#define ETHERNET_DMA_INT_EN_ETE_Pos                           10
#define ETHERNET_DMA_INT_EN_ETE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos)
#define ETHERNET_DMA_INT_EN_FBE_Pos                           13
#define ETHERNET_DMA_INT_EN_FBE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos)
#define ETHERNET_DMA_INT_EN_ERE_Pos                           14
#define ETHERNET_DMA_INT_EN_ERE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos)
#define ETHERNET_DMA_INT_EN_AIE_Pos                           15
#define ETHERNET_DMA_INT_EN_AIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos)
#define ETHERNET_DMA_INT_EN_NIE_Pos                           16
#define ETHERNET_DMA_INT_EN_NIE_Msk                           (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos)

// ---------------------------------  ETHERNET_DMA_MFRM_BUFOF  ------------------------------------
#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos                       0
#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk                       (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos)
#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos                        16
#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos)
#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos                       17
#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk                       (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos)
#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos                        28
#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk                        (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos)

// --------------------------------  ETHERNET_DMA_REC_INT_WDT  ------------------------------------
#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos                     0
#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk                     (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos)

// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_DES  ---------------------------------
#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos                0
#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)

// ------------------------------  ETHERNET_DMA_CURHOST_REC_DES  ----------------------------------
#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos                  0
#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos)

// -----------------------------  ETHERNET_DMA_CURHOST_TRANS_BUF  ---------------------------------
#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos                0
#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk                (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)

// ------------------------------  ETHERNET_DMA_CURHOST_REC_BUF  ----------------------------------
#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos                  0
#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk                  (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                ATIMER Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  ATIMER_DOWNCOUNTER  ---------------------------------------
#define ATIMER_DOWNCOUNTER_CVAL_Pos                           0
#define ATIMER_DOWNCOUNTER_CVAL_Msk                           (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos)

// --------------------------------------  ATIMER_PRESET  -----------------------------------------
#define ATIMER_PRESET_PRESETVAL_Pos                           0
#define ATIMER_PRESET_PRESETVAL_Msk                           (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos)

// --------------------------------------  ATIMER_CLR_EN  -----------------------------------------
#define ATIMER_CLR_EN_CLR_EN_Pos                              0
#define ATIMER_CLR_EN_CLR_EN_Msk                              (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos)

// --------------------------------------  ATIMER_SET_EN  -----------------------------------------
#define ATIMER_SET_EN_SET_EN_Pos                              0
#define ATIMER_SET_EN_SET_EN_Msk                              (0x01UL << ATIMER_SET_EN_SET_EN_Pos)

// --------------------------------------  ATIMER_STATUS  -----------------------------------------
#define ATIMER_STATUS_STAT_Pos                                0
#define ATIMER_STATUS_STAT_Msk                                (0x01UL << ATIMER_STATUS_STAT_Pos)

// --------------------------------------  ATIMER_ENABLE  -----------------------------------------
#define ATIMER_ENABLE_EN_Pos                                  0
#define ATIMER_ENABLE_EN_Msk                                  (0x01UL << ATIMER_ENABLE_EN_Pos)

// -------------------------------------  ATIMER_CLR_STAT  ----------------------------------------
#define ATIMER_CLR_STAT_CSTAT_Pos                             0
#define ATIMER_CLR_STAT_CSTAT_Msk                             (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos)

// -------------------------------------  ATIMER_SET_STAT  ----------------------------------------
#define ATIMER_SET_STAT_SSTAT_Pos                             0
#define ATIMER_SET_STAT_SSTAT_Msk                             (0x01UL << ATIMER_SET_STAT_SSTAT_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                REGFILE Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  REGFILE_REGFILE0  ----------------------------------------
#define REGFILE_REGFILE0_REGVAL_Pos                           0
#define REGFILE_REGFILE0_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE1  ----------------------------------------
#define REGFILE_REGFILE1_REGVAL_Pos                           0
#define REGFILE_REGFILE1_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE2  ----------------------------------------
#define REGFILE_REGFILE2_REGVAL_Pos                           0
#define REGFILE_REGFILE2_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE3  ----------------------------------------
#define REGFILE_REGFILE3_REGVAL_Pos                           0
#define REGFILE_REGFILE3_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE4  ----------------------------------------
#define REGFILE_REGFILE4_REGVAL_Pos                           0
#define REGFILE_REGFILE4_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE5  ----------------------------------------
#define REGFILE_REGFILE5_REGVAL_Pos                           0
#define REGFILE_REGFILE5_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE6  ----------------------------------------
#define REGFILE_REGFILE6_REGVAL_Pos                           0
#define REGFILE_REGFILE6_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE7  ----------------------------------------
#define REGFILE_REGFILE7_REGVAL_Pos                           0
#define REGFILE_REGFILE7_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE8  ----------------------------------------
#define REGFILE_REGFILE8_REGVAL_Pos                           0
#define REGFILE_REGFILE8_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE9  ----------------------------------------
#define REGFILE_REGFILE9_REGVAL_Pos                           0
#define REGFILE_REGFILE9_REGVAL_Msk                           (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE10  ---------------------------------------
#define REGFILE_REGFILE10_REGVAL_Pos                          0
#define REGFILE_REGFILE10_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE11  ---------------------------------------
#define REGFILE_REGFILE11_REGVAL_Pos                          0
#define REGFILE_REGFILE11_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE12  ---------------------------------------
#define REGFILE_REGFILE12_REGVAL_Pos                          0
#define REGFILE_REGFILE12_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE13  ---------------------------------------
#define REGFILE_REGFILE13_REGVAL_Pos                          0
#define REGFILE_REGFILE13_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE14  ---------------------------------------
#define REGFILE_REGFILE14_REGVAL_Pos                          0
#define REGFILE_REGFILE14_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE15  ---------------------------------------
#define REGFILE_REGFILE15_REGVAL_Pos                          0
#define REGFILE_REGFILE15_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE16  ---------------------------------------
#define REGFILE_REGFILE16_REGVAL_Pos                          0
#define REGFILE_REGFILE16_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE17  ---------------------------------------
#define REGFILE_REGFILE17_REGVAL_Pos                          0
#define REGFILE_REGFILE17_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE18  ---------------------------------------
#define REGFILE_REGFILE18_REGVAL_Pos                          0
#define REGFILE_REGFILE18_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE19  ---------------------------------------
#define REGFILE_REGFILE19_REGVAL_Pos                          0
#define REGFILE_REGFILE19_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE20  ---------------------------------------
#define REGFILE_REGFILE20_REGVAL_Pos                          0
#define REGFILE_REGFILE20_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE21  ---------------------------------------
#define REGFILE_REGFILE21_REGVAL_Pos                          0
#define REGFILE_REGFILE21_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE22  ---------------------------------------
#define REGFILE_REGFILE22_REGVAL_Pos                          0
#define REGFILE_REGFILE22_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE23  ---------------------------------------
#define REGFILE_REGFILE23_REGVAL_Pos                          0
#define REGFILE_REGFILE23_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE24  ---------------------------------------
#define REGFILE_REGFILE24_REGVAL_Pos                          0
#define REGFILE_REGFILE24_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE25  ---------------------------------------
#define REGFILE_REGFILE25_REGVAL_Pos                          0
#define REGFILE_REGFILE25_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE26  ---------------------------------------
#define REGFILE_REGFILE26_REGVAL_Pos                          0
#define REGFILE_REGFILE26_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE27  ---------------------------------------
#define REGFILE_REGFILE27_REGVAL_Pos                          0
#define REGFILE_REGFILE27_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE28  ---------------------------------------
#define REGFILE_REGFILE28_REGVAL_Pos                          0
#define REGFILE_REGFILE28_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE29  ---------------------------------------
#define REGFILE_REGFILE29_REGVAL_Pos                          0
#define REGFILE_REGFILE29_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE30  ---------------------------------------
#define REGFILE_REGFILE30_REGVAL_Pos                          0
#define REGFILE_REGFILE30_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE31  ---------------------------------------
#define REGFILE_REGFILE31_REGVAL_Pos                          0
#define REGFILE_REGFILE31_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE32  ---------------------------------------
#define REGFILE_REGFILE32_REGVAL_Pos                          0
#define REGFILE_REGFILE32_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE33  ---------------------------------------
#define REGFILE_REGFILE33_REGVAL_Pos                          0
#define REGFILE_REGFILE33_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE34  ---------------------------------------
#define REGFILE_REGFILE34_REGVAL_Pos                          0
#define REGFILE_REGFILE34_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE35  ---------------------------------------
#define REGFILE_REGFILE35_REGVAL_Pos                          0
#define REGFILE_REGFILE35_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE36  ---------------------------------------
#define REGFILE_REGFILE36_REGVAL_Pos                          0
#define REGFILE_REGFILE36_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE37  ---------------------------------------
#define REGFILE_REGFILE37_REGVAL_Pos                          0
#define REGFILE_REGFILE37_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE38  ---------------------------------------
#define REGFILE_REGFILE38_REGVAL_Pos                          0
#define REGFILE_REGFILE38_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE39  ---------------------------------------
#define REGFILE_REGFILE39_REGVAL_Pos                          0
#define REGFILE_REGFILE39_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE40  ---------------------------------------
#define REGFILE_REGFILE40_REGVAL_Pos                          0
#define REGFILE_REGFILE40_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE41  ---------------------------------------
#define REGFILE_REGFILE41_REGVAL_Pos                          0
#define REGFILE_REGFILE41_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE42  ---------------------------------------
#define REGFILE_REGFILE42_REGVAL_Pos                          0
#define REGFILE_REGFILE42_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE43  ---------------------------------------
#define REGFILE_REGFILE43_REGVAL_Pos                          0
#define REGFILE_REGFILE43_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE44  ---------------------------------------
#define REGFILE_REGFILE44_REGVAL_Pos                          0
#define REGFILE_REGFILE44_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE45  ---------------------------------------
#define REGFILE_REGFILE45_REGVAL_Pos                          0
#define REGFILE_REGFILE45_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE46  ---------------------------------------
#define REGFILE_REGFILE46_REGVAL_Pos                          0
#define REGFILE_REGFILE46_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE47  ---------------------------------------
#define REGFILE_REGFILE47_REGVAL_Pos                          0
#define REGFILE_REGFILE47_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE48  ---------------------------------------
#define REGFILE_REGFILE48_REGVAL_Pos                          0
#define REGFILE_REGFILE48_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE49  ---------------------------------------
#define REGFILE_REGFILE49_REGVAL_Pos                          0
#define REGFILE_REGFILE49_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE50  ---------------------------------------
#define REGFILE_REGFILE50_REGVAL_Pos                          0
#define REGFILE_REGFILE50_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE51  ---------------------------------------
#define REGFILE_REGFILE51_REGVAL_Pos                          0
#define REGFILE_REGFILE51_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE52  ---------------------------------------
#define REGFILE_REGFILE52_REGVAL_Pos                          0
#define REGFILE_REGFILE52_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE53  ---------------------------------------
#define REGFILE_REGFILE53_REGVAL_Pos                          0
#define REGFILE_REGFILE53_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE54  ---------------------------------------
#define REGFILE_REGFILE54_REGVAL_Pos                          0
#define REGFILE_REGFILE54_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE55  ---------------------------------------
#define REGFILE_REGFILE55_REGVAL_Pos                          0
#define REGFILE_REGFILE55_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE56  ---------------------------------------
#define REGFILE_REGFILE56_REGVAL_Pos                          0
#define REGFILE_REGFILE56_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE57  ---------------------------------------
#define REGFILE_REGFILE57_REGVAL_Pos                          0
#define REGFILE_REGFILE57_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE58  ---------------------------------------
#define REGFILE_REGFILE58_REGVAL_Pos                          0
#define REGFILE_REGFILE58_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE59  ---------------------------------------
#define REGFILE_REGFILE59_REGVAL_Pos                          0
#define REGFILE_REGFILE59_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE60  ---------------------------------------
#define REGFILE_REGFILE60_REGVAL_Pos                          0
#define REGFILE_REGFILE60_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE61  ---------------------------------------
#define REGFILE_REGFILE61_REGVAL_Pos                          0
#define REGFILE_REGFILE61_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE62  ---------------------------------------
#define REGFILE_REGFILE62_REGVAL_Pos                          0
#define REGFILE_REGFILE62_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos)

// ------------------------------------  REGFILE_REGFILE63  ---------------------------------------
#define REGFILE_REGFILE63_REGVAL_Pos                          0
#define REGFILE_REGFILE63_REGVAL_Msk                          (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  PMC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  PMC_PD0_SLEEP0_HW_ENA  -------------------------------------
#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos                  0
#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk                  (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos)

// -----------------------------------  PMC_PD0_SLEEP0_MODE  --------------------------------------
#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos                     0
#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk                     (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 CREG Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  CREG_IRCTRM  ------------------------------------------
#define CREG_IRCTRM_TRM_Pos                                   0
#define CREG_IRCTRM_TRM_Msk                                   (0x00000fffUL << CREG_IRCTRM_TRM_Pos)

// ---------------------------------------  CREG_CREG0  -------------------------------------------
#define CREG_CREG0_EN1KHZ_Pos                                 0
#define CREG_CREG0_EN1KHZ_Msk                                 (0x01UL << CREG_CREG0_EN1KHZ_Pos)
#define CREG_CREG0_EN32KHZ_Pos                                1
#define CREG_CREG0_EN32KHZ_Msk                                (0x01UL << CREG_CREG0_EN32KHZ_Pos)
#define CREG_CREG0_RESET32KHZ_Pos                             2
#define CREG_CREG0_RESET32KHZ_Msk                             (0x01UL << CREG_CREG0_RESET32KHZ_Pos)
#define CREG_CREG0_32KHZPD_Pos                                3
#define CREG_CREG0_32KHZPD_Msk                                (0x01UL << CREG_CREG0_32KHZPD_Pos)
#define CREG_CREG0_USB0PHY_Pos                                5
#define CREG_CREG0_USB0PHY_Msk                                (0x01UL << CREG_CREG0_USB0PHY_Pos)
#define CREG_CREG0_ALARMCTRL_Pos                              6
#define CREG_CREG0_ALARMCTRL_Msk                              (0x03UL << CREG_CREG0_ALARMCTRL_Pos)
#define CREG_CREG0_BODLVL1_Pos                                8
#define CREG_CREG0_BODLVL1_Msk                                (0x03UL << CREG_CREG0_BODLVL1_Pos)
#define CREG_CREG0_BODLVL2_Pos                                10
#define CREG_CREG0_BODLVL2_Msk                                (0x03UL << CREG_CREG0_BODLVL2_Pos)
#define CREG_CREG0_WAKEUP0CTRL_Pos                            14
#define CREG_CREG0_WAKEUP0CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos)
#define CREG_CREG0_WAKEUP1CTRL_Pos                            16
#define CREG_CREG0_WAKEUP1CTRL_Msk                            (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos)

// --------------------------------------  CREG_M4MEMMAP  -----------------------------------------
#define CREG_M4MEMMAP_M4MAP_Pos                               12
#define CREG_M4MEMMAP_M4MAP_Msk                               (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos)

// ---------------------------------------  CREG_CREG5  -------------------------------------------
#define CREG_CREG5_M4TAPSEL_Pos                               6
#define CREG_CREG5_M4TAPSEL_Msk                               (0x01UL << CREG_CREG5_M4TAPSEL_Pos)

// ---------------------------------------  CREG_DMAMUX  ------------------------------------------
#define CREG_DMAMUX_DMAMUXCH0_Pos                             0
#define CREG_DMAMUX_DMAMUXCH0_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos)
#define CREG_DMAMUX_DMAMUXCH1_Pos                             2
#define CREG_DMAMUX_DMAMUXCH1_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos)
#define CREG_DMAMUX_DMAMUXCH2_Pos                             4
#define CREG_DMAMUX_DMAMUXCH2_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos)
#define CREG_DMAMUX_DMAMUXCH3_Pos                             6
#define CREG_DMAMUX_DMAMUXCH3_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos)
#define CREG_DMAMUX_DMAMUXCH4_Pos                             8
#define CREG_DMAMUX_DMAMUXCH4_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos)
#define CREG_DMAMUX_DMAMUXCH5_Pos                             10
#define CREG_DMAMUX_DMAMUXCH5_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos)
#define CREG_DMAMUX_DMAMUXCH6_Pos                             12
#define CREG_DMAMUX_DMAMUXCH6_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos)
#define CREG_DMAMUX_DMAMUXCH7_Pos                             14
#define CREG_DMAMUX_DMAMUXCH7_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos)
#define CREG_DMAMUX_DMAMUXCH8_Pos                             16
#define CREG_DMAMUX_DMAMUXCH8_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos)
#define CREG_DMAMUX_DMAMUXCH9_Pos                             18
#define CREG_DMAMUX_DMAMUXCH9_Msk                             (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos)
#define CREG_DMAMUX_DMAMUXCH10_Pos                            20
#define CREG_DMAMUX_DMAMUXCH10_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos)
#define CREG_DMAMUX_DMAMUXCH11_Pos                            22
#define CREG_DMAMUX_DMAMUXCH11_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos)
#define CREG_DMAMUX_DMAMUXCH12_Pos                            24
#define CREG_DMAMUX_DMAMUXCH12_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos)
#define CREG_DMAMUX_DMAMUXCH13_Pos                            26
#define CREG_DMAMUX_DMAMUXCH13_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos)
#define CREG_DMAMUX_DMAMUXCH14_Pos                            28
#define CREG_DMAMUX_DMAMUXCH14_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos)
#define CREG_DMAMUX_DMAMUXCH15_Pos                            30
#define CREG_DMAMUX_DMAMUXCH15_Msk                            (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos)

// ---------------------------------------  CREG_ETBCFG  ------------------------------------------
#define CREG_ETBCFG_ETB_Pos                                   0
#define CREG_ETBCFG_ETB_Msk                                   (0x01UL << CREG_ETBCFG_ETB_Pos)

// ---------------------------------------  CREG_CREG6  -------------------------------------------
#define CREG_CREG6_ETHMODE_Pos                                0
#define CREG_CREG6_ETHMODE_Msk                                (0x07UL << CREG_CREG6_ETHMODE_Pos)
#define CREG_CREG6_TIMCTRL_Pos                                4
#define CREG_CREG6_TIMCTRL_Msk                                (0x01UL << CREG_CREG6_TIMCTRL_Pos)
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos                     12
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos)
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos                     13
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos)
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos                     14
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos)
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos                     15
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk                     (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos)
#define CREG_CREG6_EMC_CLK_SEL_Pos                            16
#define CREG_CREG6_EMC_CLK_SEL_Msk                            (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos)

// -------------------------------------  CREG_M4TXEVENT  -----------------------------------------
#define CREG_M4TXEVENT_TXEVCLR_Pos                            0
#define CREG_M4TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos)

// ---------------------------------------  CREG_CHIPID  ------------------------------------------
#define CREG_CHIPID_ID_Pos                                    0
#define CREG_CHIPID_ID_Msk                                    (0xffffffffUL << CREG_CHIPID_ID_Pos)

// -------------------------------------  CREG_M0TXEVENT  -----------------------------------------
#define CREG_M0TXEVENT_TXEVCLR_Pos                            0
#define CREG_M0TXEVENT_TXEVCLR_Msk                            (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos)

// ------------------------------------  CREG_M0APPMEMMAP  ----------------------------------------
#define CREG_M0APPMEMMAP_M0APPMAP_Pos                         12
#define CREG_M0APPMEMMAP_M0APPMAP_Msk                         (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos)


// ------------------------------------------------------------------------------------------------
// -----                              EVENTROUTER Position & Mask                             -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  EVENTROUTER_HILO  ----------------------------------------
#define EVENTROUTER_HILO_WAKEUP0_L_Pos                        0
#define EVENTROUTER_HILO_WAKEUP0_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos)
#define EVENTROUTER_HILO_WAKEUP1_L_Pos                        1
#define EVENTROUTER_HILO_WAKEUP1_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos)
#define EVENTROUTER_HILO_WAKEUP2_L_Pos                        2
#define EVENTROUTER_HILO_WAKEUP2_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos)
#define EVENTROUTER_HILO_WAKEUP3_L_Pos                        3
#define EVENTROUTER_HILO_WAKEUP3_L_Msk                        (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos)
#define EVENTROUTER_HILO_ATIMER_L_Pos                         4
#define EVENTROUTER_HILO_ATIMER_L_Msk                         (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos)
#define EVENTROUTER_HILO_RTC_L_Pos                            5
#define EVENTROUTER_HILO_RTC_L_Msk                            (0x01UL << EVENTROUTER_HILO_RTC_L_Pos)
#define EVENTROUTER_HILO_BOD_L_Pos                            6
#define EVENTROUTER_HILO_BOD_L_Msk                            (0x01UL << EVENTROUTER_HILO_BOD_L_Pos)
#define EVENTROUTER_HILO_WWDT_L_Pos                           7
#define EVENTROUTER_HILO_WWDT_L_Msk                           (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos)
#define EVENTROUTER_HILO_ETH_L_Pos                            8
#define EVENTROUTER_HILO_ETH_L_Msk                            (0x01UL << EVENTROUTER_HILO_ETH_L_Pos)
#define EVENTROUTER_HILO_USB0_L_Pos                           9
#define EVENTROUTER_HILO_USB0_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB0_L_Pos)
#define EVENTROUTER_HILO_USB1_L_Pos                           10
#define EVENTROUTER_HILO_USB1_L_Msk                           (0x01UL << EVENTROUTER_HILO_USB1_L_Pos)
#define EVENTROUTER_HILO_SDMMC_L_Pos                          11
#define EVENTROUTER_HILO_SDMMC_L_Msk                          (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos)
#define EVENTROUTER_HILO_CAN_L_Pos                            12
#define EVENTROUTER_HILO_CAN_L_Msk                            (0x01UL << EVENTROUTER_HILO_CAN_L_Pos)
#define EVENTROUTER_HILO_TIM2_L_Pos                           13
#define EVENTROUTER_HILO_TIM2_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos)
#define EVENTROUTER_HILO_TIM6_L_Pos                           14
#define EVENTROUTER_HILO_TIM6_L_Msk                           (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos)
#define EVENTROUTER_HILO_QEI_L_Pos                            15
#define EVENTROUTER_HILO_QEI_L_Msk                            (0x01UL << EVENTROUTER_HILO_QEI_L_Pos)
#define EVENTROUTER_HILO_TIM14_L_Pos                          16
#define EVENTROUTER_HILO_TIM14_L_Msk                          (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos)
#define EVENTROUTER_HILO_RESET_L_Pos                          19
#define EVENTROUTER_HILO_RESET_L_Msk                          (0x01UL << EVENTROUTER_HILO_RESET_L_Pos)

// ------------------------------------  EVENTROUTER_EDGE  ----------------------------------------
#define EVENTROUTER_EDGE_WAKEUP0_E_Pos                        0
#define EVENTROUTER_EDGE_WAKEUP0_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos)
#define EVENTROUTER_EDGE_WAKEUP1_E_Pos                        1
#define EVENTROUTER_EDGE_WAKEUP1_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos)
#define EVENTROUTER_EDGE_WAKEUP2_E_Pos                        2
#define EVENTROUTER_EDGE_WAKEUP2_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos)
#define EVENTROUTER_EDGE_WAKEUP3_E_Pos                        3
#define EVENTROUTER_EDGE_WAKEUP3_E_Msk                        (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos)
#define EVENTROUTER_EDGE_ATIMER_E_Pos                         4
#define EVENTROUTER_EDGE_ATIMER_E_Msk                         (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos)
#define EVENTROUTER_EDGE_RTC_E_Pos                            5
#define EVENTROUTER_EDGE_RTC_E_Msk                            (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos)
#define EVENTROUTER_EDGE_BOD_E_Pos                            6
#define EVENTROUTER_EDGE_BOD_E_Msk                            (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos)
#define EVENTROUTER_EDGE_WWDT_E_Pos                           7
#define EVENTROUTER_EDGE_WWDT_E_Msk                           (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos)
#define EVENTROUTER_EDGE_ETH_E_Pos                            8
#define EVENTROUTER_EDGE_ETH_E_Msk                            (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos)
#define EVENTROUTER_EDGE_USB0_E_Pos                           9
#define EVENTROUTER_EDGE_USB0_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos)
#define EVENTROUTER_EDGE_USB1_E_Pos                           10
#define EVENTROUTER_EDGE_USB1_E_Msk                           (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos)
#define EVENTROUTER_EDGE_SDMMC_E_Pos                          11
#define EVENTROUTER_EDGE_SDMMC_E_Msk                          (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos)
#define EVENTROUTER_EDGE_CAN_E_Pos                            12
#define EVENTROUTER_EDGE_CAN_E_Msk                            (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos)
#define EVENTROUTER_EDGE_TIM2_E_Pos                           13
#define EVENTROUTER_EDGE_TIM2_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos)
#define EVENTROUTER_EDGE_TIM6_E_Pos                           14
#define EVENTROUTER_EDGE_TIM6_E_Msk                           (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos)
#define EVENTROUTER_EDGE_QEI_E_Pos                            15
#define EVENTROUTER_EDGE_QEI_E_Msk                            (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos)
#define EVENTROUTER_EDGE_TIM14_E_Pos                          16
#define EVENTROUTER_EDGE_TIM14_E_Msk                          (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos)
#define EVENTROUTER_EDGE_RESET_E_Pos                          19
#define EVENTROUTER_EDGE_RESET_E_Msk                          (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos)

// -----------------------------------  EVENTROUTER_CLR_EN  ---------------------------------------
#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos                  0
#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos)
#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos                  1
#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos)
#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos                  2
#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos)
#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos                  3
#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk                  (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos)
#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos                   4
#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk                   (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos)
#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos                      5
#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos)
#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos                      6
#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos)
#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos                     7
#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos)
#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos                      8
#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos)
#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos                     9
#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos)
#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos                     10
#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos)
#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos                    11
#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos)
#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos                      12
#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos)
#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos                     13
#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos)
#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos                     14
#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk                     (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos)
#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos                      15
#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk                      (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos)
#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos                    16
#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos)
#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos                    19
#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk                    (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos)

// -----------------------------------  EVENTROUTER_SET_EN  ---------------------------------------
#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos                  0
#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos)
#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos                  1
#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos)
#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos                  2
#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos)
#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos                  3
#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk                  (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos)
#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos                   4
#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk                   (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos)
#define EVENTROUTER_SET_EN_RTC_SETEN_Pos                      5
#define EVENTROUTER_SET_EN_RTC_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos)
#define EVENTROUTER_SET_EN_BOD_SETEN_Pos                      6
#define EVENTROUTER_SET_EN_BOD_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos)
#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos                     7
#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos)
#define EVENTROUTER_SET_EN_ETH_SETEN_Pos                      8
#define EVENTROUTER_SET_EN_ETH_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos)
#define EVENTROUTER_SET_EN_USB0_SETEN_Pos                     9
#define EVENTROUTER_SET_EN_USB0_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos)
#define EVENTROUTER_SET_EN_USB1_SETEN_Pos                     10
#define EVENTROUTER_SET_EN_USB1_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos)
#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos                    11
#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos)
#define EVENTROUTER_SET_EN_CAN_SETEN_Pos                      12
#define EVENTROUTER_SET_EN_CAN_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos)
#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos                     13
#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos)
#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos                     14
#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk                     (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos)
#define EVENTROUTER_SET_EN_QEI_SETEN_Pos                      15
#define EVENTROUTER_SET_EN_QEI_SETEN_Msk                      (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos)
#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos                    16
#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos)
#define EVENTROUTER_SET_EN_RESET_SETEN_Pos                    19
#define EVENTROUTER_SET_EN_RESET_SETEN_Msk                    (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos)

// -----------------------------------  EVENTROUTER_STATUS  ---------------------------------------
#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos                     0
#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos)
#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos                     1
#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos)
#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos                     2
#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos)
#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos                     3
#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk                     (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos)
#define EVENTROUTER_STATUS_ATIMER_ST_Pos                      4
#define EVENTROUTER_STATUS_ATIMER_ST_Msk                      (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos)
#define EVENTROUTER_STATUS_RTC_ST_Pos                         5
#define EVENTROUTER_STATUS_RTC_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos)
#define EVENTROUTER_STATUS_BOD_ST_Pos                         6
#define EVENTROUTER_STATUS_BOD_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos)
#define EVENTROUTER_STATUS_WWDT_ST_Pos                        7
#define EVENTROUTER_STATUS_WWDT_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos)
#define EVENTROUTER_STATUS_ETH_ST_Pos                         8
#define EVENTROUTER_STATUS_ETH_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos)
#define EVENTROUTER_STATUS_USB0_ST_Pos                        9
#define EVENTROUTER_STATUS_USB0_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos)
#define EVENTROUTER_STATUS_USB1_ST_Pos                        10
#define EVENTROUTER_STATUS_USB1_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos)
#define EVENTROUTER_STATUS_SDMMC_ST_Pos                       11
#define EVENTROUTER_STATUS_SDMMC_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos)
#define EVENTROUTER_STATUS_CAN_ST_Pos                         12
#define EVENTROUTER_STATUS_CAN_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos)
#define EVENTROUTER_STATUS_TIM2_ST_Pos                        13
#define EVENTROUTER_STATUS_TIM2_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos)
#define EVENTROUTER_STATUS_TIM6_ST_Pos                        14
#define EVENTROUTER_STATUS_TIM6_ST_Msk                        (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos)
#define EVENTROUTER_STATUS_QEI_ST_Pos                         15
#define EVENTROUTER_STATUS_QEI_ST_Msk                         (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos)
#define EVENTROUTER_STATUS_TIM14_ST_Pos                       16
#define EVENTROUTER_STATUS_TIM14_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos)
#define EVENTROUTER_STATUS_RESET_ST_Pos                       19
#define EVENTROUTER_STATUS_RESET_ST_Msk                       (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos)

// -----------------------------------  EVENTROUTER_ENABLE  ---------------------------------------
#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos                     0
#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos)
#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos                     1
#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos)
#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos                     2
#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos)
#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos                     3
#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk                     (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos)
#define EVENTROUTER_ENABLE_ATIMER_EN_Pos                      4
#define EVENTROUTER_ENABLE_ATIMER_EN_Msk                      (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos)
#define EVENTROUTER_ENABLE_RTC_EN_Pos                         5
#define EVENTROUTER_ENABLE_RTC_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos)
#define EVENTROUTER_ENABLE_BOD_EN_Pos                         6
#define EVENTROUTER_ENABLE_BOD_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos)
#define EVENTROUTER_ENABLE_WWDT_EN_Pos                        7
#define EVENTROUTER_ENABLE_WWDT_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos)
#define EVENTROUTER_ENABLE_ETH_EN_Pos                         8
#define EVENTROUTER_ENABLE_ETH_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos)
#define EVENTROUTER_ENABLE_USB0_EN_Pos                        9
#define EVENTROUTER_ENABLE_USB0_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos)
#define EVENTROUTER_ENABLE_USB1_EN_Pos                        10
#define EVENTROUTER_ENABLE_USB1_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos)
#define EVENTROUTER_ENABLE_SDMMC_EN_Pos                       11
#define EVENTROUTER_ENABLE_SDMMC_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos)
#define EVENTROUTER_ENABLE_CAN_EN_Pos                         12
#define EVENTROUTER_ENABLE_CAN_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos)
#define EVENTROUTER_ENABLE_TIM2_EN_Pos                        13
#define EVENTROUTER_ENABLE_TIM2_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos)
#define EVENTROUTER_ENABLE_TIM6_EN_Pos                        14
#define EVENTROUTER_ENABLE_TIM6_EN_Msk                        (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos)
#define EVENTROUTER_ENABLE_QEI_EN_Pos                         15
#define EVENTROUTER_ENABLE_QEI_EN_Msk                         (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos)
#define EVENTROUTER_ENABLE_TIM14_EN_Pos                       16
#define EVENTROUTER_ENABLE_TIM14_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos)
#define EVENTROUTER_ENABLE_RESET_EN_Pos                       19
#define EVENTROUTER_ENABLE_RESET_EN_Msk                       (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos)

// ----------------------------------  EVENTROUTER_CLR_STAT  --------------------------------------
#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos                0
#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos                1
#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos                2
#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos                3
#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk                (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos                 4
#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk                 (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos                    5
#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos                    6
#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos                   7
#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos                    8
#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos                   9
#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos                   10
#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos                  11
#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos                    12
#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos                   13
#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos                   14
#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk                   (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos                    15
#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk                    (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos                  16
#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos)
#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos                  19
#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk                  (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos)

// ----------------------------------  EVENTROUTER_SET_STAT  --------------------------------------
#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos                0
#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos)
#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos                1
#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos)
#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos                2
#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos)
#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos                3
#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk                (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos)
#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos                 4
#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk                 (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos)
#define EVENTROUTER_SET_STAT_RTC_SETST_Pos                    5
#define EVENTROUTER_SET_STAT_RTC_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos)
#define EVENTROUTER_SET_STAT_BOD_SETST_Pos                    6
#define EVENTROUTER_SET_STAT_BOD_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos)
#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos                   7
#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos)
#define EVENTROUTER_SET_STAT_ETH_SETST_Pos                    8
#define EVENTROUTER_SET_STAT_ETH_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos)
#define EVENTROUTER_SET_STAT_USB0_SETST_Pos                   9
#define EVENTROUTER_SET_STAT_USB0_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos)
#define EVENTROUTER_SET_STAT_USB1_SETST_Pos                   10
#define EVENTROUTER_SET_STAT_USB1_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos)
#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos                  11
#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos)
#define EVENTROUTER_SET_STAT_CAN_SETST_Pos                    12
#define EVENTROUTER_SET_STAT_CAN_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos)
#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos                   13
#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos)
#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos                   14
#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk                   (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos)
#define EVENTROUTER_SET_STAT_QEI_SETST_Pos                    15
#define EVENTROUTER_SET_STAT_QEI_SETST_Msk                    (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos)
#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos                  16
#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos)
#define EVENTROUTER_SET_STAT_RESET_SETST_Pos                  19
#define EVENTROUTER_SET_STAT_RESET_SETST_Msk                  (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  RTC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  RTC_ILR  --------------------------------------------
#define RTC_ILR_RTCCIF_Pos                                    0
#define RTC_ILR_RTCCIF_Msk                                    (0x01UL << RTC_ILR_RTCCIF_Pos)
#define RTC_ILR_RTCALF_Pos                                    1
#define RTC_ILR_RTCALF_Msk                                    (0x01UL << RTC_ILR_RTCALF_Pos)

// -----------------------------------------  RTC_CCR  --------------------------------------------
#define RTC_CCR_CLKEN_Pos                                     0
#define RTC_CCR_CLKEN_Msk                                     (0x01UL << RTC_CCR_CLKEN_Pos)
#define RTC_CCR_CTCRST_Pos                                    1
#define RTC_CCR_CTCRST_Msk                                    (0x01UL << RTC_CCR_CTCRST_Pos)
#define RTC_CCR_CCALEN_Pos                                    4
#define RTC_CCR_CCALEN_Msk                                    (0x01UL << RTC_CCR_CCALEN_Pos)

// ----------------------------------------  RTC_CIIR  --------------------------------------------
#define RTC_CIIR_IMSEC_Pos                                    0
#define RTC_CIIR_IMSEC_Msk                                    (0x01UL << RTC_CIIR_IMSEC_Pos)
#define RTC_CIIR_IMMIN_Pos                                    1
#define RTC_CIIR_IMMIN_Msk                                    (0x01UL << RTC_CIIR_IMMIN_Pos)
#define RTC_CIIR_IMHOUR_Pos                                   2
#define RTC_CIIR_IMHOUR_Msk                                   (0x01UL << RTC_CIIR_IMHOUR_Pos)
#define RTC_CIIR_IMDOM_Pos                                    3
#define RTC_CIIR_IMDOM_Msk                                    (0x01UL << RTC_CIIR_IMDOM_Pos)
#define RTC_CIIR_IMDOW_Pos                                    4
#define RTC_CIIR_IMDOW_Msk                                    (0x01UL << RTC_CIIR_IMDOW_Pos)
#define RTC_CIIR_IMDOY_Pos                                    5
#define RTC_CIIR_IMDOY_Msk                                    (0x01UL << RTC_CIIR_IMDOY_Pos)
#define RTC_CIIR_IMMON_Pos                                    6
#define RTC_CIIR_IMMON_Msk                                    (0x01UL << RTC_CIIR_IMMON_Pos)
#define RTC_CIIR_IMYEAR_Pos                                   7
#define RTC_CIIR_IMYEAR_Msk                                   (0x01UL << RTC_CIIR_IMYEAR_Pos)

// -----------------------------------------  RTC_AMR  --------------------------------------------
#define RTC_AMR_AMRSEC_Pos                                    0
#define RTC_AMR_AMRSEC_Msk                                    (0x01UL << RTC_AMR_AMRSEC_Pos)
#define RTC_AMR_AMRMIN_Pos                                    1
#define RTC_AMR_AMRMIN_Msk                                    (0x01UL << RTC_AMR_AMRMIN_Pos)
#define RTC_AMR_AMRHOUR_Pos                                   2
#define RTC_AMR_AMRHOUR_Msk                                   (0x01UL << RTC_AMR_AMRHOUR_Pos)
#define RTC_AMR_AMRDOM_Pos                                    3
#define RTC_AMR_AMRDOM_Msk                                    (0x01UL << RTC_AMR_AMRDOM_Pos)
#define RTC_AMR_AMRDOW_Pos                                    4
#define RTC_AMR_AMRDOW_Msk                                    (0x01UL << RTC_AMR_AMRDOW_Pos)
#define RTC_AMR_AMRDOY_Pos                                    5
#define RTC_AMR_AMRDOY_Msk                                    (0x01UL << RTC_AMR_AMRDOY_Pos)
#define RTC_AMR_AMRMON_Pos                                    6
#define RTC_AMR_AMRMON_Msk                                    (0x01UL << RTC_AMR_AMRMON_Pos)
#define RTC_AMR_AMRYEAR_Pos                                   7
#define RTC_AMR_AMRYEAR_Msk                                   (0x01UL << RTC_AMR_AMRYEAR_Pos)

// ---------------------------------------  RTC_CTIME0  -------------------------------------------
#define RTC_CTIME0_SECONDS_Pos                                0
#define RTC_CTIME0_SECONDS_Msk                                (0x3fUL << RTC_CTIME0_SECONDS_Pos)
#define RTC_CTIME0_MINUTES_Pos                                8
#define RTC_CTIME0_MINUTES_Msk                                (0x3fUL << RTC_CTIME0_MINUTES_Pos)
#define RTC_CTIME0_HOURS_Pos                                  16
#define RTC_CTIME0_HOURS_Msk                                  (0x1fUL << RTC_CTIME0_HOURS_Pos)
#define RTC_CTIME0_DOW_Pos                                    24
#define RTC_CTIME0_DOW_Msk                                    (0x07UL << RTC_CTIME0_DOW_Pos)

// ---------------------------------------  RTC_CTIME1  -------------------------------------------
#define RTC_CTIME1_DOM_Pos                                    0
#define RTC_CTIME1_DOM_Msk                                    (0x1fUL << RTC_CTIME1_DOM_Pos)
#define RTC_CTIME1_MONTH_Pos                                  8
#define RTC_CTIME1_MONTH_Msk                                  (0x0fUL << RTC_CTIME1_MONTH_Pos)
#define RTC_CTIME1_YEAR_Pos                                   16
#define RTC_CTIME1_YEAR_Msk                                   (0x00000fffUL << RTC_CTIME1_YEAR_Pos)

// ---------------------------------------  RTC_CTIME2  -------------------------------------------
#define RTC_CTIME2_DOY_Pos                                    0
#define RTC_CTIME2_DOY_Msk                                    (0x00000fffUL << RTC_CTIME2_DOY_Pos)

// -----------------------------------------  RTC_SEC  --------------------------------------------
#define RTC_SEC_SECONDS_Pos                                   0
#define RTC_SEC_SECONDS_Msk                                   (0x3fUL << RTC_SEC_SECONDS_Pos)

// -----------------------------------------  RTC_MIN  --------------------------------------------
#define RTC_MIN_MINUTES_Pos                                   0
#define RTC_MIN_MINUTES_Msk                                   (0x3fUL << RTC_MIN_MINUTES_Pos)

// -----------------------------------------  RTC_HRS  --------------------------------------------
#define RTC_HRS_HOURS_Pos                                     0
#define RTC_HRS_HOURS_Msk                                     (0x1fUL << RTC_HRS_HOURS_Pos)

// -----------------------------------------  RTC_DOM  --------------------------------------------
#define RTC_DOM_DOM_Pos                                       0
#define RTC_DOM_DOM_Msk                                       (0x1fUL << RTC_DOM_DOM_Pos)

// -----------------------------------------  RTC_DOW  --------------------------------------------
#define RTC_DOW_DOW_Pos                                       0
#define RTC_DOW_DOW_Msk                                       (0x07UL << RTC_DOW_DOW_Pos)

// -----------------------------------------  RTC_DOY  --------------------------------------------
#define RTC_DOY_DOY_Pos                                       0
#define RTC_DOY_DOY_Msk                                       (0x000001ffUL << RTC_DOY_DOY_Pos)

// ----------------------------------------  RTC_MONTH  -------------------------------------------
#define RTC_MONTH_MONTH_Pos                                   0
#define RTC_MONTH_MONTH_Msk                                   (0x0fUL << RTC_MONTH_MONTH_Pos)

// ----------------------------------------  RTC_YEAR  --------------------------------------------
#define RTC_YEAR_YEAR_Pos                                     0
#define RTC_YEAR_YEAR_Msk                                     (0x00000fffUL << RTC_YEAR_YEAR_Pos)

// -------------------------------------  RTC_CALIBRATION  ----------------------------------------
#define RTC_CALIBRATION_CALVAL_Pos                            0
#define RTC_CALIBRATION_CALVAL_Msk                            (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos)
#define RTC_CALIBRATION_CALDIR_Pos                            17
#define RTC_CALIBRATION_CALDIR_Msk                            (0x01UL << RTC_CALIBRATION_CALDIR_Pos)

// ----------------------------------------  RTC_ASEC  --------------------------------------------
#define RTC_ASEC_SECONDS_Pos                                  0
#define RTC_ASEC_SECONDS_Msk                                  (0x3fUL << RTC_ASEC_SECONDS_Pos)

// ----------------------------------------  RTC_AMIN  --------------------------------------------
#define RTC_AMIN_MINUTES_Pos                                  0
#define RTC_AMIN_MINUTES_Msk                                  (0x3fUL << RTC_AMIN_MINUTES_Pos)

// ----------------------------------------  RTC_AHRS  --------------------------------------------
#define RTC_AHRS_HOURS_Pos                                    0
#define RTC_AHRS_HOURS_Msk                                    (0x1fUL << RTC_AHRS_HOURS_Pos)

// ----------------------------------------  RTC_ADOM  --------------------------------------------
#define RTC_ADOM_DOM_Pos                                      0
#define RTC_ADOM_DOM_Msk                                      (0x1fUL << RTC_ADOM_DOM_Pos)

// ----------------------------------------  RTC_ADOW  --------------------------------------------
#define RTC_ADOW_DOW_Pos                                      0
#define RTC_ADOW_DOW_Msk                                      (0x07UL << RTC_ADOW_DOW_Pos)

// ----------------------------------------  RTC_ADOY  --------------------------------------------
#define RTC_ADOY_DOY_Pos                                      0
#define RTC_ADOY_DOY_Msk                                      (0x000001ffUL << RTC_ADOY_DOY_Pos)

// ----------------------------------------  RTC_AMON  --------------------------------------------
#define RTC_AMON_MONTH_Pos                                    0
#define RTC_AMON_MONTH_Msk                                    (0x0fUL << RTC_AMON_MONTH_Pos)

// ----------------------------------------  RTC_AYRS  --------------------------------------------
#define RTC_AYRS_YEAR_Pos                                     0
#define RTC_AYRS_YEAR_Msk                                     (0x00000fffUL << RTC_AYRS_YEAR_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  CGU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  CGU_FREQ_MON  ------------------------------------------
#define CGU_FREQ_MON_RCNT_Pos                                 0
#define CGU_FREQ_MON_RCNT_Msk                                 (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos)
#define CGU_FREQ_MON_FCNT_Pos                                 9
#define CGU_FREQ_MON_FCNT_Msk                                 (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos)
#define CGU_FREQ_MON_MEAS_Pos                                 23
#define CGU_FREQ_MON_MEAS_Msk                                 (0x01UL << CGU_FREQ_MON_MEAS_Pos)
#define CGU_FREQ_MON_CLK_SEL_Pos                              24
#define CGU_FREQ_MON_CLK_SEL_Msk                              (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos)

// ------------------------------------  CGU_XTAL_OSC_CTRL  ---------------------------------------
#define CGU_XTAL_OSC_CTRL_ENABLE_Pos                          0
#define CGU_XTAL_OSC_CTRL_ENABLE_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos)
#define CGU_XTAL_OSC_CTRL_BYPASS_Pos                          1
#define CGU_XTAL_OSC_CTRL_BYPASS_Msk                          (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos)
#define CGU_XTAL_OSC_CTRL_HF_Pos                              2
#define CGU_XTAL_OSC_CTRL_HF_Msk                              (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos)

// ------------------------------------  CGU_PLL0USB_STAT  ----------------------------------------
#define CGU_PLL0USB_STAT_LOCK_Pos                             0
#define CGU_PLL0USB_STAT_LOCK_Msk                             (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos)
#define CGU_PLL0USB_STAT_FR_Pos                               1
#define CGU_PLL0USB_STAT_FR_Msk                               (0x01UL << CGU_PLL0USB_STAT_FR_Pos)

// ------------------------------------  CGU_PLL0USB_CTRL  ----------------------------------------
#define CGU_PLL0USB_CTRL_PD_Pos                               0
#define CGU_PLL0USB_CTRL_PD_Msk                               (0x01UL << CGU_PLL0USB_CTRL_PD_Pos)
#define CGU_PLL0USB_CTRL_BYPASS_Pos                           1
#define CGU_PLL0USB_CTRL_BYPASS_Msk                           (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos)
#define CGU_PLL0USB_CTRL_DIRECTI_Pos                          2
#define CGU_PLL0USB_CTRL_DIRECTI_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos)
#define CGU_PLL0USB_CTRL_DIRECTO_Pos                          3
#define CGU_PLL0USB_CTRL_DIRECTO_Msk                          (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos)
#define CGU_PLL0USB_CTRL_CLKEN_Pos                            4
#define CGU_PLL0USB_CTRL_CLKEN_Msk                            (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos)
#define CGU_PLL0USB_CTRL_FRM_Pos                              6
#define CGU_PLL0USB_CTRL_FRM_Msk                              (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos)
#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos                        11
#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk                        (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos)
#define CGU_PLL0USB_CTRL_CLK_SEL_Pos                          24
#define CGU_PLL0USB_CTRL_CLK_SEL_Msk                          (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos)

// ------------------------------------  CGU_PLL0USB_MDIV  ----------------------------------------
#define CGU_PLL0USB_MDIV_MDEC_Pos                             0
#define CGU_PLL0USB_MDIV_MDEC_Msk                             (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos)
#define CGU_PLL0USB_MDIV_SELP_Pos                             17
#define CGU_PLL0USB_MDIV_SELP_Msk                             (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos)
#define CGU_PLL0USB_MDIV_SELI_Pos                             22
#define CGU_PLL0USB_MDIV_SELI_Msk                             (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos)
#define CGU_PLL0USB_MDIV_SELR_Pos                             28
#define CGU_PLL0USB_MDIV_SELR_Msk                             (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos)

// -----------------------------------  CGU_PLL0USB_NP_DIV  ---------------------------------------
#define CGU_PLL0USB_NP_DIV_PDEC_Pos                           0
#define CGU_PLL0USB_NP_DIV_PDEC_Msk                           (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos)
#define CGU_PLL0USB_NP_DIV_NDEC_Pos                           12
#define CGU_PLL0USB_NP_DIV_NDEC_Msk                           (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos)

// -----------------------------------  CGU_PLL0AUDIO_STAT  ---------------------------------------
#define CGU_PLL0AUDIO_STAT_LOCK_Pos                           0
#define CGU_PLL0AUDIO_STAT_LOCK_Msk                           (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos)
#define CGU_PLL0AUDIO_STAT_FR_Pos                             1
#define CGU_PLL0AUDIO_STAT_FR_Msk                             (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos)

// -----------------------------------  CGU_PLL0AUDIO_CTRL  ---------------------------------------
#define CGU_PLL0AUDIO_CTRL_PD_Pos                             0
#define CGU_PLL0AUDIO_CTRL_PD_Msk                             (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos)
#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos                         1
#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos)
#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos                        2
#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos)
#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos                        3
#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos)
#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos                          4
#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk                          (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos)
#define CGU_PLL0AUDIO_CTRL_FRM_Pos                            6
#define CGU_PLL0AUDIO_CTRL_FRM_Msk                            (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos)
#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos                      11
#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk                      (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos)
#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos                    12
#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk                    (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos)
#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos                        13
#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk                        (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos)
#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos                         14
#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk                         (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos)
#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos                        24
#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk                        (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos)

// -----------------------------------  CGU_PLL0AUDIO_MDIV  ---------------------------------------
#define CGU_PLL0AUDIO_MDIV_MDEC_Pos                           0
#define CGU_PLL0AUDIO_MDIV_MDEC_Msk                           (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos)

// ----------------------------------  CGU_PLL0AUDIO_NP_DIV  --------------------------------------
#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos                         0
#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk                         (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos)
#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos                         12
#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk                         (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos)

// -----------------------------------  CGU_PLL0AUDIO_FRAC  ---------------------------------------
#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos                  0
#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk                  (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos)

// --------------------------------------  CGU_PLL1_STAT  -----------------------------------------
#define CGU_PLL1_STAT_LOCK_Pos                                0
#define CGU_PLL1_STAT_LOCK_Msk                                (0x01UL << CGU_PLL1_STAT_LOCK_Pos)

// --------------------------------------  CGU_PLL1_CTRL  -----------------------------------------
#define CGU_PLL1_CTRL_PD_Pos                                  0
#define CGU_PLL1_CTRL_PD_Msk                                  (0x01UL << CGU_PLL1_CTRL_PD_Pos)
#define CGU_PLL1_CTRL_BYPASS_Pos                              1
#define CGU_PLL1_CTRL_BYPASS_Msk                              (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos)
#define CGU_PLL1_CTRL_FBSEL_Pos                               6
#define CGU_PLL1_CTRL_FBSEL_Msk                               (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos)
#define CGU_PLL1_CTRL_DIRECT_Pos                              7
#define CGU_PLL1_CTRL_DIRECT_Msk                              (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos)
#define CGU_PLL1_CTRL_PSEL_Pos                                8
#define CGU_PLL1_CTRL_PSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_PSEL_Pos)
#define CGU_PLL1_CTRL_AUTOBLOCK_Pos                           11
#define CGU_PLL1_CTRL_AUTOBLOCK_Msk                           (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos)
#define CGU_PLL1_CTRL_NSEL_Pos                                12
#define CGU_PLL1_CTRL_NSEL_Msk                                (0x03UL << CGU_PLL1_CTRL_NSEL_Pos)
#define CGU_PLL1_CTRL_MSEL_Pos                                16
#define CGU_PLL1_CTRL_MSEL_Msk                                (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos)
#define CGU_PLL1_CTRL_CLK_SEL_Pos                             24
#define CGU_PLL1_CTRL_CLK_SEL_Msk                             (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos)

// -------------------------------------  CGU_IDIVA_CTRL  -----------------------------------------
#define CGU_IDIVA_CTRL_PD_Pos                                 0
#define CGU_IDIVA_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVA_CTRL_PD_Pos)
#define CGU_IDIVA_CTRL_IDIV_Pos                               2
#define CGU_IDIVA_CTRL_IDIV_Msk                               (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos)
#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos                          11
#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos)
#define CGU_IDIVA_CTRL_CLK_SEL_Pos                            24
#define CGU_IDIVA_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos)

// -------------------------------------  CGU_IDIVB_CTRL  -----------------------------------------
#define CGU_IDIVB_CTRL_PD_Pos                                 0
#define CGU_IDIVB_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVB_CTRL_PD_Pos)
#define CGU_IDIVB_CTRL_IDIV_Pos                               2
#define CGU_IDIVB_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos)
#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos                          11
#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos)
#define CGU_IDIVB_CTRL_CLK_SEL_Pos                            24
#define CGU_IDIVB_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos)

// -------------------------------------  CGU_IDIVE_CTRL  -----------------------------------------
#define CGU_IDIVE_CTRL_PD_Pos                                 0
#define CGU_IDIVE_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVE_CTRL_PD_Pos)
#define CGU_IDIVE_CTRL_IDIV_Pos                               2
#define CGU_IDIVE_CTRL_IDIV_Msk                               (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos)
#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos                          11
#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos)
#define CGU_IDIVE_CTRL_CLK_SEL_Pos                            24
#define CGU_IDIVE_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_SAFE_CLK  ---------------------------------------
#define CGU_BASE_SAFE_CLK_PD_Pos                              0
#define CGU_BASE_SAFE_CLK_PD_Msk                              (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos)
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_USB0_CLK  ---------------------------------------
#define CGU_BASE_USB0_CLK_PD_Pos                              0
#define CGU_BASE_USB0_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB0_CLK_PD_Pos)
#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_USB0_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_USB0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_PERIPH_CLK  --------------------------------------
#define CGU_BASE_PERIPH_CLK_PD_Pos                            0
#define CGU_BASE_PERIPH_CLK_PD_Msk                            (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos)
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos                     11
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos                       24
#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_USB1_CLK  ---------------------------------------
#define CGU_BASE_USB1_CLK_PD_Pos                              0
#define CGU_BASE_USB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_USB1_CLK_PD_Pos)
#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_USB1_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_USB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos)

// -------------------------------------  CGU_BASE_M4_CLK  ----------------------------------------
#define CGU_BASE_M4_CLK_PD_Pos                                0
#define CGU_BASE_M4_CLK_PD_Msk                                (0x01UL << CGU_BASE_M4_CLK_PD_Pos)
#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos                         11
#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk                         (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_M4_CLK_CLK_SEL_Pos                           24
#define CGU_BASE_M4_CLK_CLK_SEL_Msk                           (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_SPIFI_CLK  ---------------------------------------
#define CGU_BASE_SPIFI_CLK_PD_Pos                             0
#define CGU_BASE_SPIFI_CLK_PD_Msk                             (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos)
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos                      11
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos                        24
#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_SPI_CLK  ----------------------------------------
#define CGU_BASE_SPI_CLK_PD_Pos                               0
#define CGU_BASE_SPI_CLK_PD_Msk                               (0x01UL << CGU_BASE_SPI_CLK_PD_Pos)
#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos                        11
#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SPI_CLK_CLK_SEL_Pos                          24
#define CGU_BASE_SPI_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_PHY_RX_CLK  --------------------------------------
#define CGU_BASE_PHY_RX_CLK_PD_Pos                            0
#define CGU_BASE_PHY_RX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos)
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos                     11
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos                       24
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_PHY_TX_CLK  --------------------------------------
#define CGU_BASE_PHY_TX_CLK_PD_Pos                            0
#define CGU_BASE_PHY_TX_CLK_PD_Msk                            (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos)
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos                     11
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk                     (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos                       24
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk                       (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_APB1_CLK  ---------------------------------------
#define CGU_BASE_APB1_CLK_PD_Pos                              0
#define CGU_BASE_APB1_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB1_CLK_PD_Pos)
#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_APB1_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_APB1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_APB3_CLK  ---------------------------------------
#define CGU_BASE_APB3_CLK_PD_Pos                              0
#define CGU_BASE_APB3_CLK_PD_Msk                              (0x01UL << CGU_BASE_APB3_CLK_PD_Pos)
#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_APB3_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_APB3_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_LCD_CLK  ----------------------------------------
#define CGU_BASE_LCD_CLK_PD_Pos                               0
#define CGU_BASE_LCD_CLK_PD_Msk                               (0x01UL << CGU_BASE_LCD_CLK_PD_Pos)
#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos                        11
#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_LCD_CLK_CLK_SEL_Pos                          24
#define CGU_BASE_LCD_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_SDIO_CLK  ---------------------------------------
#define CGU_BASE_SDIO_CLK_PD_Pos                              0
#define CGU_BASE_SDIO_CLK_PD_Msk                              (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos)
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_SSP0_CLK  ---------------------------------------
#define CGU_BASE_SSP0_CLK_PD_Pos                              0
#define CGU_BASE_SSP0_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos)
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_SSP1_CLK  ---------------------------------------
#define CGU_BASE_SSP1_CLK_PD_Pos                              0
#define CGU_BASE_SSP1_CLK_PD_Msk                              (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos)
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_UART0_CLK  ---------------------------------------
#define CGU_BASE_UART0_CLK_PD_Pos                             0
#define CGU_BASE_UART0_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART0_CLK_PD_Pos)
#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos                      11
#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_UART0_CLK_CLK_SEL_Pos                        24
#define CGU_BASE_UART0_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_UART1_CLK  ---------------------------------------
#define CGU_BASE_UART1_CLK_PD_Pos                             0
#define CGU_BASE_UART1_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART1_CLK_PD_Pos)
#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos                      11
#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_UART1_CLK_CLK_SEL_Pos                        24
#define CGU_BASE_UART1_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_UART2_CLK  ---------------------------------------
#define CGU_BASE_UART2_CLK_PD_Pos                             0
#define CGU_BASE_UART2_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART2_CLK_PD_Pos)
#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos                      11
#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_UART2_CLK_CLK_SEL_Pos                        24
#define CGU_BASE_UART2_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos)

// -----------------------------------  CGU_BASE_UART3_CLK  ---------------------------------------
#define CGU_BASE_UART3_CLK_PD_Pos                             0
#define CGU_BASE_UART3_CLK_PD_Msk                             (0x01UL << CGU_BASE_UART3_CLK_PD_Pos)
#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos                      11
#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk                      (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_UART3_CLK_CLK_SEL_Pos                        24
#define CGU_BASE_UART3_CLK_CLK_SEL_Msk                        (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_OUT_CLK  ----------------------------------------
#define CGU_BASE_OUT_CLK_PD_Pos                               0
#define CGU_BASE_OUT_CLK_PD_Msk                               (0x01UL << CGU_BASE_OUT_CLK_PD_Pos)
#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos                        11
#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk                        (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_OUT_CLK_CLK_SEL_Pos                          24
#define CGU_BASE_OUT_CLK_CLK_SEL_Msk                          (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos)

// ------------------------------------  CGU_BASE_APLL_CLK  ---------------------------------------
#define CGU_BASE_APLL_CLK_PD_Pos                              0
#define CGU_BASE_APLL_CLK_PD_Msk                              (0x01UL << CGU_BASE_APLL_CLK_PD_Pos)
#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos                       11
#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk                       (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_APLL_CLK_CLK_SEL_Pos                         24
#define CGU_BASE_APLL_CLK_CLK_SEL_Msk                         (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos)

// ----------------------------------  CGU_BASE_CGU_OUT0_CLK  -------------------------------------
#define CGU_BASE_CGU_OUT0_CLK_PD_Pos                          0
#define CGU_BASE_CGU_OUT0_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos)
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos                   11
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos                     24
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos)

// ----------------------------------  CGU_BASE_CGU_OUT1_CLK  -------------------------------------
#define CGU_BASE_CGU_OUT1_CLK_PD_Pos                          0
#define CGU_BASE_CGU_OUT1_CLK_PD_Msk                          (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos)
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos                   11
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk                   (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos)
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos                     24
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk                     (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos)

// -------------------------------------  CGU_IDIVC_CTRL  -----------------------------------------
#define CGU_IDIVC_CTRL_PD_Pos                                 0
#define CGU_IDIVC_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVC_CTRL_PD_Pos)
#define CGU_IDIVC_CTRL_IDIV_Pos                               2
#define CGU_IDIVC_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos)
#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos                          11
#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos)
#define CGU_IDIVC_CTRL_CLK_SEL_Pos                            24
#define CGU_IDIVC_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos)

// -------------------------------------  CGU_IDIVD_CTRL  -----------------------------------------
#define CGU_IDIVD_CTRL_PD_Pos                                 0
#define CGU_IDIVD_CTRL_PD_Msk                                 (0x01UL << CGU_IDIVD_CTRL_PD_Pos)
#define CGU_IDIVD_CTRL_IDIV_Pos                               2
#define CGU_IDIVD_CTRL_IDIV_Msk                               (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos)
#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos                          11
#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk                          (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos)
#define CGU_IDIVD_CTRL_CLK_SEL_Pos                            24
#define CGU_IDIVD_CTRL_CLK_SEL_Msk                            (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 CCU1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  CCU1_PM  --------------------------------------------
#define CCU1_PM_PD_Pos                                        0
#define CCU1_PM_PD_Msk                                        (0x01UL << CCU1_PM_PD_Pos)

// -------------------------------------  CCU1_BASE_STAT  -----------------------------------------
#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos                  0
#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos)
#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos                  1
#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos)
#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos                 2
#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk                 (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos)
#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos                    3
#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk                    (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos)
#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos                  7
#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos)
#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos                  8
#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk                  (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos)

// ----------------------------------  CCU1_CLK_APB3_BUS_CFG  -------------------------------------
#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos                         0
#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos)
#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos                        1
#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_BUS_STAT  -------------------------------------
#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos                        0
#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos)
#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos                       1
#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_I2C1_CFG  -------------------------------------
#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos                        0
#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos)
#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos                       1
#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_I2C1_STAT  ------------------------------------
#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos                       0
#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos)
#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_APB3_DAC_CFG  -------------------------------------
#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos                         0
#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos)
#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos                        1
#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_DAC_STAT  -------------------------------------
#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos                        0
#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos)
#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos                       1
#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_ADC0_CFG  -------------------------------------
#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos                        0
#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos)
#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos                       1
#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_ADC0_STAT  ------------------------------------
#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos                       0
#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos)
#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_ADC1_CFG  -------------------------------------
#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos                        0
#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos)
#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos                       1
#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_ADC1_STAT  ------------------------------------
#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos                       0
#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos)
#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_CAN0_CFG  -------------------------------------
#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos                        0
#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos)
#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos                       1
#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos)
#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB3_CAN0_STAT  ------------------------------------
#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos                       0
#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos)
#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos)
#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_APB1_BUS_CFG  -------------------------------------
#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos                         0
#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos)
#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos                        1
#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos)
#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB1_BUS_STAT  -------------------------------------
#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos                        0
#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos)
#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos                       1
#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos)
#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos)

// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_CFG  ----------------------------------
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos                  0
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk                  (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos)
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos                 1
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos)
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos               2
#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk               (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos)

// ------------------------------  CCU1_CLK_APB1_MOTOCONPWM_STAT  ---------------------------------
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos                 0
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk                 (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos)
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos                1
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk                (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos)
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos              2
#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk              (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_ABP1_I2C0_CFG  -------------------------------------
#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos                        0
#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos)
#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos                       1
#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos)
#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB1_I2C0_STAT  ------------------------------------
#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos                       0
#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos)
#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos)
#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_APB1_I2S_CFG  -------------------------------------
#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos                         0
#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos)
#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos                        1
#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos)
#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB1_I2S_STAT  -------------------------------------
#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos                        0
#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos)
#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos                       1
#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos)
#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB1_CAN1_CFG  -------------------------------------
#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos                        0
#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos)
#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos                       1
#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos)
#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_APB1_CAN1_STAT  ------------------------------------
#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos                       0
#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos)
#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos                      1
#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos)
#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_SPIFI_CFG  ---------------------------------------
#define CCU1_CLK_SPIFI_CFG_RUN_Pos                            0
#define CCU1_CLK_SPIFI_CFG_RUN_Msk                            (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos)
#define CCU1_CLK_SPIFI_CFG_AUTO_Pos                           1
#define CCU1_CLK_SPIFI_CFG_AUTO_Msk                           (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos)
#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos                         2
#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk                         (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_SPIFI_STAT  --------------------------------------
#define CCU1_CLK_SPIFI_STAT_RUN_Pos                           0
#define CCU1_CLK_SPIFI_STAT_RUN_Msk                           (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos)
#define CCU1_CLK_SPIFI_STAT_AUTO_Pos                          1
#define CCU1_CLK_SPIFI_STAT_AUTO_Msk                          (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos)
#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos                        2
#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk                        (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_BUS_CFG  --------------------------------------
#define CCU1_CLK_M4_BUS_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_BUS_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos)
#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos)
#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_BUS_STAT  --------------------------------------
#define CCU1_CLK_M4_BUS_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_BUS_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos)
#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos)
#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SPIFI_CFG  -------------------------------------
#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos                         0
#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos)
#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos                        1
#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_SPIFI_STAT  -------------------------------------
#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos                        0
#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos)
#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos                       1
#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_GPIO_CFG  --------------------------------------
#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos)
#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos)
#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_GPIO_STAT  -------------------------------------
#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos)
#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos)
#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_LCD_CFG  --------------------------------------
#define CCU1_CLK_M4_LCD_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_LCD_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos)
#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos)
#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_LCD_STAT  --------------------------------------
#define CCU1_CLK_M4_LCD_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_LCD_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos)
#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos)
#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_M4_ETHERNET_CFG  ------------------------------------
#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos                      0
#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos)
#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos                     1
#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos)
#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos                   2
#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_M4_ETHERNET_STAT  -----------------------------------
#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos                     0
#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos)
#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos                    1
#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos)
#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos                  2
#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_USB0_CFG  --------------------------------------
#define CCU1_CLK_M4_USB0_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_USB0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos)
#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos)
#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_USB0_STAT  -------------------------------------
#define CCU1_CLK_M4_USB0_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_USB0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos)
#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos)
#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_EMC_CFG  --------------------------------------
#define CCU1_CLK_M4_EMC_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_EMC_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos)
#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos)
#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_EMC_STAT  --------------------------------------
#define CCU1_CLK_M4_EMC_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_EMC_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos)
#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos)
#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SDIO_CFG  --------------------------------------
#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos)
#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SDIO_STAT  -------------------------------------
#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos)
#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_DMA_CFG  --------------------------------------
#define CCU1_CLK_M4_DMA_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_DMA_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos)
#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos)
#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_DMA_STAT  --------------------------------------
#define CCU1_CLK_M4_DMA_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_DMA_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos)
#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos)
#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_M4CORE_CFG  -------------------------------------
#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos)
#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos)
#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_M3CORE_STAT  ------------------------------------
#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos)
#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos)
#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_SCT_CFG  --------------------------------------
#define CCU1_CLK_M4_SCT_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_SCT_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos)
#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SCT_STAT  --------------------------------------
#define CCU1_CLK_M4_SCT_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_SCT_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos)
#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_USB1_CFG  --------------------------------------
#define CCU1_CLK_M4_USB1_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_USB1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos)
#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos)
#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_USB1_STAT  -------------------------------------
#define CCU1_CLK_M4_USB1_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_USB1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos)
#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos)
#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_EMCDIV_CFG  -------------------------------------
#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos)
#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos)
#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_EMCDIV_STAT  ------------------------------------
#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos)
#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos)
#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_M0APP_CFG  -------------------------------------
#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos                         0
#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos)
#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos                        1
#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos)
#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_M0APP_STAT  -------------------------------------
#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos                        0
#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos)
#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos                       1
#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos)
#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_WWDT_CFG  --------------------------------------
#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos)
#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos)
#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_WWDT_STAT  -------------------------------------
#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos)
#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos)
#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART0_CFG  -------------------------------------
#define CCU1_CLK_M4_USART0_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_USART0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos)
#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos)
#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART0_STAT  ------------------------------------
#define CCU1_CLK_M4_USART0_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_USART0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos)
#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos)
#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_UART1_CFG  -------------------------------------
#define CCU1_CLK_M4_UART1_CFG_RUN_Pos                         0
#define CCU1_CLK_M4_UART1_CFG_RUN_Msk                         (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos)
#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos                        1
#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos)
#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos                      2
#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_UART1_STAT  -------------------------------------
#define CCU1_CLK_M4_UART1_STAT_RUN_Pos                        0
#define CCU1_CLK_M4_UART1_STAT_RUN_Msk                        (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos)
#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos                       1
#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos)
#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos                     2
#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SSP0_CFG  --------------------------------------
#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos)
#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SSP0_STAT  -------------------------------------
#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos)
#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER0_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos)
#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos)
#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER0_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos)
#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos)
#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER1_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos)
#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos)
#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER1_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos)
#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos)
#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_SCU_CFG  --------------------------------------
#define CCU1_CLK_M4_SCU_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_SCU_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos)
#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SCU_STAT  --------------------------------------
#define CCU1_CLK_M4_SCU_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_SCU_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos)
#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_CREG_CFG  --------------------------------------
#define CCU1_CLK_M4_CREG_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_CREG_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos)
#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos)
#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_CREG_STAT  -------------------------------------
#define CCU1_CLK_M4_CREG_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_CREG_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos)
#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos)
#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_RITIMER_CFG  ------------------------------------
#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos                       0
#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos)
#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos                      1
#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos)
#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos                    2
#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_M4_RITIMER_STAT  ------------------------------------
#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos                      0
#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos)
#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos                     1
#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos)
#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos                   2
#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART2_CFG  -------------------------------------
#define CCU1_CLK_M4_USART2_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_USART2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos)
#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos)
#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART2_STAT  ------------------------------------
#define CCU1_CLK_M4_USART2_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_USART2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos)
#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos)
#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART3_CFG  -------------------------------------
#define CCU1_CLK_M4_USART3_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_USART3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos)
#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos)
#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_USART3_STAT  ------------------------------------
#define CCU1_CLK_M4_USART3_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_USART3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos)
#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos)
#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER2_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos)
#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos)
#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER2_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos)
#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos)
#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER3_CFG  -------------------------------------
#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos                        0
#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk                        (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos)
#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos                       1
#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos)
#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos                     2
#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk                     (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_M4_TIMER3_STAT  ------------------------------------
#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos                       0
#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk                       (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos)
#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos                      1
#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk                      (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos)
#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos                    2
#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk                    (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SSP1_CFG  --------------------------------------
#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos                          0
#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk                          (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos)
#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos                         1
#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos)
#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos                       2
#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_SSP1_STAT  -------------------------------------
#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos                         0
#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk                         (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos)
#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos                        1
#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk                        (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos)
#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos                      2
#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk                      (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_M4_QEI_CFG  --------------------------------------
#define CCU1_CLK_M4_QEI_CFG_RUN_Pos                           0
#define CCU1_CLK_M4_QEI_CFG_RUN_Msk                           (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos)
#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos                          1
#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk                          (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos)
#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos                        2
#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk                        (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos)

// ----------------------------------  CCU1_CLK_M4_QEI_STAT  --------------------------------------
#define CCU1_CLK_M4_QEI_STAT_RUN_Pos                          0
#define CCU1_CLK_M4_QEI_STAT_RUN_Msk                          (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos)
#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos                         1
#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk                         (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos)
#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos                       2
#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk                       (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos)

// ---------------------------------  CCU1_CLK_PERIPH_BUS_CFG  ------------------------------------
#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos                       0
#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk                       (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos)
#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos                      1
#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos)
#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos                    2
#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk                    (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_PERIPH_BUS_STAT  ------------------------------------
#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos                      0
#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos)
#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos                     1
#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos)
#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos                   2
#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_PERIPH_CORE_CFG  ------------------------------------
#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos                      0
#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk                      (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos)
#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos                     1
#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos)
#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos                   2
#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk                   (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_PERIPH_CORE_STAT  -----------------------------------
#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos                     0
#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos)
#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos                    1
#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos)
#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos                  2
#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos)

// --------------------------------  CCU1_CLK_PERIPH_SGPIO_CFG  -----------------------------------
#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos                     0
#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk                     (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos)
#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos                    1
#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos)
#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos                  2
#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk                  (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos)

// -------------------------------  CCU1_CLK_PERIPH_SGPIO_STAT  -----------------------------------
#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos                    0
#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk                    (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos)
#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos                   1
#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk                   (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos)
#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos                 2
#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk                 (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos)

// ------------------------------------  CCU1_CLK_USB0_CFG  ---------------------------------------
#define CCU1_CLK_USB0_CFG_RUN_Pos                             0
#define CCU1_CLK_USB0_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos)
#define CCU1_CLK_USB0_CFG_AUTO_Pos                            1
#define CCU1_CLK_USB0_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos)
#define CCU1_CLK_USB0_CFG_WAKEUP_Pos                          2
#define CCU1_CLK_USB0_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_USB0_STAT  ---------------------------------------
#define CCU1_CLK_USB0_STAT_RUN_Pos                            0
#define CCU1_CLK_USB0_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos)
#define CCU1_CLK_USB0_STAT_AUTO_Pos                           1
#define CCU1_CLK_USB0_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos)
#define CCU1_CLK_USB0_STAT_WAKEUP_Pos                         2
#define CCU1_CLK_USB0_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos)

// ------------------------------------  CCU1_CLK_USB1_CFG  ---------------------------------------
#define CCU1_CLK_USB1_CFG_RUN_Pos                             0
#define CCU1_CLK_USB1_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos)
#define CCU1_CLK_USB1_CFG_AUTO_Pos                            1
#define CCU1_CLK_USB1_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos)
#define CCU1_CLK_USB1_CFG_WAKEUP_Pos                          2
#define CCU1_CLK_USB1_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_USB1_STAT  ---------------------------------------
#define CCU1_CLK_USB1_STAT_RUN_Pos                            0
#define CCU1_CLK_USB1_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos)
#define CCU1_CLK_USB1_STAT_AUTO_Pos                           1
#define CCU1_CLK_USB1_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos)
#define CCU1_CLK_USB1_STAT_WAKEUP_Pos                         2
#define CCU1_CLK_USB1_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos)

// ------------------------------------  CCU1_CLK_SPI_CFG  ----------------------------------------
#define CCU1_CLK_SPI_CFG_RUN_Pos                              0
#define CCU1_CLK_SPI_CFG_RUN_Msk                              (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos)
#define CCU1_CLK_SPI_CFG_AUTO_Pos                             1
#define CCU1_CLK_SPI_CFG_AUTO_Msk                             (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos)
#define CCU1_CLK_SPI_CFG_WAKEUP_Pos                           2
#define CCU1_CLK_SPI_CFG_WAKEUP_Msk                           (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos)

// ------------------------------------  CCU1_CLK_SPI_STAT  ---------------------------------------
#define CCU1_CLK_SPI_STAT_RUN_Pos                             0
#define CCU1_CLK_SPI_STAT_RUN_Msk                             (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos)
#define CCU1_CLK_SPI_STAT_AUTO_Pos                            1
#define CCU1_CLK_SPI_STAT_AUTO_Msk                            (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos)
#define CCU1_CLK_SPI_STAT_WAKEUP_Pos                          2
#define CCU1_CLK_SPI_STAT_WAKEUP_Msk                          (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos)

// ------------------------------------  CCU1_CLK_VADC_CFG  ---------------------------------------
#define CCU1_CLK_VADC_CFG_RUN_Pos                             0
#define CCU1_CLK_VADC_CFG_RUN_Msk                             (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos)
#define CCU1_CLK_VADC_CFG_AUTO_Pos                            1
#define CCU1_CLK_VADC_CFG_AUTO_Msk                            (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos)
#define CCU1_CLK_VADC_CFG_WAKEUP_Pos                          2
#define CCU1_CLK_VADC_CFG_WAKEUP_Msk                          (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos)

// -----------------------------------  CCU1_CLK_VADC_STAT  ---------------------------------------
#define CCU1_CLK_VADC_STAT_RUN_Pos                            0
#define CCU1_CLK_VADC_STAT_RUN_Msk                            (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos)
#define CCU1_CLK_VADC_STAT_AUTO_Pos                           1
#define CCU1_CLK_VADC_STAT_AUTO_Msk                           (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos)
#define CCU1_CLK_VADC_STAT_WAKEUP_Pos                         2
#define CCU1_CLK_VADC_STAT_WAKEUP_Msk                         (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 CCU2 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  CCU2_PM  --------------------------------------------
#define CCU2_PM_PD_Pos                                        0
#define CCU2_PM_PD_Msk                                        (0x01UL << CCU2_PM_PD_Pos)

// -------------------------------------  CCU2_BASE_STAT  -----------------------------------------
#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos                     1
#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos)
#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos                     2
#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos)
#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos                     3
#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos)
#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos                     4
#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk                     (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos)
#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos                      5
#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos)
#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos                      6
#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk                      (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos)

// ------------------------------------  CCU2_CLK_APLL_CFG  ---------------------------------------
#define CCU2_CLK_APLL_CFG_RUN_Pos                             0
#define CCU2_CLK_APLL_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos)
#define CCU2_CLK_APLL_CFG_AUTO_Pos                            1
#define CCU2_CLK_APLL_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos)
#define CCU2_CLK_APLL_CFG_WAKEUP_Pos                          2
#define CCU2_CLK_APLL_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos)

// -----------------------------------  CCU2_CLK_APLL_STAT  ---------------------------------------
#define CCU2_CLK_APLL_STAT_RUN_Pos                            0
#define CCU2_CLK_APLL_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos)
#define CCU2_CLK_APLL_STAT_AUTO_Pos                           1
#define CCU2_CLK_APLL_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos)
#define CCU2_CLK_APLL_STAT_WAKEUP_Pos                         2
#define CCU2_CLK_APLL_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB2_USART3_CFG  ------------------------------------
#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos                      0
#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos)
#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos                     1
#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos)
#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos                   2
#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB2_USART3_STAT  -----------------------------------
#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos                     0
#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos)
#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos                    1
#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos)
#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos                  2
#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB2_USART2_CFG  ------------------------------------
#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos                      0
#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos)
#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos                     1
#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos)
#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos                   2
#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB2_USART2_STAT  -----------------------------------
#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos                     0
#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos)
#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos                    1
#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos)
#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos                  2
#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos)

// -------------------------------  CCU2_CLK_APB0_UART1_BUS_CFG  ----------------------------------
#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos                   0
#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos)
#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos                  1
#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk                  (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos)
#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos                2
#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk                (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB0_UART1_STAT  ------------------------------------
#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos                      0
#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos)
#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos                     1
#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos)
#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos                   2
#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB0_USART0_CFG  ------------------------------------
#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos                      0
#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk                      (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos)
#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos                     1
#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos)
#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos                   2
#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk                   (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos)

// --------------------------------  CCU2_CLK_APB0_USART0_STAT  -----------------------------------
#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos                     0
#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk                     (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos)
#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos                    1
#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk                    (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos)
#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos                  2
#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk                  (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos)

// ---------------------------------  CCU2_CLK_APB2_SSP1_CFG  -------------------------------------
#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos                        0
#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos)
#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos                       1
#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos)
#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos                     2
#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos)

// ---------------------------------  CCU2_CLK_APB2_SSP1_STAT  ------------------------------------
#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos                       0
#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos)
#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos                      1
#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos)
#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos                    2
#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos)

// ---------------------------------  CCU2_CLK_APB0_SSP0_CFG  -------------------------------------
#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos                        0
#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk                        (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos)
#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos                       1
#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos)
#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos                     2
#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk                     (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos)

// ---------------------------------  CCU2_CLK_APB0_SSP0_STAT  ------------------------------------
#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos                       0
#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk                       (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos)
#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos                      1
#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk                      (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos)
#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos                    2
#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk                    (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos)

// ------------------------------------  CCU2_CLK_SDIO_CFG  ---------------------------------------
#define CCU2_CLK_SDIO_CFG_RUN_Pos                             0
#define CCU2_CLK_SDIO_CFG_RUN_Msk                             (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos)
#define CCU2_CLK_SDIO_CFG_AUTO_Pos                            1
#define CCU2_CLK_SDIO_CFG_AUTO_Msk                            (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos)
#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos                          2
#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk                          (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos)

// -----------------------------------  CCU2_CLK_SDIO_STAT  ---------------------------------------
#define CCU2_CLK_SDIO_STAT_RUN_Pos                            0
#define CCU2_CLK_SDIO_STAT_RUN_Msk                            (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos)
#define CCU2_CLK_SDIO_STAT_AUTO_Pos                           1
#define CCU2_CLK_SDIO_STAT_AUTO_Msk                           (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos)
#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos                         2
#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk                         (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  RGU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  RGU_RESET_CTRL0  ----------------------------------------
#define RGU_RESET_CTRL0_CORE_RST_Pos                          0
#define RGU_RESET_CTRL0_CORE_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos)
#define RGU_RESET_CTRL0_PERIPH_RST_Pos                        1
#define RGU_RESET_CTRL0_PERIPH_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos)
#define RGU_RESET_CTRL0_MASTER_RST_Pos                        2
#define RGU_RESET_CTRL0_MASTER_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos)
#define RGU_RESET_CTRL0_WWDT_RST_Pos                          4
#define RGU_RESET_CTRL0_WWDT_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos)
#define RGU_RESET_CTRL0_CREG_RST_Pos                          5
#define RGU_RESET_CTRL0_CREG_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos)
#define RGU_RESET_CTRL0_BUS_RST_Pos                           8
#define RGU_RESET_CTRL0_BUS_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos)
#define RGU_RESET_CTRL0_SCU_RST_Pos                           9
#define RGU_RESET_CTRL0_SCU_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos)
#define RGU_RESET_CTRL0_PINMUX_RST_Pos                        10
#define RGU_RESET_CTRL0_PINMUX_RST_Msk                        (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos)
#define RGU_RESET_CTRL0_M4_RST_Pos                            13
#define RGU_RESET_CTRL0_M4_RST_Msk                            (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos)
#define RGU_RESET_CTRL0_LCD_RST_Pos                           16
#define RGU_RESET_CTRL0_LCD_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos)
#define RGU_RESET_CTRL0_USB0_RST_Pos                          17
#define RGU_RESET_CTRL0_USB0_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos)
#define RGU_RESET_CTRL0_USB1_RST_Pos                          18
#define RGU_RESET_CTRL0_USB1_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos)
#define RGU_RESET_CTRL0_DMA_RST_Pos                           19
#define RGU_RESET_CTRL0_DMA_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos)
#define RGU_RESET_CTRL0_SDIO_RST_Pos                          20
#define RGU_RESET_CTRL0_SDIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos)
#define RGU_RESET_CTRL0_EMC_RST_Pos                           21
#define RGU_RESET_CTRL0_EMC_RST_Msk                           (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos)
#define RGU_RESET_CTRL0_ETHERNET_RST_Pos                      22
#define RGU_RESET_CTRL0_ETHERNET_RST_Msk                      (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos)
#define RGU_RESET_CTRL0_GPIO_RST_Pos                          28
#define RGU_RESET_CTRL0_GPIO_RST_Msk                          (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos)

// -------------------------------------  RGU_RESET_CTRL1  ----------------------------------------
#define RGU_RESET_CTRL1_TIMER0_RST_Pos                        0
#define RGU_RESET_CTRL1_TIMER0_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos)
#define RGU_RESET_CTRL1_TIMER1_RST_Pos                        1
#define RGU_RESET_CTRL1_TIMER1_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos)
#define RGU_RESET_CTRL1_TIMER2_RST_Pos                        2
#define RGU_RESET_CTRL1_TIMER2_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos)
#define RGU_RESET_CTRL1_TIMER3_RST_Pos                        3
#define RGU_RESET_CTRL1_TIMER3_RST_Msk                        (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos)
#define RGU_RESET_CTRL1_RITIMER_RST_Pos                       4
#define RGU_RESET_CTRL1_RITIMER_RST_Msk                       (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos)
#define RGU_RESET_CTRL1_SCT_RST_Pos                           5
#define RGU_RESET_CTRL1_SCT_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos)
#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos                    6
#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk                    (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos)
#define RGU_RESET_CTRL1_QEI_RST_Pos                           7
#define RGU_RESET_CTRL1_QEI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos)
#define RGU_RESET_CTRL1_ADC0_RST_Pos                          8
#define RGU_RESET_CTRL1_ADC0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos)
#define RGU_RESET_CTRL1_ADC1_RST_Pos                          9
#define RGU_RESET_CTRL1_ADC1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos)
#define RGU_RESET_CTRL1_DAC_RST_Pos                           10
#define RGU_RESET_CTRL1_DAC_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos)
#define RGU_RESET_CTRL1_UART0_RST_Pos                         12
#define RGU_RESET_CTRL1_UART0_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos)
#define RGU_RESET_CTRL1_UART1_RST_Pos                         13
#define RGU_RESET_CTRL1_UART1_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos)
#define RGU_RESET_CTRL1_UART2_RST_Pos                         14
#define RGU_RESET_CTRL1_UART2_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos)
#define RGU_RESET_CTRL1_UART3_RST_Pos                         15
#define RGU_RESET_CTRL1_UART3_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos)
#define RGU_RESET_CTRL1_I2C0_RST_Pos                          16
#define RGU_RESET_CTRL1_I2C0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos)
#define RGU_RESET_CTRL1_I2C1_RST_Pos                          17
#define RGU_RESET_CTRL1_I2C1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos)
#define RGU_RESET_CTRL1_SSP0_RST_Pos                          18
#define RGU_RESET_CTRL1_SSP0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos)
#define RGU_RESET_CTRL1_SSP1_RST_Pos                          19
#define RGU_RESET_CTRL1_SSP1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos)
#define RGU_RESET_CTRL1_I2S_RST_Pos                           20
#define RGU_RESET_CTRL1_I2S_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos)
#define RGU_RESET_CTRL1_SPIFI_RST_Pos                         21
#define RGU_RESET_CTRL1_SPIFI_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos)
#define RGU_RESET_CTRL1_CAN1_RST_Pos                          22
#define RGU_RESET_CTRL1_CAN1_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos)
#define RGU_RESET_CTRL1_CAN0_RST_Pos                          23
#define RGU_RESET_CTRL1_CAN0_RST_Msk                          (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos)
#define RGU_RESET_CTRL1_M0APP_RST_Pos                         24
#define RGU_RESET_CTRL1_M0APP_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos)
#define RGU_RESET_CTRL1_SGPIO_RST_Pos                         25
#define RGU_RESET_CTRL1_SGPIO_RST_Msk                         (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos)
#define RGU_RESET_CTRL1_SPI_RST_Pos                           26
#define RGU_RESET_CTRL1_SPI_RST_Msk                           (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos)

// ------------------------------------  RGU_RESET_STATUS0  ---------------------------------------
#define RGU_RESET_STATUS0_CORE_RST_Pos                        0
#define RGU_RESET_STATUS0_CORE_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos)
#define RGU_RESET_STATUS0_PERIPH_RST_Pos                      2
#define RGU_RESET_STATUS0_PERIPH_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos)
#define RGU_RESET_STATUS0_MASTER_RST_Pos                      4
#define RGU_RESET_STATUS0_MASTER_RST_Msk                      (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos)
#define RGU_RESET_STATUS0_WWDT_RST_Pos                        8
#define RGU_RESET_STATUS0_WWDT_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos)
#define RGU_RESET_STATUS0_CREG_RST_Pos                        10
#define RGU_RESET_STATUS0_CREG_RST_Msk                        (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos)
#define RGU_RESET_STATUS0_BUS_RST_Pos                         16
#define RGU_RESET_STATUS0_BUS_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos)
#define RGU_RESET_STATUS0_SCU_RST_Pos                         18
#define RGU_RESET_STATUS0_SCU_RST_Msk                         (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos)
#define RGU_RESET_STATUS0_M4_RST_Pos                          26
#define RGU_RESET_STATUS0_M4_RST_Msk                          (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos)

// ------------------------------------  RGU_RESET_STATUS1  ---------------------------------------
#define RGU_RESET_STATUS1_LCD_RST_Pos                         0
#define RGU_RESET_STATUS1_LCD_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos)
#define RGU_RESET_STATUS1_USB0_RST_Pos                        2
#define RGU_RESET_STATUS1_USB0_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos)
#define RGU_RESET_STATUS1_USB1_RST_Pos                        4
#define RGU_RESET_STATUS1_USB1_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos)
#define RGU_RESET_STATUS1_DMA_RST_Pos                         6
#define RGU_RESET_STATUS1_DMA_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos)
#define RGU_RESET_STATUS1_SDIO_RST_Pos                        8
#define RGU_RESET_STATUS1_SDIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos)
#define RGU_RESET_STATUS1_EMC_RST_Pos                         10
#define RGU_RESET_STATUS1_EMC_RST_Msk                         (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos)
#define RGU_RESET_STATUS1_ETHERNET_RST_Pos                    12
#define RGU_RESET_STATUS1_ETHERNET_RST_Msk                    (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos)
#define RGU_RESET_STATUS1_GPIO_RST_Pos                        24
#define RGU_RESET_STATUS1_GPIO_RST_Msk                        (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos)

// ------------------------------------  RGU_RESET_STATUS2  ---------------------------------------
#define RGU_RESET_STATUS2_TIMER0_RST_Pos                      0
#define RGU_RESET_STATUS2_TIMER0_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos)
#define RGU_RESET_STATUS2_TIMER1_RST_Pos                      2
#define RGU_RESET_STATUS2_TIMER1_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos)
#define RGU_RESET_STATUS2_TIMER2_RST_Pos                      4
#define RGU_RESET_STATUS2_TIMER2_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos)
#define RGU_RESET_STATUS2_TIMER3_RST_Pos                      6
#define RGU_RESET_STATUS2_TIMER3_RST_Msk                      (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos)
#define RGU_RESET_STATUS2_RITIMER_RST_Pos                     8
#define RGU_RESET_STATUS2_RITIMER_RST_Msk                     (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos)
#define RGU_RESET_STATUS2_SCT_RST_Pos                         10
#define RGU_RESET_STATUS2_SCT_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos)
#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos                  12
#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk                  (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos)
#define RGU_RESET_STATUS2_QEI_RST_Pos                         14
#define RGU_RESET_STATUS2_QEI_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos)
#define RGU_RESET_STATUS2_ADC0_RST_Pos                        16
#define RGU_RESET_STATUS2_ADC0_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos)
#define RGU_RESET_STATUS2_ADC1_RST_Pos                        18
#define RGU_RESET_STATUS2_ADC1_RST_Msk                        (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos)
#define RGU_RESET_STATUS2_DAC_RST_Pos                         20
#define RGU_RESET_STATUS2_DAC_RST_Msk                         (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos)
#define RGU_RESET_STATUS2_UART0_RST_Pos                       24
#define RGU_RESET_STATUS2_UART0_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos)
#define RGU_RESET_STATUS2_UART1_RST_Pos                       26
#define RGU_RESET_STATUS2_UART1_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos)
#define RGU_RESET_STATUS2_UART2_RST_Pos                       28
#define RGU_RESET_STATUS2_UART2_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos)
#define RGU_RESET_STATUS2_UART3_RST_Pos                       30
#define RGU_RESET_STATUS2_UART3_RST_Msk                       (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos)

// ------------------------------------  RGU_RESET_STATUS3  ---------------------------------------
#define RGU_RESET_STATUS3_I2C0_RST_Pos                        0
#define RGU_RESET_STATUS3_I2C0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos)
#define RGU_RESET_STATUS3_I2C1_RST_Pos                        2
#define RGU_RESET_STATUS3_I2C1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos)
#define RGU_RESET_STATUS3_SSP0_RST_Pos                        4
#define RGU_RESET_STATUS3_SSP0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos)
#define RGU_RESET_STATUS3_SSP1_RST_Pos                        6
#define RGU_RESET_STATUS3_SSP1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos)
#define RGU_RESET_STATUS3_I2S_RST_Pos                         8
#define RGU_RESET_STATUS3_I2S_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos)
#define RGU_RESET_STATUS3_SPIFI_RST_Pos                       10
#define RGU_RESET_STATUS3_SPIFI_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos)
#define RGU_RESET_STATUS3_CAN1_RST_Pos                        12
#define RGU_RESET_STATUS3_CAN1_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos)
#define RGU_RESET_STATUS3_CAN0_RST_Pos                        14
#define RGU_RESET_STATUS3_CAN0_RST_Msk                        (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos)
#define RGU_RESET_STATUS3_M0APP_RST_Pos                       16
#define RGU_RESET_STATUS3_M0APP_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos)
#define RGU_RESET_STATUS3_SGPIO_RST_Pos                       18
#define RGU_RESET_STATUS3_SGPIO_RST_Msk                       (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos)
#define RGU_RESET_STATUS3_SPI_RST_Pos                         20
#define RGU_RESET_STATUS3_SPI_RST_Msk                         (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos)

// --------------------------------  RGU_RESET_ACTIVE_STATUS0  ------------------------------------
#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos                 0
#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos               1
#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos               2
#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos                 4
#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos                 5
#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos                  8
#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos                  9
#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos               10
#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos                   13
#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk                   (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos                  16
#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos                 17
#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos                 18
#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos                  19
#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos                 20
#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos                  21
#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos             22
#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk             (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos                 28
#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos)

// --------------------------------  RGU_RESET_ACTIVE_STATUS1  ------------------------------------
#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos               0
#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos               1
#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos               2
#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos               3
#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk               (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos              4
#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk              (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos                  5
#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos           6
#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk           (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos                  7
#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos                 8
#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos                 9
#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos                  10
#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos                12
#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos                13
#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos                14
#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos                15
#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos                 16
#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos                 17
#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos                 18
#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos                 19
#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos                  20
#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos                21
#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos                 22
#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos                 23
#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk                 (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos                24
#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos                25
#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk                (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos)
#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos                  26
#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk                  (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT0  --------------------------------------
#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos                     0
#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos)
#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos                     4
#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk                     (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos)
#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos                    5
#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT1  --------------------------------------
#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos                    1
#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT2  --------------------------------------
#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos              2
#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT4  --------------------------------------
#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos                    1
#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT5  --------------------------------------
#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos                    1
#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk                    (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT8  --------------------------------------
#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos              2
#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos)

// -----------------------------------  RGU_RESET_EXT_STAT9  --------------------------------------
#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos              2
#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk              (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT13  --------------------------------------
#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT16  --------------------------------------
#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT17  --------------------------------------
#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT18  --------------------------------------
#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT19  --------------------------------------
#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT20  --------------------------------------
#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT21  --------------------------------------
#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT22  --------------------------------------
#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT23  --------------------------------------
#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos                 3
#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk                 (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT28  --------------------------------------
#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT32  --------------------------------------
#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT33  --------------------------------------
#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT34  --------------------------------------
#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT35  --------------------------------------
#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT36  --------------------------------------
#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT37  --------------------------------------
#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT38  --------------------------------------
#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT39  --------------------------------------
#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT40  --------------------------------------
#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT41  --------------------------------------
#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT42  --------------------------------------
#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT44  --------------------------------------
#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT45  --------------------------------------
#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT46  --------------------------------------
#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT47  --------------------------------------
#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT48  --------------------------------------
#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT49  --------------------------------------
#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT50  --------------------------------------
#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT51  --------------------------------------
#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT52  --------------------------------------
#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT53  --------------------------------------
#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT54  --------------------------------------
#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)

// ----------------------------------  RGU_RESET_EXT_STAT55  --------------------------------------
#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos             2
#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk             (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 WWDT Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  WWDT_MOD  --------------------------------------------
#define WWDT_MOD_WDEN_Pos                                     0
#define WWDT_MOD_WDEN_Msk                                     (0x01UL << WWDT_MOD_WDEN_Pos)
#define WWDT_MOD_WDRESET_Pos                                  1
#define WWDT_MOD_WDRESET_Msk                                  (0x01UL << WWDT_MOD_WDRESET_Pos)
#define WWDT_MOD_WDTOF_Pos                                    2
#define WWDT_MOD_WDTOF_Msk                                    (0x01UL << WWDT_MOD_WDTOF_Pos)
#define WWDT_MOD_WDINT_Pos                                    3
#define WWDT_MOD_WDINT_Msk                                    (0x01UL << WWDT_MOD_WDINT_Pos)
#define WWDT_MOD_WDPROTECT_Pos                                4
#define WWDT_MOD_WDPROTECT_Msk                                (0x01UL << WWDT_MOD_WDPROTECT_Pos)

// -----------------------------------------  WWDT_TC  --------------------------------------------
#define WWDT_TC_WDTC_Pos                                      0
#define WWDT_TC_WDTC_Msk                                      (0x00ffffffUL << WWDT_TC_WDTC_Pos)

// ----------------------------------------  WWDT_FEED  -------------------------------------------
#define WWDT_FEED_Feed_Pos                                    0
#define WWDT_FEED_Feed_Msk                                    (0x000000ffUL << WWDT_FEED_Feed_Pos)

// -----------------------------------------  WWDT_TV  --------------------------------------------
#define WWDT_TV_Count_Pos                                     0
#define WWDT_TV_Count_Msk                                     (0x00ffffffUL << WWDT_TV_Count_Pos)

// --------------------------------------  WWDT_WARNINT  ------------------------------------------
#define WWDT_WARNINT_WDWARNINT_Pos                            0
#define WWDT_WARNINT_WDWARNINT_Msk                            (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos)

// ---------------------------------------  WWDT_WINDOW  ------------------------------------------
#define WWDT_WINDOW_WDWINDOW_Pos                              0
#define WWDT_WINDOW_WDWINDOW_Msk                              (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                USART0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART0_RBR  -------------------------------------------
#define USART0_RBR_RBR_Pos                                    0
#define USART0_RBR_RBR_Msk                                    (0x000000ffUL << USART0_RBR_RBR_Pos)

// ---------------------------------------  USART0_THR  -------------------------------------------
#define USART0_THR_THR_Pos                                    0
#define USART0_THR_THR_Msk                                    (0x000000ffUL << USART0_THR_THR_Pos)

// ---------------------------------------  USART0_DLL  -------------------------------------------
#define USART0_DLL_DLLSB_Pos                                  0
#define USART0_DLL_DLLSB_Msk                                  (0x000000ffUL << USART0_DLL_DLLSB_Pos)

// ---------------------------------------  USART0_DLM  -------------------------------------------
#define USART0_DLM_DLMSB_Pos                                  0
#define USART0_DLM_DLMSB_Msk                                  (0x000000ffUL << USART0_DLM_DLMSB_Pos)

// ---------------------------------------  USART0_IER  -------------------------------------------
#define USART0_IER_RBRIE_Pos                                  0
#define USART0_IER_RBRIE_Msk                                  (0x01UL << USART0_IER_RBRIE_Pos)
#define USART0_IER_THREIE_Pos                                 1
#define USART0_IER_THREIE_Msk                                 (0x01UL << USART0_IER_THREIE_Pos)
#define USART0_IER_RXIE_Pos                                   2
#define USART0_IER_RXIE_Msk                                   (0x01UL << USART0_IER_RXIE_Pos)
#define USART0_IER_ABEOINTEN_Pos                              8
#define USART0_IER_ABEOINTEN_Msk                              (0x01UL << USART0_IER_ABEOINTEN_Pos)
#define USART0_IER_ABTOINTEN_Pos                              9
#define USART0_IER_ABTOINTEN_Msk                              (0x01UL << USART0_IER_ABTOINTEN_Pos)

// ---------------------------------------  USART0_IIR  -------------------------------------------
#define USART0_IIR_INTSTATUS_Pos                              0
#define USART0_IIR_INTSTATUS_Msk                              (0x01UL << USART0_IIR_INTSTATUS_Pos)
#define USART0_IIR_INTID_Pos                                  1
#define USART0_IIR_INTID_Msk                                  (0x07UL << USART0_IIR_INTID_Pos)
#define USART0_IIR_FIFOENABLE_Pos                             6
#define USART0_IIR_FIFOENABLE_Msk                             (0x03UL << USART0_IIR_FIFOENABLE_Pos)
#define USART0_IIR_ABEOINT_Pos                                8
#define USART0_IIR_ABEOINT_Msk                                (0x01UL << USART0_IIR_ABEOINT_Pos)
#define USART0_IIR_ABTOINT_Pos                                9
#define USART0_IIR_ABTOINT_Msk                                (0x01UL << USART0_IIR_ABTOINT_Pos)

// ---------------------------------------  USART0_FCR  -------------------------------------------
#define USART0_FCR_FIFOEN_Pos                                 0
#define USART0_FCR_FIFOEN_Msk                                 (0x01UL << USART0_FCR_FIFOEN_Pos)
#define USART0_FCR_RXFIFORES_Pos                              1
#define USART0_FCR_RXFIFORES_Msk                              (0x01UL << USART0_FCR_RXFIFORES_Pos)
#define USART0_FCR_TXFIFORES_Pos                              2
#define USART0_FCR_TXFIFORES_Msk                              (0x01UL << USART0_FCR_TXFIFORES_Pos)
#define USART0_FCR_DMAMODE_Pos                                3
#define USART0_FCR_DMAMODE_Msk                                (0x01UL << USART0_FCR_DMAMODE_Pos)
#define USART0_FCR_RXTRIGLVL_Pos                              6
#define USART0_FCR_RXTRIGLVL_Msk                              (0x03UL << USART0_FCR_RXTRIGLVL_Pos)

// ---------------------------------------  USART0_LCR  -------------------------------------------
#define USART0_LCR_WLS_Pos                                    0
#define USART0_LCR_WLS_Msk                                    (0x03UL << USART0_LCR_WLS_Pos)
#define USART0_LCR_SBS_Pos                                    2
#define USART0_LCR_SBS_Msk                                    (0x01UL << USART0_LCR_SBS_Pos)
#define USART0_LCR_PE_Pos                                     3
#define USART0_LCR_PE_Msk                                     (0x01UL << USART0_LCR_PE_Pos)
#define USART0_LCR_PS_Pos                                     4
#define USART0_LCR_PS_Msk                                     (0x03UL << USART0_LCR_PS_Pos)
#define USART0_LCR_BC_Pos                                     6
#define USART0_LCR_BC_Msk                                     (0x01UL << USART0_LCR_BC_Pos)
#define USART0_LCR_DLAB_Pos                                   7
#define USART0_LCR_DLAB_Msk                                   (0x01UL << USART0_LCR_DLAB_Pos)

// ---------------------------------------  USART0_LSR  -------------------------------------------
#define USART0_LSR_RDR_Pos                                    0
#define USART0_LSR_RDR_Msk                                    (0x01UL << USART0_LSR_RDR_Pos)
#define USART0_LSR_OE_Pos                                     1
#define USART0_LSR_OE_Msk                                     (0x01UL << USART0_LSR_OE_Pos)
#define USART0_LSR_PE_Pos                                     2
#define USART0_LSR_PE_Msk                                     (0x01UL << USART0_LSR_PE_Pos)
#define USART0_LSR_FE_Pos                                     3
#define USART0_LSR_FE_Msk                                     (0x01UL << USART0_LSR_FE_Pos)
#define USART0_LSR_BI_Pos                                     4
#define USART0_LSR_BI_Msk                                     (0x01UL << USART0_LSR_BI_Pos)
#define USART0_LSR_THRE_Pos                                   5
#define USART0_LSR_THRE_Msk                                   (0x01UL << USART0_LSR_THRE_Pos)
#define USART0_LSR_TEMT_Pos                                   6
#define USART0_LSR_TEMT_Msk                                   (0x01UL << USART0_LSR_TEMT_Pos)
#define USART0_LSR_RXFE_Pos                                   7
#define USART0_LSR_RXFE_Msk                                   (0x01UL << USART0_LSR_RXFE_Pos)
#define USART0_LSR_TXERR_Pos                                  8
#define USART0_LSR_TXERR_Msk                                  (0x01UL << USART0_LSR_TXERR_Pos)

// ---------------------------------------  USART0_SCR  -------------------------------------------
#define USART0_SCR_PAD_Pos                                    0
#define USART0_SCR_PAD_Msk                                    (0x000000ffUL << USART0_SCR_PAD_Pos)

// ---------------------------------------  USART0_ACR  -------------------------------------------
#define USART0_ACR_START_Pos                                  0
#define USART0_ACR_START_Msk                                  (0x01UL << USART0_ACR_START_Pos)
#define USART0_ACR_MODE_Pos                                   1
#define USART0_ACR_MODE_Msk                                   (0x01UL << USART0_ACR_MODE_Pos)
#define USART0_ACR_AUTORESTART_Pos                            2
#define USART0_ACR_AUTORESTART_Msk                            (0x01UL << USART0_ACR_AUTORESTART_Pos)
#define USART0_ACR_ABEOINTCLR_Pos                             8
#define USART0_ACR_ABEOINTCLR_Msk                             (0x01UL << USART0_ACR_ABEOINTCLR_Pos)
#define USART0_ACR_ABTOINTCLR_Pos                             9
#define USART0_ACR_ABTOINTCLR_Msk                             (0x01UL << USART0_ACR_ABTOINTCLR_Pos)

// ---------------------------------------  USART0_ICR  -------------------------------------------
#define USART0_ICR_IRDAEN_Pos                                 0
#define USART0_ICR_IRDAEN_Msk                                 (0x01UL << USART0_ICR_IRDAEN_Pos)
#define USART0_ICR_IRDAINV_Pos                                1
#define USART0_ICR_IRDAINV_Msk                                (0x01UL << USART0_ICR_IRDAINV_Pos)
#define USART0_ICR_FIXPULSEEN_Pos                             2
#define USART0_ICR_FIXPULSEEN_Msk                             (0x01UL << USART0_ICR_FIXPULSEEN_Pos)
#define USART0_ICR_PULSEDIV_Pos                               3
#define USART0_ICR_PULSEDIV_Msk                               (0x07UL << USART0_ICR_PULSEDIV_Pos)

// ---------------------------------------  USART0_FDR  -------------------------------------------
#define USART0_FDR_DIVADDVAL_Pos                              0
#define USART0_FDR_DIVADDVAL_Msk                              (0x0fUL << USART0_FDR_DIVADDVAL_Pos)
#define USART0_FDR_MULVAL_Pos                                 4
#define USART0_FDR_MULVAL_Msk                                 (0x0fUL << USART0_FDR_MULVAL_Pos)

// ---------------------------------------  USART0_OSR  -------------------------------------------
#define USART0_OSR_OSFRAC_Pos                                 1
#define USART0_OSR_OSFRAC_Msk                                 (0x07UL << USART0_OSR_OSFRAC_Pos)
#define USART0_OSR_OSINT_Pos                                  4
#define USART0_OSR_OSINT_Msk                                  (0x0fUL << USART0_OSR_OSINT_Pos)
#define USART0_OSR_FDINT_Pos                                  8
#define USART0_OSR_FDINT_Msk                                  (0x7fUL << USART0_OSR_FDINT_Pos)

// ---------------------------------------  USART0_HDEN  ------------------------------------------
#define USART0_HDEN_HDEN_Pos                                  0
#define USART0_HDEN_HDEN_Msk                                  (0x01UL << USART0_HDEN_HDEN_Pos)

// -------------------------------------  USART0_SCICTRL  -----------------------------------------
#define USART0_SCICTRL_SCIEN_Pos                              0
#define USART0_SCICTRL_SCIEN_Msk                              (0x01UL << USART0_SCICTRL_SCIEN_Pos)
#define USART0_SCICTRL_NACKDIS_Pos                            1
#define USART0_SCICTRL_NACKDIS_Msk                            (0x01UL << USART0_SCICTRL_NACKDIS_Pos)
#define USART0_SCICTRL_PROTSEL_Pos                            2
#define USART0_SCICTRL_PROTSEL_Msk                            (0x01UL << USART0_SCICTRL_PROTSEL_Pos)
#define USART0_SCICTRL_TXRETRY_Pos                            5
#define USART0_SCICTRL_TXRETRY_Msk                            (0x07UL << USART0_SCICTRL_TXRETRY_Pos)
#define USART0_SCICTRL_GUARDTIME_Pos                          8
#define USART0_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos)

// ------------------------------------  USART0_RS485CTRL  ----------------------------------------
#define USART0_RS485CTRL_NMMEN_Pos                            0
#define USART0_RS485CTRL_NMMEN_Msk                            (0x01UL << USART0_RS485CTRL_NMMEN_Pos)
#define USART0_RS485CTRL_RXDIS_Pos                            1
#define USART0_RS485CTRL_RXDIS_Msk                            (0x01UL << USART0_RS485CTRL_RXDIS_Pos)
#define USART0_RS485CTRL_AADEN_Pos                            2
#define USART0_RS485CTRL_AADEN_Msk                            (0x01UL << USART0_RS485CTRL_AADEN_Pos)
#define USART0_RS485CTRL_DCTRL_Pos                            4
#define USART0_RS485CTRL_DCTRL_Msk                            (0x01UL << USART0_RS485CTRL_DCTRL_Pos)
#define USART0_RS485CTRL_OINV_Pos                             5
#define USART0_RS485CTRL_OINV_Msk                             (0x01UL << USART0_RS485CTRL_OINV_Pos)

// ----------------------------------  USART0_RS485ADRMATCH  --------------------------------------
#define USART0_RS485ADRMATCH_ADRMATCH_Pos                     0
#define USART0_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos)

// -------------------------------------  USART0_RS485DLY  ----------------------------------------
#define USART0_RS485DLY_DLY_Pos                               0
#define USART0_RS485DLY_DLY_Msk                               (0x000000ffUL << USART0_RS485DLY_DLY_Pos)

// -------------------------------------  USART0_SYNCCTRL  ----------------------------------------
#define USART0_SYNCCTRL_SYNC_Pos                              0
#define USART0_SYNCCTRL_SYNC_Msk                              (0x01UL << USART0_SYNCCTRL_SYNC_Pos)
#define USART0_SYNCCTRL_CSRC_Pos                              1
#define USART0_SYNCCTRL_CSRC_Msk                              (0x01UL << USART0_SYNCCTRL_CSRC_Pos)
#define USART0_SYNCCTRL_FES_Pos                               2
#define USART0_SYNCCTRL_FES_Msk                               (0x01UL << USART0_SYNCCTRL_FES_Pos)
#define USART0_SYNCCTRL_TSBYPASS_Pos                          3
#define USART0_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos)
#define USART0_SYNCCTRL_CSCEN_Pos                             4
#define USART0_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART0_SYNCCTRL_CSCEN_Pos)
#define USART0_SYNCCTRL_SSSDIS_Pos                            5
#define USART0_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos)
#define USART0_SYNCCTRL_CCCLR_Pos                             6
#define USART0_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART0_SYNCCTRL_CCCLR_Pos)

// ---------------------------------------  USART0_TER  -------------------------------------------
#define USART0_TER_TXEN_Pos                                   0
#define USART0_TER_TXEN_Msk                                   (0x01UL << USART0_TER_TXEN_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                USART2 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART2_DLL  -------------------------------------------
#define USART2_DLL_DLLSB_Pos                                  0
#define USART2_DLL_DLLSB_Msk                                  (0x000000ffUL << USART2_DLL_DLLSB_Pos)

// ---------------------------------------  USART2_THR  -------------------------------------------
#define USART2_THR_THR_Pos                                    0
#define USART2_THR_THR_Msk                                    (0x000000ffUL << USART2_THR_THR_Pos)

// ---------------------------------------  USART2_RBR  -------------------------------------------
#define USART2_RBR_RBR_Pos                                    0
#define USART2_RBR_RBR_Msk                                    (0x000000ffUL << USART2_RBR_RBR_Pos)

// ---------------------------------------  USART2_IER  -------------------------------------------
#define USART2_IER_RBRIE_Pos                                  0
#define USART2_IER_RBRIE_Msk                                  (0x01UL << USART2_IER_RBRIE_Pos)
#define USART2_IER_THREIE_Pos                                 1
#define USART2_IER_THREIE_Msk                                 (0x01UL << USART2_IER_THREIE_Pos)
#define USART2_IER_RXIE_Pos                                   2
#define USART2_IER_RXIE_Msk                                   (0x01UL << USART2_IER_RXIE_Pos)
#define USART2_IER_ABEOINTEN_Pos                              8
#define USART2_IER_ABEOINTEN_Msk                              (0x01UL << USART2_IER_ABEOINTEN_Pos)
#define USART2_IER_ABTOINTEN_Pos                              9
#define USART2_IER_ABTOINTEN_Msk                              (0x01UL << USART2_IER_ABTOINTEN_Pos)

// ---------------------------------------  USART2_DLM  -------------------------------------------
#define USART2_DLM_DLMSB_Pos                                  0
#define USART2_DLM_DLMSB_Msk                                  (0x000000ffUL << USART2_DLM_DLMSB_Pos)

// ---------------------------------------  USART2_FCR  -------------------------------------------
#define USART2_FCR_FIFOEN_Pos                                 0
#define USART2_FCR_FIFOEN_Msk                                 (0x01UL << USART2_FCR_FIFOEN_Pos)
#define USART2_FCR_RXFIFORES_Pos                              1
#define USART2_FCR_RXFIFORES_Msk                              (0x01UL << USART2_FCR_RXFIFORES_Pos)
#define USART2_FCR_TXFIFORES_Pos                              2
#define USART2_FCR_TXFIFORES_Msk                              (0x01UL << USART2_FCR_TXFIFORES_Pos)
#define USART2_FCR_DMAMODE_Pos                                3
#define USART2_FCR_DMAMODE_Msk                                (0x01UL << USART2_FCR_DMAMODE_Pos)
#define USART2_FCR_RXTRIGLVL_Pos                              6
#define USART2_FCR_RXTRIGLVL_Msk                              (0x03UL << USART2_FCR_RXTRIGLVL_Pos)

// ---------------------------------------  USART2_IIR  -------------------------------------------
#define USART2_IIR_INTSTATUS_Pos                              0
#define USART2_IIR_INTSTATUS_Msk                              (0x01UL << USART2_IIR_INTSTATUS_Pos)
#define USART2_IIR_INTID_Pos                                  1
#define USART2_IIR_INTID_Msk                                  (0x07UL << USART2_IIR_INTID_Pos)
#define USART2_IIR_FIFOENABLE_Pos                             6
#define USART2_IIR_FIFOENABLE_Msk                             (0x03UL << USART2_IIR_FIFOENABLE_Pos)
#define USART2_IIR_ABEOINT_Pos                                8
#define USART2_IIR_ABEOINT_Msk                                (0x01UL << USART2_IIR_ABEOINT_Pos)
#define USART2_IIR_ABTOINT_Pos                                9
#define USART2_IIR_ABTOINT_Msk                                (0x01UL << USART2_IIR_ABTOINT_Pos)

// ---------------------------------------  USART2_LCR  -------------------------------------------
#define USART2_LCR_WLS_Pos                                    0
#define USART2_LCR_WLS_Msk                                    (0x03UL << USART2_LCR_WLS_Pos)
#define USART2_LCR_SBS_Pos                                    2
#define USART2_LCR_SBS_Msk                                    (0x01UL << USART2_LCR_SBS_Pos)
#define USART2_LCR_PE_Pos                                     3
#define USART2_LCR_PE_Msk                                     (0x01UL << USART2_LCR_PE_Pos)
#define USART2_LCR_PS_Pos                                     4
#define USART2_LCR_PS_Msk                                     (0x03UL << USART2_LCR_PS_Pos)
#define USART2_LCR_BC_Pos                                     6
#define USART2_LCR_BC_Msk                                     (0x01UL << USART2_LCR_BC_Pos)
#define USART2_LCR_DLAB_Pos                                   7
#define USART2_LCR_DLAB_Msk                                   (0x01UL << USART2_LCR_DLAB_Pos)

// ---------------------------------------  USART2_LSR  -------------------------------------------
#define USART2_LSR_RDR_Pos                                    0
#define USART2_LSR_RDR_Msk                                    (0x01UL << USART2_LSR_RDR_Pos)
#define USART2_LSR_OE_Pos                                     1
#define USART2_LSR_OE_Msk                                     (0x01UL << USART2_LSR_OE_Pos)
#define USART2_LSR_PE_Pos                                     2
#define USART2_LSR_PE_Msk                                     (0x01UL << USART2_LSR_PE_Pos)
#define USART2_LSR_FE_Pos                                     3
#define USART2_LSR_FE_Msk                                     (0x01UL << USART2_LSR_FE_Pos)
#define USART2_LSR_BI_Pos                                     4
#define USART2_LSR_BI_Msk                                     (0x01UL << USART2_LSR_BI_Pos)
#define USART2_LSR_THRE_Pos                                   5
#define USART2_LSR_THRE_Msk                                   (0x01UL << USART2_LSR_THRE_Pos)
#define USART2_LSR_TEMT_Pos                                   6
#define USART2_LSR_TEMT_Msk                                   (0x01UL << USART2_LSR_TEMT_Pos)
#define USART2_LSR_RXFE_Pos                                   7
#define USART2_LSR_RXFE_Msk                                   (0x01UL << USART2_LSR_RXFE_Pos)
#define USART2_LSR_TXERR_Pos                                  8
#define USART2_LSR_TXERR_Msk                                  (0x01UL << USART2_LSR_TXERR_Pos)

// ---------------------------------------  USART2_SCR  -------------------------------------------
#define USART2_SCR_PAD_Pos                                    0
#define USART2_SCR_PAD_Msk                                    (0x000000ffUL << USART2_SCR_PAD_Pos)

// ---------------------------------------  USART2_ACR  -------------------------------------------
#define USART2_ACR_START_Pos                                  0
#define USART2_ACR_START_Msk                                  (0x01UL << USART2_ACR_START_Pos)
#define USART2_ACR_MODE_Pos                                   1
#define USART2_ACR_MODE_Msk                                   (0x01UL << USART2_ACR_MODE_Pos)
#define USART2_ACR_AUTORESTART_Pos                            2
#define USART2_ACR_AUTORESTART_Msk                            (0x01UL << USART2_ACR_AUTORESTART_Pos)
#define USART2_ACR_ABEOINTCLR_Pos                             8
#define USART2_ACR_ABEOINTCLR_Msk                             (0x01UL << USART2_ACR_ABEOINTCLR_Pos)
#define USART2_ACR_ABTOINTCLR_Pos                             9
#define USART2_ACR_ABTOINTCLR_Msk                             (0x01UL << USART2_ACR_ABTOINTCLR_Pos)

// ---------------------------------------  USART2_ICR  -------------------------------------------
#define USART2_ICR_IRDAEN_Pos                                 0
#define USART2_ICR_IRDAEN_Msk                                 (0x01UL << USART2_ICR_IRDAEN_Pos)
#define USART2_ICR_IRDAINV_Pos                                1
#define USART2_ICR_IRDAINV_Msk                                (0x01UL << USART2_ICR_IRDAINV_Pos)
#define USART2_ICR_FIXPULSEEN_Pos                             2
#define USART2_ICR_FIXPULSEEN_Msk                             (0x01UL << USART2_ICR_FIXPULSEEN_Pos)
#define USART2_ICR_PULSEDIV_Pos                               3
#define USART2_ICR_PULSEDIV_Msk                               (0x07UL << USART2_ICR_PULSEDIV_Pos)

// ---------------------------------------  USART2_FDR  -------------------------------------------
#define USART2_FDR_DIVADDVAL_Pos                              0
#define USART2_FDR_DIVADDVAL_Msk                              (0x0fUL << USART2_FDR_DIVADDVAL_Pos)
#define USART2_FDR_MULVAL_Pos                                 4
#define USART2_FDR_MULVAL_Msk                                 (0x0fUL << USART2_FDR_MULVAL_Pos)

// ---------------------------------------  USART2_OSR  -------------------------------------------
#define USART2_OSR_OSFRAC_Pos                                 1
#define USART2_OSR_OSFRAC_Msk                                 (0x07UL << USART2_OSR_OSFRAC_Pos)
#define USART2_OSR_OSINT_Pos                                  4
#define USART2_OSR_OSINT_Msk                                  (0x0fUL << USART2_OSR_OSINT_Pos)
#define USART2_OSR_FDINT_Pos                                  8
#define USART2_OSR_FDINT_Msk                                  (0x7fUL << USART2_OSR_FDINT_Pos)

// ---------------------------------------  USART2_HDEN  ------------------------------------------
#define USART2_HDEN_HDEN_Pos                                  0
#define USART2_HDEN_HDEN_Msk                                  (0x01UL << USART2_HDEN_HDEN_Pos)

// -------------------------------------  USART2_SCICTRL  -----------------------------------------
#define USART2_SCICTRL_SCIEN_Pos                              0
#define USART2_SCICTRL_SCIEN_Msk                              (0x01UL << USART2_SCICTRL_SCIEN_Pos)
#define USART2_SCICTRL_NACKDIS_Pos                            1
#define USART2_SCICTRL_NACKDIS_Msk                            (0x01UL << USART2_SCICTRL_NACKDIS_Pos)
#define USART2_SCICTRL_PROTSEL_Pos                            2
#define USART2_SCICTRL_PROTSEL_Msk                            (0x01UL << USART2_SCICTRL_PROTSEL_Pos)
#define USART2_SCICTRL_TXRETRY_Pos                            5
#define USART2_SCICTRL_TXRETRY_Msk                            (0x07UL << USART2_SCICTRL_TXRETRY_Pos)
#define USART2_SCICTRL_GUARDTIME_Pos                          8
#define USART2_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos)

// ------------------------------------  USART2_RS485CTRL  ----------------------------------------
#define USART2_RS485CTRL_NMMEN_Pos                            0
#define USART2_RS485CTRL_NMMEN_Msk                            (0x01UL << USART2_RS485CTRL_NMMEN_Pos)
#define USART2_RS485CTRL_RXDIS_Pos                            1
#define USART2_RS485CTRL_RXDIS_Msk                            (0x01UL << USART2_RS485CTRL_RXDIS_Pos)
#define USART2_RS485CTRL_AADEN_Pos                            2
#define USART2_RS485CTRL_AADEN_Msk                            (0x01UL << USART2_RS485CTRL_AADEN_Pos)
#define USART2_RS485CTRL_DCTRL_Pos                            4
#define USART2_RS485CTRL_DCTRL_Msk                            (0x01UL << USART2_RS485CTRL_DCTRL_Pos)
#define USART2_RS485CTRL_OINV_Pos                             5
#define USART2_RS485CTRL_OINV_Msk                             (0x01UL << USART2_RS485CTRL_OINV_Pos)

// ----------------------------------  USART2_RS485ADRMATCH  --------------------------------------
#define USART2_RS485ADRMATCH_ADRMATCH_Pos                     0
#define USART2_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos)

// -------------------------------------  USART2_RS485DLY  ----------------------------------------
#define USART2_RS485DLY_DLY_Pos                               0
#define USART2_RS485DLY_DLY_Msk                               (0x000000ffUL << USART2_RS485DLY_DLY_Pos)

// -------------------------------------  USART2_SYNCCTRL  ----------------------------------------
#define USART2_SYNCCTRL_SYNC_Pos                              0
#define USART2_SYNCCTRL_SYNC_Msk                              (0x01UL << USART2_SYNCCTRL_SYNC_Pos)
#define USART2_SYNCCTRL_CSRC_Pos                              1
#define USART2_SYNCCTRL_CSRC_Msk                              (0x01UL << USART2_SYNCCTRL_CSRC_Pos)
#define USART2_SYNCCTRL_FES_Pos                               2
#define USART2_SYNCCTRL_FES_Msk                               (0x01UL << USART2_SYNCCTRL_FES_Pos)
#define USART2_SYNCCTRL_TSBYPASS_Pos                          3
#define USART2_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos)
#define USART2_SYNCCTRL_CSCEN_Pos                             4
#define USART2_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART2_SYNCCTRL_CSCEN_Pos)
#define USART2_SYNCCTRL_SSSDIS_Pos                            5
#define USART2_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos)
#define USART2_SYNCCTRL_CCCLR_Pos                             6
#define USART2_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART2_SYNCCTRL_CCCLR_Pos)

// ---------------------------------------  USART2_TER  -------------------------------------------
#define USART2_TER_TXEN_Pos                                   0
#define USART2_TER_TXEN_Msk                                   (0x01UL << USART2_TER_TXEN_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                USART3 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  USART3_DLL  -------------------------------------------
#define USART3_DLL_DLLSB_Pos                                  0
#define USART3_DLL_DLLSB_Msk                                  (0x000000ffUL << USART3_DLL_DLLSB_Pos)

// ---------------------------------------  USART3_THR  -------------------------------------------
#define USART3_THR_THR_Pos                                    0
#define USART3_THR_THR_Msk                                    (0x000000ffUL << USART3_THR_THR_Pos)

// ---------------------------------------  USART3_RBR  -------------------------------------------
#define USART3_RBR_RBR_Pos                                    0
#define USART3_RBR_RBR_Msk                                    (0x000000ffUL << USART3_RBR_RBR_Pos)

// ---------------------------------------  USART3_IER  -------------------------------------------
#define USART3_IER_RBRIE_Pos                                  0
#define USART3_IER_RBRIE_Msk                                  (0x01UL << USART3_IER_RBRIE_Pos)
#define USART3_IER_THREIE_Pos                                 1
#define USART3_IER_THREIE_Msk                                 (0x01UL << USART3_IER_THREIE_Pos)
#define USART3_IER_RXIE_Pos                                   2
#define USART3_IER_RXIE_Msk                                   (0x01UL << USART3_IER_RXIE_Pos)
#define USART3_IER_ABEOINTEN_Pos                              8
#define USART3_IER_ABEOINTEN_Msk                              (0x01UL << USART3_IER_ABEOINTEN_Pos)
#define USART3_IER_ABTOINTEN_Pos                              9
#define USART3_IER_ABTOINTEN_Msk                              (0x01UL << USART3_IER_ABTOINTEN_Pos)

// ---------------------------------------  USART3_DLM  -------------------------------------------
#define USART3_DLM_DLMSB_Pos                                  0
#define USART3_DLM_DLMSB_Msk                                  (0x000000ffUL << USART3_DLM_DLMSB_Pos)

// ---------------------------------------  USART3_FCR  -------------------------------------------
#define USART3_FCR_FIFOEN_Pos                                 0
#define USART3_FCR_FIFOEN_Msk                                 (0x01UL << USART3_FCR_FIFOEN_Pos)
#define USART3_FCR_RXFIFORES_Pos                              1
#define USART3_FCR_RXFIFORES_Msk                              (0x01UL << USART3_FCR_RXFIFORES_Pos)
#define USART3_FCR_TXFIFORES_Pos                              2
#define USART3_FCR_TXFIFORES_Msk                              (0x01UL << USART3_FCR_TXFIFORES_Pos)
#define USART3_FCR_DMAMODE_Pos                                3
#define USART3_FCR_DMAMODE_Msk                                (0x01UL << USART3_FCR_DMAMODE_Pos)
#define USART3_FCR_RXTRIGLVL_Pos                              6
#define USART3_FCR_RXTRIGLVL_Msk                              (0x03UL << USART3_FCR_RXTRIGLVL_Pos)

// ---------------------------------------  USART3_IIR  -------------------------------------------
#define USART3_IIR_INTSTATUS_Pos                              0
#define USART3_IIR_INTSTATUS_Msk                              (0x01UL << USART3_IIR_INTSTATUS_Pos)
#define USART3_IIR_INTID_Pos                                  1
#define USART3_IIR_INTID_Msk                                  (0x07UL << USART3_IIR_INTID_Pos)
#define USART3_IIR_FIFOENABLE_Pos                             6
#define USART3_IIR_FIFOENABLE_Msk                             (0x03UL << USART3_IIR_FIFOENABLE_Pos)
#define USART3_IIR_ABEOINT_Pos                                8
#define USART3_IIR_ABEOINT_Msk                                (0x01UL << USART3_IIR_ABEOINT_Pos)
#define USART3_IIR_ABTOINT_Pos                                9
#define USART3_IIR_ABTOINT_Msk                                (0x01UL << USART3_IIR_ABTOINT_Pos)

// ---------------------------------------  USART3_LCR  -------------------------------------------
#define USART3_LCR_WLS_Pos                                    0
#define USART3_LCR_WLS_Msk                                    (0x03UL << USART3_LCR_WLS_Pos)
#define USART3_LCR_SBS_Pos                                    2
#define USART3_LCR_SBS_Msk                                    (0x01UL << USART3_LCR_SBS_Pos)
#define USART3_LCR_PE_Pos                                     3
#define USART3_LCR_PE_Msk                                     (0x01UL << USART3_LCR_PE_Pos)
#define USART3_LCR_PS_Pos                                     4
#define USART3_LCR_PS_Msk                                     (0x03UL << USART3_LCR_PS_Pos)
#define USART3_LCR_BC_Pos                                     6
#define USART3_LCR_BC_Msk                                     (0x01UL << USART3_LCR_BC_Pos)
#define USART3_LCR_DLAB_Pos                                   7
#define USART3_LCR_DLAB_Msk                                   (0x01UL << USART3_LCR_DLAB_Pos)

// ---------------------------------------  USART3_LSR  -------------------------------------------
#define USART3_LSR_RDR_Pos                                    0
#define USART3_LSR_RDR_Msk                                    (0x01UL << USART3_LSR_RDR_Pos)
#define USART3_LSR_OE_Pos                                     1
#define USART3_LSR_OE_Msk                                     (0x01UL << USART3_LSR_OE_Pos)
#define USART3_LSR_PE_Pos                                     2
#define USART3_LSR_PE_Msk                                     (0x01UL << USART3_LSR_PE_Pos)
#define USART3_LSR_FE_Pos                                     3
#define USART3_LSR_FE_Msk                                     (0x01UL << USART3_LSR_FE_Pos)
#define USART3_LSR_BI_Pos                                     4
#define USART3_LSR_BI_Msk                                     (0x01UL << USART3_LSR_BI_Pos)
#define USART3_LSR_THRE_Pos                                   5
#define USART3_LSR_THRE_Msk                                   (0x01UL << USART3_LSR_THRE_Pos)
#define USART3_LSR_TEMT_Pos                                   6
#define USART3_LSR_TEMT_Msk                                   (0x01UL << USART3_LSR_TEMT_Pos)
#define USART3_LSR_RXFE_Pos                                   7
#define USART3_LSR_RXFE_Msk                                   (0x01UL << USART3_LSR_RXFE_Pos)
#define USART3_LSR_TXERR_Pos                                  8
#define USART3_LSR_TXERR_Msk                                  (0x01UL << USART3_LSR_TXERR_Pos)

// ---------------------------------------  USART3_SCR  -------------------------------------------
#define USART3_SCR_PAD_Pos                                    0
#define USART3_SCR_PAD_Msk                                    (0x000000ffUL << USART3_SCR_PAD_Pos)

// ---------------------------------------  USART3_ACR  -------------------------------------------
#define USART3_ACR_START_Pos                                  0
#define USART3_ACR_START_Msk                                  (0x01UL << USART3_ACR_START_Pos)
#define USART3_ACR_MODE_Pos                                   1
#define USART3_ACR_MODE_Msk                                   (0x01UL << USART3_ACR_MODE_Pos)
#define USART3_ACR_AUTORESTART_Pos                            2
#define USART3_ACR_AUTORESTART_Msk                            (0x01UL << USART3_ACR_AUTORESTART_Pos)
#define USART3_ACR_ABEOINTCLR_Pos                             8
#define USART3_ACR_ABEOINTCLR_Msk                             (0x01UL << USART3_ACR_ABEOINTCLR_Pos)
#define USART3_ACR_ABTOINTCLR_Pos                             9
#define USART3_ACR_ABTOINTCLR_Msk                             (0x01UL << USART3_ACR_ABTOINTCLR_Pos)

// ---------------------------------------  USART3_ICR  -------------------------------------------
#define USART3_ICR_IRDAEN_Pos                                 0
#define USART3_ICR_IRDAEN_Msk                                 (0x01UL << USART3_ICR_IRDAEN_Pos)
#define USART3_ICR_IRDAINV_Pos                                1
#define USART3_ICR_IRDAINV_Msk                                (0x01UL << USART3_ICR_IRDAINV_Pos)
#define USART3_ICR_FIXPULSEEN_Pos                             2
#define USART3_ICR_FIXPULSEEN_Msk                             (0x01UL << USART3_ICR_FIXPULSEEN_Pos)
#define USART3_ICR_PULSEDIV_Pos                               3
#define USART3_ICR_PULSEDIV_Msk                               (0x07UL << USART3_ICR_PULSEDIV_Pos)

// ---------------------------------------  USART3_FDR  -------------------------------------------
#define USART3_FDR_DIVADDVAL_Pos                              0
#define USART3_FDR_DIVADDVAL_Msk                              (0x0fUL << USART3_FDR_DIVADDVAL_Pos)
#define USART3_FDR_MULVAL_Pos                                 4
#define USART3_FDR_MULVAL_Msk                                 (0x0fUL << USART3_FDR_MULVAL_Pos)

// ---------------------------------------  USART3_OSR  -------------------------------------------
#define USART3_OSR_OSFRAC_Pos                                 1
#define USART3_OSR_OSFRAC_Msk                                 (0x07UL << USART3_OSR_OSFRAC_Pos)
#define USART3_OSR_OSINT_Pos                                  4
#define USART3_OSR_OSINT_Msk                                  (0x0fUL << USART3_OSR_OSINT_Pos)
#define USART3_OSR_FDINT_Pos                                  8
#define USART3_OSR_FDINT_Msk                                  (0x7fUL << USART3_OSR_FDINT_Pos)

// ---------------------------------------  USART3_HDEN  ------------------------------------------
#define USART3_HDEN_HDEN_Pos                                  0
#define USART3_HDEN_HDEN_Msk                                  (0x01UL << USART3_HDEN_HDEN_Pos)

// -------------------------------------  USART3_SCICTRL  -----------------------------------------
#define USART3_SCICTRL_SCIEN_Pos                              0
#define USART3_SCICTRL_SCIEN_Msk                              (0x01UL << USART3_SCICTRL_SCIEN_Pos)
#define USART3_SCICTRL_NACKDIS_Pos                            1
#define USART3_SCICTRL_NACKDIS_Msk                            (0x01UL << USART3_SCICTRL_NACKDIS_Pos)
#define USART3_SCICTRL_PROTSEL_Pos                            2
#define USART3_SCICTRL_PROTSEL_Msk                            (0x01UL << USART3_SCICTRL_PROTSEL_Pos)
#define USART3_SCICTRL_TXRETRY_Pos                            5
#define USART3_SCICTRL_TXRETRY_Msk                            (0x07UL << USART3_SCICTRL_TXRETRY_Pos)
#define USART3_SCICTRL_GUARDTIME_Pos                          8
#define USART3_SCICTRL_GUARDTIME_Msk                          (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos)

// ------------------------------------  USART3_RS485CTRL  ----------------------------------------
#define USART3_RS485CTRL_NMMEN_Pos                            0
#define USART3_RS485CTRL_NMMEN_Msk                            (0x01UL << USART3_RS485CTRL_NMMEN_Pos)
#define USART3_RS485CTRL_RXDIS_Pos                            1
#define USART3_RS485CTRL_RXDIS_Msk                            (0x01UL << USART3_RS485CTRL_RXDIS_Pos)
#define USART3_RS485CTRL_AADEN_Pos                            2
#define USART3_RS485CTRL_AADEN_Msk                            (0x01UL << USART3_RS485CTRL_AADEN_Pos)
#define USART3_RS485CTRL_DCTRL_Pos                            4
#define USART3_RS485CTRL_DCTRL_Msk                            (0x01UL << USART3_RS485CTRL_DCTRL_Pos)
#define USART3_RS485CTRL_OINV_Pos                             5
#define USART3_RS485CTRL_OINV_Msk                             (0x01UL << USART3_RS485CTRL_OINV_Pos)

// ----------------------------------  USART3_RS485ADRMATCH  --------------------------------------
#define USART3_RS485ADRMATCH_ADRMATCH_Pos                     0
#define USART3_RS485ADRMATCH_ADRMATCH_Msk                     (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos)

// -------------------------------------  USART3_RS485DLY  ----------------------------------------
#define USART3_RS485DLY_DLY_Pos                               0
#define USART3_RS485DLY_DLY_Msk                               (0x000000ffUL << USART3_RS485DLY_DLY_Pos)

// -------------------------------------  USART3_SYNCCTRL  ----------------------------------------
#define USART3_SYNCCTRL_SYNC_Pos                              0
#define USART3_SYNCCTRL_SYNC_Msk                              (0x01UL << USART3_SYNCCTRL_SYNC_Pos)
#define USART3_SYNCCTRL_CSRC_Pos                              1
#define USART3_SYNCCTRL_CSRC_Msk                              (0x01UL << USART3_SYNCCTRL_CSRC_Pos)
#define USART3_SYNCCTRL_FES_Pos                               2
#define USART3_SYNCCTRL_FES_Msk                               (0x01UL << USART3_SYNCCTRL_FES_Pos)
#define USART3_SYNCCTRL_TSBYPASS_Pos                          3
#define USART3_SYNCCTRL_TSBYPASS_Msk                          (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos)
#define USART3_SYNCCTRL_CSCEN_Pos                             4
#define USART3_SYNCCTRL_CSCEN_Msk                             (0x01UL << USART3_SYNCCTRL_CSCEN_Pos)
#define USART3_SYNCCTRL_SSSDIS_Pos                            5
#define USART3_SYNCCTRL_SSSDIS_Msk                            (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos)
#define USART3_SYNCCTRL_CCCLR_Pos                             6
#define USART3_SYNCCTRL_CCCLR_Msk                             (0x01UL << USART3_SYNCCTRL_CCCLR_Pos)

// ---------------------------------------  USART3_TER  -------------------------------------------
#define USART3_TER_TXEN_Pos                                   0
#define USART3_TER_TXEN_Msk                                   (0x01UL << USART3_TER_TXEN_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 UART1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  UART1_RBR  -------------------------------------------
#define UART1_RBR_RBR_Pos                                     0
#define UART1_RBR_RBR_Msk                                     (0x000000ffUL << UART1_RBR_RBR_Pos)

// ----------------------------------------  UART1_THR  -------------------------------------------
#define UART1_THR_THR_Pos                                     0
#define UART1_THR_THR_Msk                                     (0x000000ffUL << UART1_THR_THR_Pos)

// ----------------------------------------  UART1_DLL  -------------------------------------------
#define UART1_DLL_DLLSB_Pos                                   0
#define UART1_DLL_DLLSB_Msk                                   (0x000000ffUL << UART1_DLL_DLLSB_Pos)

// ----------------------------------------  UART1_DLM  -------------------------------------------
#define UART1_DLM_DLMSB_Pos                                   0
#define UART1_DLM_DLMSB_Msk                                   (0x000000ffUL << UART1_DLM_DLMSB_Pos)

// ----------------------------------------  UART1_IER  -------------------------------------------
#define UART1_IER_RBRIE_Pos                                   0
#define UART1_IER_RBRIE_Msk                                   (0x01UL << UART1_IER_RBRIE_Pos)
#define UART1_IER_THREIE_Pos                                  1
#define UART1_IER_THREIE_Msk                                  (0x01UL << UART1_IER_THREIE_Pos)
#define UART1_IER_RXIE_Pos                                    2
#define UART1_IER_RXIE_Msk                                    (0x01UL << UART1_IER_RXIE_Pos)
#define UART1_IER_MSIE_Pos                                    3
#define UART1_IER_MSIE_Msk                                    (0x01UL << UART1_IER_MSIE_Pos)
#define UART1_IER_CTSIE_Pos                                   7
#define UART1_IER_CTSIE_Msk                                   (0x01UL << UART1_IER_CTSIE_Pos)
#define UART1_IER_ABEOIE_Pos                                  8
#define UART1_IER_ABEOIE_Msk                                  (0x01UL << UART1_IER_ABEOIE_Pos)
#define UART1_IER_ABTOIE_Pos                                  9
#define UART1_IER_ABTOIE_Msk                                  (0x01UL << UART1_IER_ABTOIE_Pos)

// ----------------------------------------  UART1_IIR  -------------------------------------------
#define UART1_IIR_INTSTATUS_Pos                               0
#define UART1_IIR_INTSTATUS_Msk                               (0x01UL << UART1_IIR_INTSTATUS_Pos)
#define UART1_IIR_INTID_Pos                                   1
#define UART1_IIR_INTID_Msk                                   (0x07UL << UART1_IIR_INTID_Pos)
#define UART1_IIR_FIFOENABLE_Pos                              6
#define UART1_IIR_FIFOENABLE_Msk                              (0x03UL << UART1_IIR_FIFOENABLE_Pos)
#define UART1_IIR_ABEOINT_Pos                                 8
#define UART1_IIR_ABEOINT_Msk                                 (0x01UL << UART1_IIR_ABEOINT_Pos)
#define UART1_IIR_ABTOINT_Pos                                 9
#define UART1_IIR_ABTOINT_Msk                                 (0x01UL << UART1_IIR_ABTOINT_Pos)

// ----------------------------------------  UART1_FCR  -------------------------------------------
#define UART1_FCR_FIFOEN_Pos                                  0
#define UART1_FCR_FIFOEN_Msk                                  (0x01UL << UART1_FCR_FIFOEN_Pos)
#define UART1_FCR_RXFIFORES_Pos                               1
#define UART1_FCR_RXFIFORES_Msk                               (0x01UL << UART1_FCR_RXFIFORES_Pos)
#define UART1_FCR_TXFIFORES_Pos                               2
#define UART1_FCR_TXFIFORES_Msk                               (0x01UL << UART1_FCR_TXFIFORES_Pos)
#define UART1_FCR_DMAMODE_Pos                                 3
#define UART1_FCR_DMAMODE_Msk                                 (0x01UL << UART1_FCR_DMAMODE_Pos)
#define UART1_FCR_RXTRIGLVL_Pos                               6
#define UART1_FCR_RXTRIGLVL_Msk                               (0x03UL << UART1_FCR_RXTRIGLVL_Pos)

// ----------------------------------------  UART1_LCR  -------------------------------------------
#define UART1_LCR_WLS_Pos                                     0
#define UART1_LCR_WLS_Msk                                     (0x03UL << UART1_LCR_WLS_Pos)
#define UART1_LCR_SBS_Pos                                     2
#define UART1_LCR_SBS_Msk                                     (0x01UL << UART1_LCR_SBS_Pos)
#define UART1_LCR_PE_Pos                                      3
#define UART1_LCR_PE_Msk                                      (0x01UL << UART1_LCR_PE_Pos)
#define UART1_LCR_PS_Pos                                      4
#define UART1_LCR_PS_Msk                                      (0x03UL << UART1_LCR_PS_Pos)
#define UART1_LCR_BC_Pos                                      6
#define UART1_LCR_BC_Msk                                      (0x01UL << UART1_LCR_BC_Pos)
#define UART1_LCR_DLAB_Pos                                    7
#define UART1_LCR_DLAB_Msk                                    (0x01UL << UART1_LCR_DLAB_Pos)

// ----------------------------------------  UART1_MCR  -------------------------------------------
#define UART1_MCR_DTRCTRL_Pos                                 0
#define UART1_MCR_DTRCTRL_Msk                                 (0x01UL << UART1_MCR_DTRCTRL_Pos)
#define UART1_MCR_RTSCTRL_Pos                                 1
#define UART1_MCR_RTSCTRL_Msk                                 (0x01UL << UART1_MCR_RTSCTRL_Pos)
#define UART1_MCR_LMS_Pos                                     4
#define UART1_MCR_LMS_Msk                                     (0x01UL << UART1_MCR_LMS_Pos)
#define UART1_MCR_RTSEN_Pos                                   6
#define UART1_MCR_RTSEN_Msk                                   (0x01UL << UART1_MCR_RTSEN_Pos)
#define UART1_MCR_CTSEN_Pos                                   7
#define UART1_MCR_CTSEN_Msk                                   (0x01UL << UART1_MCR_CTSEN_Pos)

// ----------------------------------------  UART1_LSR  -------------------------------------------
#define UART1_LSR_RDR_Pos                                     0
#define UART1_LSR_RDR_Msk                                     (0x01UL << UART1_LSR_RDR_Pos)
#define UART1_LSR_OE_Pos                                      1
#define UART1_LSR_OE_Msk                                      (0x01UL << UART1_LSR_OE_Pos)
#define UART1_LSR_PE_Pos                                      2
#define UART1_LSR_PE_Msk                                      (0x01UL << UART1_LSR_PE_Pos)
#define UART1_LSR_FE_Pos                                      3
#define UART1_LSR_FE_Msk                                      (0x01UL << UART1_LSR_FE_Pos)
#define UART1_LSR_BI_Pos                                      4
#define UART1_LSR_BI_Msk                                      (0x01UL << UART1_LSR_BI_Pos)
#define UART1_LSR_THRE_Pos                                    5
#define UART1_LSR_THRE_Msk                                    (0x01UL << UART1_LSR_THRE_Pos)
#define UART1_LSR_TEMT_Pos                                    6
#define UART1_LSR_TEMT_Msk                                    (0x01UL << UART1_LSR_TEMT_Pos)
#define UART1_LSR_RXFE_Pos                                    7
#define UART1_LSR_RXFE_Msk                                    (0x01UL << UART1_LSR_RXFE_Pos)

// ----------------------------------------  UART1_MSR  -------------------------------------------
#define UART1_MSR_DCTS_Pos                                    0
#define UART1_MSR_DCTS_Msk                                    (0x01UL << UART1_MSR_DCTS_Pos)
#define UART1_MSR_DDSR_Pos                                    1
#define UART1_MSR_DDSR_Msk                                    (0x01UL << UART1_MSR_DDSR_Pos)
#define UART1_MSR_TERI_Pos                                    2
#define UART1_MSR_TERI_Msk                                    (0x01UL << UART1_MSR_TERI_Pos)
#define UART1_MSR_DDCD_Pos                                    3
#define UART1_MSR_DDCD_Msk                                    (0x01UL << UART1_MSR_DDCD_Pos)
#define UART1_MSR_CTS_Pos                                     4
#define UART1_MSR_CTS_Msk                                     (0x01UL << UART1_MSR_CTS_Pos)
#define UART1_MSR_DSR_Pos                                     5
#define UART1_MSR_DSR_Msk                                     (0x01UL << UART1_MSR_DSR_Pos)
#define UART1_MSR_RI_Pos                                      6
#define UART1_MSR_RI_Msk                                      (0x01UL << UART1_MSR_RI_Pos)
#define UART1_MSR_DCD_Pos                                     7
#define UART1_MSR_DCD_Msk                                     (0x01UL << UART1_MSR_DCD_Pos)

// ----------------------------------------  UART1_SCR  -------------------------------------------
#define UART1_SCR_Pad_Pos                                     0
#define UART1_SCR_Pad_Msk                                     (0x000000ffUL << UART1_SCR_Pad_Pos)

// ----------------------------------------  UART1_ACR  -------------------------------------------
#define UART1_ACR_START_Pos                                   0
#define UART1_ACR_START_Msk                                   (0x01UL << UART1_ACR_START_Pos)
#define UART1_ACR_MODE_Pos                                    1
#define UART1_ACR_MODE_Msk                                    (0x01UL << UART1_ACR_MODE_Pos)
#define UART1_ACR_AUTORESTART_Pos                             2
#define UART1_ACR_AUTORESTART_Msk                             (0x01UL << UART1_ACR_AUTORESTART_Pos)
#define UART1_ACR_ABEOINTCLR_Pos                              8
#define UART1_ACR_ABEOINTCLR_Msk                              (0x01UL << UART1_ACR_ABEOINTCLR_Pos)
#define UART1_ACR_ABTOINTCLR_Pos                              9
#define UART1_ACR_ABTOINTCLR_Msk                              (0x01UL << UART1_ACR_ABTOINTCLR_Pos)

// ----------------------------------------  UART1_FDR  -------------------------------------------
#define UART1_FDR_DIVADDVAL_Pos                               0
#define UART1_FDR_DIVADDVAL_Msk                               (0x0fUL << UART1_FDR_DIVADDVAL_Pos)
#define UART1_FDR_MULVAL_Pos                                  4
#define UART1_FDR_MULVAL_Msk                                  (0x0fUL << UART1_FDR_MULVAL_Pos)

// ----------------------------------------  UART1_TER  -------------------------------------------
#define UART1_TER_TXEN_Pos                                    7
#define UART1_TER_TXEN_Msk                                    (0x01UL << UART1_TER_TXEN_Pos)

// -------------------------------------  UART1_RS485CTRL  ----------------------------------------
#define UART1_RS485CTRL_NMMEN_Pos                             0
#define UART1_RS485CTRL_NMMEN_Msk                             (0x01UL << UART1_RS485CTRL_NMMEN_Pos)
#define UART1_RS485CTRL_RXDIS_Pos                             1
#define UART1_RS485CTRL_RXDIS_Msk                             (0x01UL << UART1_RS485CTRL_RXDIS_Pos)
#define UART1_RS485CTRL_AADEN_Pos                             2
#define UART1_RS485CTRL_AADEN_Msk                             (0x01UL << UART1_RS485CTRL_AADEN_Pos)
#define UART1_RS485CTRL_SEL_Pos                               3
#define UART1_RS485CTRL_SEL_Msk                               (0x01UL << UART1_RS485CTRL_SEL_Pos)
#define UART1_RS485CTRL_DCTRL_Pos                             4
#define UART1_RS485CTRL_DCTRL_Msk                             (0x01UL << UART1_RS485CTRL_DCTRL_Pos)
#define UART1_RS485CTRL_OINV_Pos                              5
#define UART1_RS485CTRL_OINV_Msk                              (0x01UL << UART1_RS485CTRL_OINV_Pos)

// -----------------------------------  UART1_RS485ADRMATCH  --------------------------------------
#define UART1_RS485ADRMATCH_ADRMATCH_Pos                      0
#define UART1_RS485ADRMATCH_ADRMATCH_Msk                      (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos)

// -------------------------------------  UART1_RS485DLY  -----------------------------------------
#define UART1_RS485DLY_DLY_Pos                                0
#define UART1_RS485DLY_DLY_Msk                                (0x000000ffUL << UART1_RS485DLY_DLY_Pos)

// --------------------------------------  UART1_FIFOLVL  -----------------------------------------
#define UART1_FIFOLVL_RXFIFILVL_Pos                           0
#define UART1_FIFOLVL_RXFIFILVL_Msk                           (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos)
#define UART1_FIFOLVL_TXFIFOLVL_Pos                           8
#define UART1_FIFOLVL_TXFIFOLVL_Msk                           (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 SSP0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  SSP0_CR0  --------------------------------------------
#define SSP0_CR0_DSS_Pos                                      0
#define SSP0_CR0_DSS_Msk                                      (0x0fUL << SSP0_CR0_DSS_Pos)
#define SSP0_CR0_FRF_Pos                                      4
#define SSP0_CR0_FRF_Msk                                      (0x03UL << SSP0_CR0_FRF_Pos)
#define SSP0_CR0_CPOL_Pos                                     6
#define SSP0_CR0_CPOL_Msk                                     (0x01UL << SSP0_CR0_CPOL_Pos)
#define SSP0_CR0_CPHA_Pos                                     7
#define SSP0_CR0_CPHA_Msk                                     (0x01UL << SSP0_CR0_CPHA_Pos)
#define SSP0_CR0_SCR_Pos                                      8
#define SSP0_CR0_SCR_Msk                                      (0x000000ffUL << SSP0_CR0_SCR_Pos)

// ----------------------------------------  SSP0_CR1  --------------------------------------------
#define SSP0_CR1_LBM_Pos                                      0
#define SSP0_CR1_LBM_Msk                                      (0x01UL << SSP0_CR1_LBM_Pos)
#define SSP0_CR1_SSE_Pos                                      1
#define SSP0_CR1_SSE_Msk                                      (0x01UL << SSP0_CR1_SSE_Pos)
#define SSP0_CR1_MS_Pos                                       2
#define SSP0_CR1_MS_Msk                                       (0x01UL << SSP0_CR1_MS_Pos)
#define SSP0_CR1_SOD_Pos                                      3
#define SSP0_CR1_SOD_Msk                                      (0x01UL << SSP0_CR1_SOD_Pos)

// -----------------------------------------  SSP0_DR  --------------------------------------------
#define SSP0_DR_DATA_Pos                                      0
#define SSP0_DR_DATA_Msk                                      (0x0000ffffUL << SSP0_DR_DATA_Pos)

// -----------------------------------------  SSP0_SR  --------------------------------------------
#define SSP0_SR_TFE_Pos                                       0
#define SSP0_SR_TFE_Msk                                       (0x01UL << SSP0_SR_TFE_Pos)
#define SSP0_SR_TNF_Pos                                       1
#define SSP0_SR_TNF_Msk                                       (0x01UL << SSP0_SR_TNF_Pos)
#define SSP0_SR_RNE_Pos                                       2
#define SSP0_SR_RNE_Msk                                       (0x01UL << SSP0_SR_RNE_Pos)
#define SSP0_SR_RFF_Pos                                       3
#define SSP0_SR_RFF_Msk                                       (0x01UL << SSP0_SR_RFF_Pos)
#define SSP0_SR_BSY_Pos                                       4
#define SSP0_SR_BSY_Msk                                       (0x01UL << SSP0_SR_BSY_Pos)

// ----------------------------------------  SSP0_CPSR  -------------------------------------------
#define SSP0_CPSR_CPSDVSR_Pos                                 0
#define SSP0_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos)

// ----------------------------------------  SSP0_IMSC  -------------------------------------------
#define SSP0_IMSC_RORIM_Pos                                   0
#define SSP0_IMSC_RORIM_Msk                                   (0x01UL << SSP0_IMSC_RORIM_Pos)
#define SSP0_IMSC_RTIM_Pos                                    1
#define SSP0_IMSC_RTIM_Msk                                    (0x01UL << SSP0_IMSC_RTIM_Pos)
#define SSP0_IMSC_RXIM_Pos                                    2
#define SSP0_IMSC_RXIM_Msk                                    (0x01UL << SSP0_IMSC_RXIM_Pos)
#define SSP0_IMSC_TXIM_Pos                                    3
#define SSP0_IMSC_TXIM_Msk                                    (0x01UL << SSP0_IMSC_TXIM_Pos)

// ----------------------------------------  SSP0_RIS  --------------------------------------------
#define SSP0_RIS_RORRIS_Pos                                   0
#define SSP0_RIS_RORRIS_Msk                                   (0x01UL << SSP0_RIS_RORRIS_Pos)
#define SSP0_RIS_RTRIS_Pos                                    1
#define SSP0_RIS_RTRIS_Msk                                    (0x01UL << SSP0_RIS_RTRIS_Pos)
#define SSP0_RIS_RXRIS_Pos                                    2
#define SSP0_RIS_RXRIS_Msk                                    (0x01UL << SSP0_RIS_RXRIS_Pos)
#define SSP0_RIS_TXRIS_Pos                                    3
#define SSP0_RIS_TXRIS_Msk                                    (0x01UL << SSP0_RIS_TXRIS_Pos)

// ----------------------------------------  SSP0_MIS  --------------------------------------------
#define SSP0_MIS_RORMIS_Pos                                   0
#define SSP0_MIS_RORMIS_Msk                                   (0x01UL << SSP0_MIS_RORMIS_Pos)
#define SSP0_MIS_RTMIS_Pos                                    1
#define SSP0_MIS_RTMIS_Msk                                    (0x01UL << SSP0_MIS_RTMIS_Pos)
#define SSP0_MIS_RXMIS_Pos                                    2
#define SSP0_MIS_RXMIS_Msk                                    (0x01UL << SSP0_MIS_RXMIS_Pos)
#define SSP0_MIS_TXMIS_Pos                                    3
#define SSP0_MIS_TXMIS_Msk                                    (0x01UL << SSP0_MIS_TXMIS_Pos)

// ----------------------------------------  SSP0_ICR  --------------------------------------------
#define SSP0_ICR_RORIC_Pos                                    0
#define SSP0_ICR_RORIC_Msk                                    (0x01UL << SSP0_ICR_RORIC_Pos)
#define SSP0_ICR_RTIC_Pos                                     1
#define SSP0_ICR_RTIC_Msk                                     (0x01UL << SSP0_ICR_RTIC_Pos)

// ---------------------------------------  SSP0_DMACR  -------------------------------------------
#define SSP0_DMACR_RXDMAE_Pos                                 0
#define SSP0_DMACR_RXDMAE_Msk                                 (0x01UL << SSP0_DMACR_RXDMAE_Pos)
#define SSP0_DMACR_TXDMAE_Pos                                 1
#define SSP0_DMACR_TXDMAE_Msk                                 (0x01UL << SSP0_DMACR_TXDMAE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 SSP1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  SSP1_CR0  --------------------------------------------
#define SSP1_CR0_DSS_Pos                                      0
#define SSP1_CR0_DSS_Msk                                      (0x0fUL << SSP1_CR0_DSS_Pos)
#define SSP1_CR0_FRF_Pos                                      4
#define SSP1_CR0_FRF_Msk                                      (0x03UL << SSP1_CR0_FRF_Pos)
#define SSP1_CR0_CPOL_Pos                                     6
#define SSP1_CR0_CPOL_Msk                                     (0x01UL << SSP1_CR0_CPOL_Pos)
#define SSP1_CR0_CPHA_Pos                                     7
#define SSP1_CR0_CPHA_Msk                                     (0x01UL << SSP1_CR0_CPHA_Pos)
#define SSP1_CR0_SCR_Pos                                      8
#define SSP1_CR0_SCR_Msk                                      (0x000000ffUL << SSP1_CR0_SCR_Pos)

// ----------------------------------------  SSP1_CR1  --------------------------------------------
#define SSP1_CR1_LBM_Pos                                      0
#define SSP1_CR1_LBM_Msk                                      (0x01UL << SSP1_CR1_LBM_Pos)
#define SSP1_CR1_SSE_Pos                                      1
#define SSP1_CR1_SSE_Msk                                      (0x01UL << SSP1_CR1_SSE_Pos)
#define SSP1_CR1_MS_Pos                                       2
#define SSP1_CR1_MS_Msk                                       (0x01UL << SSP1_CR1_MS_Pos)
#define SSP1_CR1_SOD_Pos                                      3
#define SSP1_CR1_SOD_Msk                                      (0x01UL << SSP1_CR1_SOD_Pos)

// -----------------------------------------  SSP1_DR  --------------------------------------------
#define SSP1_DR_DATA_Pos                                      0
#define SSP1_DR_DATA_Msk                                      (0x0000ffffUL << SSP1_DR_DATA_Pos)

// -----------------------------------------  SSP1_SR  --------------------------------------------
#define SSP1_SR_TFE_Pos                                       0
#define SSP1_SR_TFE_Msk                                       (0x01UL << SSP1_SR_TFE_Pos)
#define SSP1_SR_TNF_Pos                                       1
#define SSP1_SR_TNF_Msk                                       (0x01UL << SSP1_SR_TNF_Pos)
#define SSP1_SR_RNE_Pos                                       2
#define SSP1_SR_RNE_Msk                                       (0x01UL << SSP1_SR_RNE_Pos)
#define SSP1_SR_RFF_Pos                                       3
#define SSP1_SR_RFF_Msk                                       (0x01UL << SSP1_SR_RFF_Pos)
#define SSP1_SR_BSY_Pos                                       4
#define SSP1_SR_BSY_Msk                                       (0x01UL << SSP1_SR_BSY_Pos)

// ----------------------------------------  SSP1_CPSR  -------------------------------------------
#define SSP1_CPSR_CPSDVSR_Pos                                 0
#define SSP1_CPSR_CPSDVSR_Msk                                 (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos)

// ----------------------------------------  SSP1_IMSC  -------------------------------------------
#define SSP1_IMSC_RORIM_Pos                                   0
#define SSP1_IMSC_RORIM_Msk                                   (0x01UL << SSP1_IMSC_RORIM_Pos)
#define SSP1_IMSC_RTIM_Pos                                    1
#define SSP1_IMSC_RTIM_Msk                                    (0x01UL << SSP1_IMSC_RTIM_Pos)
#define SSP1_IMSC_RXIM_Pos                                    2
#define SSP1_IMSC_RXIM_Msk                                    (0x01UL << SSP1_IMSC_RXIM_Pos)
#define SSP1_IMSC_TXIM_Pos                                    3
#define SSP1_IMSC_TXIM_Msk                                    (0x01UL << SSP1_IMSC_TXIM_Pos)

// ----------------------------------------  SSP1_RIS  --------------------------------------------
#define SSP1_RIS_RORRIS_Pos                                   0
#define SSP1_RIS_RORRIS_Msk                                   (0x01UL << SSP1_RIS_RORRIS_Pos)
#define SSP1_RIS_RTRIS_Pos                                    1
#define SSP1_RIS_RTRIS_Msk                                    (0x01UL << SSP1_RIS_RTRIS_Pos)
#define SSP1_RIS_RXRIS_Pos                                    2
#define SSP1_RIS_RXRIS_Msk                                    (0x01UL << SSP1_RIS_RXRIS_Pos)
#define SSP1_RIS_TXRIS_Pos                                    3
#define SSP1_RIS_TXRIS_Msk                                    (0x01UL << SSP1_RIS_TXRIS_Pos)

// ----------------------------------------  SSP1_MIS  --------------------------------------------
#define SSP1_MIS_RORMIS_Pos                                   0
#define SSP1_MIS_RORMIS_Msk                                   (0x01UL << SSP1_MIS_RORMIS_Pos)
#define SSP1_MIS_RTMIS_Pos                                    1
#define SSP1_MIS_RTMIS_Msk                                    (0x01UL << SSP1_MIS_RTMIS_Pos)
#define SSP1_MIS_RXMIS_Pos                                    2
#define SSP1_MIS_RXMIS_Msk                                    (0x01UL << SSP1_MIS_RXMIS_Pos)
#define SSP1_MIS_TXMIS_Pos                                    3
#define SSP1_MIS_TXMIS_Msk                                    (0x01UL << SSP1_MIS_TXMIS_Pos)

// ----------------------------------------  SSP1_ICR  --------------------------------------------
#define SSP1_ICR_RORIC_Pos                                    0
#define SSP1_ICR_RORIC_Msk                                    (0x01UL << SSP1_ICR_RORIC_Pos)
#define SSP1_ICR_RTIC_Pos                                     1
#define SSP1_ICR_RTIC_Msk                                     (0x01UL << SSP1_ICR_RTIC_Pos)

// ---------------------------------------  SSP1_DMACR  -------------------------------------------
#define SSP1_DMACR_RXDMAE_Pos                                 0
#define SSP1_DMACR_RXDMAE_Msk                                 (0x01UL << SSP1_DMACR_RXDMAE_Pos)
#define SSP1_DMACR_TXDMAE_Pos                                 1
#define SSP1_DMACR_TXDMAE_Msk                                 (0x01UL << SSP1_DMACR_TXDMAE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                TIMER0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER0_IR  -------------------------------------------
#define TIMER0_IR_MR0INT_Pos                                  0
#define TIMER0_IR_MR0INT_Msk                                  (0x01UL << TIMER0_IR_MR0INT_Pos)
#define TIMER0_IR_MR1INT_Pos                                  1
#define TIMER0_IR_MR1INT_Msk                                  (0x01UL << TIMER0_IR_MR1INT_Pos)
#define TIMER0_IR_MR2INT_Pos                                  2
#define TIMER0_IR_MR2INT_Msk                                  (0x01UL << TIMER0_IR_MR2INT_Pos)
#define TIMER0_IR_MR3INT_Pos                                  3
#define TIMER0_IR_MR3INT_Msk                                  (0x01UL << TIMER0_IR_MR3INT_Pos)
#define TIMER0_IR_CR0INT_Pos                                  4
#define TIMER0_IR_CR0INT_Msk                                  (0x01UL << TIMER0_IR_CR0INT_Pos)
#define TIMER0_IR_CR1INT_Pos                                  5
#define TIMER0_IR_CR1INT_Msk                                  (0x01UL << TIMER0_IR_CR1INT_Pos)
#define TIMER0_IR_CR2INT_Pos                                  6
#define TIMER0_IR_CR2INT_Msk                                  (0x01UL << TIMER0_IR_CR2INT_Pos)
#define TIMER0_IR_CR3INT_Pos                                  7
#define TIMER0_IR_CR3INT_Msk                                  (0x01UL << TIMER0_IR_CR3INT_Pos)

// ---------------------------------------  TIMER0_TCR  -------------------------------------------
#define TIMER0_TCR_CEN_Pos                                    0
#define TIMER0_TCR_CEN_Msk                                    (0x01UL << TIMER0_TCR_CEN_Pos)
#define TIMER0_TCR_CRST_Pos                                   1
#define TIMER0_TCR_CRST_Msk                                   (0x01UL << TIMER0_TCR_CRST_Pos)

// ----------------------------------------  TIMER0_TC  -------------------------------------------
#define TIMER0_TC_TC_Pos                                      0
#define TIMER0_TC_TC_Msk                                      (0xffffffffUL << TIMER0_TC_TC_Pos)

// ----------------------------------------  TIMER0_PR  -------------------------------------------
#define TIMER0_PR_PM_Pos                                      0
#define TIMER0_PR_PM_Msk                                      (0xffffffffUL << TIMER0_PR_PM_Pos)

// ----------------------------------------  TIMER0_PC  -------------------------------------------
#define TIMER0_PC_PC_Pos                                      0
#define TIMER0_PC_PC_Msk                                      (0xffffffffUL << TIMER0_PC_PC_Pos)

// ---------------------------------------  TIMER0_MCR  -------------------------------------------
#define TIMER0_MCR_MR0I_Pos                                   0
#define TIMER0_MCR_MR0I_Msk                                   (0x01UL << TIMER0_MCR_MR0I_Pos)
#define TIMER0_MCR_MR0R_Pos                                   1
#define TIMER0_MCR_MR0R_Msk                                   (0x01UL << TIMER0_MCR_MR0R_Pos)
#define TIMER0_MCR_MR0S_Pos                                   2
#define TIMER0_MCR_MR0S_Msk                                   (0x01UL << TIMER0_MCR_MR0S_Pos)
#define TIMER0_MCR_MR1I_Pos                                   3
#define TIMER0_MCR_MR1I_Msk                                   (0x01UL << TIMER0_MCR_MR1I_Pos)
#define TIMER0_MCR_MR1R_Pos                                   4
#define TIMER0_MCR_MR1R_Msk                                   (0x01UL << TIMER0_MCR_MR1R_Pos)
#define TIMER0_MCR_MR1S_Pos                                   5
#define TIMER0_MCR_MR1S_Msk                                   (0x01UL << TIMER0_MCR_MR1S_Pos)
#define TIMER0_MCR_MR2I_Pos                                   6
#define TIMER0_MCR_MR2I_Msk                                   (0x01UL << TIMER0_MCR_MR2I_Pos)
#define TIMER0_MCR_MR2R_Pos                                   7
#define TIMER0_MCR_MR2R_Msk                                   (0x01UL << TIMER0_MCR_MR2R_Pos)
#define TIMER0_MCR_MR2S_Pos                                   8
#define TIMER0_MCR_MR2S_Msk                                   (0x01UL << TIMER0_MCR_MR2S_Pos)
#define TIMER0_MCR_MR3I_Pos                                   9
#define TIMER0_MCR_MR3I_Msk                                   (0x01UL << TIMER0_MCR_MR3I_Pos)
#define TIMER0_MCR_MR3R_Pos                                   10
#define TIMER0_MCR_MR3R_Msk                                   (0x01UL << TIMER0_MCR_MR3R_Pos)
#define TIMER0_MCR_MR3S_Pos                                   11
#define TIMER0_MCR_MR3S_Msk                                   (0x01UL << TIMER0_MCR_MR3S_Pos)

// ---------------------------------------  TIMER0_MR0  -------------------------------------------
#define TIMER0_MR0_MATCH_Pos                                  0
#define TIMER0_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR0_MATCH_Pos)

// ---------------------------------------  TIMER0_MR1  -------------------------------------------
#define TIMER0_MR1_MATCH_Pos                                  0
#define TIMER0_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR1_MATCH_Pos)

// ---------------------------------------  TIMER0_MR2  -------------------------------------------
#define TIMER0_MR2_MATCH_Pos                                  0
#define TIMER0_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR2_MATCH_Pos)

// ---------------------------------------  TIMER0_MR3  -------------------------------------------
#define TIMER0_MR3_MATCH_Pos                                  0
#define TIMER0_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER0_MR3_MATCH_Pos)

// ---------------------------------------  TIMER0_CCR  -------------------------------------------
#define TIMER0_CCR_CAP0RE_Pos                                 0
#define TIMER0_CCR_CAP0RE_Msk                                 (0x01UL << TIMER0_CCR_CAP0RE_Pos)
#define TIMER0_CCR_CAP0FE_Pos                                 1
#define TIMER0_CCR_CAP0FE_Msk                                 (0x01UL << TIMER0_CCR_CAP0FE_Pos)
#define TIMER0_CCR_CAP0I_Pos                                  2
#define TIMER0_CCR_CAP0I_Msk                                  (0x01UL << TIMER0_CCR_CAP0I_Pos)
#define TIMER0_CCR_CAP1RE_Pos                                 3
#define TIMER0_CCR_CAP1RE_Msk                                 (0x01UL << TIMER0_CCR_CAP1RE_Pos)
#define TIMER0_CCR_CAP1FE_Pos                                 4
#define TIMER0_CCR_CAP1FE_Msk                                 (0x01UL << TIMER0_CCR_CAP1FE_Pos)
#define TIMER0_CCR_CAP1I_Pos                                  5
#define TIMER0_CCR_CAP1I_Msk                                  (0x01UL << TIMER0_CCR_CAP1I_Pos)
#define TIMER0_CCR_CAP2RE_Pos                                 6
#define TIMER0_CCR_CAP2RE_Msk                                 (0x01UL << TIMER0_CCR_CAP2RE_Pos)
#define TIMER0_CCR_CAP2FE_Pos                                 7
#define TIMER0_CCR_CAP2FE_Msk                                 (0x01UL << TIMER0_CCR_CAP2FE_Pos)
#define TIMER0_CCR_CAP2I_Pos                                  8
#define TIMER0_CCR_CAP2I_Msk                                  (0x01UL << TIMER0_CCR_CAP2I_Pos)
#define TIMER0_CCR_CAP3RE_Pos                                 9
#define TIMER0_CCR_CAP3RE_Msk                                 (0x01UL << TIMER0_CCR_CAP3RE_Pos)
#define TIMER0_CCR_CAP3FE_Pos                                 10
#define TIMER0_CCR_CAP3FE_Msk                                 (0x01UL << TIMER0_CCR_CAP3FE_Pos)
#define TIMER0_CCR_CAP3I_Pos                                  11
#define TIMER0_CCR_CAP3I_Msk                                  (0x01UL << TIMER0_CCR_CAP3I_Pos)

// ---------------------------------------  TIMER0_CR0  -------------------------------------------
#define TIMER0_CR0_CAP_Pos                                    0
#define TIMER0_CR0_CAP_Msk                                    (0xffffffffUL << TIMER0_CR0_CAP_Pos)

// ---------------------------------------  TIMER0_CR1  -------------------------------------------
#define TIMER0_CR1_CAP_Pos                                    0
#define TIMER0_CR1_CAP_Msk                                    (0xffffffffUL << TIMER0_CR1_CAP_Pos)

// ---------------------------------------  TIMER0_CR2  -------------------------------------------
#define TIMER0_CR2_CAP_Pos                                    0
#define TIMER0_CR2_CAP_Msk                                    (0xffffffffUL << TIMER0_CR2_CAP_Pos)

// ---------------------------------------  TIMER0_CR3  -------------------------------------------
#define TIMER0_CR3_CAP_Pos                                    0
#define TIMER0_CR3_CAP_Msk                                    (0xffffffffUL << TIMER0_CR3_CAP_Pos)

// ---------------------------------------  TIMER0_EMR  -------------------------------------------
#define TIMER0_EMR_EM0_Pos                                    0
#define TIMER0_EMR_EM0_Msk                                    (0x01UL << TIMER0_EMR_EM0_Pos)
#define TIMER0_EMR_EM1_Pos                                    1
#define TIMER0_EMR_EM1_Msk                                    (0x01UL << TIMER0_EMR_EM1_Pos)
#define TIMER0_EMR_EM2_Pos                                    2
#define TIMER0_EMR_EM2_Msk                                    (0x01UL << TIMER0_EMR_EM2_Pos)
#define TIMER0_EMR_EM3_Pos                                    3
#define TIMER0_EMR_EM3_Msk                                    (0x01UL << TIMER0_EMR_EM3_Pos)
#define TIMER0_EMR_EMC0_Pos                                   4
#define TIMER0_EMR_EMC0_Msk                                   (0x03UL << TIMER0_EMR_EMC0_Pos)
#define TIMER0_EMR_EMC1_Pos                                   6
#define TIMER0_EMR_EMC1_Msk                                   (0x03UL << TIMER0_EMR_EMC1_Pos)
#define TIMER0_EMR_EMC2_Pos                                   8
#define TIMER0_EMR_EMC2_Msk                                   (0x03UL << TIMER0_EMR_EMC2_Pos)
#define TIMER0_EMR_EMC3_Pos                                   10
#define TIMER0_EMR_EMC3_Msk                                   (0x03UL << TIMER0_EMR_EMC3_Pos)

// ---------------------------------------  TIMER0_CTCR  ------------------------------------------
#define TIMER0_CTCR_CTMODE_Pos                                0
#define TIMER0_CTCR_CTMODE_Msk                                (0x03UL << TIMER0_CTCR_CTMODE_Pos)
#define TIMER0_CTCR_CINSEL_Pos                                2
#define TIMER0_CTCR_CINSEL_Msk                                (0x03UL << TIMER0_CTCR_CINSEL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                TIMER1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER1_IR  -------------------------------------------
#define TIMER1_IR_MR0INT_Pos                                  0
#define TIMER1_IR_MR0INT_Msk                                  (0x01UL << TIMER1_IR_MR0INT_Pos)
#define TIMER1_IR_MR1INT_Pos                                  1
#define TIMER1_IR_MR1INT_Msk                                  (0x01UL << TIMER1_IR_MR1INT_Pos)
#define TIMER1_IR_MR2INT_Pos                                  2
#define TIMER1_IR_MR2INT_Msk                                  (0x01UL << TIMER1_IR_MR2INT_Pos)
#define TIMER1_IR_MR3INT_Pos                                  3
#define TIMER1_IR_MR3INT_Msk                                  (0x01UL << TIMER1_IR_MR3INT_Pos)
#define TIMER1_IR_CR0INT_Pos                                  4
#define TIMER1_IR_CR0INT_Msk                                  (0x01UL << TIMER1_IR_CR0INT_Pos)
#define TIMER1_IR_CR1INT_Pos                                  5
#define TIMER1_IR_CR1INT_Msk                                  (0x01UL << TIMER1_IR_CR1INT_Pos)
#define TIMER1_IR_CR2INT_Pos                                  6
#define TIMER1_IR_CR2INT_Msk                                  (0x01UL << TIMER1_IR_CR2INT_Pos)
#define TIMER1_IR_CR3INT_Pos                                  7
#define TIMER1_IR_CR3INT_Msk                                  (0x01UL << TIMER1_IR_CR3INT_Pos)

// ---------------------------------------  TIMER1_TCR  -------------------------------------------
#define TIMER1_TCR_CEN_Pos                                    0
#define TIMER1_TCR_CEN_Msk                                    (0x01UL << TIMER1_TCR_CEN_Pos)
#define TIMER1_TCR_CRST_Pos                                   1
#define TIMER1_TCR_CRST_Msk                                   (0x01UL << TIMER1_TCR_CRST_Pos)

// ----------------------------------------  TIMER1_TC  -------------------------------------------
#define TIMER1_TC_TC_Pos                                      0
#define TIMER1_TC_TC_Msk                                      (0xffffffffUL << TIMER1_TC_TC_Pos)

// ----------------------------------------  TIMER1_PR  -------------------------------------------
#define TIMER1_PR_PM_Pos                                      0
#define TIMER1_PR_PM_Msk                                      (0xffffffffUL << TIMER1_PR_PM_Pos)

// ----------------------------------------  TIMER1_PC  -------------------------------------------
#define TIMER1_PC_PC_Pos                                      0
#define TIMER1_PC_PC_Msk                                      (0xffffffffUL << TIMER1_PC_PC_Pos)

// ---------------------------------------  TIMER1_MCR  -------------------------------------------
#define TIMER1_MCR_MR0I_Pos                                   0
#define TIMER1_MCR_MR0I_Msk                                   (0x01UL << TIMER1_MCR_MR0I_Pos)
#define TIMER1_MCR_MR0R_Pos                                   1
#define TIMER1_MCR_MR0R_Msk                                   (0x01UL << TIMER1_MCR_MR0R_Pos)
#define TIMER1_MCR_MR0S_Pos                                   2
#define TIMER1_MCR_MR0S_Msk                                   (0x01UL << TIMER1_MCR_MR0S_Pos)
#define TIMER1_MCR_MR1I_Pos                                   3
#define TIMER1_MCR_MR1I_Msk                                   (0x01UL << TIMER1_MCR_MR1I_Pos)
#define TIMER1_MCR_MR1R_Pos                                   4
#define TIMER1_MCR_MR1R_Msk                                   (0x01UL << TIMER1_MCR_MR1R_Pos)
#define TIMER1_MCR_MR1S_Pos                                   5
#define TIMER1_MCR_MR1S_Msk                                   (0x01UL << TIMER1_MCR_MR1S_Pos)
#define TIMER1_MCR_MR2I_Pos                                   6
#define TIMER1_MCR_MR2I_Msk                                   (0x01UL << TIMER1_MCR_MR2I_Pos)
#define TIMER1_MCR_MR2R_Pos                                   7
#define TIMER1_MCR_MR2R_Msk                                   (0x01UL << TIMER1_MCR_MR2R_Pos)
#define TIMER1_MCR_MR2S_Pos                                   8
#define TIMER1_MCR_MR2S_Msk                                   (0x01UL << TIMER1_MCR_MR2S_Pos)
#define TIMER1_MCR_MR3I_Pos                                   9
#define TIMER1_MCR_MR3I_Msk                                   (0x01UL << TIMER1_MCR_MR3I_Pos)
#define TIMER1_MCR_MR3R_Pos                                   10
#define TIMER1_MCR_MR3R_Msk                                   (0x01UL << TIMER1_MCR_MR3R_Pos)
#define TIMER1_MCR_MR3S_Pos                                   11
#define TIMER1_MCR_MR3S_Msk                                   (0x01UL << TIMER1_MCR_MR3S_Pos)

// ---------------------------------------  TIMER1_MR0  -------------------------------------------
#define TIMER1_MR0_MATCH_Pos                                  0
#define TIMER1_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR0_MATCH_Pos)

// ---------------------------------------  TIMER1_MR1  -------------------------------------------
#define TIMER1_MR1_MATCH_Pos                                  0
#define TIMER1_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR1_MATCH_Pos)

// ---------------------------------------  TIMER1_MR2  -------------------------------------------
#define TIMER1_MR2_MATCH_Pos                                  0
#define TIMER1_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR2_MATCH_Pos)

// ---------------------------------------  TIMER1_MR3  -------------------------------------------
#define TIMER1_MR3_MATCH_Pos                                  0
#define TIMER1_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER1_MR3_MATCH_Pos)

// ---------------------------------------  TIMER1_CCR  -------------------------------------------
#define TIMER1_CCR_CAP0RE_Pos                                 0
#define TIMER1_CCR_CAP0RE_Msk                                 (0x01UL << TIMER1_CCR_CAP0RE_Pos)
#define TIMER1_CCR_CAP0FE_Pos                                 1
#define TIMER1_CCR_CAP0FE_Msk                                 (0x01UL << TIMER1_CCR_CAP0FE_Pos)
#define TIMER1_CCR_CAP0I_Pos                                  2
#define TIMER1_CCR_CAP0I_Msk                                  (0x01UL << TIMER1_CCR_CAP0I_Pos)
#define TIMER1_CCR_CAP1RE_Pos                                 3
#define TIMER1_CCR_CAP1RE_Msk                                 (0x01UL << TIMER1_CCR_CAP1RE_Pos)
#define TIMER1_CCR_CAP1FE_Pos                                 4
#define TIMER1_CCR_CAP1FE_Msk                                 (0x01UL << TIMER1_CCR_CAP1FE_Pos)
#define TIMER1_CCR_CAP1I_Pos                                  5
#define TIMER1_CCR_CAP1I_Msk                                  (0x01UL << TIMER1_CCR_CAP1I_Pos)
#define TIMER1_CCR_CAP2RE_Pos                                 6
#define TIMER1_CCR_CAP2RE_Msk                                 (0x01UL << TIMER1_CCR_CAP2RE_Pos)
#define TIMER1_CCR_CAP2FE_Pos                                 7
#define TIMER1_CCR_CAP2FE_Msk                                 (0x01UL << TIMER1_CCR_CAP2FE_Pos)
#define TIMER1_CCR_CAP2I_Pos                                  8
#define TIMER1_CCR_CAP2I_Msk                                  (0x01UL << TIMER1_CCR_CAP2I_Pos)
#define TIMER1_CCR_CAP3RE_Pos                                 9
#define TIMER1_CCR_CAP3RE_Msk                                 (0x01UL << TIMER1_CCR_CAP3RE_Pos)
#define TIMER1_CCR_CAP3FE_Pos                                 10
#define TIMER1_CCR_CAP3FE_Msk                                 (0x01UL << TIMER1_CCR_CAP3FE_Pos)
#define TIMER1_CCR_CAP3I_Pos                                  11
#define TIMER1_CCR_CAP3I_Msk                                  (0x01UL << TIMER1_CCR_CAP3I_Pos)

// ---------------------------------------  TIMER1_CR0  -------------------------------------------
#define TIMER1_CR0_CAP_Pos                                    0
#define TIMER1_CR0_CAP_Msk                                    (0xffffffffUL << TIMER1_CR0_CAP_Pos)

// ---------------------------------------  TIMER1_CR1  -------------------------------------------
#define TIMER1_CR1_CAP_Pos                                    0
#define TIMER1_CR1_CAP_Msk                                    (0xffffffffUL << TIMER1_CR1_CAP_Pos)

// ---------------------------------------  TIMER1_CR2  -------------------------------------------
#define TIMER1_CR2_CAP_Pos                                    0
#define TIMER1_CR2_CAP_Msk                                    (0xffffffffUL << TIMER1_CR2_CAP_Pos)

// ---------------------------------------  TIMER1_CR3  -------------------------------------------
#define TIMER1_CR3_CAP_Pos                                    0
#define TIMER1_CR3_CAP_Msk                                    (0xffffffffUL << TIMER1_CR3_CAP_Pos)

// ---------------------------------------  TIMER1_EMR  -------------------------------------------
#define TIMER1_EMR_EM0_Pos                                    0
#define TIMER1_EMR_EM0_Msk                                    (0x01UL << TIMER1_EMR_EM0_Pos)
#define TIMER1_EMR_EM1_Pos                                    1
#define TIMER1_EMR_EM1_Msk                                    (0x01UL << TIMER1_EMR_EM1_Pos)
#define TIMER1_EMR_EM2_Pos                                    2
#define TIMER1_EMR_EM2_Msk                                    (0x01UL << TIMER1_EMR_EM2_Pos)
#define TIMER1_EMR_EM3_Pos                                    3
#define TIMER1_EMR_EM3_Msk                                    (0x01UL << TIMER1_EMR_EM3_Pos)
#define TIMER1_EMR_EMC0_Pos                                   4
#define TIMER1_EMR_EMC0_Msk                                   (0x03UL << TIMER1_EMR_EMC0_Pos)
#define TIMER1_EMR_EMC1_Pos                                   6
#define TIMER1_EMR_EMC1_Msk                                   (0x03UL << TIMER1_EMR_EMC1_Pos)
#define TIMER1_EMR_EMC2_Pos                                   8
#define TIMER1_EMR_EMC2_Msk                                   (0x03UL << TIMER1_EMR_EMC2_Pos)
#define TIMER1_EMR_EMC3_Pos                                   10
#define TIMER1_EMR_EMC3_Msk                                   (0x03UL << TIMER1_EMR_EMC3_Pos)

// ---------------------------------------  TIMER1_CTCR  ------------------------------------------
#define TIMER1_CTCR_CTMODE_Pos                                0
#define TIMER1_CTCR_CTMODE_Msk                                (0x03UL << TIMER1_CTCR_CTMODE_Pos)
#define TIMER1_CTCR_CINSEL_Pos                                2
#define TIMER1_CTCR_CINSEL_Msk                                (0x03UL << TIMER1_CTCR_CINSEL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                TIMER2 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER2_IR  -------------------------------------------
#define TIMER2_IR_MR0INT_Pos                                  0
#define TIMER2_IR_MR0INT_Msk                                  (0x01UL << TIMER2_IR_MR0INT_Pos)
#define TIMER2_IR_MR1INT_Pos                                  1
#define TIMER2_IR_MR1INT_Msk                                  (0x01UL << TIMER2_IR_MR1INT_Pos)
#define TIMER2_IR_MR2INT_Pos                                  2
#define TIMER2_IR_MR2INT_Msk                                  (0x01UL << TIMER2_IR_MR2INT_Pos)
#define TIMER2_IR_MR3INT_Pos                                  3
#define TIMER2_IR_MR3INT_Msk                                  (0x01UL << TIMER2_IR_MR3INT_Pos)
#define TIMER2_IR_CR0INT_Pos                                  4
#define TIMER2_IR_CR0INT_Msk                                  (0x01UL << TIMER2_IR_CR0INT_Pos)
#define TIMER2_IR_CR1INT_Pos                                  5
#define TIMER2_IR_CR1INT_Msk                                  (0x01UL << TIMER2_IR_CR1INT_Pos)
#define TIMER2_IR_CR2INT_Pos                                  6
#define TIMER2_IR_CR2INT_Msk                                  (0x01UL << TIMER2_IR_CR2INT_Pos)
#define TIMER2_IR_CR3INT_Pos                                  7
#define TIMER2_IR_CR3INT_Msk                                  (0x01UL << TIMER2_IR_CR3INT_Pos)

// ---------------------------------------  TIMER2_TCR  -------------------------------------------
#define TIMER2_TCR_CEN_Pos                                    0
#define TIMER2_TCR_CEN_Msk                                    (0x01UL << TIMER2_TCR_CEN_Pos)
#define TIMER2_TCR_CRST_Pos                                   1
#define TIMER2_TCR_CRST_Msk                                   (0x01UL << TIMER2_TCR_CRST_Pos)

// ----------------------------------------  TIMER2_TC  -------------------------------------------
#define TIMER2_TC_TC_Pos                                      0
#define TIMER2_TC_TC_Msk                                      (0xffffffffUL << TIMER2_TC_TC_Pos)

// ----------------------------------------  TIMER2_PR  -------------------------------------------
#define TIMER2_PR_PM_Pos                                      0
#define TIMER2_PR_PM_Msk                                      (0xffffffffUL << TIMER2_PR_PM_Pos)

// ----------------------------------------  TIMER2_PC  -------------------------------------------
#define TIMER2_PC_PC_Pos                                      0
#define TIMER2_PC_PC_Msk                                      (0xffffffffUL << TIMER2_PC_PC_Pos)

// ---------------------------------------  TIMER2_MCR  -------------------------------------------
#define TIMER2_MCR_MR0I_Pos                                   0
#define TIMER2_MCR_MR0I_Msk                                   (0x01UL << TIMER2_MCR_MR0I_Pos)
#define TIMER2_MCR_MR0R_Pos                                   1
#define TIMER2_MCR_MR0R_Msk                                   (0x01UL << TIMER2_MCR_MR0R_Pos)
#define TIMER2_MCR_MR0S_Pos                                   2
#define TIMER2_MCR_MR0S_Msk                                   (0x01UL << TIMER2_MCR_MR0S_Pos)
#define TIMER2_MCR_MR1I_Pos                                   3
#define TIMER2_MCR_MR1I_Msk                                   (0x01UL << TIMER2_MCR_MR1I_Pos)
#define TIMER2_MCR_MR1R_Pos                                   4
#define TIMER2_MCR_MR1R_Msk                                   (0x01UL << TIMER2_MCR_MR1R_Pos)
#define TIMER2_MCR_MR1S_Pos                                   5
#define TIMER2_MCR_MR1S_Msk                                   (0x01UL << TIMER2_MCR_MR1S_Pos)
#define TIMER2_MCR_MR2I_Pos                                   6
#define TIMER2_MCR_MR2I_Msk                                   (0x01UL << TIMER2_MCR_MR2I_Pos)
#define TIMER2_MCR_MR2R_Pos                                   7
#define TIMER2_MCR_MR2R_Msk                                   (0x01UL << TIMER2_MCR_MR2R_Pos)
#define TIMER2_MCR_MR2S_Pos                                   8
#define TIMER2_MCR_MR2S_Msk                                   (0x01UL << TIMER2_MCR_MR2S_Pos)
#define TIMER2_MCR_MR3I_Pos                                   9
#define TIMER2_MCR_MR3I_Msk                                   (0x01UL << TIMER2_MCR_MR3I_Pos)
#define TIMER2_MCR_MR3R_Pos                                   10
#define TIMER2_MCR_MR3R_Msk                                   (0x01UL << TIMER2_MCR_MR3R_Pos)
#define TIMER2_MCR_MR3S_Pos                                   11
#define TIMER2_MCR_MR3S_Msk                                   (0x01UL << TIMER2_MCR_MR3S_Pos)

// ---------------------------------------  TIMER2_MR0  -------------------------------------------
#define TIMER2_MR0_MATCH_Pos                                  0
#define TIMER2_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR0_MATCH_Pos)

// ---------------------------------------  TIMER2_MR1  -------------------------------------------
#define TIMER2_MR1_MATCH_Pos                                  0
#define TIMER2_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR1_MATCH_Pos)

// ---------------------------------------  TIMER2_MR2  -------------------------------------------
#define TIMER2_MR2_MATCH_Pos                                  0
#define TIMER2_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR2_MATCH_Pos)

// ---------------------------------------  TIMER2_MR3  -------------------------------------------
#define TIMER2_MR3_MATCH_Pos                                  0
#define TIMER2_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER2_MR3_MATCH_Pos)

// ---------------------------------------  TIMER2_CCR  -------------------------------------------
#define TIMER2_CCR_CAP0RE_Pos                                 0
#define TIMER2_CCR_CAP0RE_Msk                                 (0x01UL << TIMER2_CCR_CAP0RE_Pos)
#define TIMER2_CCR_CAP0FE_Pos                                 1
#define TIMER2_CCR_CAP0FE_Msk                                 (0x01UL << TIMER2_CCR_CAP0FE_Pos)
#define TIMER2_CCR_CAP0I_Pos                                  2
#define TIMER2_CCR_CAP0I_Msk                                  (0x01UL << TIMER2_CCR_CAP0I_Pos)
#define TIMER2_CCR_CAP1RE_Pos                                 3
#define TIMER2_CCR_CAP1RE_Msk                                 (0x01UL << TIMER2_CCR_CAP1RE_Pos)
#define TIMER2_CCR_CAP1FE_Pos                                 4
#define TIMER2_CCR_CAP1FE_Msk                                 (0x01UL << TIMER2_CCR_CAP1FE_Pos)
#define TIMER2_CCR_CAP1I_Pos                                  5
#define TIMER2_CCR_CAP1I_Msk                                  (0x01UL << TIMER2_CCR_CAP1I_Pos)
#define TIMER2_CCR_CAP2RE_Pos                                 6
#define TIMER2_CCR_CAP2RE_Msk                                 (0x01UL << TIMER2_CCR_CAP2RE_Pos)
#define TIMER2_CCR_CAP2FE_Pos                                 7
#define TIMER2_CCR_CAP2FE_Msk                                 (0x01UL << TIMER2_CCR_CAP2FE_Pos)
#define TIMER2_CCR_CAP2I_Pos                                  8
#define TIMER2_CCR_CAP2I_Msk                                  (0x01UL << TIMER2_CCR_CAP2I_Pos)
#define TIMER2_CCR_CAP3RE_Pos                                 9
#define TIMER2_CCR_CAP3RE_Msk                                 (0x01UL << TIMER2_CCR_CAP3RE_Pos)
#define TIMER2_CCR_CAP3FE_Pos                                 10
#define TIMER2_CCR_CAP3FE_Msk                                 (0x01UL << TIMER2_CCR_CAP3FE_Pos)
#define TIMER2_CCR_CAP3I_Pos                                  11
#define TIMER2_CCR_CAP3I_Msk                                  (0x01UL << TIMER2_CCR_CAP3I_Pos)

// ---------------------------------------  TIMER2_CR0  -------------------------------------------
#define TIMER2_CR0_CAP_Pos                                    0
#define TIMER2_CR0_CAP_Msk                                    (0xffffffffUL << TIMER2_CR0_CAP_Pos)

// ---------------------------------------  TIMER2_CR1  -------------------------------------------
#define TIMER2_CR1_CAP_Pos                                    0
#define TIMER2_CR1_CAP_Msk                                    (0xffffffffUL << TIMER2_CR1_CAP_Pos)

// ---------------------------------------  TIMER2_CR2  -------------------------------------------
#define TIMER2_CR2_CAP_Pos                                    0
#define TIMER2_CR2_CAP_Msk                                    (0xffffffffUL << TIMER2_CR2_CAP_Pos)

// ---------------------------------------  TIMER2_CR3  -------------------------------------------
#define TIMER2_CR3_CAP_Pos                                    0
#define TIMER2_CR3_CAP_Msk                                    (0xffffffffUL << TIMER2_CR3_CAP_Pos)

// ---------------------------------------  TIMER2_EMR  -------------------------------------------
#define TIMER2_EMR_EM0_Pos                                    0
#define TIMER2_EMR_EM0_Msk                                    (0x01UL << TIMER2_EMR_EM0_Pos)
#define TIMER2_EMR_EM1_Pos                                    1
#define TIMER2_EMR_EM1_Msk                                    (0x01UL << TIMER2_EMR_EM1_Pos)
#define TIMER2_EMR_EM2_Pos                                    2
#define TIMER2_EMR_EM2_Msk                                    (0x01UL << TIMER2_EMR_EM2_Pos)
#define TIMER2_EMR_EM3_Pos                                    3
#define TIMER2_EMR_EM3_Msk                                    (0x01UL << TIMER2_EMR_EM3_Pos)
#define TIMER2_EMR_EMC0_Pos                                   4
#define TIMER2_EMR_EMC0_Msk                                   (0x03UL << TIMER2_EMR_EMC0_Pos)
#define TIMER2_EMR_EMC1_Pos                                   6
#define TIMER2_EMR_EMC1_Msk                                   (0x03UL << TIMER2_EMR_EMC1_Pos)
#define TIMER2_EMR_EMC2_Pos                                   8
#define TIMER2_EMR_EMC2_Msk                                   (0x03UL << TIMER2_EMR_EMC2_Pos)
#define TIMER2_EMR_EMC3_Pos                                   10
#define TIMER2_EMR_EMC3_Msk                                   (0x03UL << TIMER2_EMR_EMC3_Pos)

// ---------------------------------------  TIMER2_CTCR  ------------------------------------------
#define TIMER2_CTCR_CTMODE_Pos                                0
#define TIMER2_CTCR_CTMODE_Msk                                (0x03UL << TIMER2_CTCR_CTMODE_Pos)
#define TIMER2_CTCR_CINSEL_Pos                                2
#define TIMER2_CTCR_CINSEL_Msk                                (0x03UL << TIMER2_CTCR_CINSEL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                TIMER3 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  TIMER3_IR  -------------------------------------------
#define TIMER3_IR_MR0INT_Pos                                  0
#define TIMER3_IR_MR0INT_Msk                                  (0x01UL << TIMER3_IR_MR0INT_Pos)
#define TIMER3_IR_MR1INT_Pos                                  1
#define TIMER3_IR_MR1INT_Msk                                  (0x01UL << TIMER3_IR_MR1INT_Pos)
#define TIMER3_IR_MR2INT_Pos                                  2
#define TIMER3_IR_MR2INT_Msk                                  (0x01UL << TIMER3_IR_MR2INT_Pos)
#define TIMER3_IR_MR3INT_Pos                                  3
#define TIMER3_IR_MR3INT_Msk                                  (0x01UL << TIMER3_IR_MR3INT_Pos)
#define TIMER3_IR_CR0INT_Pos                                  4
#define TIMER3_IR_CR0INT_Msk                                  (0x01UL << TIMER3_IR_CR0INT_Pos)
#define TIMER3_IR_CR1INT_Pos                                  5
#define TIMER3_IR_CR1INT_Msk                                  (0x01UL << TIMER3_IR_CR1INT_Pos)
#define TIMER3_IR_CR2INT_Pos                                  6
#define TIMER3_IR_CR2INT_Msk                                  (0x01UL << TIMER3_IR_CR2INT_Pos)
#define TIMER3_IR_CR3INT_Pos                                  7
#define TIMER3_IR_CR3INT_Msk                                  (0x01UL << TIMER3_IR_CR3INT_Pos)

// ---------------------------------------  TIMER3_TCR  -------------------------------------------
#define TIMER3_TCR_CEN_Pos                                    0
#define TIMER3_TCR_CEN_Msk                                    (0x01UL << TIMER3_TCR_CEN_Pos)
#define TIMER3_TCR_CRST_Pos                                   1
#define TIMER3_TCR_CRST_Msk                                   (0x01UL << TIMER3_TCR_CRST_Pos)

// ----------------------------------------  TIMER3_TC  -------------------------------------------
#define TIMER3_TC_TC_Pos                                      0
#define TIMER3_TC_TC_Msk                                      (0xffffffffUL << TIMER3_TC_TC_Pos)

// ----------------------------------------  TIMER3_PR  -------------------------------------------
#define TIMER3_PR_PM_Pos                                      0
#define TIMER3_PR_PM_Msk                                      (0xffffffffUL << TIMER3_PR_PM_Pos)

// ----------------------------------------  TIMER3_PC  -------------------------------------------
#define TIMER3_PC_PC_Pos                                      0
#define TIMER3_PC_PC_Msk                                      (0xffffffffUL << TIMER3_PC_PC_Pos)

// ---------------------------------------  TIMER3_MCR  -------------------------------------------
#define TIMER3_MCR_MR0I_Pos                                   0
#define TIMER3_MCR_MR0I_Msk                                   (0x01UL << TIMER3_MCR_MR0I_Pos)
#define TIMER3_MCR_MR0R_Pos                                   1
#define TIMER3_MCR_MR0R_Msk                                   (0x01UL << TIMER3_MCR_MR0R_Pos)
#define TIMER3_MCR_MR0S_Pos                                   2
#define TIMER3_MCR_MR0S_Msk                                   (0x01UL << TIMER3_MCR_MR0S_Pos)
#define TIMER3_MCR_MR1I_Pos                                   3
#define TIMER3_MCR_MR1I_Msk                                   (0x01UL << TIMER3_MCR_MR1I_Pos)
#define TIMER3_MCR_MR1R_Pos                                   4
#define TIMER3_MCR_MR1R_Msk                                   (0x01UL << TIMER3_MCR_MR1R_Pos)
#define TIMER3_MCR_MR1S_Pos                                   5
#define TIMER3_MCR_MR1S_Msk                                   (0x01UL << TIMER3_MCR_MR1S_Pos)
#define TIMER3_MCR_MR2I_Pos                                   6
#define TIMER3_MCR_MR2I_Msk                                   (0x01UL << TIMER3_MCR_MR2I_Pos)
#define TIMER3_MCR_MR2R_Pos                                   7
#define TIMER3_MCR_MR2R_Msk                                   (0x01UL << TIMER3_MCR_MR2R_Pos)
#define TIMER3_MCR_MR2S_Pos                                   8
#define TIMER3_MCR_MR2S_Msk                                   (0x01UL << TIMER3_MCR_MR2S_Pos)
#define TIMER3_MCR_MR3I_Pos                                   9
#define TIMER3_MCR_MR3I_Msk                                   (0x01UL << TIMER3_MCR_MR3I_Pos)
#define TIMER3_MCR_MR3R_Pos                                   10
#define TIMER3_MCR_MR3R_Msk                                   (0x01UL << TIMER3_MCR_MR3R_Pos)
#define TIMER3_MCR_MR3S_Pos                                   11
#define TIMER3_MCR_MR3S_Msk                                   (0x01UL << TIMER3_MCR_MR3S_Pos)

// ---------------------------------------  TIMER3_MR0  -------------------------------------------
#define TIMER3_MR0_MATCH_Pos                                  0
#define TIMER3_MR0_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR0_MATCH_Pos)

// ---------------------------------------  TIMER3_MR1  -------------------------------------------
#define TIMER3_MR1_MATCH_Pos                                  0
#define TIMER3_MR1_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR1_MATCH_Pos)

// ---------------------------------------  TIMER3_MR2  -------------------------------------------
#define TIMER3_MR2_MATCH_Pos                                  0
#define TIMER3_MR2_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR2_MATCH_Pos)

// ---------------------------------------  TIMER3_MR3  -------------------------------------------
#define TIMER3_MR3_MATCH_Pos                                  0
#define TIMER3_MR3_MATCH_Msk                                  (0xffffffffUL << TIMER3_MR3_MATCH_Pos)

// ---------------------------------------  TIMER3_CCR  -------------------------------------------
#define TIMER3_CCR_CAP0RE_Pos                                 0
#define TIMER3_CCR_CAP0RE_Msk                                 (0x01UL << TIMER3_CCR_CAP0RE_Pos)
#define TIMER3_CCR_CAP0FE_Pos                                 1
#define TIMER3_CCR_CAP0FE_Msk                                 (0x01UL << TIMER3_CCR_CAP0FE_Pos)
#define TIMER3_CCR_CAP0I_Pos                                  2
#define TIMER3_CCR_CAP0I_Msk                                  (0x01UL << TIMER3_CCR_CAP0I_Pos)
#define TIMER3_CCR_CAP1RE_Pos                                 3
#define TIMER3_CCR_CAP1RE_Msk                                 (0x01UL << TIMER3_CCR_CAP1RE_Pos)
#define TIMER3_CCR_CAP1FE_Pos                                 4
#define TIMER3_CCR_CAP1FE_Msk                                 (0x01UL << TIMER3_CCR_CAP1FE_Pos)
#define TIMER3_CCR_CAP1I_Pos                                  5
#define TIMER3_CCR_CAP1I_Msk                                  (0x01UL << TIMER3_CCR_CAP1I_Pos)
#define TIMER3_CCR_CAP2RE_Pos                                 6
#define TIMER3_CCR_CAP2RE_Msk                                 (0x01UL << TIMER3_CCR_CAP2RE_Pos)
#define TIMER3_CCR_CAP2FE_Pos                                 7
#define TIMER3_CCR_CAP2FE_Msk                                 (0x01UL << TIMER3_CCR_CAP2FE_Pos)
#define TIMER3_CCR_CAP2I_Pos                                  8
#define TIMER3_CCR_CAP2I_Msk                                  (0x01UL << TIMER3_CCR_CAP2I_Pos)
#define TIMER3_CCR_CAP3RE_Pos                                 9
#define TIMER3_CCR_CAP3RE_Msk                                 (0x01UL << TIMER3_CCR_CAP3RE_Pos)
#define TIMER3_CCR_CAP3FE_Pos                                 10
#define TIMER3_CCR_CAP3FE_Msk                                 (0x01UL << TIMER3_CCR_CAP3FE_Pos)
#define TIMER3_CCR_CAP3I_Pos                                  11
#define TIMER3_CCR_CAP3I_Msk                                  (0x01UL << TIMER3_CCR_CAP3I_Pos)

// ---------------------------------------  TIMER3_CR0  -------------------------------------------
#define TIMER3_CR0_CAP_Pos                                    0
#define TIMER3_CR0_CAP_Msk                                    (0xffffffffUL << TIMER3_CR0_CAP_Pos)

// ---------------------------------------  TIMER3_CR1  -------------------------------------------
#define TIMER3_CR1_CAP_Pos                                    0
#define TIMER3_CR1_CAP_Msk                                    (0xffffffffUL << TIMER3_CR1_CAP_Pos)

// ---------------------------------------  TIMER3_CR2  -------------------------------------------
#define TIMER3_CR2_CAP_Pos                                    0
#define TIMER3_CR2_CAP_Msk                                    (0xffffffffUL << TIMER3_CR2_CAP_Pos)

// ---------------------------------------  TIMER3_CR3  -------------------------------------------
#define TIMER3_CR3_CAP_Pos                                    0
#define TIMER3_CR3_CAP_Msk                                    (0xffffffffUL << TIMER3_CR3_CAP_Pos)

// ---------------------------------------  TIMER3_EMR  -------------------------------------------
#define TIMER3_EMR_EM0_Pos                                    0
#define TIMER3_EMR_EM0_Msk                                    (0x01UL << TIMER3_EMR_EM0_Pos)
#define TIMER3_EMR_EM1_Pos                                    1
#define TIMER3_EMR_EM1_Msk                                    (0x01UL << TIMER3_EMR_EM1_Pos)
#define TIMER3_EMR_EM2_Pos                                    2
#define TIMER3_EMR_EM2_Msk                                    (0x01UL << TIMER3_EMR_EM2_Pos)
#define TIMER3_EMR_EM3_Pos                                    3
#define TIMER3_EMR_EM3_Msk                                    (0x01UL << TIMER3_EMR_EM3_Pos)
#define TIMER3_EMR_EMC0_Pos                                   4
#define TIMER3_EMR_EMC0_Msk                                   (0x03UL << TIMER3_EMR_EMC0_Pos)
#define TIMER3_EMR_EMC1_Pos                                   6
#define TIMER3_EMR_EMC1_Msk                                   (0x03UL << TIMER3_EMR_EMC1_Pos)
#define TIMER3_EMR_EMC2_Pos                                   8
#define TIMER3_EMR_EMC2_Msk                                   (0x03UL << TIMER3_EMR_EMC2_Pos)
#define TIMER3_EMR_EMC3_Pos                                   10
#define TIMER3_EMR_EMC3_Msk                                   (0x03UL << TIMER3_EMR_EMC3_Pos)

// ---------------------------------------  TIMER3_CTCR  ------------------------------------------
#define TIMER3_CTCR_CTMODE_Pos                                0
#define TIMER3_CTCR_CTMODE_Msk                                (0x03UL << TIMER3_CTCR_CTMODE_Pos)
#define TIMER3_CTCR_CINSEL_Pos                                2
#define TIMER3_CTCR_CINSEL_Msk                                (0x03UL << TIMER3_CTCR_CINSEL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  SCU Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  SCU_SFSP0_0  ------------------------------------------
#define SCU_SFSP0_0_MODE_Pos                                  0
#define SCU_SFSP0_0_MODE_Msk                                  (0x07UL << SCU_SFSP0_0_MODE_Pos)
#define SCU_SFSP0_0_EPD_Pos                                   3
#define SCU_SFSP0_0_EPD_Msk                                   (0x01UL << SCU_SFSP0_0_EPD_Pos)
#define SCU_SFSP0_0_EPUN_Pos                                  4
#define SCU_SFSP0_0_EPUN_Msk                                  (0x01UL << SCU_SFSP0_0_EPUN_Pos)
#define SCU_SFSP0_0_EHS_Pos                                   5
#define SCU_SFSP0_0_EHS_Msk                                   (0x01UL << SCU_SFSP0_0_EHS_Pos)
#define SCU_SFSP0_0_EZI_Pos                                   6
#define SCU_SFSP0_0_EZI_Msk                                   (0x01UL << SCU_SFSP0_0_EZI_Pos)

// ---------------------------------------  SCU_SFSP0_1  ------------------------------------------
#define SCU_SFSP0_1_MODE_Pos                                  0
#define SCU_SFSP0_1_MODE_Msk                                  (0x07UL << SCU_SFSP0_1_MODE_Pos)
#define SCU_SFSP0_1_EPD_Pos                                   3
#define SCU_SFSP0_1_EPD_Msk                                   (0x01UL << SCU_SFSP0_1_EPD_Pos)
#define SCU_SFSP0_1_EPUN_Pos                                  4
#define SCU_SFSP0_1_EPUN_Msk                                  (0x01UL << SCU_SFSP0_1_EPUN_Pos)
#define SCU_SFSP0_1_EHS_Pos                                   5
#define SCU_SFSP0_1_EHS_Msk                                   (0x01UL << SCU_SFSP0_1_EHS_Pos)
#define SCU_SFSP0_1_EZI_Pos                                   6
#define SCU_SFSP0_1_EZI_Msk                                   (0x01UL << SCU_SFSP0_1_EZI_Pos)

// ---------------------------------------  SCU_SFSP1_0  ------------------------------------------
#define SCU_SFSP1_0_MODE_Pos                                  0
#define SCU_SFSP1_0_MODE_Msk                                  (0x07UL << SCU_SFSP1_0_MODE_Pos)
#define SCU_SFSP1_0_EPD_Pos                                   3
#define SCU_SFSP1_0_EPD_Msk                                   (0x01UL << SCU_SFSP1_0_EPD_Pos)
#define SCU_SFSP1_0_EPUN_Pos                                  4
#define SCU_SFSP1_0_EPUN_Msk                                  (0x01UL << SCU_SFSP1_0_EPUN_Pos)
#define SCU_SFSP1_0_EHS_Pos                                   5
#define SCU_SFSP1_0_EHS_Msk                                   (0x01UL << SCU_SFSP1_0_EHS_Pos)
#define SCU_SFSP1_0_EZI_Pos                                   6
#define SCU_SFSP1_0_EZI_Msk                                   (0x01UL << SCU_SFSP1_0_EZI_Pos)
#define SCU_SFSP1_0_EHD_Pos                                   8
#define SCU_SFSP1_0_EHD_Msk                                   (0x03UL << SCU_SFSP1_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_1  ------------------------------------------
#define SCU_SFSP1_1_MODE_Pos                                  0
#define SCU_SFSP1_1_MODE_Msk                                  (0x07UL << SCU_SFSP1_1_MODE_Pos)
#define SCU_SFSP1_1_EPD_Pos                                   3
#define SCU_SFSP1_1_EPD_Msk                                   (0x01UL << SCU_SFSP1_1_EPD_Pos)
#define SCU_SFSP1_1_EPUN_Pos                                  4
#define SCU_SFSP1_1_EPUN_Msk                                  (0x01UL << SCU_SFSP1_1_EPUN_Pos)
#define SCU_SFSP1_1_EHS_Pos                                   5
#define SCU_SFSP1_1_EHS_Msk                                   (0x01UL << SCU_SFSP1_1_EHS_Pos)
#define SCU_SFSP1_1_EZI_Pos                                   6
#define SCU_SFSP1_1_EZI_Msk                                   (0x01UL << SCU_SFSP1_1_EZI_Pos)
#define SCU_SFSP1_1_EHD_Pos                                   8
#define SCU_SFSP1_1_EHD_Msk                                   (0x03UL << SCU_SFSP1_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_2  ------------------------------------------
#define SCU_SFSP1_2_MODE_Pos                                  0
#define SCU_SFSP1_2_MODE_Msk                                  (0x07UL << SCU_SFSP1_2_MODE_Pos)
#define SCU_SFSP1_2_EPD_Pos                                   3
#define SCU_SFSP1_2_EPD_Msk                                   (0x01UL << SCU_SFSP1_2_EPD_Pos)
#define SCU_SFSP1_2_EPUN_Pos                                  4
#define SCU_SFSP1_2_EPUN_Msk                                  (0x01UL << SCU_SFSP1_2_EPUN_Pos)
#define SCU_SFSP1_2_EHS_Pos                                   5
#define SCU_SFSP1_2_EHS_Msk                                   (0x01UL << SCU_SFSP1_2_EHS_Pos)
#define SCU_SFSP1_2_EZI_Pos                                   6
#define SCU_SFSP1_2_EZI_Msk                                   (0x01UL << SCU_SFSP1_2_EZI_Pos)
#define SCU_SFSP1_2_EHD_Pos                                   8
#define SCU_SFSP1_2_EHD_Msk                                   (0x03UL << SCU_SFSP1_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_3  ------------------------------------------
#define SCU_SFSP1_3_MODE_Pos                                  0
#define SCU_SFSP1_3_MODE_Msk                                  (0x07UL << SCU_SFSP1_3_MODE_Pos)
#define SCU_SFSP1_3_EPD_Pos                                   3
#define SCU_SFSP1_3_EPD_Msk                                   (0x01UL << SCU_SFSP1_3_EPD_Pos)
#define SCU_SFSP1_3_EPUN_Pos                                  4
#define SCU_SFSP1_3_EPUN_Msk                                  (0x01UL << SCU_SFSP1_3_EPUN_Pos)
#define SCU_SFSP1_3_EHS_Pos                                   5
#define SCU_SFSP1_3_EHS_Msk                                   (0x01UL << SCU_SFSP1_3_EHS_Pos)
#define SCU_SFSP1_3_EZI_Pos                                   6
#define SCU_SFSP1_3_EZI_Msk                                   (0x01UL << SCU_SFSP1_3_EZI_Pos)
#define SCU_SFSP1_3_EHD_Pos                                   8
#define SCU_SFSP1_3_EHD_Msk                                   (0x03UL << SCU_SFSP1_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_4  ------------------------------------------
#define SCU_SFSP1_4_MODE_Pos                                  0
#define SCU_SFSP1_4_MODE_Msk                                  (0x07UL << SCU_SFSP1_4_MODE_Pos)
#define SCU_SFSP1_4_EPD_Pos                                   3
#define SCU_SFSP1_4_EPD_Msk                                   (0x01UL << SCU_SFSP1_4_EPD_Pos)
#define SCU_SFSP1_4_EPUN_Pos                                  4
#define SCU_SFSP1_4_EPUN_Msk                                  (0x01UL << SCU_SFSP1_4_EPUN_Pos)
#define SCU_SFSP1_4_EHS_Pos                                   5
#define SCU_SFSP1_4_EHS_Msk                                   (0x01UL << SCU_SFSP1_4_EHS_Pos)
#define SCU_SFSP1_4_EZI_Pos                                   6
#define SCU_SFSP1_4_EZI_Msk                                   (0x01UL << SCU_SFSP1_4_EZI_Pos)
#define SCU_SFSP1_4_EHD_Pos                                   8
#define SCU_SFSP1_4_EHD_Msk                                   (0x03UL << SCU_SFSP1_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_5  ------------------------------------------
#define SCU_SFSP1_5_MODE_Pos                                  0
#define SCU_SFSP1_5_MODE_Msk                                  (0x07UL << SCU_SFSP1_5_MODE_Pos)
#define SCU_SFSP1_5_EPD_Pos                                   3
#define SCU_SFSP1_5_EPD_Msk                                   (0x01UL << SCU_SFSP1_5_EPD_Pos)
#define SCU_SFSP1_5_EPUN_Pos                                  4
#define SCU_SFSP1_5_EPUN_Msk                                  (0x01UL << SCU_SFSP1_5_EPUN_Pos)
#define SCU_SFSP1_5_EHS_Pos                                   5
#define SCU_SFSP1_5_EHS_Msk                                   (0x01UL << SCU_SFSP1_5_EHS_Pos)
#define SCU_SFSP1_5_EZI_Pos                                   6
#define SCU_SFSP1_5_EZI_Msk                                   (0x01UL << SCU_SFSP1_5_EZI_Pos)
#define SCU_SFSP1_5_EHD_Pos                                   8
#define SCU_SFSP1_5_EHD_Msk                                   (0x03UL << SCU_SFSP1_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_6  ------------------------------------------
#define SCU_SFSP1_6_MODE_Pos                                  0
#define SCU_SFSP1_6_MODE_Msk                                  (0x07UL << SCU_SFSP1_6_MODE_Pos)
#define SCU_SFSP1_6_EPD_Pos                                   3
#define SCU_SFSP1_6_EPD_Msk                                   (0x01UL << SCU_SFSP1_6_EPD_Pos)
#define SCU_SFSP1_6_EPUN_Pos                                  4
#define SCU_SFSP1_6_EPUN_Msk                                  (0x01UL << SCU_SFSP1_6_EPUN_Pos)
#define SCU_SFSP1_6_EHS_Pos                                   5
#define SCU_SFSP1_6_EHS_Msk                                   (0x01UL << SCU_SFSP1_6_EHS_Pos)
#define SCU_SFSP1_6_EZI_Pos                                   6
#define SCU_SFSP1_6_EZI_Msk                                   (0x01UL << SCU_SFSP1_6_EZI_Pos)
#define SCU_SFSP1_6_EHD_Pos                                   8
#define SCU_SFSP1_6_EHD_Msk                                   (0x03UL << SCU_SFSP1_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_7  ------------------------------------------
#define SCU_SFSP1_7_MODE_Pos                                  0
#define SCU_SFSP1_7_MODE_Msk                                  (0x07UL << SCU_SFSP1_7_MODE_Pos)
#define SCU_SFSP1_7_EPD_Pos                                   3
#define SCU_SFSP1_7_EPD_Msk                                   (0x01UL << SCU_SFSP1_7_EPD_Pos)
#define SCU_SFSP1_7_EPUN_Pos                                  4
#define SCU_SFSP1_7_EPUN_Msk                                  (0x01UL << SCU_SFSP1_7_EPUN_Pos)
#define SCU_SFSP1_7_EHS_Pos                                   5
#define SCU_SFSP1_7_EHS_Msk                                   (0x01UL << SCU_SFSP1_7_EHS_Pos)
#define SCU_SFSP1_7_EZI_Pos                                   6
#define SCU_SFSP1_7_EZI_Msk                                   (0x01UL << SCU_SFSP1_7_EZI_Pos)
#define SCU_SFSP1_7_EHD_Pos                                   8
#define SCU_SFSP1_7_EHD_Msk                                   (0x03UL << SCU_SFSP1_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_8  ------------------------------------------
#define SCU_SFSP1_8_MODE_Pos                                  0
#define SCU_SFSP1_8_MODE_Msk                                  (0x07UL << SCU_SFSP1_8_MODE_Pos)
#define SCU_SFSP1_8_EPD_Pos                                   3
#define SCU_SFSP1_8_EPD_Msk                                   (0x01UL << SCU_SFSP1_8_EPD_Pos)
#define SCU_SFSP1_8_EPUN_Pos                                  4
#define SCU_SFSP1_8_EPUN_Msk                                  (0x01UL << SCU_SFSP1_8_EPUN_Pos)
#define SCU_SFSP1_8_EHS_Pos                                   5
#define SCU_SFSP1_8_EHS_Msk                                   (0x01UL << SCU_SFSP1_8_EHS_Pos)
#define SCU_SFSP1_8_EZI_Pos                                   6
#define SCU_SFSP1_8_EZI_Msk                                   (0x01UL << SCU_SFSP1_8_EZI_Pos)
#define SCU_SFSP1_8_EHD_Pos                                   8
#define SCU_SFSP1_8_EHD_Msk                                   (0x03UL << SCU_SFSP1_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP1_9  ------------------------------------------
#define SCU_SFSP1_9_MODE_Pos                                  0
#define SCU_SFSP1_9_MODE_Msk                                  (0x07UL << SCU_SFSP1_9_MODE_Pos)
#define SCU_SFSP1_9_EPD_Pos                                   3
#define SCU_SFSP1_9_EPD_Msk                                   (0x01UL << SCU_SFSP1_9_EPD_Pos)
#define SCU_SFSP1_9_EPUN_Pos                                  4
#define SCU_SFSP1_9_EPUN_Msk                                  (0x01UL << SCU_SFSP1_9_EPUN_Pos)
#define SCU_SFSP1_9_EHS_Pos                                   5
#define SCU_SFSP1_9_EHS_Msk                                   (0x01UL << SCU_SFSP1_9_EHS_Pos)
#define SCU_SFSP1_9_EZI_Pos                                   6
#define SCU_SFSP1_9_EZI_Msk                                   (0x01UL << SCU_SFSP1_9_EZI_Pos)
#define SCU_SFSP1_9_EHD_Pos                                   8
#define SCU_SFSP1_9_EHD_Msk                                   (0x03UL << SCU_SFSP1_9_EHD_Pos)

// --------------------------------------  SCU_SFSP1_10  ------------------------------------------
#define SCU_SFSP1_10_MODE_Pos                                 0
#define SCU_SFSP1_10_MODE_Msk                                 (0x07UL << SCU_SFSP1_10_MODE_Pos)
#define SCU_SFSP1_10_EPD_Pos                                  3
#define SCU_SFSP1_10_EPD_Msk                                  (0x01UL << SCU_SFSP1_10_EPD_Pos)
#define SCU_SFSP1_10_EPUN_Pos                                 4
#define SCU_SFSP1_10_EPUN_Msk                                 (0x01UL << SCU_SFSP1_10_EPUN_Pos)
#define SCU_SFSP1_10_EHS_Pos                                  5
#define SCU_SFSP1_10_EHS_Msk                                  (0x01UL << SCU_SFSP1_10_EHS_Pos)
#define SCU_SFSP1_10_EZI_Pos                                  6
#define SCU_SFSP1_10_EZI_Msk                                  (0x01UL << SCU_SFSP1_10_EZI_Pos)
#define SCU_SFSP1_10_EHD_Pos                                  8
#define SCU_SFSP1_10_EHD_Msk                                  (0x03UL << SCU_SFSP1_10_EHD_Pos)

// --------------------------------------  SCU_SFSP1_11  ------------------------------------------
#define SCU_SFSP1_11_MODE_Pos                                 0
#define SCU_SFSP1_11_MODE_Msk                                 (0x07UL << SCU_SFSP1_11_MODE_Pos)
#define SCU_SFSP1_11_EPD_Pos                                  3
#define SCU_SFSP1_11_EPD_Msk                                  (0x01UL << SCU_SFSP1_11_EPD_Pos)
#define SCU_SFSP1_11_EPUN_Pos                                 4
#define SCU_SFSP1_11_EPUN_Msk                                 (0x01UL << SCU_SFSP1_11_EPUN_Pos)
#define SCU_SFSP1_11_EHS_Pos                                  5
#define SCU_SFSP1_11_EHS_Msk                                  (0x01UL << SCU_SFSP1_11_EHS_Pos)
#define SCU_SFSP1_11_EZI_Pos                                  6
#define SCU_SFSP1_11_EZI_Msk                                  (0x01UL << SCU_SFSP1_11_EZI_Pos)
#define SCU_SFSP1_11_EHD_Pos                                  8
#define SCU_SFSP1_11_EHD_Msk                                  (0x03UL << SCU_SFSP1_11_EHD_Pos)

// --------------------------------------  SCU_SFSP1_12  ------------------------------------------
#define SCU_SFSP1_12_MODE_Pos                                 0
#define SCU_SFSP1_12_MODE_Msk                                 (0x07UL << SCU_SFSP1_12_MODE_Pos)
#define SCU_SFSP1_12_EPD_Pos                                  3
#define SCU_SFSP1_12_EPD_Msk                                  (0x01UL << SCU_SFSP1_12_EPD_Pos)
#define SCU_SFSP1_12_EPUN_Pos                                 4
#define SCU_SFSP1_12_EPUN_Msk                                 (0x01UL << SCU_SFSP1_12_EPUN_Pos)
#define SCU_SFSP1_12_EHS_Pos                                  5
#define SCU_SFSP1_12_EHS_Msk                                  (0x01UL << SCU_SFSP1_12_EHS_Pos)
#define SCU_SFSP1_12_EZI_Pos                                  6
#define SCU_SFSP1_12_EZI_Msk                                  (0x01UL << SCU_SFSP1_12_EZI_Pos)
#define SCU_SFSP1_12_EHD_Pos                                  8
#define SCU_SFSP1_12_EHD_Msk                                  (0x03UL << SCU_SFSP1_12_EHD_Pos)

// --------------------------------------  SCU_SFSP1_13  ------------------------------------------
#define SCU_SFSP1_13_MODE_Pos                                 0
#define SCU_SFSP1_13_MODE_Msk                                 (0x07UL << SCU_SFSP1_13_MODE_Pos)
#define SCU_SFSP1_13_EPD_Pos                                  3
#define SCU_SFSP1_13_EPD_Msk                                  (0x01UL << SCU_SFSP1_13_EPD_Pos)
#define SCU_SFSP1_13_EPUN_Pos                                 4
#define SCU_SFSP1_13_EPUN_Msk                                 (0x01UL << SCU_SFSP1_13_EPUN_Pos)
#define SCU_SFSP1_13_EHS_Pos                                  5
#define SCU_SFSP1_13_EHS_Msk                                  (0x01UL << SCU_SFSP1_13_EHS_Pos)
#define SCU_SFSP1_13_EZI_Pos                                  6
#define SCU_SFSP1_13_EZI_Msk                                  (0x01UL << SCU_SFSP1_13_EZI_Pos)
#define SCU_SFSP1_13_EHD_Pos                                  8
#define SCU_SFSP1_13_EHD_Msk                                  (0x03UL << SCU_SFSP1_13_EHD_Pos)

// --------------------------------------  SCU_SFSP1_14  ------------------------------------------
#define SCU_SFSP1_14_MODE_Pos                                 0
#define SCU_SFSP1_14_MODE_Msk                                 (0x07UL << SCU_SFSP1_14_MODE_Pos)
#define SCU_SFSP1_14_EPD_Pos                                  3
#define SCU_SFSP1_14_EPD_Msk                                  (0x01UL << SCU_SFSP1_14_EPD_Pos)
#define SCU_SFSP1_14_EPUN_Pos                                 4
#define SCU_SFSP1_14_EPUN_Msk                                 (0x01UL << SCU_SFSP1_14_EPUN_Pos)
#define SCU_SFSP1_14_EHS_Pos                                  5
#define SCU_SFSP1_14_EHS_Msk                                  (0x01UL << SCU_SFSP1_14_EHS_Pos)
#define SCU_SFSP1_14_EZI_Pos                                  6
#define SCU_SFSP1_14_EZI_Msk                                  (0x01UL << SCU_SFSP1_14_EZI_Pos)
#define SCU_SFSP1_14_EHD_Pos                                  8
#define SCU_SFSP1_14_EHD_Msk                                  (0x03UL << SCU_SFSP1_14_EHD_Pos)

// --------------------------------------  SCU_SFSP1_15  ------------------------------------------
#define SCU_SFSP1_15_MODE_Pos                                 0
#define SCU_SFSP1_15_MODE_Msk                                 (0x07UL << SCU_SFSP1_15_MODE_Pos)
#define SCU_SFSP1_15_EPD_Pos                                  3
#define SCU_SFSP1_15_EPD_Msk                                  (0x01UL << SCU_SFSP1_15_EPD_Pos)
#define SCU_SFSP1_15_EPUN_Pos                                 4
#define SCU_SFSP1_15_EPUN_Msk                                 (0x01UL << SCU_SFSP1_15_EPUN_Pos)
#define SCU_SFSP1_15_EHS_Pos                                  5
#define SCU_SFSP1_15_EHS_Msk                                  (0x01UL << SCU_SFSP1_15_EHS_Pos)
#define SCU_SFSP1_15_EZI_Pos                                  6
#define SCU_SFSP1_15_EZI_Msk                                  (0x01UL << SCU_SFSP1_15_EZI_Pos)
#define SCU_SFSP1_15_EHD_Pos                                  8
#define SCU_SFSP1_15_EHD_Msk                                  (0x03UL << SCU_SFSP1_15_EHD_Pos)

// --------------------------------------  SCU_SFSP1_16  ------------------------------------------
#define SCU_SFSP1_16_MODE_Pos                                 0
#define SCU_SFSP1_16_MODE_Msk                                 (0x07UL << SCU_SFSP1_16_MODE_Pos)
#define SCU_SFSP1_16_EPD_Pos                                  3
#define SCU_SFSP1_16_EPD_Msk                                  (0x01UL << SCU_SFSP1_16_EPD_Pos)
#define SCU_SFSP1_16_EPUN_Pos                                 4
#define SCU_SFSP1_16_EPUN_Msk                                 (0x01UL << SCU_SFSP1_16_EPUN_Pos)
#define SCU_SFSP1_16_EHS_Pos                                  5
#define SCU_SFSP1_16_EHS_Msk                                  (0x01UL << SCU_SFSP1_16_EHS_Pos)
#define SCU_SFSP1_16_EZI_Pos                                  6
#define SCU_SFSP1_16_EZI_Msk                                  (0x01UL << SCU_SFSP1_16_EZI_Pos)
#define SCU_SFSP1_16_EHD_Pos                                  8
#define SCU_SFSP1_16_EHD_Msk                                  (0x03UL << SCU_SFSP1_16_EHD_Pos)

// --------------------------------------  SCU_SFSP1_17  ------------------------------------------
#define SCU_SFSP1_17_MODE_Pos                                 0
#define SCU_SFSP1_17_MODE_Msk                                 (0x07UL << SCU_SFSP1_17_MODE_Pos)
#define SCU_SFSP1_17_EPD_Pos                                  3
#define SCU_SFSP1_17_EPD_Msk                                  (0x01UL << SCU_SFSP1_17_EPD_Pos)
#define SCU_SFSP1_17_EPUN_Pos                                 4
#define SCU_SFSP1_17_EPUN_Msk                                 (0x01UL << SCU_SFSP1_17_EPUN_Pos)
#define SCU_SFSP1_17_EHS_Pos                                  5
#define SCU_SFSP1_17_EHS_Msk                                  (0x01UL << SCU_SFSP1_17_EHS_Pos)
#define SCU_SFSP1_17_EZI_Pos                                  6
#define SCU_SFSP1_17_EZI_Msk                                  (0x01UL << SCU_SFSP1_17_EZI_Pos)
#define SCU_SFSP1_17_EHD_Pos                                  8
#define SCU_SFSP1_17_EHD_Msk                                  (0x03UL << SCU_SFSP1_17_EHD_Pos)

// --------------------------------------  SCU_SFSP1_18  ------------------------------------------
#define SCU_SFSP1_18_MODE_Pos                                 0
#define SCU_SFSP1_18_MODE_Msk                                 (0x07UL << SCU_SFSP1_18_MODE_Pos)
#define SCU_SFSP1_18_EPD_Pos                                  3
#define SCU_SFSP1_18_EPD_Msk                                  (0x01UL << SCU_SFSP1_18_EPD_Pos)
#define SCU_SFSP1_18_EPUN_Pos                                 4
#define SCU_SFSP1_18_EPUN_Msk                                 (0x01UL << SCU_SFSP1_18_EPUN_Pos)
#define SCU_SFSP1_18_EHS_Pos                                  5
#define SCU_SFSP1_18_EHS_Msk                                  (0x01UL << SCU_SFSP1_18_EHS_Pos)
#define SCU_SFSP1_18_EZI_Pos                                  6
#define SCU_SFSP1_18_EZI_Msk                                  (0x01UL << SCU_SFSP1_18_EZI_Pos)
#define SCU_SFSP1_18_EHD_Pos                                  8
#define SCU_SFSP1_18_EHD_Msk                                  (0x03UL << SCU_SFSP1_18_EHD_Pos)

// --------------------------------------  SCU_SFSP1_19  ------------------------------------------
#define SCU_SFSP1_19_MODE_Pos                                 0
#define SCU_SFSP1_19_MODE_Msk                                 (0x07UL << SCU_SFSP1_19_MODE_Pos)
#define SCU_SFSP1_19_EPD_Pos                                  3
#define SCU_SFSP1_19_EPD_Msk                                  (0x01UL << SCU_SFSP1_19_EPD_Pos)
#define SCU_SFSP1_19_EPUN_Pos                                 4
#define SCU_SFSP1_19_EPUN_Msk                                 (0x01UL << SCU_SFSP1_19_EPUN_Pos)
#define SCU_SFSP1_19_EHS_Pos                                  5
#define SCU_SFSP1_19_EHS_Msk                                  (0x01UL << SCU_SFSP1_19_EHS_Pos)
#define SCU_SFSP1_19_EZI_Pos                                  6
#define SCU_SFSP1_19_EZI_Msk                                  (0x01UL << SCU_SFSP1_19_EZI_Pos)
#define SCU_SFSP1_19_EHD_Pos                                  8
#define SCU_SFSP1_19_EHD_Msk                                  (0x03UL << SCU_SFSP1_19_EHD_Pos)

// --------------------------------------  SCU_SFSP1_20  ------------------------------------------
#define SCU_SFSP1_20_MODE_Pos                                 0
#define SCU_SFSP1_20_MODE_Msk                                 (0x07UL << SCU_SFSP1_20_MODE_Pos)
#define SCU_SFSP1_20_EPD_Pos                                  3
#define SCU_SFSP1_20_EPD_Msk                                  (0x01UL << SCU_SFSP1_20_EPD_Pos)
#define SCU_SFSP1_20_EPUN_Pos                                 4
#define SCU_SFSP1_20_EPUN_Msk                                 (0x01UL << SCU_SFSP1_20_EPUN_Pos)
#define SCU_SFSP1_20_EHS_Pos                                  5
#define SCU_SFSP1_20_EHS_Msk                                  (0x01UL << SCU_SFSP1_20_EHS_Pos)
#define SCU_SFSP1_20_EZI_Pos                                  6
#define SCU_SFSP1_20_EZI_Msk                                  (0x01UL << SCU_SFSP1_20_EZI_Pos)
#define SCU_SFSP1_20_EHD_Pos                                  8
#define SCU_SFSP1_20_EHD_Msk                                  (0x03UL << SCU_SFSP1_20_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_0  ------------------------------------------
#define SCU_SFSP2_0_MODE_Pos                                  0
#define SCU_SFSP2_0_MODE_Msk                                  (0x07UL << SCU_SFSP2_0_MODE_Pos)
#define SCU_SFSP2_0_EPD_Pos                                   3
#define SCU_SFSP2_0_EPD_Msk                                   (0x01UL << SCU_SFSP2_0_EPD_Pos)
#define SCU_SFSP2_0_EPUN_Pos                                  4
#define SCU_SFSP2_0_EPUN_Msk                                  (0x01UL << SCU_SFSP2_0_EPUN_Pos)
#define SCU_SFSP2_0_EHS_Pos                                   5
#define SCU_SFSP2_0_EHS_Msk                                   (0x01UL << SCU_SFSP2_0_EHS_Pos)
#define SCU_SFSP2_0_EZI_Pos                                   6
#define SCU_SFSP2_0_EZI_Msk                                   (0x01UL << SCU_SFSP2_0_EZI_Pos)
#define SCU_SFSP2_0_EHD_Pos                                   8
#define SCU_SFSP2_0_EHD_Msk                                   (0x03UL << SCU_SFSP2_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_1  ------------------------------------------
#define SCU_SFSP2_1_MODE_Pos                                  0
#define SCU_SFSP2_1_MODE_Msk                                  (0x07UL << SCU_SFSP2_1_MODE_Pos)
#define SCU_SFSP2_1_EPD_Pos                                   3
#define SCU_SFSP2_1_EPD_Msk                                   (0x01UL << SCU_SFSP2_1_EPD_Pos)
#define SCU_SFSP2_1_EPUN_Pos                                  4
#define SCU_SFSP2_1_EPUN_Msk                                  (0x01UL << SCU_SFSP2_1_EPUN_Pos)
#define SCU_SFSP2_1_EHS_Pos                                   5
#define SCU_SFSP2_1_EHS_Msk                                   (0x01UL << SCU_SFSP2_1_EHS_Pos)
#define SCU_SFSP2_1_EZI_Pos                                   6
#define SCU_SFSP2_1_EZI_Msk                                   (0x01UL << SCU_SFSP2_1_EZI_Pos)
#define SCU_SFSP2_1_EHD_Pos                                   8
#define SCU_SFSP2_1_EHD_Msk                                   (0x03UL << SCU_SFSP2_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_2  ------------------------------------------
#define SCU_SFSP2_2_MODE_Pos                                  0
#define SCU_SFSP2_2_MODE_Msk                                  (0x07UL << SCU_SFSP2_2_MODE_Pos)
#define SCU_SFSP2_2_EPD_Pos                                   3
#define SCU_SFSP2_2_EPD_Msk                                   (0x01UL << SCU_SFSP2_2_EPD_Pos)
#define SCU_SFSP2_2_EPUN_Pos                                  4
#define SCU_SFSP2_2_EPUN_Msk                                  (0x01UL << SCU_SFSP2_2_EPUN_Pos)
#define SCU_SFSP2_2_EHS_Pos                                   5
#define SCU_SFSP2_2_EHS_Msk                                   (0x01UL << SCU_SFSP2_2_EHS_Pos)
#define SCU_SFSP2_2_EZI_Pos                                   6
#define SCU_SFSP2_2_EZI_Msk                                   (0x01UL << SCU_SFSP2_2_EZI_Pos)
#define SCU_SFSP2_2_EHD_Pos                                   8
#define SCU_SFSP2_2_EHD_Msk                                   (0x03UL << SCU_SFSP2_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_3  ------------------------------------------
#define SCU_SFSP2_3_MODE_Pos                                  0
#define SCU_SFSP2_3_MODE_Msk                                  (0x07UL << SCU_SFSP2_3_MODE_Pos)
#define SCU_SFSP2_3_EPD_Pos                                   3
#define SCU_SFSP2_3_EPD_Msk                                   (0x01UL << SCU_SFSP2_3_EPD_Pos)
#define SCU_SFSP2_3_EPUN_Pos                                  4
#define SCU_SFSP2_3_EPUN_Msk                                  (0x01UL << SCU_SFSP2_3_EPUN_Pos)
#define SCU_SFSP2_3_EHS_Pos                                   5
#define SCU_SFSP2_3_EHS_Msk                                   (0x01UL << SCU_SFSP2_3_EHS_Pos)
#define SCU_SFSP2_3_EZI_Pos                                   6
#define SCU_SFSP2_3_EZI_Msk                                   (0x01UL << SCU_SFSP2_3_EZI_Pos)
#define SCU_SFSP2_3_EHD_Pos                                   8
#define SCU_SFSP2_3_EHD_Msk                                   (0x03UL << SCU_SFSP2_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_4  ------------------------------------------
#define SCU_SFSP2_4_MODE_Pos                                  0
#define SCU_SFSP2_4_MODE_Msk                                  (0x07UL << SCU_SFSP2_4_MODE_Pos)
#define SCU_SFSP2_4_EPD_Pos                                   3
#define SCU_SFSP2_4_EPD_Msk                                   (0x01UL << SCU_SFSP2_4_EPD_Pos)
#define SCU_SFSP2_4_EPUN_Pos                                  4
#define SCU_SFSP2_4_EPUN_Msk                                  (0x01UL << SCU_SFSP2_4_EPUN_Pos)
#define SCU_SFSP2_4_EHS_Pos                                   5
#define SCU_SFSP2_4_EHS_Msk                                   (0x01UL << SCU_SFSP2_4_EHS_Pos)
#define SCU_SFSP2_4_EZI_Pos                                   6
#define SCU_SFSP2_4_EZI_Msk                                   (0x01UL << SCU_SFSP2_4_EZI_Pos)
#define SCU_SFSP2_4_EHD_Pos                                   8
#define SCU_SFSP2_4_EHD_Msk                                   (0x03UL << SCU_SFSP2_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_5  ------------------------------------------
#define SCU_SFSP2_5_MODE_Pos                                  0
#define SCU_SFSP2_5_MODE_Msk                                  (0x07UL << SCU_SFSP2_5_MODE_Pos)
#define SCU_SFSP2_5_EPD_Pos                                   3
#define SCU_SFSP2_5_EPD_Msk                                   (0x01UL << SCU_SFSP2_5_EPD_Pos)
#define SCU_SFSP2_5_EPUN_Pos                                  4
#define SCU_SFSP2_5_EPUN_Msk                                  (0x01UL << SCU_SFSP2_5_EPUN_Pos)
#define SCU_SFSP2_5_EHS_Pos                                   5
#define SCU_SFSP2_5_EHS_Msk                                   (0x01UL << SCU_SFSP2_5_EHS_Pos)
#define SCU_SFSP2_5_EZI_Pos                                   6
#define SCU_SFSP2_5_EZI_Msk                                   (0x01UL << SCU_SFSP2_5_EZI_Pos)
#define SCU_SFSP2_5_EHD_Pos                                   8
#define SCU_SFSP2_5_EHD_Msk                                   (0x03UL << SCU_SFSP2_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_6  ------------------------------------------
#define SCU_SFSP2_6_MODE_Pos                                  0
#define SCU_SFSP2_6_MODE_Msk                                  (0x07UL << SCU_SFSP2_6_MODE_Pos)
#define SCU_SFSP2_6_EPD_Pos                                   3
#define SCU_SFSP2_6_EPD_Msk                                   (0x01UL << SCU_SFSP2_6_EPD_Pos)
#define SCU_SFSP2_6_EPUN_Pos                                  4
#define SCU_SFSP2_6_EPUN_Msk                                  (0x01UL << SCU_SFSP2_6_EPUN_Pos)
#define SCU_SFSP2_6_EHS_Pos                                   5
#define SCU_SFSP2_6_EHS_Msk                                   (0x01UL << SCU_SFSP2_6_EHS_Pos)
#define SCU_SFSP2_6_EZI_Pos                                   6
#define SCU_SFSP2_6_EZI_Msk                                   (0x01UL << SCU_SFSP2_6_EZI_Pos)
#define SCU_SFSP2_6_EHD_Pos                                   8
#define SCU_SFSP2_6_EHD_Msk                                   (0x03UL << SCU_SFSP2_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_7  ------------------------------------------
#define SCU_SFSP2_7_MODE_Pos                                  0
#define SCU_SFSP2_7_MODE_Msk                                  (0x07UL << SCU_SFSP2_7_MODE_Pos)
#define SCU_SFSP2_7_EPD_Pos                                   3
#define SCU_SFSP2_7_EPD_Msk                                   (0x01UL << SCU_SFSP2_7_EPD_Pos)
#define SCU_SFSP2_7_EPUN_Pos                                  4
#define SCU_SFSP2_7_EPUN_Msk                                  (0x01UL << SCU_SFSP2_7_EPUN_Pos)
#define SCU_SFSP2_7_EHS_Pos                                   5
#define SCU_SFSP2_7_EHS_Msk                                   (0x01UL << SCU_SFSP2_7_EHS_Pos)
#define SCU_SFSP2_7_EZI_Pos                                   6
#define SCU_SFSP2_7_EZI_Msk                                   (0x01UL << SCU_SFSP2_7_EZI_Pos)
#define SCU_SFSP2_7_EHD_Pos                                   8
#define SCU_SFSP2_7_EHD_Msk                                   (0x03UL << SCU_SFSP2_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_8  ------------------------------------------
#define SCU_SFSP2_8_MODE_Pos                                  0
#define SCU_SFSP2_8_MODE_Msk                                  (0x07UL << SCU_SFSP2_8_MODE_Pos)
#define SCU_SFSP2_8_EPD_Pos                                   3
#define SCU_SFSP2_8_EPD_Msk                                   (0x01UL << SCU_SFSP2_8_EPD_Pos)
#define SCU_SFSP2_8_EPUN_Pos                                  4
#define SCU_SFSP2_8_EPUN_Msk                                  (0x01UL << SCU_SFSP2_8_EPUN_Pos)
#define SCU_SFSP2_8_EHS_Pos                                   5
#define SCU_SFSP2_8_EHS_Msk                                   (0x01UL << SCU_SFSP2_8_EHS_Pos)
#define SCU_SFSP2_8_EZI_Pos                                   6
#define SCU_SFSP2_8_EZI_Msk                                   (0x01UL << SCU_SFSP2_8_EZI_Pos)
#define SCU_SFSP2_8_EHD_Pos                                   8
#define SCU_SFSP2_8_EHD_Msk                                   (0x03UL << SCU_SFSP2_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP2_9  ------------------------------------------
#define SCU_SFSP2_9_MODE_Pos                                  0
#define SCU_SFSP2_9_MODE_Msk                                  (0x07UL << SCU_SFSP2_9_MODE_Pos)
#define SCU_SFSP2_9_EPD_Pos                                   3
#define SCU_SFSP2_9_EPD_Msk                                   (0x01UL << SCU_SFSP2_9_EPD_Pos)
#define SCU_SFSP2_9_EPUN_Pos                                  4
#define SCU_SFSP2_9_EPUN_Msk                                  (0x01UL << SCU_SFSP2_9_EPUN_Pos)
#define SCU_SFSP2_9_EHS_Pos                                   5
#define SCU_SFSP2_9_EHS_Msk                                   (0x01UL << SCU_SFSP2_9_EHS_Pos)
#define SCU_SFSP2_9_EZI_Pos                                   6
#define SCU_SFSP2_9_EZI_Msk                                   (0x01UL << SCU_SFSP2_9_EZI_Pos)
#define SCU_SFSP2_9_EHD_Pos                                   8
#define SCU_SFSP2_9_EHD_Msk                                   (0x03UL << SCU_SFSP2_9_EHD_Pos)

// --------------------------------------  SCU_SFSP2_10  ------------------------------------------
#define SCU_SFSP2_10_MODE_Pos                                 0
#define SCU_SFSP2_10_MODE_Msk                                 (0x07UL << SCU_SFSP2_10_MODE_Pos)
#define SCU_SFSP2_10_EPD_Pos                                  3
#define SCU_SFSP2_10_EPD_Msk                                  (0x01UL << SCU_SFSP2_10_EPD_Pos)
#define SCU_SFSP2_10_EPUN_Pos                                 4
#define SCU_SFSP2_10_EPUN_Msk                                 (0x01UL << SCU_SFSP2_10_EPUN_Pos)
#define SCU_SFSP2_10_EHS_Pos                                  5
#define SCU_SFSP2_10_EHS_Msk                                  (0x01UL << SCU_SFSP2_10_EHS_Pos)
#define SCU_SFSP2_10_EZI_Pos                                  6
#define SCU_SFSP2_10_EZI_Msk                                  (0x01UL << SCU_SFSP2_10_EZI_Pos)
#define SCU_SFSP2_10_EHD_Pos                                  8
#define SCU_SFSP2_10_EHD_Msk                                  (0x03UL << SCU_SFSP2_10_EHD_Pos)

// --------------------------------------  SCU_SFSP2_11  ------------------------------------------
#define SCU_SFSP2_11_MODE_Pos                                 0
#define SCU_SFSP2_11_MODE_Msk                                 (0x07UL << SCU_SFSP2_11_MODE_Pos)
#define SCU_SFSP2_11_EPD_Pos                                  3
#define SCU_SFSP2_11_EPD_Msk                                  (0x01UL << SCU_SFSP2_11_EPD_Pos)
#define SCU_SFSP2_11_EPUN_Pos                                 4
#define SCU_SFSP2_11_EPUN_Msk                                 (0x01UL << SCU_SFSP2_11_EPUN_Pos)
#define SCU_SFSP2_11_EHS_Pos                                  5
#define SCU_SFSP2_11_EHS_Msk                                  (0x01UL << SCU_SFSP2_11_EHS_Pos)
#define SCU_SFSP2_11_EZI_Pos                                  6
#define SCU_SFSP2_11_EZI_Msk                                  (0x01UL << SCU_SFSP2_11_EZI_Pos)
#define SCU_SFSP2_11_EHD_Pos                                  8
#define SCU_SFSP2_11_EHD_Msk                                  (0x03UL << SCU_SFSP2_11_EHD_Pos)

// --------------------------------------  SCU_SFSP2_12  ------------------------------------------
#define SCU_SFSP2_12_MODE_Pos                                 0
#define SCU_SFSP2_12_MODE_Msk                                 (0x07UL << SCU_SFSP2_12_MODE_Pos)
#define SCU_SFSP2_12_EPD_Pos                                  3
#define SCU_SFSP2_12_EPD_Msk                                  (0x01UL << SCU_SFSP2_12_EPD_Pos)
#define SCU_SFSP2_12_EPUN_Pos                                 4
#define SCU_SFSP2_12_EPUN_Msk                                 (0x01UL << SCU_SFSP2_12_EPUN_Pos)
#define SCU_SFSP2_12_EHS_Pos                                  5
#define SCU_SFSP2_12_EHS_Msk                                  (0x01UL << SCU_SFSP2_12_EHS_Pos)
#define SCU_SFSP2_12_EZI_Pos                                  6
#define SCU_SFSP2_12_EZI_Msk                                  (0x01UL << SCU_SFSP2_12_EZI_Pos)
#define SCU_SFSP2_12_EHD_Pos                                  8
#define SCU_SFSP2_12_EHD_Msk                                  (0x03UL << SCU_SFSP2_12_EHD_Pos)

// --------------------------------------  SCU_SFSP2_13  ------------------------------------------
#define SCU_SFSP2_13_MODE_Pos                                 0
#define SCU_SFSP2_13_MODE_Msk                                 (0x07UL << SCU_SFSP2_13_MODE_Pos)
#define SCU_SFSP2_13_EPD_Pos                                  3
#define SCU_SFSP2_13_EPD_Msk                                  (0x01UL << SCU_SFSP2_13_EPD_Pos)
#define SCU_SFSP2_13_EPUN_Pos                                 4
#define SCU_SFSP2_13_EPUN_Msk                                 (0x01UL << SCU_SFSP2_13_EPUN_Pos)
#define SCU_SFSP2_13_EHS_Pos                                  5
#define SCU_SFSP2_13_EHS_Msk                                  (0x01UL << SCU_SFSP2_13_EHS_Pos)
#define SCU_SFSP2_13_EZI_Pos                                  6
#define SCU_SFSP2_13_EZI_Msk                                  (0x01UL << SCU_SFSP2_13_EZI_Pos)
#define SCU_SFSP2_13_EHD_Pos                                  8
#define SCU_SFSP2_13_EHD_Msk                                  (0x03UL << SCU_SFSP2_13_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_0  ------------------------------------------
#define SCU_SFSP3_0_MODE_Pos                                  0
#define SCU_SFSP3_0_MODE_Msk                                  (0x07UL << SCU_SFSP3_0_MODE_Pos)
#define SCU_SFSP3_0_EPD_Pos                                   3
#define SCU_SFSP3_0_EPD_Msk                                   (0x01UL << SCU_SFSP3_0_EPD_Pos)
#define SCU_SFSP3_0_EPUN_Pos                                  4
#define SCU_SFSP3_0_EPUN_Msk                                  (0x01UL << SCU_SFSP3_0_EPUN_Pos)
#define SCU_SFSP3_0_EHS_Pos                                   5
#define SCU_SFSP3_0_EHS_Msk                                   (0x01UL << SCU_SFSP3_0_EHS_Pos)
#define SCU_SFSP3_0_EZI_Pos                                   6
#define SCU_SFSP3_0_EZI_Msk                                   (0x01UL << SCU_SFSP3_0_EZI_Pos)
#define SCU_SFSP3_0_EHD_Pos                                   8
#define SCU_SFSP3_0_EHD_Msk                                   (0x03UL << SCU_SFSP3_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_1  ------------------------------------------
#define SCU_SFSP3_1_MODE_Pos                                  0
#define SCU_SFSP3_1_MODE_Msk                                  (0x07UL << SCU_SFSP3_1_MODE_Pos)
#define SCU_SFSP3_1_EPD_Pos                                   3
#define SCU_SFSP3_1_EPD_Msk                                   (0x01UL << SCU_SFSP3_1_EPD_Pos)
#define SCU_SFSP3_1_EPUN_Pos                                  4
#define SCU_SFSP3_1_EPUN_Msk                                  (0x01UL << SCU_SFSP3_1_EPUN_Pos)
#define SCU_SFSP3_1_EHS_Pos                                   5
#define SCU_SFSP3_1_EHS_Msk                                   (0x01UL << SCU_SFSP3_1_EHS_Pos)
#define SCU_SFSP3_1_EZI_Pos                                   6
#define SCU_SFSP3_1_EZI_Msk                                   (0x01UL << SCU_SFSP3_1_EZI_Pos)
#define SCU_SFSP3_1_EHD_Pos                                   8
#define SCU_SFSP3_1_EHD_Msk                                   (0x03UL << SCU_SFSP3_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_2  ------------------------------------------
#define SCU_SFSP3_2_MODE_Pos                                  0
#define SCU_SFSP3_2_MODE_Msk                                  (0x07UL << SCU_SFSP3_2_MODE_Pos)
#define SCU_SFSP3_2_EPD_Pos                                   3
#define SCU_SFSP3_2_EPD_Msk                                   (0x01UL << SCU_SFSP3_2_EPD_Pos)
#define SCU_SFSP3_2_EPUN_Pos                                  4
#define SCU_SFSP3_2_EPUN_Msk                                  (0x01UL << SCU_SFSP3_2_EPUN_Pos)
#define SCU_SFSP3_2_EHS_Pos                                   5
#define SCU_SFSP3_2_EHS_Msk                                   (0x01UL << SCU_SFSP3_2_EHS_Pos)
#define SCU_SFSP3_2_EZI_Pos                                   6
#define SCU_SFSP3_2_EZI_Msk                                   (0x01UL << SCU_SFSP3_2_EZI_Pos)
#define SCU_SFSP3_2_EHD_Pos                                   8
#define SCU_SFSP3_2_EHD_Msk                                   (0x03UL << SCU_SFSP3_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_3  ------------------------------------------
#define SCU_SFSP3_3_MODE_Pos                                  0
#define SCU_SFSP3_3_MODE_Msk                                  (0x07UL << SCU_SFSP3_3_MODE_Pos)
#define SCU_SFSP3_3_EPD_Pos                                   3
#define SCU_SFSP3_3_EPD_Msk                                   (0x01UL << SCU_SFSP3_3_EPD_Pos)
#define SCU_SFSP3_3_EPUN_Pos                                  4
#define SCU_SFSP3_3_EPUN_Msk                                  (0x01UL << SCU_SFSP3_3_EPUN_Pos)
#define SCU_SFSP3_3_EHS_Pos                                   5
#define SCU_SFSP3_3_EHS_Msk                                   (0x01UL << SCU_SFSP3_3_EHS_Pos)
#define SCU_SFSP3_3_EZI_Pos                                   6
#define SCU_SFSP3_3_EZI_Msk                                   (0x01UL << SCU_SFSP3_3_EZI_Pos)
#define SCU_SFSP3_3_EHD_Pos                                   8
#define SCU_SFSP3_3_EHD_Msk                                   (0x03UL << SCU_SFSP3_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_4  ------------------------------------------
#define SCU_SFSP3_4_MODE_Pos                                  0
#define SCU_SFSP3_4_MODE_Msk                                  (0x07UL << SCU_SFSP3_4_MODE_Pos)
#define SCU_SFSP3_4_EPD_Pos                                   3
#define SCU_SFSP3_4_EPD_Msk                                   (0x01UL << SCU_SFSP3_4_EPD_Pos)
#define SCU_SFSP3_4_EPUN_Pos                                  4
#define SCU_SFSP3_4_EPUN_Msk                                  (0x01UL << SCU_SFSP3_4_EPUN_Pos)
#define SCU_SFSP3_4_EHS_Pos                                   5
#define SCU_SFSP3_4_EHS_Msk                                   (0x01UL << SCU_SFSP3_4_EHS_Pos)
#define SCU_SFSP3_4_EZI_Pos                                   6
#define SCU_SFSP3_4_EZI_Msk                                   (0x01UL << SCU_SFSP3_4_EZI_Pos)
#define SCU_SFSP3_4_EHD_Pos                                   8
#define SCU_SFSP3_4_EHD_Msk                                   (0x03UL << SCU_SFSP3_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_5  ------------------------------------------
#define SCU_SFSP3_5_MODE_Pos                                  0
#define SCU_SFSP3_5_MODE_Msk                                  (0x07UL << SCU_SFSP3_5_MODE_Pos)
#define SCU_SFSP3_5_EPD_Pos                                   3
#define SCU_SFSP3_5_EPD_Msk                                   (0x01UL << SCU_SFSP3_5_EPD_Pos)
#define SCU_SFSP3_5_EPUN_Pos                                  4
#define SCU_SFSP3_5_EPUN_Msk                                  (0x01UL << SCU_SFSP3_5_EPUN_Pos)
#define SCU_SFSP3_5_EHS_Pos                                   5
#define SCU_SFSP3_5_EHS_Msk                                   (0x01UL << SCU_SFSP3_5_EHS_Pos)
#define SCU_SFSP3_5_EZI_Pos                                   6
#define SCU_SFSP3_5_EZI_Msk                                   (0x01UL << SCU_SFSP3_5_EZI_Pos)
#define SCU_SFSP3_5_EHD_Pos                                   8
#define SCU_SFSP3_5_EHD_Msk                                   (0x03UL << SCU_SFSP3_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_6  ------------------------------------------
#define SCU_SFSP3_6_MODE_Pos                                  0
#define SCU_SFSP3_6_MODE_Msk                                  (0x07UL << SCU_SFSP3_6_MODE_Pos)
#define SCU_SFSP3_6_EPD_Pos                                   3
#define SCU_SFSP3_6_EPD_Msk                                   (0x01UL << SCU_SFSP3_6_EPD_Pos)
#define SCU_SFSP3_6_EPUN_Pos                                  4
#define SCU_SFSP3_6_EPUN_Msk                                  (0x01UL << SCU_SFSP3_6_EPUN_Pos)
#define SCU_SFSP3_6_EHS_Pos                                   5
#define SCU_SFSP3_6_EHS_Msk                                   (0x01UL << SCU_SFSP3_6_EHS_Pos)
#define SCU_SFSP3_6_EZI_Pos                                   6
#define SCU_SFSP3_6_EZI_Msk                                   (0x01UL << SCU_SFSP3_6_EZI_Pos)
#define SCU_SFSP3_6_EHD_Pos                                   8
#define SCU_SFSP3_6_EHD_Msk                                   (0x03UL << SCU_SFSP3_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_7  ------------------------------------------
#define SCU_SFSP3_7_MODE_Pos                                  0
#define SCU_SFSP3_7_MODE_Msk                                  (0x07UL << SCU_SFSP3_7_MODE_Pos)
#define SCU_SFSP3_7_EPD_Pos                                   3
#define SCU_SFSP3_7_EPD_Msk                                   (0x01UL << SCU_SFSP3_7_EPD_Pos)
#define SCU_SFSP3_7_EPUN_Pos                                  4
#define SCU_SFSP3_7_EPUN_Msk                                  (0x01UL << SCU_SFSP3_7_EPUN_Pos)
#define SCU_SFSP3_7_EHS_Pos                                   5
#define SCU_SFSP3_7_EHS_Msk                                   (0x01UL << SCU_SFSP3_7_EHS_Pos)
#define SCU_SFSP3_7_EZI_Pos                                   6
#define SCU_SFSP3_7_EZI_Msk                                   (0x01UL << SCU_SFSP3_7_EZI_Pos)
#define SCU_SFSP3_7_EHD_Pos                                   8
#define SCU_SFSP3_7_EHD_Msk                                   (0x03UL << SCU_SFSP3_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP3_8  ------------------------------------------
#define SCU_SFSP3_8_MODE_Pos                                  0
#define SCU_SFSP3_8_MODE_Msk                                  (0x07UL << SCU_SFSP3_8_MODE_Pos)
#define SCU_SFSP3_8_EPD_Pos                                   3
#define SCU_SFSP3_8_EPD_Msk                                   (0x01UL << SCU_SFSP3_8_EPD_Pos)
#define SCU_SFSP3_8_EPUN_Pos                                  4
#define SCU_SFSP3_8_EPUN_Msk                                  (0x01UL << SCU_SFSP3_8_EPUN_Pos)
#define SCU_SFSP3_8_EHS_Pos                                   5
#define SCU_SFSP3_8_EHS_Msk                                   (0x01UL << SCU_SFSP3_8_EHS_Pos)
#define SCU_SFSP3_8_EZI_Pos                                   6
#define SCU_SFSP3_8_EZI_Msk                                   (0x01UL << SCU_SFSP3_8_EZI_Pos)
#define SCU_SFSP3_8_EHD_Pos                                   8
#define SCU_SFSP3_8_EHD_Msk                                   (0x03UL << SCU_SFSP3_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_0  ------------------------------------------
#define SCU_SFSP4_0_MODE_Pos                                  0
#define SCU_SFSP4_0_MODE_Msk                                  (0x07UL << SCU_SFSP4_0_MODE_Pos)
#define SCU_SFSP4_0_EPD_Pos                                   3
#define SCU_SFSP4_0_EPD_Msk                                   (0x01UL << SCU_SFSP4_0_EPD_Pos)
#define SCU_SFSP4_0_EPUN_Pos                                  4
#define SCU_SFSP4_0_EPUN_Msk                                  (0x01UL << SCU_SFSP4_0_EPUN_Pos)
#define SCU_SFSP4_0_EHS_Pos                                   5
#define SCU_SFSP4_0_EHS_Msk                                   (0x01UL << SCU_SFSP4_0_EHS_Pos)
#define SCU_SFSP4_0_EZI_Pos                                   6
#define SCU_SFSP4_0_EZI_Msk                                   (0x01UL << SCU_SFSP4_0_EZI_Pos)
#define SCU_SFSP4_0_EHD_Pos                                   8
#define SCU_SFSP4_0_EHD_Msk                                   (0x03UL << SCU_SFSP4_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_1  ------------------------------------------
#define SCU_SFSP4_1_MODE_Pos                                  0
#define SCU_SFSP4_1_MODE_Msk                                  (0x07UL << SCU_SFSP4_1_MODE_Pos)
#define SCU_SFSP4_1_EPD_Pos                                   3
#define SCU_SFSP4_1_EPD_Msk                                   (0x01UL << SCU_SFSP4_1_EPD_Pos)
#define SCU_SFSP4_1_EPUN_Pos                                  4
#define SCU_SFSP4_1_EPUN_Msk                                  (0x01UL << SCU_SFSP4_1_EPUN_Pos)
#define SCU_SFSP4_1_EHS_Pos                                   5
#define SCU_SFSP4_1_EHS_Msk                                   (0x01UL << SCU_SFSP4_1_EHS_Pos)
#define SCU_SFSP4_1_EZI_Pos                                   6
#define SCU_SFSP4_1_EZI_Msk                                   (0x01UL << SCU_SFSP4_1_EZI_Pos)
#define SCU_SFSP4_1_EHD_Pos                                   8
#define SCU_SFSP4_1_EHD_Msk                                   (0x03UL << SCU_SFSP4_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_2  ------------------------------------------
#define SCU_SFSP4_2_MODE_Pos                                  0
#define SCU_SFSP4_2_MODE_Msk                                  (0x07UL << SCU_SFSP4_2_MODE_Pos)
#define SCU_SFSP4_2_EPD_Pos                                   3
#define SCU_SFSP4_2_EPD_Msk                                   (0x01UL << SCU_SFSP4_2_EPD_Pos)
#define SCU_SFSP4_2_EPUN_Pos                                  4
#define SCU_SFSP4_2_EPUN_Msk                                  (0x01UL << SCU_SFSP4_2_EPUN_Pos)
#define SCU_SFSP4_2_EHS_Pos                                   5
#define SCU_SFSP4_2_EHS_Msk                                   (0x01UL << SCU_SFSP4_2_EHS_Pos)
#define SCU_SFSP4_2_EZI_Pos                                   6
#define SCU_SFSP4_2_EZI_Msk                                   (0x01UL << SCU_SFSP4_2_EZI_Pos)
#define SCU_SFSP4_2_EHD_Pos                                   8
#define SCU_SFSP4_2_EHD_Msk                                   (0x03UL << SCU_SFSP4_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_3  ------------------------------------------
#define SCU_SFSP4_3_MODE_Pos                                  0
#define SCU_SFSP4_3_MODE_Msk                                  (0x07UL << SCU_SFSP4_3_MODE_Pos)
#define SCU_SFSP4_3_EPD_Pos                                   3
#define SCU_SFSP4_3_EPD_Msk                                   (0x01UL << SCU_SFSP4_3_EPD_Pos)
#define SCU_SFSP4_3_EPUN_Pos                                  4
#define SCU_SFSP4_3_EPUN_Msk                                  (0x01UL << SCU_SFSP4_3_EPUN_Pos)
#define SCU_SFSP4_3_EHS_Pos                                   5
#define SCU_SFSP4_3_EHS_Msk                                   (0x01UL << SCU_SFSP4_3_EHS_Pos)
#define SCU_SFSP4_3_EZI_Pos                                   6
#define SCU_SFSP4_3_EZI_Msk                                   (0x01UL << SCU_SFSP4_3_EZI_Pos)
#define SCU_SFSP4_3_EHD_Pos                                   8
#define SCU_SFSP4_3_EHD_Msk                                   (0x03UL << SCU_SFSP4_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_4  ------------------------------------------
#define SCU_SFSP4_4_MODE_Pos                                  0
#define SCU_SFSP4_4_MODE_Msk                                  (0x07UL << SCU_SFSP4_4_MODE_Pos)
#define SCU_SFSP4_4_EPD_Pos                                   3
#define SCU_SFSP4_4_EPD_Msk                                   (0x01UL << SCU_SFSP4_4_EPD_Pos)
#define SCU_SFSP4_4_EPUN_Pos                                  4
#define SCU_SFSP4_4_EPUN_Msk                                  (0x01UL << SCU_SFSP4_4_EPUN_Pos)
#define SCU_SFSP4_4_EHS_Pos                                   5
#define SCU_SFSP4_4_EHS_Msk                                   (0x01UL << SCU_SFSP4_4_EHS_Pos)
#define SCU_SFSP4_4_EZI_Pos                                   6
#define SCU_SFSP4_4_EZI_Msk                                   (0x01UL << SCU_SFSP4_4_EZI_Pos)
#define SCU_SFSP4_4_EHD_Pos                                   8
#define SCU_SFSP4_4_EHD_Msk                                   (0x03UL << SCU_SFSP4_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_5  ------------------------------------------
#define SCU_SFSP4_5_MODE_Pos                                  0
#define SCU_SFSP4_5_MODE_Msk                                  (0x07UL << SCU_SFSP4_5_MODE_Pos)
#define SCU_SFSP4_5_EPD_Pos                                   3
#define SCU_SFSP4_5_EPD_Msk                                   (0x01UL << SCU_SFSP4_5_EPD_Pos)
#define SCU_SFSP4_5_EPUN_Pos                                  4
#define SCU_SFSP4_5_EPUN_Msk                                  (0x01UL << SCU_SFSP4_5_EPUN_Pos)
#define SCU_SFSP4_5_EHS_Pos                                   5
#define SCU_SFSP4_5_EHS_Msk                                   (0x01UL << SCU_SFSP4_5_EHS_Pos)
#define SCU_SFSP4_5_EZI_Pos                                   6
#define SCU_SFSP4_5_EZI_Msk                                   (0x01UL << SCU_SFSP4_5_EZI_Pos)
#define SCU_SFSP4_5_EHD_Pos                                   8
#define SCU_SFSP4_5_EHD_Msk                                   (0x03UL << SCU_SFSP4_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_6  ------------------------------------------
#define SCU_SFSP4_6_MODE_Pos                                  0
#define SCU_SFSP4_6_MODE_Msk                                  (0x07UL << SCU_SFSP4_6_MODE_Pos)
#define SCU_SFSP4_6_EPD_Pos                                   3
#define SCU_SFSP4_6_EPD_Msk                                   (0x01UL << SCU_SFSP4_6_EPD_Pos)
#define SCU_SFSP4_6_EPUN_Pos                                  4
#define SCU_SFSP4_6_EPUN_Msk                                  (0x01UL << SCU_SFSP4_6_EPUN_Pos)
#define SCU_SFSP4_6_EHS_Pos                                   5
#define SCU_SFSP4_6_EHS_Msk                                   (0x01UL << SCU_SFSP4_6_EHS_Pos)
#define SCU_SFSP4_6_EZI_Pos                                   6
#define SCU_SFSP4_6_EZI_Msk                                   (0x01UL << SCU_SFSP4_6_EZI_Pos)
#define SCU_SFSP4_6_EHD_Pos                                   8
#define SCU_SFSP4_6_EHD_Msk                                   (0x03UL << SCU_SFSP4_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_7  ------------------------------------------
#define SCU_SFSP4_7_MODE_Pos                                  0
#define SCU_SFSP4_7_MODE_Msk                                  (0x07UL << SCU_SFSP4_7_MODE_Pos)
#define SCU_SFSP4_7_EPD_Pos                                   3
#define SCU_SFSP4_7_EPD_Msk                                   (0x01UL << SCU_SFSP4_7_EPD_Pos)
#define SCU_SFSP4_7_EPUN_Pos                                  4
#define SCU_SFSP4_7_EPUN_Msk                                  (0x01UL << SCU_SFSP4_7_EPUN_Pos)
#define SCU_SFSP4_7_EHS_Pos                                   5
#define SCU_SFSP4_7_EHS_Msk                                   (0x01UL << SCU_SFSP4_7_EHS_Pos)
#define SCU_SFSP4_7_EZI_Pos                                   6
#define SCU_SFSP4_7_EZI_Msk                                   (0x01UL << SCU_SFSP4_7_EZI_Pos)
#define SCU_SFSP4_7_EHD_Pos                                   8
#define SCU_SFSP4_7_EHD_Msk                                   (0x03UL << SCU_SFSP4_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_8  ------------------------------------------
#define SCU_SFSP4_8_MODE_Pos                                  0
#define SCU_SFSP4_8_MODE_Msk                                  (0x07UL << SCU_SFSP4_8_MODE_Pos)
#define SCU_SFSP4_8_EPD_Pos                                   3
#define SCU_SFSP4_8_EPD_Msk                                   (0x01UL << SCU_SFSP4_8_EPD_Pos)
#define SCU_SFSP4_8_EPUN_Pos                                  4
#define SCU_SFSP4_8_EPUN_Msk                                  (0x01UL << SCU_SFSP4_8_EPUN_Pos)
#define SCU_SFSP4_8_EHS_Pos                                   5
#define SCU_SFSP4_8_EHS_Msk                                   (0x01UL << SCU_SFSP4_8_EHS_Pos)
#define SCU_SFSP4_8_EZI_Pos                                   6
#define SCU_SFSP4_8_EZI_Msk                                   (0x01UL << SCU_SFSP4_8_EZI_Pos)
#define SCU_SFSP4_8_EHD_Pos                                   8
#define SCU_SFSP4_8_EHD_Msk                                   (0x03UL << SCU_SFSP4_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP4_9  ------------------------------------------
#define SCU_SFSP4_9_MODE_Pos                                  0
#define SCU_SFSP4_9_MODE_Msk                                  (0x07UL << SCU_SFSP4_9_MODE_Pos)
#define SCU_SFSP4_9_EPD_Pos                                   3
#define SCU_SFSP4_9_EPD_Msk                                   (0x01UL << SCU_SFSP4_9_EPD_Pos)
#define SCU_SFSP4_9_EPUN_Pos                                  4
#define SCU_SFSP4_9_EPUN_Msk                                  (0x01UL << SCU_SFSP4_9_EPUN_Pos)
#define SCU_SFSP4_9_EHS_Pos                                   5
#define SCU_SFSP4_9_EHS_Msk                                   (0x01UL << SCU_SFSP4_9_EHS_Pos)
#define SCU_SFSP4_9_EZI_Pos                                   6
#define SCU_SFSP4_9_EZI_Msk                                   (0x01UL << SCU_SFSP4_9_EZI_Pos)
#define SCU_SFSP4_9_EHD_Pos                                   8
#define SCU_SFSP4_9_EHD_Msk                                   (0x03UL << SCU_SFSP4_9_EHD_Pos)

// --------------------------------------  SCU_SFSP4_10  ------------------------------------------
#define SCU_SFSP4_10_MODE_Pos                                 0
#define SCU_SFSP4_10_MODE_Msk                                 (0x07UL << SCU_SFSP4_10_MODE_Pos)
#define SCU_SFSP4_10_EPD_Pos                                  3
#define SCU_SFSP4_10_EPD_Msk                                  (0x01UL << SCU_SFSP4_10_EPD_Pos)
#define SCU_SFSP4_10_EPUN_Pos                                 4
#define SCU_SFSP4_10_EPUN_Msk                                 (0x01UL << SCU_SFSP4_10_EPUN_Pos)
#define SCU_SFSP4_10_EHS_Pos                                  5
#define SCU_SFSP4_10_EHS_Msk                                  (0x01UL << SCU_SFSP4_10_EHS_Pos)
#define SCU_SFSP4_10_EZI_Pos                                  6
#define SCU_SFSP4_10_EZI_Msk                                  (0x01UL << SCU_SFSP4_10_EZI_Pos)
#define SCU_SFSP4_10_EHD_Pos                                  8
#define SCU_SFSP4_10_EHD_Msk                                  (0x03UL << SCU_SFSP4_10_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_0  ------------------------------------------
#define SCU_SFSP5_0_MODE_Pos                                  0
#define SCU_SFSP5_0_MODE_Msk                                  (0x07UL << SCU_SFSP5_0_MODE_Pos)
#define SCU_SFSP5_0_EPD_Pos                                   3
#define SCU_SFSP5_0_EPD_Msk                                   (0x01UL << SCU_SFSP5_0_EPD_Pos)
#define SCU_SFSP5_0_EPUN_Pos                                  4
#define SCU_SFSP5_0_EPUN_Msk                                  (0x01UL << SCU_SFSP5_0_EPUN_Pos)
#define SCU_SFSP5_0_EHS_Pos                                   5
#define SCU_SFSP5_0_EHS_Msk                                   (0x01UL << SCU_SFSP5_0_EHS_Pos)
#define SCU_SFSP5_0_EZI_Pos                                   6
#define SCU_SFSP5_0_EZI_Msk                                   (0x01UL << SCU_SFSP5_0_EZI_Pos)
#define SCU_SFSP5_0_EHD_Pos                                   8
#define SCU_SFSP5_0_EHD_Msk                                   (0x03UL << SCU_SFSP5_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_1  ------------------------------------------
#define SCU_SFSP5_1_MODE_Pos                                  0
#define SCU_SFSP5_1_MODE_Msk                                  (0x07UL << SCU_SFSP5_1_MODE_Pos)
#define SCU_SFSP5_1_EPD_Pos                                   3
#define SCU_SFSP5_1_EPD_Msk                                   (0x01UL << SCU_SFSP5_1_EPD_Pos)
#define SCU_SFSP5_1_EPUN_Pos                                  4
#define SCU_SFSP5_1_EPUN_Msk                                  (0x01UL << SCU_SFSP5_1_EPUN_Pos)
#define SCU_SFSP5_1_EHS_Pos                                   5
#define SCU_SFSP5_1_EHS_Msk                                   (0x01UL << SCU_SFSP5_1_EHS_Pos)
#define SCU_SFSP5_1_EZI_Pos                                   6
#define SCU_SFSP5_1_EZI_Msk                                   (0x01UL << SCU_SFSP5_1_EZI_Pos)
#define SCU_SFSP5_1_EHD_Pos                                   8
#define SCU_SFSP5_1_EHD_Msk                                   (0x03UL << SCU_SFSP5_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_2  ------------------------------------------
#define SCU_SFSP5_2_MODE_Pos                                  0
#define SCU_SFSP5_2_MODE_Msk                                  (0x07UL << SCU_SFSP5_2_MODE_Pos)
#define SCU_SFSP5_2_EPD_Pos                                   3
#define SCU_SFSP5_2_EPD_Msk                                   (0x01UL << SCU_SFSP5_2_EPD_Pos)
#define SCU_SFSP5_2_EPUN_Pos                                  4
#define SCU_SFSP5_2_EPUN_Msk                                  (0x01UL << SCU_SFSP5_2_EPUN_Pos)
#define SCU_SFSP5_2_EHS_Pos                                   5
#define SCU_SFSP5_2_EHS_Msk                                   (0x01UL << SCU_SFSP5_2_EHS_Pos)
#define SCU_SFSP5_2_EZI_Pos                                   6
#define SCU_SFSP5_2_EZI_Msk                                   (0x01UL << SCU_SFSP5_2_EZI_Pos)
#define SCU_SFSP5_2_EHD_Pos                                   8
#define SCU_SFSP5_2_EHD_Msk                                   (0x03UL << SCU_SFSP5_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_3  ------------------------------------------
#define SCU_SFSP5_3_MODE_Pos                                  0
#define SCU_SFSP5_3_MODE_Msk                                  (0x07UL << SCU_SFSP5_3_MODE_Pos)
#define SCU_SFSP5_3_EPD_Pos                                   3
#define SCU_SFSP5_3_EPD_Msk                                   (0x01UL << SCU_SFSP5_3_EPD_Pos)
#define SCU_SFSP5_3_EPUN_Pos                                  4
#define SCU_SFSP5_3_EPUN_Msk                                  (0x01UL << SCU_SFSP5_3_EPUN_Pos)
#define SCU_SFSP5_3_EHS_Pos                                   5
#define SCU_SFSP5_3_EHS_Msk                                   (0x01UL << SCU_SFSP5_3_EHS_Pos)
#define SCU_SFSP5_3_EZI_Pos                                   6
#define SCU_SFSP5_3_EZI_Msk                                   (0x01UL << SCU_SFSP5_3_EZI_Pos)
#define SCU_SFSP5_3_EHD_Pos                                   8
#define SCU_SFSP5_3_EHD_Msk                                   (0x03UL << SCU_SFSP5_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_4  ------------------------------------------
#define SCU_SFSP5_4_MODE_Pos                                  0
#define SCU_SFSP5_4_MODE_Msk                                  (0x07UL << SCU_SFSP5_4_MODE_Pos)
#define SCU_SFSP5_4_EPD_Pos                                   3
#define SCU_SFSP5_4_EPD_Msk                                   (0x01UL << SCU_SFSP5_4_EPD_Pos)
#define SCU_SFSP5_4_EPUN_Pos                                  4
#define SCU_SFSP5_4_EPUN_Msk                                  (0x01UL << SCU_SFSP5_4_EPUN_Pos)
#define SCU_SFSP5_4_EHS_Pos                                   5
#define SCU_SFSP5_4_EHS_Msk                                   (0x01UL << SCU_SFSP5_4_EHS_Pos)
#define SCU_SFSP5_4_EZI_Pos                                   6
#define SCU_SFSP5_4_EZI_Msk                                   (0x01UL << SCU_SFSP5_4_EZI_Pos)
#define SCU_SFSP5_4_EHD_Pos                                   8
#define SCU_SFSP5_4_EHD_Msk                                   (0x03UL << SCU_SFSP5_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_5  ------------------------------------------
#define SCU_SFSP5_5_MODE_Pos                                  0
#define SCU_SFSP5_5_MODE_Msk                                  (0x07UL << SCU_SFSP5_5_MODE_Pos)
#define SCU_SFSP5_5_EPD_Pos                                   3
#define SCU_SFSP5_5_EPD_Msk                                   (0x01UL << SCU_SFSP5_5_EPD_Pos)
#define SCU_SFSP5_5_EPUN_Pos                                  4
#define SCU_SFSP5_5_EPUN_Msk                                  (0x01UL << SCU_SFSP5_5_EPUN_Pos)
#define SCU_SFSP5_5_EHS_Pos                                   5
#define SCU_SFSP5_5_EHS_Msk                                   (0x01UL << SCU_SFSP5_5_EHS_Pos)
#define SCU_SFSP5_5_EZI_Pos                                   6
#define SCU_SFSP5_5_EZI_Msk                                   (0x01UL << SCU_SFSP5_5_EZI_Pos)
#define SCU_SFSP5_5_EHD_Pos                                   8
#define SCU_SFSP5_5_EHD_Msk                                   (0x03UL << SCU_SFSP5_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_6  ------------------------------------------
#define SCU_SFSP5_6_MODE_Pos                                  0
#define SCU_SFSP5_6_MODE_Msk                                  (0x07UL << SCU_SFSP5_6_MODE_Pos)
#define SCU_SFSP5_6_EPD_Pos                                   3
#define SCU_SFSP5_6_EPD_Msk                                   (0x01UL << SCU_SFSP5_6_EPD_Pos)
#define SCU_SFSP5_6_EPUN_Pos                                  4
#define SCU_SFSP5_6_EPUN_Msk                                  (0x01UL << SCU_SFSP5_6_EPUN_Pos)
#define SCU_SFSP5_6_EHS_Pos                                   5
#define SCU_SFSP5_6_EHS_Msk                                   (0x01UL << SCU_SFSP5_6_EHS_Pos)
#define SCU_SFSP5_6_EZI_Pos                                   6
#define SCU_SFSP5_6_EZI_Msk                                   (0x01UL << SCU_SFSP5_6_EZI_Pos)
#define SCU_SFSP5_6_EHD_Pos                                   8
#define SCU_SFSP5_6_EHD_Msk                                   (0x03UL << SCU_SFSP5_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP5_7  ------------------------------------------
#define SCU_SFSP5_7_MODE_Pos                                  0
#define SCU_SFSP5_7_MODE_Msk                                  (0x07UL << SCU_SFSP5_7_MODE_Pos)
#define SCU_SFSP5_7_EPD_Pos                                   3
#define SCU_SFSP5_7_EPD_Msk                                   (0x01UL << SCU_SFSP5_7_EPD_Pos)
#define SCU_SFSP5_7_EPUN_Pos                                  4
#define SCU_SFSP5_7_EPUN_Msk                                  (0x01UL << SCU_SFSP5_7_EPUN_Pos)
#define SCU_SFSP5_7_EHS_Pos                                   5
#define SCU_SFSP5_7_EHS_Msk                                   (0x01UL << SCU_SFSP5_7_EHS_Pos)
#define SCU_SFSP5_7_EZI_Pos                                   6
#define SCU_SFSP5_7_EZI_Msk                                   (0x01UL << SCU_SFSP5_7_EZI_Pos)
#define SCU_SFSP5_7_EHD_Pos                                   8
#define SCU_SFSP5_7_EHD_Msk                                   (0x03UL << SCU_SFSP5_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_0  ------------------------------------------
#define SCU_SFSP6_0_MODE_Pos                                  0
#define SCU_SFSP6_0_MODE_Msk                                  (0x07UL << SCU_SFSP6_0_MODE_Pos)
#define SCU_SFSP6_0_EPD_Pos                                   3
#define SCU_SFSP6_0_EPD_Msk                                   (0x01UL << SCU_SFSP6_0_EPD_Pos)
#define SCU_SFSP6_0_EPUN_Pos                                  4
#define SCU_SFSP6_0_EPUN_Msk                                  (0x01UL << SCU_SFSP6_0_EPUN_Pos)
#define SCU_SFSP6_0_EHS_Pos                                   5
#define SCU_SFSP6_0_EHS_Msk                                   (0x01UL << SCU_SFSP6_0_EHS_Pos)
#define SCU_SFSP6_0_EZI_Pos                                   6
#define SCU_SFSP6_0_EZI_Msk                                   (0x01UL << SCU_SFSP6_0_EZI_Pos)
#define SCU_SFSP6_0_EHD_Pos                                   8
#define SCU_SFSP6_0_EHD_Msk                                   (0x03UL << SCU_SFSP6_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_1  ------------------------------------------
#define SCU_SFSP6_1_MODE_Pos                                  0
#define SCU_SFSP6_1_MODE_Msk                                  (0x07UL << SCU_SFSP6_1_MODE_Pos)
#define SCU_SFSP6_1_EPD_Pos                                   3
#define SCU_SFSP6_1_EPD_Msk                                   (0x01UL << SCU_SFSP6_1_EPD_Pos)
#define SCU_SFSP6_1_EPUN_Pos                                  4
#define SCU_SFSP6_1_EPUN_Msk                                  (0x01UL << SCU_SFSP6_1_EPUN_Pos)
#define SCU_SFSP6_1_EHS_Pos                                   5
#define SCU_SFSP6_1_EHS_Msk                                   (0x01UL << SCU_SFSP6_1_EHS_Pos)
#define SCU_SFSP6_1_EZI_Pos                                   6
#define SCU_SFSP6_1_EZI_Msk                                   (0x01UL << SCU_SFSP6_1_EZI_Pos)
#define SCU_SFSP6_1_EHD_Pos                                   8
#define SCU_SFSP6_1_EHD_Msk                                   (0x03UL << SCU_SFSP6_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_2  ------------------------------------------
#define SCU_SFSP6_2_MODE_Pos                                  0
#define SCU_SFSP6_2_MODE_Msk                                  (0x07UL << SCU_SFSP6_2_MODE_Pos)
#define SCU_SFSP6_2_EPD_Pos                                   3
#define SCU_SFSP6_2_EPD_Msk                                   (0x01UL << SCU_SFSP6_2_EPD_Pos)
#define SCU_SFSP6_2_EPUN_Pos                                  4
#define SCU_SFSP6_2_EPUN_Msk                                  (0x01UL << SCU_SFSP6_2_EPUN_Pos)
#define SCU_SFSP6_2_EHS_Pos                                   5
#define SCU_SFSP6_2_EHS_Msk                                   (0x01UL << SCU_SFSP6_2_EHS_Pos)
#define SCU_SFSP6_2_EZI_Pos                                   6
#define SCU_SFSP6_2_EZI_Msk                                   (0x01UL << SCU_SFSP6_2_EZI_Pos)
#define SCU_SFSP6_2_EHD_Pos                                   8
#define SCU_SFSP6_2_EHD_Msk                                   (0x03UL << SCU_SFSP6_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_3  ------------------------------------------
#define SCU_SFSP6_3_MODE_Pos                                  0
#define SCU_SFSP6_3_MODE_Msk                                  (0x07UL << SCU_SFSP6_3_MODE_Pos)
#define SCU_SFSP6_3_EPD_Pos                                   3
#define SCU_SFSP6_3_EPD_Msk                                   (0x01UL << SCU_SFSP6_3_EPD_Pos)
#define SCU_SFSP6_3_EPUN_Pos                                  4
#define SCU_SFSP6_3_EPUN_Msk                                  (0x01UL << SCU_SFSP6_3_EPUN_Pos)
#define SCU_SFSP6_3_EHS_Pos                                   5
#define SCU_SFSP6_3_EHS_Msk                                   (0x01UL << SCU_SFSP6_3_EHS_Pos)
#define SCU_SFSP6_3_EZI_Pos                                   6
#define SCU_SFSP6_3_EZI_Msk                                   (0x01UL << SCU_SFSP6_3_EZI_Pos)
#define SCU_SFSP6_3_EHD_Pos                                   8
#define SCU_SFSP6_3_EHD_Msk                                   (0x03UL << SCU_SFSP6_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_4  ------------------------------------------
#define SCU_SFSP6_4_MODE_Pos                                  0
#define SCU_SFSP6_4_MODE_Msk                                  (0x07UL << SCU_SFSP6_4_MODE_Pos)
#define SCU_SFSP6_4_EPD_Pos                                   3
#define SCU_SFSP6_4_EPD_Msk                                   (0x01UL << SCU_SFSP6_4_EPD_Pos)
#define SCU_SFSP6_4_EPUN_Pos                                  4
#define SCU_SFSP6_4_EPUN_Msk                                  (0x01UL << SCU_SFSP6_4_EPUN_Pos)
#define SCU_SFSP6_4_EHS_Pos                                   5
#define SCU_SFSP6_4_EHS_Msk                                   (0x01UL << SCU_SFSP6_4_EHS_Pos)
#define SCU_SFSP6_4_EZI_Pos                                   6
#define SCU_SFSP6_4_EZI_Msk                                   (0x01UL << SCU_SFSP6_4_EZI_Pos)
#define SCU_SFSP6_4_EHD_Pos                                   8
#define SCU_SFSP6_4_EHD_Msk                                   (0x03UL << SCU_SFSP6_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_5  ------------------------------------------
#define SCU_SFSP6_5_MODE_Pos                                  0
#define SCU_SFSP6_5_MODE_Msk                                  (0x07UL << SCU_SFSP6_5_MODE_Pos)
#define SCU_SFSP6_5_EPD_Pos                                   3
#define SCU_SFSP6_5_EPD_Msk                                   (0x01UL << SCU_SFSP6_5_EPD_Pos)
#define SCU_SFSP6_5_EPUN_Pos                                  4
#define SCU_SFSP6_5_EPUN_Msk                                  (0x01UL << SCU_SFSP6_5_EPUN_Pos)
#define SCU_SFSP6_5_EHS_Pos                                   5
#define SCU_SFSP6_5_EHS_Msk                                   (0x01UL << SCU_SFSP6_5_EHS_Pos)
#define SCU_SFSP6_5_EZI_Pos                                   6
#define SCU_SFSP6_5_EZI_Msk                                   (0x01UL << SCU_SFSP6_5_EZI_Pos)
#define SCU_SFSP6_5_EHD_Pos                                   8
#define SCU_SFSP6_5_EHD_Msk                                   (0x03UL << SCU_SFSP6_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_6  ------------------------------------------
#define SCU_SFSP6_6_MODE_Pos                                  0
#define SCU_SFSP6_6_MODE_Msk                                  (0x07UL << SCU_SFSP6_6_MODE_Pos)
#define SCU_SFSP6_6_EPD_Pos                                   3
#define SCU_SFSP6_6_EPD_Msk                                   (0x01UL << SCU_SFSP6_6_EPD_Pos)
#define SCU_SFSP6_6_EPUN_Pos                                  4
#define SCU_SFSP6_6_EPUN_Msk                                  (0x01UL << SCU_SFSP6_6_EPUN_Pos)
#define SCU_SFSP6_6_EHS_Pos                                   5
#define SCU_SFSP6_6_EHS_Msk                                   (0x01UL << SCU_SFSP6_6_EHS_Pos)
#define SCU_SFSP6_6_EZI_Pos                                   6
#define SCU_SFSP6_6_EZI_Msk                                   (0x01UL << SCU_SFSP6_6_EZI_Pos)
#define SCU_SFSP6_6_EHD_Pos                                   8
#define SCU_SFSP6_6_EHD_Msk                                   (0x03UL << SCU_SFSP6_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_7  ------------------------------------------
#define SCU_SFSP6_7_MODE_Pos                                  0
#define SCU_SFSP6_7_MODE_Msk                                  (0x07UL << SCU_SFSP6_7_MODE_Pos)
#define SCU_SFSP6_7_EPD_Pos                                   3
#define SCU_SFSP6_7_EPD_Msk                                   (0x01UL << SCU_SFSP6_7_EPD_Pos)
#define SCU_SFSP6_7_EPUN_Pos                                  4
#define SCU_SFSP6_7_EPUN_Msk                                  (0x01UL << SCU_SFSP6_7_EPUN_Pos)
#define SCU_SFSP6_7_EHS_Pos                                   5
#define SCU_SFSP6_7_EHS_Msk                                   (0x01UL << SCU_SFSP6_7_EHS_Pos)
#define SCU_SFSP6_7_EZI_Pos                                   6
#define SCU_SFSP6_7_EZI_Msk                                   (0x01UL << SCU_SFSP6_7_EZI_Pos)
#define SCU_SFSP6_7_EHD_Pos                                   8
#define SCU_SFSP6_7_EHD_Msk                                   (0x03UL << SCU_SFSP6_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_8  ------------------------------------------
#define SCU_SFSP6_8_MODE_Pos                                  0
#define SCU_SFSP6_8_MODE_Msk                                  (0x07UL << SCU_SFSP6_8_MODE_Pos)
#define SCU_SFSP6_8_EPD_Pos                                   3
#define SCU_SFSP6_8_EPD_Msk                                   (0x01UL << SCU_SFSP6_8_EPD_Pos)
#define SCU_SFSP6_8_EPUN_Pos                                  4
#define SCU_SFSP6_8_EPUN_Msk                                  (0x01UL << SCU_SFSP6_8_EPUN_Pos)
#define SCU_SFSP6_8_EHS_Pos                                   5
#define SCU_SFSP6_8_EHS_Msk                                   (0x01UL << SCU_SFSP6_8_EHS_Pos)
#define SCU_SFSP6_8_EZI_Pos                                   6
#define SCU_SFSP6_8_EZI_Msk                                   (0x01UL << SCU_SFSP6_8_EZI_Pos)
#define SCU_SFSP6_8_EHD_Pos                                   8
#define SCU_SFSP6_8_EHD_Msk                                   (0x03UL << SCU_SFSP6_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP6_9  ------------------------------------------
#define SCU_SFSP6_9_MODE_Pos                                  0
#define SCU_SFSP6_9_MODE_Msk                                  (0x07UL << SCU_SFSP6_9_MODE_Pos)
#define SCU_SFSP6_9_EPD_Pos                                   3
#define SCU_SFSP6_9_EPD_Msk                                   (0x01UL << SCU_SFSP6_9_EPD_Pos)
#define SCU_SFSP6_9_EPUN_Pos                                  4
#define SCU_SFSP6_9_EPUN_Msk                                  (0x01UL << SCU_SFSP6_9_EPUN_Pos)
#define SCU_SFSP6_9_EHS_Pos                                   5
#define SCU_SFSP6_9_EHS_Msk                                   (0x01UL << SCU_SFSP6_9_EHS_Pos)
#define SCU_SFSP6_9_EZI_Pos                                   6
#define SCU_SFSP6_9_EZI_Msk                                   (0x01UL << SCU_SFSP6_9_EZI_Pos)
#define SCU_SFSP6_9_EHD_Pos                                   8
#define SCU_SFSP6_9_EHD_Msk                                   (0x03UL << SCU_SFSP6_9_EHD_Pos)

// --------------------------------------  SCU_SFSP6_10  ------------------------------------------
#define SCU_SFSP6_10_MODE_Pos                                 0
#define SCU_SFSP6_10_MODE_Msk                                 (0x07UL << SCU_SFSP6_10_MODE_Pos)
#define SCU_SFSP6_10_EPD_Pos                                  3
#define SCU_SFSP6_10_EPD_Msk                                  (0x01UL << SCU_SFSP6_10_EPD_Pos)
#define SCU_SFSP6_10_EPUN_Pos                                 4
#define SCU_SFSP6_10_EPUN_Msk                                 (0x01UL << SCU_SFSP6_10_EPUN_Pos)
#define SCU_SFSP6_10_EHS_Pos                                  5
#define SCU_SFSP6_10_EHS_Msk                                  (0x01UL << SCU_SFSP6_10_EHS_Pos)
#define SCU_SFSP6_10_EZI_Pos                                  6
#define SCU_SFSP6_10_EZI_Msk                                  (0x01UL << SCU_SFSP6_10_EZI_Pos)
#define SCU_SFSP6_10_EHD_Pos                                  8
#define SCU_SFSP6_10_EHD_Msk                                  (0x03UL << SCU_SFSP6_10_EHD_Pos)

// --------------------------------------  SCU_SFSP6_11  ------------------------------------------
#define SCU_SFSP6_11_MODE_Pos                                 0
#define SCU_SFSP6_11_MODE_Msk                                 (0x07UL << SCU_SFSP6_11_MODE_Pos)
#define SCU_SFSP6_11_EPD_Pos                                  3
#define SCU_SFSP6_11_EPD_Msk                                  (0x01UL << SCU_SFSP6_11_EPD_Pos)
#define SCU_SFSP6_11_EPUN_Pos                                 4
#define SCU_SFSP6_11_EPUN_Msk                                 (0x01UL << SCU_SFSP6_11_EPUN_Pos)
#define SCU_SFSP6_11_EHS_Pos                                  5
#define SCU_SFSP6_11_EHS_Msk                                  (0x01UL << SCU_SFSP6_11_EHS_Pos)
#define SCU_SFSP6_11_EZI_Pos                                  6
#define SCU_SFSP6_11_EZI_Msk                                  (0x01UL << SCU_SFSP6_11_EZI_Pos)
#define SCU_SFSP6_11_EHD_Pos                                  8
#define SCU_SFSP6_11_EHD_Msk                                  (0x03UL << SCU_SFSP6_11_EHD_Pos)

// --------------------------------------  SCU_SFSP6_12  ------------------------------------------
#define SCU_SFSP6_12_MODE_Pos                                 0
#define SCU_SFSP6_12_MODE_Msk                                 (0x07UL << SCU_SFSP6_12_MODE_Pos)
#define SCU_SFSP6_12_EPD_Pos                                  3
#define SCU_SFSP6_12_EPD_Msk                                  (0x01UL << SCU_SFSP6_12_EPD_Pos)
#define SCU_SFSP6_12_EPUN_Pos                                 4
#define SCU_SFSP6_12_EPUN_Msk                                 (0x01UL << SCU_SFSP6_12_EPUN_Pos)
#define SCU_SFSP6_12_EHS_Pos                                  5
#define SCU_SFSP6_12_EHS_Msk                                  (0x01UL << SCU_SFSP6_12_EHS_Pos)
#define SCU_SFSP6_12_EZI_Pos                                  6
#define SCU_SFSP6_12_EZI_Msk                                  (0x01UL << SCU_SFSP6_12_EZI_Pos)
#define SCU_SFSP6_12_EHD_Pos                                  8
#define SCU_SFSP6_12_EHD_Msk                                  (0x03UL << SCU_SFSP6_12_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_0  ------------------------------------------
#define SCU_SFSP7_0_MODE_Pos                                  0
#define SCU_SFSP7_0_MODE_Msk                                  (0x07UL << SCU_SFSP7_0_MODE_Pos)
#define SCU_SFSP7_0_EPD_Pos                                   3
#define SCU_SFSP7_0_EPD_Msk                                   (0x01UL << SCU_SFSP7_0_EPD_Pos)
#define SCU_SFSP7_0_EPUN_Pos                                  4
#define SCU_SFSP7_0_EPUN_Msk                                  (0x01UL << SCU_SFSP7_0_EPUN_Pos)
#define SCU_SFSP7_0_EHS_Pos                                   5
#define SCU_SFSP7_0_EHS_Msk                                   (0x01UL << SCU_SFSP7_0_EHS_Pos)
#define SCU_SFSP7_0_EZI_Pos                                   6
#define SCU_SFSP7_0_EZI_Msk                                   (0x01UL << SCU_SFSP7_0_EZI_Pos)
#define SCU_SFSP7_0_EHD_Pos                                   8
#define SCU_SFSP7_0_EHD_Msk                                   (0x03UL << SCU_SFSP7_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_1  ------------------------------------------
#define SCU_SFSP7_1_MODE_Pos                                  0
#define SCU_SFSP7_1_MODE_Msk                                  (0x07UL << SCU_SFSP7_1_MODE_Pos)
#define SCU_SFSP7_1_EPD_Pos                                   3
#define SCU_SFSP7_1_EPD_Msk                                   (0x01UL << SCU_SFSP7_1_EPD_Pos)
#define SCU_SFSP7_1_EPUN_Pos                                  4
#define SCU_SFSP7_1_EPUN_Msk                                  (0x01UL << SCU_SFSP7_1_EPUN_Pos)
#define SCU_SFSP7_1_EHS_Pos                                   5
#define SCU_SFSP7_1_EHS_Msk                                   (0x01UL << SCU_SFSP7_1_EHS_Pos)
#define SCU_SFSP7_1_EZI_Pos                                   6
#define SCU_SFSP7_1_EZI_Msk                                   (0x01UL << SCU_SFSP7_1_EZI_Pos)
#define SCU_SFSP7_1_EHD_Pos                                   8
#define SCU_SFSP7_1_EHD_Msk                                   (0x03UL << SCU_SFSP7_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_2  ------------------------------------------
#define SCU_SFSP7_2_MODE_Pos                                  0
#define SCU_SFSP7_2_MODE_Msk                                  (0x07UL << SCU_SFSP7_2_MODE_Pos)
#define SCU_SFSP7_2_EPD_Pos                                   3
#define SCU_SFSP7_2_EPD_Msk                                   (0x01UL << SCU_SFSP7_2_EPD_Pos)
#define SCU_SFSP7_2_EPUN_Pos                                  4
#define SCU_SFSP7_2_EPUN_Msk                                  (0x01UL << SCU_SFSP7_2_EPUN_Pos)
#define SCU_SFSP7_2_EHS_Pos                                   5
#define SCU_SFSP7_2_EHS_Msk                                   (0x01UL << SCU_SFSP7_2_EHS_Pos)
#define SCU_SFSP7_2_EZI_Pos                                   6
#define SCU_SFSP7_2_EZI_Msk                                   (0x01UL << SCU_SFSP7_2_EZI_Pos)
#define SCU_SFSP7_2_EHD_Pos                                   8
#define SCU_SFSP7_2_EHD_Msk                                   (0x03UL << SCU_SFSP7_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_3  ------------------------------------------
#define SCU_SFSP7_3_MODE_Pos                                  0
#define SCU_SFSP7_3_MODE_Msk                                  (0x07UL << SCU_SFSP7_3_MODE_Pos)
#define SCU_SFSP7_3_EPD_Pos                                   3
#define SCU_SFSP7_3_EPD_Msk                                   (0x01UL << SCU_SFSP7_3_EPD_Pos)
#define SCU_SFSP7_3_EPUN_Pos                                  4
#define SCU_SFSP7_3_EPUN_Msk                                  (0x01UL << SCU_SFSP7_3_EPUN_Pos)
#define SCU_SFSP7_3_EHS_Pos                                   5
#define SCU_SFSP7_3_EHS_Msk                                   (0x01UL << SCU_SFSP7_3_EHS_Pos)
#define SCU_SFSP7_3_EZI_Pos                                   6
#define SCU_SFSP7_3_EZI_Msk                                   (0x01UL << SCU_SFSP7_3_EZI_Pos)
#define SCU_SFSP7_3_EHD_Pos                                   8
#define SCU_SFSP7_3_EHD_Msk                                   (0x03UL << SCU_SFSP7_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_4  ------------------------------------------
#define SCU_SFSP7_4_MODE_Pos                                  0
#define SCU_SFSP7_4_MODE_Msk                                  (0x07UL << SCU_SFSP7_4_MODE_Pos)
#define SCU_SFSP7_4_EPD_Pos                                   3
#define SCU_SFSP7_4_EPD_Msk                                   (0x01UL << SCU_SFSP7_4_EPD_Pos)
#define SCU_SFSP7_4_EPUN_Pos                                  4
#define SCU_SFSP7_4_EPUN_Msk                                  (0x01UL << SCU_SFSP7_4_EPUN_Pos)
#define SCU_SFSP7_4_EHS_Pos                                   5
#define SCU_SFSP7_4_EHS_Msk                                   (0x01UL << SCU_SFSP7_4_EHS_Pos)
#define SCU_SFSP7_4_EZI_Pos                                   6
#define SCU_SFSP7_4_EZI_Msk                                   (0x01UL << SCU_SFSP7_4_EZI_Pos)
#define SCU_SFSP7_4_EHD_Pos                                   8
#define SCU_SFSP7_4_EHD_Msk                                   (0x03UL << SCU_SFSP7_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_5  ------------------------------------------
#define SCU_SFSP7_5_MODE_Pos                                  0
#define SCU_SFSP7_5_MODE_Msk                                  (0x07UL << SCU_SFSP7_5_MODE_Pos)
#define SCU_SFSP7_5_EPD_Pos                                   3
#define SCU_SFSP7_5_EPD_Msk                                   (0x01UL << SCU_SFSP7_5_EPD_Pos)
#define SCU_SFSP7_5_EPUN_Pos                                  4
#define SCU_SFSP7_5_EPUN_Msk                                  (0x01UL << SCU_SFSP7_5_EPUN_Pos)
#define SCU_SFSP7_5_EHS_Pos                                   5
#define SCU_SFSP7_5_EHS_Msk                                   (0x01UL << SCU_SFSP7_5_EHS_Pos)
#define SCU_SFSP7_5_EZI_Pos                                   6
#define SCU_SFSP7_5_EZI_Msk                                   (0x01UL << SCU_SFSP7_5_EZI_Pos)
#define SCU_SFSP7_5_EHD_Pos                                   8
#define SCU_SFSP7_5_EHD_Msk                                   (0x03UL << SCU_SFSP7_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_6  ------------------------------------------
#define SCU_SFSP7_6_MODE_Pos                                  0
#define SCU_SFSP7_6_MODE_Msk                                  (0x07UL << SCU_SFSP7_6_MODE_Pos)
#define SCU_SFSP7_6_EPD_Pos                                   3
#define SCU_SFSP7_6_EPD_Msk                                   (0x01UL << SCU_SFSP7_6_EPD_Pos)
#define SCU_SFSP7_6_EPUN_Pos                                  4
#define SCU_SFSP7_6_EPUN_Msk                                  (0x01UL << SCU_SFSP7_6_EPUN_Pos)
#define SCU_SFSP7_6_EHS_Pos                                   5
#define SCU_SFSP7_6_EHS_Msk                                   (0x01UL << SCU_SFSP7_6_EHS_Pos)
#define SCU_SFSP7_6_EZI_Pos                                   6
#define SCU_SFSP7_6_EZI_Msk                                   (0x01UL << SCU_SFSP7_6_EZI_Pos)
#define SCU_SFSP7_6_EHD_Pos                                   8
#define SCU_SFSP7_6_EHD_Msk                                   (0x03UL << SCU_SFSP7_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP7_7  ------------------------------------------
#define SCU_SFSP7_7_MODE_Pos                                  0
#define SCU_SFSP7_7_MODE_Msk                                  (0x07UL << SCU_SFSP7_7_MODE_Pos)
#define SCU_SFSP7_7_EPD_Pos                                   3
#define SCU_SFSP7_7_EPD_Msk                                   (0x01UL << SCU_SFSP7_7_EPD_Pos)
#define SCU_SFSP7_7_EPUN_Pos                                  4
#define SCU_SFSP7_7_EPUN_Msk                                  (0x01UL << SCU_SFSP7_7_EPUN_Pos)
#define SCU_SFSP7_7_EHS_Pos                                   5
#define SCU_SFSP7_7_EHS_Msk                                   (0x01UL << SCU_SFSP7_7_EHS_Pos)
#define SCU_SFSP7_7_EZI_Pos                                   6
#define SCU_SFSP7_7_EZI_Msk                                   (0x01UL << SCU_SFSP7_7_EZI_Pos)
#define SCU_SFSP7_7_EHD_Pos                                   8
#define SCU_SFSP7_7_EHD_Msk                                   (0x03UL << SCU_SFSP7_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_0  ------------------------------------------
#define SCU_SFSP8_0_MODE_Pos                                  0
#define SCU_SFSP8_0_MODE_Msk                                  (0x07UL << SCU_SFSP8_0_MODE_Pos)
#define SCU_SFSP8_0_EPD_Pos                                   3
#define SCU_SFSP8_0_EPD_Msk                                   (0x01UL << SCU_SFSP8_0_EPD_Pos)
#define SCU_SFSP8_0_EPUN_Pos                                  4
#define SCU_SFSP8_0_EPUN_Msk                                  (0x01UL << SCU_SFSP8_0_EPUN_Pos)
#define SCU_SFSP8_0_EHS_Pos                                   5
#define SCU_SFSP8_0_EHS_Msk                                   (0x01UL << SCU_SFSP8_0_EHS_Pos)
#define SCU_SFSP8_0_EZI_Pos                                   6
#define SCU_SFSP8_0_EZI_Msk                                   (0x01UL << SCU_SFSP8_0_EZI_Pos)
#define SCU_SFSP8_0_EHD_Pos                                   8
#define SCU_SFSP8_0_EHD_Msk                                   (0x03UL << SCU_SFSP8_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_1  ------------------------------------------
#define SCU_SFSP8_1_MODE_Pos                                  0
#define SCU_SFSP8_1_MODE_Msk                                  (0x07UL << SCU_SFSP8_1_MODE_Pos)
#define SCU_SFSP8_1_EPD_Pos                                   3
#define SCU_SFSP8_1_EPD_Msk                                   (0x01UL << SCU_SFSP8_1_EPD_Pos)
#define SCU_SFSP8_1_EPUN_Pos                                  4
#define SCU_SFSP8_1_EPUN_Msk                                  (0x01UL << SCU_SFSP8_1_EPUN_Pos)
#define SCU_SFSP8_1_EHS_Pos                                   5
#define SCU_SFSP8_1_EHS_Msk                                   (0x01UL << SCU_SFSP8_1_EHS_Pos)
#define SCU_SFSP8_1_EZI_Pos                                   6
#define SCU_SFSP8_1_EZI_Msk                                   (0x01UL << SCU_SFSP8_1_EZI_Pos)
#define SCU_SFSP8_1_EHD_Pos                                   8
#define SCU_SFSP8_1_EHD_Msk                                   (0x03UL << SCU_SFSP8_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_2  ------------------------------------------
#define SCU_SFSP8_2_MODE_Pos                                  0
#define SCU_SFSP8_2_MODE_Msk                                  (0x07UL << SCU_SFSP8_2_MODE_Pos)
#define SCU_SFSP8_2_EPD_Pos                                   3
#define SCU_SFSP8_2_EPD_Msk                                   (0x01UL << SCU_SFSP8_2_EPD_Pos)
#define SCU_SFSP8_2_EPUN_Pos                                  4
#define SCU_SFSP8_2_EPUN_Msk                                  (0x01UL << SCU_SFSP8_2_EPUN_Pos)
#define SCU_SFSP8_2_EHS_Pos                                   5
#define SCU_SFSP8_2_EHS_Msk                                   (0x01UL << SCU_SFSP8_2_EHS_Pos)
#define SCU_SFSP8_2_EZI_Pos                                   6
#define SCU_SFSP8_2_EZI_Msk                                   (0x01UL << SCU_SFSP8_2_EZI_Pos)
#define SCU_SFSP8_2_EHD_Pos                                   8
#define SCU_SFSP8_2_EHD_Msk                                   (0x03UL << SCU_SFSP8_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_3  ------------------------------------------
#define SCU_SFSP8_3_MODE_Pos                                  0
#define SCU_SFSP8_3_MODE_Msk                                  (0x07UL << SCU_SFSP8_3_MODE_Pos)
#define SCU_SFSP8_3_EPD_Pos                                   3
#define SCU_SFSP8_3_EPD_Msk                                   (0x01UL << SCU_SFSP8_3_EPD_Pos)
#define SCU_SFSP8_3_EPUN_Pos                                  4
#define SCU_SFSP8_3_EPUN_Msk                                  (0x01UL << SCU_SFSP8_3_EPUN_Pos)
#define SCU_SFSP8_3_EHS_Pos                                   5
#define SCU_SFSP8_3_EHS_Msk                                   (0x01UL << SCU_SFSP8_3_EHS_Pos)
#define SCU_SFSP8_3_EZI_Pos                                   6
#define SCU_SFSP8_3_EZI_Msk                                   (0x01UL << SCU_SFSP8_3_EZI_Pos)
#define SCU_SFSP8_3_EHD_Pos                                   8
#define SCU_SFSP8_3_EHD_Msk                                   (0x03UL << SCU_SFSP8_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_4  ------------------------------------------
#define SCU_SFSP8_4_MODE_Pos                                  0
#define SCU_SFSP8_4_MODE_Msk                                  (0x07UL << SCU_SFSP8_4_MODE_Pos)
#define SCU_SFSP8_4_EPD_Pos                                   3
#define SCU_SFSP8_4_EPD_Msk                                   (0x01UL << SCU_SFSP8_4_EPD_Pos)
#define SCU_SFSP8_4_EPUN_Pos                                  4
#define SCU_SFSP8_4_EPUN_Msk                                  (0x01UL << SCU_SFSP8_4_EPUN_Pos)
#define SCU_SFSP8_4_EHS_Pos                                   5
#define SCU_SFSP8_4_EHS_Msk                                   (0x01UL << SCU_SFSP8_4_EHS_Pos)
#define SCU_SFSP8_4_EZI_Pos                                   6
#define SCU_SFSP8_4_EZI_Msk                                   (0x01UL << SCU_SFSP8_4_EZI_Pos)
#define SCU_SFSP8_4_EHD_Pos                                   8
#define SCU_SFSP8_4_EHD_Msk                                   (0x03UL << SCU_SFSP8_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_5  ------------------------------------------
#define SCU_SFSP8_5_MODE_Pos                                  0
#define SCU_SFSP8_5_MODE_Msk                                  (0x07UL << SCU_SFSP8_5_MODE_Pos)
#define SCU_SFSP8_5_EPD_Pos                                   3
#define SCU_SFSP8_5_EPD_Msk                                   (0x01UL << SCU_SFSP8_5_EPD_Pos)
#define SCU_SFSP8_5_EPUN_Pos                                  4
#define SCU_SFSP8_5_EPUN_Msk                                  (0x01UL << SCU_SFSP8_5_EPUN_Pos)
#define SCU_SFSP8_5_EHS_Pos                                   5
#define SCU_SFSP8_5_EHS_Msk                                   (0x01UL << SCU_SFSP8_5_EHS_Pos)
#define SCU_SFSP8_5_EZI_Pos                                   6
#define SCU_SFSP8_5_EZI_Msk                                   (0x01UL << SCU_SFSP8_5_EZI_Pos)
#define SCU_SFSP8_5_EHD_Pos                                   8
#define SCU_SFSP8_5_EHD_Msk                                   (0x03UL << SCU_SFSP8_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_6  ------------------------------------------
#define SCU_SFSP8_6_MODE_Pos                                  0
#define SCU_SFSP8_6_MODE_Msk                                  (0x07UL << SCU_SFSP8_6_MODE_Pos)
#define SCU_SFSP8_6_EPD_Pos                                   3
#define SCU_SFSP8_6_EPD_Msk                                   (0x01UL << SCU_SFSP8_6_EPD_Pos)
#define SCU_SFSP8_6_EPUN_Pos                                  4
#define SCU_SFSP8_6_EPUN_Msk                                  (0x01UL << SCU_SFSP8_6_EPUN_Pos)
#define SCU_SFSP8_6_EHS_Pos                                   5
#define SCU_SFSP8_6_EHS_Msk                                   (0x01UL << SCU_SFSP8_6_EHS_Pos)
#define SCU_SFSP8_6_EZI_Pos                                   6
#define SCU_SFSP8_6_EZI_Msk                                   (0x01UL << SCU_SFSP8_6_EZI_Pos)
#define SCU_SFSP8_6_EHD_Pos                                   8
#define SCU_SFSP8_6_EHD_Msk                                   (0x03UL << SCU_SFSP8_6_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_7  ------------------------------------------
#define SCU_SFSP8_7_MODE_Pos                                  0
#define SCU_SFSP8_7_MODE_Msk                                  (0x07UL << SCU_SFSP8_7_MODE_Pos)
#define SCU_SFSP8_7_EPD_Pos                                   3
#define SCU_SFSP8_7_EPD_Msk                                   (0x01UL << SCU_SFSP8_7_EPD_Pos)
#define SCU_SFSP8_7_EPUN_Pos                                  4
#define SCU_SFSP8_7_EPUN_Msk                                  (0x01UL << SCU_SFSP8_7_EPUN_Pos)
#define SCU_SFSP8_7_EHS_Pos                                   5
#define SCU_SFSP8_7_EHS_Msk                                   (0x01UL << SCU_SFSP8_7_EHS_Pos)
#define SCU_SFSP8_7_EZI_Pos                                   6
#define SCU_SFSP8_7_EZI_Msk                                   (0x01UL << SCU_SFSP8_7_EZI_Pos)
#define SCU_SFSP8_7_EHD_Pos                                   8
#define SCU_SFSP8_7_EHD_Msk                                   (0x03UL << SCU_SFSP8_7_EHD_Pos)

// ---------------------------------------  SCU_SFSP8_8  ------------------------------------------
#define SCU_SFSP8_8_MODE_Pos                                  0
#define SCU_SFSP8_8_MODE_Msk                                  (0x07UL << SCU_SFSP8_8_MODE_Pos)
#define SCU_SFSP8_8_EPD_Pos                                   3
#define SCU_SFSP8_8_EPD_Msk                                   (0x01UL << SCU_SFSP8_8_EPD_Pos)
#define SCU_SFSP8_8_EPUN_Pos                                  4
#define SCU_SFSP8_8_EPUN_Msk                                  (0x01UL << SCU_SFSP8_8_EPUN_Pos)
#define SCU_SFSP8_8_EHS_Pos                                   5
#define SCU_SFSP8_8_EHS_Msk                                   (0x01UL << SCU_SFSP8_8_EHS_Pos)
#define SCU_SFSP8_8_EZI_Pos                                   6
#define SCU_SFSP8_8_EZI_Msk                                   (0x01UL << SCU_SFSP8_8_EZI_Pos)
#define SCU_SFSP8_8_EHD_Pos                                   8
#define SCU_SFSP8_8_EHD_Msk                                   (0x03UL << SCU_SFSP8_8_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_0  ------------------------------------------
#define SCU_SFSP9_0_MODE_Pos                                  0
#define SCU_SFSP9_0_MODE_Msk                                  (0x07UL << SCU_SFSP9_0_MODE_Pos)
#define SCU_SFSP9_0_EPD_Pos                                   3
#define SCU_SFSP9_0_EPD_Msk                                   (0x01UL << SCU_SFSP9_0_EPD_Pos)
#define SCU_SFSP9_0_EPUN_Pos                                  4
#define SCU_SFSP9_0_EPUN_Msk                                  (0x01UL << SCU_SFSP9_0_EPUN_Pos)
#define SCU_SFSP9_0_EHS_Pos                                   5
#define SCU_SFSP9_0_EHS_Msk                                   (0x01UL << SCU_SFSP9_0_EHS_Pos)
#define SCU_SFSP9_0_EZI_Pos                                   6
#define SCU_SFSP9_0_EZI_Msk                                   (0x01UL << SCU_SFSP9_0_EZI_Pos)
#define SCU_SFSP9_0_EHD_Pos                                   8
#define SCU_SFSP9_0_EHD_Msk                                   (0x03UL << SCU_SFSP9_0_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_1  ------------------------------------------
#define SCU_SFSP9_1_MODE_Pos                                  0
#define SCU_SFSP9_1_MODE_Msk                                  (0x07UL << SCU_SFSP9_1_MODE_Pos)
#define SCU_SFSP9_1_EPD_Pos                                   3
#define SCU_SFSP9_1_EPD_Msk                                   (0x01UL << SCU_SFSP9_1_EPD_Pos)
#define SCU_SFSP9_1_EPUN_Pos                                  4
#define SCU_SFSP9_1_EPUN_Msk                                  (0x01UL << SCU_SFSP9_1_EPUN_Pos)
#define SCU_SFSP9_1_EHS_Pos                                   5
#define SCU_SFSP9_1_EHS_Msk                                   (0x01UL << SCU_SFSP9_1_EHS_Pos)
#define SCU_SFSP9_1_EZI_Pos                                   6
#define SCU_SFSP9_1_EZI_Msk                                   (0x01UL << SCU_SFSP9_1_EZI_Pos)
#define SCU_SFSP9_1_EHD_Pos                                   8
#define SCU_SFSP9_1_EHD_Msk                                   (0x03UL << SCU_SFSP9_1_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_2  ------------------------------------------
#define SCU_SFSP9_2_MODE_Pos                                  0
#define SCU_SFSP9_2_MODE_Msk                                  (0x07UL << SCU_SFSP9_2_MODE_Pos)
#define SCU_SFSP9_2_EPD_Pos                                   3
#define SCU_SFSP9_2_EPD_Msk                                   (0x01UL << SCU_SFSP9_2_EPD_Pos)
#define SCU_SFSP9_2_EPUN_Pos                                  4
#define SCU_SFSP9_2_EPUN_Msk                                  (0x01UL << SCU_SFSP9_2_EPUN_Pos)
#define SCU_SFSP9_2_EHS_Pos                                   5
#define SCU_SFSP9_2_EHS_Msk                                   (0x01UL << SCU_SFSP9_2_EHS_Pos)
#define SCU_SFSP9_2_EZI_Pos                                   6
#define SCU_SFSP9_2_EZI_Msk                                   (0x01UL << SCU_SFSP9_2_EZI_Pos)
#define SCU_SFSP9_2_EHD_Pos                                   8
#define SCU_SFSP9_2_EHD_Msk                                   (0x03UL << SCU_SFSP9_2_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_3  ------------------------------------------
#define SCU_SFSP9_3_MODE_Pos                                  0
#define SCU_SFSP9_3_MODE_Msk                                  (0x07UL << SCU_SFSP9_3_MODE_Pos)
#define SCU_SFSP9_3_EPD_Pos                                   3
#define SCU_SFSP9_3_EPD_Msk                                   (0x01UL << SCU_SFSP9_3_EPD_Pos)
#define SCU_SFSP9_3_EPUN_Pos                                  4
#define SCU_SFSP9_3_EPUN_Msk                                  (0x01UL << SCU_SFSP9_3_EPUN_Pos)
#define SCU_SFSP9_3_EHS_Pos                                   5
#define SCU_SFSP9_3_EHS_Msk                                   (0x01UL << SCU_SFSP9_3_EHS_Pos)
#define SCU_SFSP9_3_EZI_Pos                                   6
#define SCU_SFSP9_3_EZI_Msk                                   (0x01UL << SCU_SFSP9_3_EZI_Pos)
#define SCU_SFSP9_3_EHD_Pos                                   8
#define SCU_SFSP9_3_EHD_Msk                                   (0x03UL << SCU_SFSP9_3_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_4  ------------------------------------------
#define SCU_SFSP9_4_MODE_Pos                                  0
#define SCU_SFSP9_4_MODE_Msk                                  (0x07UL << SCU_SFSP9_4_MODE_Pos)
#define SCU_SFSP9_4_EPD_Pos                                   3
#define SCU_SFSP9_4_EPD_Msk                                   (0x01UL << SCU_SFSP9_4_EPD_Pos)
#define SCU_SFSP9_4_EPUN_Pos                                  4
#define SCU_SFSP9_4_EPUN_Msk                                  (0x01UL << SCU_SFSP9_4_EPUN_Pos)
#define SCU_SFSP9_4_EHS_Pos                                   5
#define SCU_SFSP9_4_EHS_Msk                                   (0x01UL << SCU_SFSP9_4_EHS_Pos)
#define SCU_SFSP9_4_EZI_Pos                                   6
#define SCU_SFSP9_4_EZI_Msk                                   (0x01UL << SCU_SFSP9_4_EZI_Pos)
#define SCU_SFSP9_4_EHD_Pos                                   8
#define SCU_SFSP9_4_EHD_Msk                                   (0x03UL << SCU_SFSP9_4_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_5  ------------------------------------------
#define SCU_SFSP9_5_MODE_Pos                                  0
#define SCU_SFSP9_5_MODE_Msk                                  (0x07UL << SCU_SFSP9_5_MODE_Pos)
#define SCU_SFSP9_5_EPD_Pos                                   3
#define SCU_SFSP9_5_EPD_Msk                                   (0x01UL << SCU_SFSP9_5_EPD_Pos)
#define SCU_SFSP9_5_EPUN_Pos                                  4
#define SCU_SFSP9_5_EPUN_Msk                                  (0x01UL << SCU_SFSP9_5_EPUN_Pos)
#define SCU_SFSP9_5_EHS_Pos                                   5
#define SCU_SFSP9_5_EHS_Msk                                   (0x01UL << SCU_SFSP9_5_EHS_Pos)
#define SCU_SFSP9_5_EZI_Pos                                   6
#define SCU_SFSP9_5_EZI_Msk                                   (0x01UL << SCU_SFSP9_5_EZI_Pos)
#define SCU_SFSP9_5_EHD_Pos                                   8
#define SCU_SFSP9_5_EHD_Msk                                   (0x03UL << SCU_SFSP9_5_EHD_Pos)

// ---------------------------------------  SCU_SFSP9_6  ------------------------------------------
#define SCU_SFSP9_6_MODE_Pos                                  0
#define SCU_SFSP9_6_MODE_Msk                                  (0x07UL << SCU_SFSP9_6_MODE_Pos)
#define SCU_SFSP9_6_EPD_Pos                                   3
#define SCU_SFSP9_6_EPD_Msk                                   (0x01UL << SCU_SFSP9_6_EPD_Pos)
#define SCU_SFSP9_6_EPUN_Pos                                  4
#define SCU_SFSP9_6_EPUN_Msk                                  (0x01UL << SCU_SFSP9_6_EPUN_Pos)
#define SCU_SFSP9_6_EHS_Pos                                   5
#define SCU_SFSP9_6_EHS_Msk                                   (0x01UL << SCU_SFSP9_6_EHS_Pos)
#define SCU_SFSP9_6_EZI_Pos                                   6
#define SCU_SFSP9_6_EZI_Msk                                   (0x01UL << SCU_SFSP9_6_EZI_Pos)
#define SCU_SFSP9_6_EHD_Pos                                   8
#define SCU_SFSP9_6_EHD_Msk                                   (0x03UL << SCU_SFSP9_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPA_0  ------------------------------------------
#define SCU_SFSPA_0_MODE_Pos                                  0
#define SCU_SFSPA_0_MODE_Msk                                  (0x07UL << SCU_SFSPA_0_MODE_Pos)
#define SCU_SFSPA_0_EPD_Pos                                   3
#define SCU_SFSPA_0_EPD_Msk                                   (0x01UL << SCU_SFSPA_0_EPD_Pos)
#define SCU_SFSPA_0_EPUN_Pos                                  4
#define SCU_SFSPA_0_EPUN_Msk                                  (0x01UL << SCU_SFSPA_0_EPUN_Pos)
#define SCU_SFSPA_0_EHS_Pos                                   5
#define SCU_SFSPA_0_EHS_Msk                                   (0x01UL << SCU_SFSPA_0_EHS_Pos)
#define SCU_SFSPA_0_EZI_Pos                                   6
#define SCU_SFSPA_0_EZI_Msk                                   (0x01UL << SCU_SFSPA_0_EZI_Pos)
#define SCU_SFSPA_0_EHD_Pos                                   8
#define SCU_SFSPA_0_EHD_Msk                                   (0x03UL << SCU_SFSPA_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPA_1  ------------------------------------------
#define SCU_SFSPA_1_MODE_Pos                                  0
#define SCU_SFSPA_1_MODE_Msk                                  (0x07UL << SCU_SFSPA_1_MODE_Pos)
#define SCU_SFSPA_1_EPD_Pos                                   3
#define SCU_SFSPA_1_EPD_Msk                                   (0x01UL << SCU_SFSPA_1_EPD_Pos)
#define SCU_SFSPA_1_EPUN_Pos                                  4
#define SCU_SFSPA_1_EPUN_Msk                                  (0x01UL << SCU_SFSPA_1_EPUN_Pos)
#define SCU_SFSPA_1_EHS_Pos                                   5
#define SCU_SFSPA_1_EHS_Msk                                   (0x01UL << SCU_SFSPA_1_EHS_Pos)
#define SCU_SFSPA_1_EZI_Pos                                   6
#define SCU_SFSPA_1_EZI_Msk                                   (0x01UL << SCU_SFSPA_1_EZI_Pos)
#define SCU_SFSPA_1_EHD_Pos                                   8
#define SCU_SFSPA_1_EHD_Msk                                   (0x03UL << SCU_SFSPA_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPA_2  ------------------------------------------
#define SCU_SFSPA_2_MODE_Pos                                  0
#define SCU_SFSPA_2_MODE_Msk                                  (0x07UL << SCU_SFSPA_2_MODE_Pos)
#define SCU_SFSPA_2_EPD_Pos                                   3
#define SCU_SFSPA_2_EPD_Msk                                   (0x01UL << SCU_SFSPA_2_EPD_Pos)
#define SCU_SFSPA_2_EPUN_Pos                                  4
#define SCU_SFSPA_2_EPUN_Msk                                  (0x01UL << SCU_SFSPA_2_EPUN_Pos)
#define SCU_SFSPA_2_EHS_Pos                                   5
#define SCU_SFSPA_2_EHS_Msk                                   (0x01UL << SCU_SFSPA_2_EHS_Pos)
#define SCU_SFSPA_2_EZI_Pos                                   6
#define SCU_SFSPA_2_EZI_Msk                                   (0x01UL << SCU_SFSPA_2_EZI_Pos)
#define SCU_SFSPA_2_EHD_Pos                                   8
#define SCU_SFSPA_2_EHD_Msk                                   (0x03UL << SCU_SFSPA_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPA_3  ------------------------------------------
#define SCU_SFSPA_3_MODE_Pos                                  0
#define SCU_SFSPA_3_MODE_Msk                                  (0x07UL << SCU_SFSPA_3_MODE_Pos)
#define SCU_SFSPA_3_EPD_Pos                                   3
#define SCU_SFSPA_3_EPD_Msk                                   (0x01UL << SCU_SFSPA_3_EPD_Pos)
#define SCU_SFSPA_3_EPUN_Pos                                  4
#define SCU_SFSPA_3_EPUN_Msk                                  (0x01UL << SCU_SFSPA_3_EPUN_Pos)
#define SCU_SFSPA_3_EHS_Pos                                   5
#define SCU_SFSPA_3_EHS_Msk                                   (0x01UL << SCU_SFSPA_3_EHS_Pos)
#define SCU_SFSPA_3_EZI_Pos                                   6
#define SCU_SFSPA_3_EZI_Msk                                   (0x01UL << SCU_SFSPA_3_EZI_Pos)
#define SCU_SFSPA_3_EHD_Pos                                   8
#define SCU_SFSPA_3_EHD_Msk                                   (0x03UL << SCU_SFSPA_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPA_4  ------------------------------------------
#define SCU_SFSPA_4_MODE_Pos                                  0
#define SCU_SFSPA_4_MODE_Msk                                  (0x07UL << SCU_SFSPA_4_MODE_Pos)
#define SCU_SFSPA_4_EPD_Pos                                   3
#define SCU_SFSPA_4_EPD_Msk                                   (0x01UL << SCU_SFSPA_4_EPD_Pos)
#define SCU_SFSPA_4_EPUN_Pos                                  4
#define SCU_SFSPA_4_EPUN_Msk                                  (0x01UL << SCU_SFSPA_4_EPUN_Pos)
#define SCU_SFSPA_4_EHS_Pos                                   5
#define SCU_SFSPA_4_EHS_Msk                                   (0x01UL << SCU_SFSPA_4_EHS_Pos)
#define SCU_SFSPA_4_EZI_Pos                                   6
#define SCU_SFSPA_4_EZI_Msk                                   (0x01UL << SCU_SFSPA_4_EZI_Pos)
#define SCU_SFSPA_4_EHD_Pos                                   8
#define SCU_SFSPA_4_EHD_Msk                                   (0x03UL << SCU_SFSPA_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_0  ------------------------------------------
#define SCU_SFSPB_0_MODE_Pos                                  0
#define SCU_SFSPB_0_MODE_Msk                                  (0x07UL << SCU_SFSPB_0_MODE_Pos)
#define SCU_SFSPB_0_EPD_Pos                                   3
#define SCU_SFSPB_0_EPD_Msk                                   (0x01UL << SCU_SFSPB_0_EPD_Pos)
#define SCU_SFSPB_0_EPUN_Pos                                  4
#define SCU_SFSPB_0_EPUN_Msk                                  (0x01UL << SCU_SFSPB_0_EPUN_Pos)
#define SCU_SFSPB_0_EHS_Pos                                   5
#define SCU_SFSPB_0_EHS_Msk                                   (0x01UL << SCU_SFSPB_0_EHS_Pos)
#define SCU_SFSPB_0_EZI_Pos                                   6
#define SCU_SFSPB_0_EZI_Msk                                   (0x01UL << SCU_SFSPB_0_EZI_Pos)
#define SCU_SFSPB_0_EHD_Pos                                   8
#define SCU_SFSPB_0_EHD_Msk                                   (0x03UL << SCU_SFSPB_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_1  ------------------------------------------
#define SCU_SFSPB_1_MODE_Pos                                  0
#define SCU_SFSPB_1_MODE_Msk                                  (0x07UL << SCU_SFSPB_1_MODE_Pos)
#define SCU_SFSPB_1_EPD_Pos                                   3
#define SCU_SFSPB_1_EPD_Msk                                   (0x01UL << SCU_SFSPB_1_EPD_Pos)
#define SCU_SFSPB_1_EPUN_Pos                                  4
#define SCU_SFSPB_1_EPUN_Msk                                  (0x01UL << SCU_SFSPB_1_EPUN_Pos)
#define SCU_SFSPB_1_EHS_Pos                                   5
#define SCU_SFSPB_1_EHS_Msk                                   (0x01UL << SCU_SFSPB_1_EHS_Pos)
#define SCU_SFSPB_1_EZI_Pos                                   6
#define SCU_SFSPB_1_EZI_Msk                                   (0x01UL << SCU_SFSPB_1_EZI_Pos)
#define SCU_SFSPB_1_EHD_Pos                                   8
#define SCU_SFSPB_1_EHD_Msk                                   (0x03UL << SCU_SFSPB_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_2  ------------------------------------------
#define SCU_SFSPB_2_MODE_Pos                                  0
#define SCU_SFSPB_2_MODE_Msk                                  (0x07UL << SCU_SFSPB_2_MODE_Pos)
#define SCU_SFSPB_2_EPD_Pos                                   3
#define SCU_SFSPB_2_EPD_Msk                                   (0x01UL << SCU_SFSPB_2_EPD_Pos)
#define SCU_SFSPB_2_EPUN_Pos                                  4
#define SCU_SFSPB_2_EPUN_Msk                                  (0x01UL << SCU_SFSPB_2_EPUN_Pos)
#define SCU_SFSPB_2_EHS_Pos                                   5
#define SCU_SFSPB_2_EHS_Msk                                   (0x01UL << SCU_SFSPB_2_EHS_Pos)
#define SCU_SFSPB_2_EZI_Pos                                   6
#define SCU_SFSPB_2_EZI_Msk                                   (0x01UL << SCU_SFSPB_2_EZI_Pos)
#define SCU_SFSPB_2_EHD_Pos                                   8
#define SCU_SFSPB_2_EHD_Msk                                   (0x03UL << SCU_SFSPB_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_3  ------------------------------------------
#define SCU_SFSPB_3_MODE_Pos                                  0
#define SCU_SFSPB_3_MODE_Msk                                  (0x07UL << SCU_SFSPB_3_MODE_Pos)
#define SCU_SFSPB_3_EPD_Pos                                   3
#define SCU_SFSPB_3_EPD_Msk                                   (0x01UL << SCU_SFSPB_3_EPD_Pos)
#define SCU_SFSPB_3_EPUN_Pos                                  4
#define SCU_SFSPB_3_EPUN_Msk                                  (0x01UL << SCU_SFSPB_3_EPUN_Pos)
#define SCU_SFSPB_3_EHS_Pos                                   5
#define SCU_SFSPB_3_EHS_Msk                                   (0x01UL << SCU_SFSPB_3_EHS_Pos)
#define SCU_SFSPB_3_EZI_Pos                                   6
#define SCU_SFSPB_3_EZI_Msk                                   (0x01UL << SCU_SFSPB_3_EZI_Pos)
#define SCU_SFSPB_3_EHD_Pos                                   8
#define SCU_SFSPB_3_EHD_Msk                                   (0x03UL << SCU_SFSPB_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_4  ------------------------------------------
#define SCU_SFSPB_4_MODE_Pos                                  0
#define SCU_SFSPB_4_MODE_Msk                                  (0x07UL << SCU_SFSPB_4_MODE_Pos)
#define SCU_SFSPB_4_EPD_Pos                                   3
#define SCU_SFSPB_4_EPD_Msk                                   (0x01UL << SCU_SFSPB_4_EPD_Pos)
#define SCU_SFSPB_4_EPUN_Pos                                  4
#define SCU_SFSPB_4_EPUN_Msk                                  (0x01UL << SCU_SFSPB_4_EPUN_Pos)
#define SCU_SFSPB_4_EHS_Pos                                   5
#define SCU_SFSPB_4_EHS_Msk                                   (0x01UL << SCU_SFSPB_4_EHS_Pos)
#define SCU_SFSPB_4_EZI_Pos                                   6
#define SCU_SFSPB_4_EZI_Msk                                   (0x01UL << SCU_SFSPB_4_EZI_Pos)
#define SCU_SFSPB_4_EHD_Pos                                   8
#define SCU_SFSPB_4_EHD_Msk                                   (0x03UL << SCU_SFSPB_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_5  ------------------------------------------
#define SCU_SFSPB_5_MODE_Pos                                  0
#define SCU_SFSPB_5_MODE_Msk                                  (0x07UL << SCU_SFSPB_5_MODE_Pos)
#define SCU_SFSPB_5_EPD_Pos                                   3
#define SCU_SFSPB_5_EPD_Msk                                   (0x01UL << SCU_SFSPB_5_EPD_Pos)
#define SCU_SFSPB_5_EPUN_Pos                                  4
#define SCU_SFSPB_5_EPUN_Msk                                  (0x01UL << SCU_SFSPB_5_EPUN_Pos)
#define SCU_SFSPB_5_EHS_Pos                                   5
#define SCU_SFSPB_5_EHS_Msk                                   (0x01UL << SCU_SFSPB_5_EHS_Pos)
#define SCU_SFSPB_5_EZI_Pos                                   6
#define SCU_SFSPB_5_EZI_Msk                                   (0x01UL << SCU_SFSPB_5_EZI_Pos)
#define SCU_SFSPB_5_EHD_Pos                                   8
#define SCU_SFSPB_5_EHD_Msk                                   (0x03UL << SCU_SFSPB_5_EHD_Pos)

// ---------------------------------------  SCU_SFSPB_6  ------------------------------------------
#define SCU_SFSPB_6_MODE_Pos                                  0
#define SCU_SFSPB_6_MODE_Msk                                  (0x07UL << SCU_SFSPB_6_MODE_Pos)
#define SCU_SFSPB_6_EPD_Pos                                   3
#define SCU_SFSPB_6_EPD_Msk                                   (0x01UL << SCU_SFSPB_6_EPD_Pos)
#define SCU_SFSPB_6_EPUN_Pos                                  4
#define SCU_SFSPB_6_EPUN_Msk                                  (0x01UL << SCU_SFSPB_6_EPUN_Pos)
#define SCU_SFSPB_6_EHS_Pos                                   5
#define SCU_SFSPB_6_EHS_Msk                                   (0x01UL << SCU_SFSPB_6_EHS_Pos)
#define SCU_SFSPB_6_EZI_Pos                                   6
#define SCU_SFSPB_6_EZI_Msk                                   (0x01UL << SCU_SFSPB_6_EZI_Pos)
#define SCU_SFSPB_6_EHD_Pos                                   8
#define SCU_SFSPB_6_EHD_Msk                                   (0x03UL << SCU_SFSPB_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_0  ------------------------------------------
#define SCU_SFSPC_0_MODE_Pos                                  0
#define SCU_SFSPC_0_MODE_Msk                                  (0x07UL << SCU_SFSPC_0_MODE_Pos)
#define SCU_SFSPC_0_EPD_Pos                                   3
#define SCU_SFSPC_0_EPD_Msk                                   (0x01UL << SCU_SFSPC_0_EPD_Pos)
#define SCU_SFSPC_0_EPUN_Pos                                  4
#define SCU_SFSPC_0_EPUN_Msk                                  (0x01UL << SCU_SFSPC_0_EPUN_Pos)
#define SCU_SFSPC_0_EHS_Pos                                   5
#define SCU_SFSPC_0_EHS_Msk                                   (0x01UL << SCU_SFSPC_0_EHS_Pos)
#define SCU_SFSPC_0_EZI_Pos                                   6
#define SCU_SFSPC_0_EZI_Msk                                   (0x01UL << SCU_SFSPC_0_EZI_Pos)
#define SCU_SFSPC_0_EHD_Pos                                   8
#define SCU_SFSPC_0_EHD_Msk                                   (0x03UL << SCU_SFSPC_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_1  ------------------------------------------
#define SCU_SFSPC_1_MODE_Pos                                  0
#define SCU_SFSPC_1_MODE_Msk                                  (0x07UL << SCU_SFSPC_1_MODE_Pos)
#define SCU_SFSPC_1_EPD_Pos                                   3
#define SCU_SFSPC_1_EPD_Msk                                   (0x01UL << SCU_SFSPC_1_EPD_Pos)
#define SCU_SFSPC_1_EPUN_Pos                                  4
#define SCU_SFSPC_1_EPUN_Msk                                  (0x01UL << SCU_SFSPC_1_EPUN_Pos)
#define SCU_SFSPC_1_EHS_Pos                                   5
#define SCU_SFSPC_1_EHS_Msk                                   (0x01UL << SCU_SFSPC_1_EHS_Pos)
#define SCU_SFSPC_1_EZI_Pos                                   6
#define SCU_SFSPC_1_EZI_Msk                                   (0x01UL << SCU_SFSPC_1_EZI_Pos)
#define SCU_SFSPC_1_EHD_Pos                                   8
#define SCU_SFSPC_1_EHD_Msk                                   (0x03UL << SCU_SFSPC_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_2  ------------------------------------------
#define SCU_SFSPC_2_MODE_Pos                                  0
#define SCU_SFSPC_2_MODE_Msk                                  (0x07UL << SCU_SFSPC_2_MODE_Pos)
#define SCU_SFSPC_2_EPD_Pos                                   3
#define SCU_SFSPC_2_EPD_Msk                                   (0x01UL << SCU_SFSPC_2_EPD_Pos)
#define SCU_SFSPC_2_EPUN_Pos                                  4
#define SCU_SFSPC_2_EPUN_Msk                                  (0x01UL << SCU_SFSPC_2_EPUN_Pos)
#define SCU_SFSPC_2_EHS_Pos                                   5
#define SCU_SFSPC_2_EHS_Msk                                   (0x01UL << SCU_SFSPC_2_EHS_Pos)
#define SCU_SFSPC_2_EZI_Pos                                   6
#define SCU_SFSPC_2_EZI_Msk                                   (0x01UL << SCU_SFSPC_2_EZI_Pos)
#define SCU_SFSPC_2_EHD_Pos                                   8
#define SCU_SFSPC_2_EHD_Msk                                   (0x03UL << SCU_SFSPC_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_3  ------------------------------------------
#define SCU_SFSPC_3_MODE_Pos                                  0
#define SCU_SFSPC_3_MODE_Msk                                  (0x07UL << SCU_SFSPC_3_MODE_Pos)
#define SCU_SFSPC_3_EPD_Pos                                   3
#define SCU_SFSPC_3_EPD_Msk                                   (0x01UL << SCU_SFSPC_3_EPD_Pos)
#define SCU_SFSPC_3_EPUN_Pos                                  4
#define SCU_SFSPC_3_EPUN_Msk                                  (0x01UL << SCU_SFSPC_3_EPUN_Pos)
#define SCU_SFSPC_3_EHS_Pos                                   5
#define SCU_SFSPC_3_EHS_Msk                                   (0x01UL << SCU_SFSPC_3_EHS_Pos)
#define SCU_SFSPC_3_EZI_Pos                                   6
#define SCU_SFSPC_3_EZI_Msk                                   (0x01UL << SCU_SFSPC_3_EZI_Pos)
#define SCU_SFSPC_3_EHD_Pos                                   8
#define SCU_SFSPC_3_EHD_Msk                                   (0x03UL << SCU_SFSPC_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_4  ------------------------------------------
#define SCU_SFSPC_4_MODE_Pos                                  0
#define SCU_SFSPC_4_MODE_Msk                                  (0x07UL << SCU_SFSPC_4_MODE_Pos)
#define SCU_SFSPC_4_EPD_Pos                                   3
#define SCU_SFSPC_4_EPD_Msk                                   (0x01UL << SCU_SFSPC_4_EPD_Pos)
#define SCU_SFSPC_4_EPUN_Pos                                  4
#define SCU_SFSPC_4_EPUN_Msk                                  (0x01UL << SCU_SFSPC_4_EPUN_Pos)
#define SCU_SFSPC_4_EHS_Pos                                   5
#define SCU_SFSPC_4_EHS_Msk                                   (0x01UL << SCU_SFSPC_4_EHS_Pos)
#define SCU_SFSPC_4_EZI_Pos                                   6
#define SCU_SFSPC_4_EZI_Msk                                   (0x01UL << SCU_SFSPC_4_EZI_Pos)
#define SCU_SFSPC_4_EHD_Pos                                   8
#define SCU_SFSPC_4_EHD_Msk                                   (0x03UL << SCU_SFSPC_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_5  ------------------------------------------
#define SCU_SFSPC_5_MODE_Pos                                  0
#define SCU_SFSPC_5_MODE_Msk                                  (0x07UL << SCU_SFSPC_5_MODE_Pos)
#define SCU_SFSPC_5_EPD_Pos                                   3
#define SCU_SFSPC_5_EPD_Msk                                   (0x01UL << SCU_SFSPC_5_EPD_Pos)
#define SCU_SFSPC_5_EPUN_Pos                                  4
#define SCU_SFSPC_5_EPUN_Msk                                  (0x01UL << SCU_SFSPC_5_EPUN_Pos)
#define SCU_SFSPC_5_EHS_Pos                                   5
#define SCU_SFSPC_5_EHS_Msk                                   (0x01UL << SCU_SFSPC_5_EHS_Pos)
#define SCU_SFSPC_5_EZI_Pos                                   6
#define SCU_SFSPC_5_EZI_Msk                                   (0x01UL << SCU_SFSPC_5_EZI_Pos)
#define SCU_SFSPC_5_EHD_Pos                                   8
#define SCU_SFSPC_5_EHD_Msk                                   (0x03UL << SCU_SFSPC_5_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_6  ------------------------------------------
#define SCU_SFSPC_6_MODE_Pos                                  0
#define SCU_SFSPC_6_MODE_Msk                                  (0x07UL << SCU_SFSPC_6_MODE_Pos)
#define SCU_SFSPC_6_EPD_Pos                                   3
#define SCU_SFSPC_6_EPD_Msk                                   (0x01UL << SCU_SFSPC_6_EPD_Pos)
#define SCU_SFSPC_6_EPUN_Pos                                  4
#define SCU_SFSPC_6_EPUN_Msk                                  (0x01UL << SCU_SFSPC_6_EPUN_Pos)
#define SCU_SFSPC_6_EHS_Pos                                   5
#define SCU_SFSPC_6_EHS_Msk                                   (0x01UL << SCU_SFSPC_6_EHS_Pos)
#define SCU_SFSPC_6_EZI_Pos                                   6
#define SCU_SFSPC_6_EZI_Msk                                   (0x01UL << SCU_SFSPC_6_EZI_Pos)
#define SCU_SFSPC_6_EHD_Pos                                   8
#define SCU_SFSPC_6_EHD_Msk                                   (0x03UL << SCU_SFSPC_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_7  ------------------------------------------
#define SCU_SFSPC_7_MODE_Pos                                  0
#define SCU_SFSPC_7_MODE_Msk                                  (0x07UL << SCU_SFSPC_7_MODE_Pos)
#define SCU_SFSPC_7_EPD_Pos                                   3
#define SCU_SFSPC_7_EPD_Msk                                   (0x01UL << SCU_SFSPC_7_EPD_Pos)
#define SCU_SFSPC_7_EPUN_Pos                                  4
#define SCU_SFSPC_7_EPUN_Msk                                  (0x01UL << SCU_SFSPC_7_EPUN_Pos)
#define SCU_SFSPC_7_EHS_Pos                                   5
#define SCU_SFSPC_7_EHS_Msk                                   (0x01UL << SCU_SFSPC_7_EHS_Pos)
#define SCU_SFSPC_7_EZI_Pos                                   6
#define SCU_SFSPC_7_EZI_Msk                                   (0x01UL << SCU_SFSPC_7_EZI_Pos)
#define SCU_SFSPC_7_EHD_Pos                                   8
#define SCU_SFSPC_7_EHD_Msk                                   (0x03UL << SCU_SFSPC_7_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_8  ------------------------------------------
#define SCU_SFSPC_8_MODE_Pos                                  0
#define SCU_SFSPC_8_MODE_Msk                                  (0x07UL << SCU_SFSPC_8_MODE_Pos)
#define SCU_SFSPC_8_EPD_Pos                                   3
#define SCU_SFSPC_8_EPD_Msk                                   (0x01UL << SCU_SFSPC_8_EPD_Pos)
#define SCU_SFSPC_8_EPUN_Pos                                  4
#define SCU_SFSPC_8_EPUN_Msk                                  (0x01UL << SCU_SFSPC_8_EPUN_Pos)
#define SCU_SFSPC_8_EHS_Pos                                   5
#define SCU_SFSPC_8_EHS_Msk                                   (0x01UL << SCU_SFSPC_8_EHS_Pos)
#define SCU_SFSPC_8_EZI_Pos                                   6
#define SCU_SFSPC_8_EZI_Msk                                   (0x01UL << SCU_SFSPC_8_EZI_Pos)
#define SCU_SFSPC_8_EHD_Pos                                   8
#define SCU_SFSPC_8_EHD_Msk                                   (0x03UL << SCU_SFSPC_8_EHD_Pos)

// ---------------------------------------  SCU_SFSPC_9  ------------------------------------------
#define SCU_SFSPC_9_MODE_Pos                                  0
#define SCU_SFSPC_9_MODE_Msk                                  (0x07UL << SCU_SFSPC_9_MODE_Pos)
#define SCU_SFSPC_9_EPD_Pos                                   3
#define SCU_SFSPC_9_EPD_Msk                                   (0x01UL << SCU_SFSPC_9_EPD_Pos)
#define SCU_SFSPC_9_EPUN_Pos                                  4
#define SCU_SFSPC_9_EPUN_Msk                                  (0x01UL << SCU_SFSPC_9_EPUN_Pos)
#define SCU_SFSPC_9_EHS_Pos                                   5
#define SCU_SFSPC_9_EHS_Msk                                   (0x01UL << SCU_SFSPC_9_EHS_Pos)
#define SCU_SFSPC_9_EZI_Pos                                   6
#define SCU_SFSPC_9_EZI_Msk                                   (0x01UL << SCU_SFSPC_9_EZI_Pos)
#define SCU_SFSPC_9_EHD_Pos                                   8
#define SCU_SFSPC_9_EHD_Msk                                   (0x03UL << SCU_SFSPC_9_EHD_Pos)

// --------------------------------------  SCU_SFSPC_10  ------------------------------------------
#define SCU_SFSPC_10_MODE_Pos                                 0
#define SCU_SFSPC_10_MODE_Msk                                 (0x07UL << SCU_SFSPC_10_MODE_Pos)
#define SCU_SFSPC_10_EPD_Pos                                  3
#define SCU_SFSPC_10_EPD_Msk                                  (0x01UL << SCU_SFSPC_10_EPD_Pos)
#define SCU_SFSPC_10_EPUN_Pos                                 4
#define SCU_SFSPC_10_EPUN_Msk                                 (0x01UL << SCU_SFSPC_10_EPUN_Pos)
#define SCU_SFSPC_10_EHS_Pos                                  5
#define SCU_SFSPC_10_EHS_Msk                                  (0x01UL << SCU_SFSPC_10_EHS_Pos)
#define SCU_SFSPC_10_EZI_Pos                                  6
#define SCU_SFSPC_10_EZI_Msk                                  (0x01UL << SCU_SFSPC_10_EZI_Pos)
#define SCU_SFSPC_10_EHD_Pos                                  8
#define SCU_SFSPC_10_EHD_Msk                                  (0x03UL << SCU_SFSPC_10_EHD_Pos)

// --------------------------------------  SCU_SFSPC_11  ------------------------------------------
#define SCU_SFSPC_11_MODE_Pos                                 0
#define SCU_SFSPC_11_MODE_Msk                                 (0x07UL << SCU_SFSPC_11_MODE_Pos)
#define SCU_SFSPC_11_EPD_Pos                                  3
#define SCU_SFSPC_11_EPD_Msk                                  (0x01UL << SCU_SFSPC_11_EPD_Pos)
#define SCU_SFSPC_11_EPUN_Pos                                 4
#define SCU_SFSPC_11_EPUN_Msk                                 (0x01UL << SCU_SFSPC_11_EPUN_Pos)
#define SCU_SFSPC_11_EHS_Pos                                  5
#define SCU_SFSPC_11_EHS_Msk                                  (0x01UL << SCU_SFSPC_11_EHS_Pos)
#define SCU_SFSPC_11_EZI_Pos                                  6
#define SCU_SFSPC_11_EZI_Msk                                  (0x01UL << SCU_SFSPC_11_EZI_Pos)
#define SCU_SFSPC_11_EHD_Pos                                  8
#define SCU_SFSPC_11_EHD_Msk                                  (0x03UL << SCU_SFSPC_11_EHD_Pos)

// --------------------------------------  SCU_SFSPC_12  ------------------------------------------
#define SCU_SFSPC_12_MODE_Pos                                 0
#define SCU_SFSPC_12_MODE_Msk                                 (0x07UL << SCU_SFSPC_12_MODE_Pos)
#define SCU_SFSPC_12_EPD_Pos                                  3
#define SCU_SFSPC_12_EPD_Msk                                  (0x01UL << SCU_SFSPC_12_EPD_Pos)
#define SCU_SFSPC_12_EPUN_Pos                                 4
#define SCU_SFSPC_12_EPUN_Msk                                 (0x01UL << SCU_SFSPC_12_EPUN_Pos)
#define SCU_SFSPC_12_EHS_Pos                                  5
#define SCU_SFSPC_12_EHS_Msk                                  (0x01UL << SCU_SFSPC_12_EHS_Pos)
#define SCU_SFSPC_12_EZI_Pos                                  6
#define SCU_SFSPC_12_EZI_Msk                                  (0x01UL << SCU_SFSPC_12_EZI_Pos)
#define SCU_SFSPC_12_EHD_Pos                                  8
#define SCU_SFSPC_12_EHD_Msk                                  (0x03UL << SCU_SFSPC_12_EHD_Pos)

// --------------------------------------  SCU_SFSPC_13  ------------------------------------------
#define SCU_SFSPC_13_MODE_Pos                                 0
#define SCU_SFSPC_13_MODE_Msk                                 (0x07UL << SCU_SFSPC_13_MODE_Pos)
#define SCU_SFSPC_13_EPD_Pos                                  3
#define SCU_SFSPC_13_EPD_Msk                                  (0x01UL << SCU_SFSPC_13_EPD_Pos)
#define SCU_SFSPC_13_EPUN_Pos                                 4
#define SCU_SFSPC_13_EPUN_Msk                                 (0x01UL << SCU_SFSPC_13_EPUN_Pos)
#define SCU_SFSPC_13_EHS_Pos                                  5
#define SCU_SFSPC_13_EHS_Msk                                  (0x01UL << SCU_SFSPC_13_EHS_Pos)
#define SCU_SFSPC_13_EZI_Pos                                  6
#define SCU_SFSPC_13_EZI_Msk                                  (0x01UL << SCU_SFSPC_13_EZI_Pos)
#define SCU_SFSPC_13_EHD_Pos                                  8
#define SCU_SFSPC_13_EHD_Msk                                  (0x03UL << SCU_SFSPC_13_EHD_Pos)

// --------------------------------------  SCU_SFSPC_14  ------------------------------------------
#define SCU_SFSPC_14_MODE_Pos                                 0
#define SCU_SFSPC_14_MODE_Msk                                 (0x07UL << SCU_SFSPC_14_MODE_Pos)
#define SCU_SFSPC_14_EPD_Pos                                  3
#define SCU_SFSPC_14_EPD_Msk                                  (0x01UL << SCU_SFSPC_14_EPD_Pos)
#define SCU_SFSPC_14_EPUN_Pos                                 4
#define SCU_SFSPC_14_EPUN_Msk                                 (0x01UL << SCU_SFSPC_14_EPUN_Pos)
#define SCU_SFSPC_14_EHS_Pos                                  5
#define SCU_SFSPC_14_EHS_Msk                                  (0x01UL << SCU_SFSPC_14_EHS_Pos)
#define SCU_SFSPC_14_EZI_Pos                                  6
#define SCU_SFSPC_14_EZI_Msk                                  (0x01UL << SCU_SFSPC_14_EZI_Pos)
#define SCU_SFSPC_14_EHD_Pos                                  8
#define SCU_SFSPC_14_EHD_Msk                                  (0x03UL << SCU_SFSPC_14_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_0  ------------------------------------------
#define SCU_SFSPD_0_MODE_Pos                                  0
#define SCU_SFSPD_0_MODE_Msk                                  (0x07UL << SCU_SFSPD_0_MODE_Pos)
#define SCU_SFSPD_0_EPD_Pos                                   3
#define SCU_SFSPD_0_EPD_Msk                                   (0x01UL << SCU_SFSPD_0_EPD_Pos)
#define SCU_SFSPD_0_EPUN_Pos                                  4
#define SCU_SFSPD_0_EPUN_Msk                                  (0x01UL << SCU_SFSPD_0_EPUN_Pos)
#define SCU_SFSPD_0_EHS_Pos                                   5
#define SCU_SFSPD_0_EHS_Msk                                   (0x01UL << SCU_SFSPD_0_EHS_Pos)
#define SCU_SFSPD_0_EZI_Pos                                   6
#define SCU_SFSPD_0_EZI_Msk                                   (0x01UL << SCU_SFSPD_0_EZI_Pos)
#define SCU_SFSPD_0_EHD_Pos                                   8
#define SCU_SFSPD_0_EHD_Msk                                   (0x03UL << SCU_SFSPD_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_1  ------------------------------------------
#define SCU_SFSPD_1_MODE_Pos                                  0
#define SCU_SFSPD_1_MODE_Msk                                  (0x07UL << SCU_SFSPD_1_MODE_Pos)
#define SCU_SFSPD_1_EPD_Pos                                   3
#define SCU_SFSPD_1_EPD_Msk                                   (0x01UL << SCU_SFSPD_1_EPD_Pos)
#define SCU_SFSPD_1_EPUN_Pos                                  4
#define SCU_SFSPD_1_EPUN_Msk                                  (0x01UL << SCU_SFSPD_1_EPUN_Pos)
#define SCU_SFSPD_1_EHS_Pos                                   5
#define SCU_SFSPD_1_EHS_Msk                                   (0x01UL << SCU_SFSPD_1_EHS_Pos)
#define SCU_SFSPD_1_EZI_Pos                                   6
#define SCU_SFSPD_1_EZI_Msk                                   (0x01UL << SCU_SFSPD_1_EZI_Pos)
#define SCU_SFSPD_1_EHD_Pos                                   8
#define SCU_SFSPD_1_EHD_Msk                                   (0x03UL << SCU_SFSPD_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_2  ------------------------------------------
#define SCU_SFSPD_2_MODE_Pos                                  0
#define SCU_SFSPD_2_MODE_Msk                                  (0x07UL << SCU_SFSPD_2_MODE_Pos)
#define SCU_SFSPD_2_EPD_Pos                                   3
#define SCU_SFSPD_2_EPD_Msk                                   (0x01UL << SCU_SFSPD_2_EPD_Pos)
#define SCU_SFSPD_2_EPUN_Pos                                  4
#define SCU_SFSPD_2_EPUN_Msk                                  (0x01UL << SCU_SFSPD_2_EPUN_Pos)
#define SCU_SFSPD_2_EHS_Pos                                   5
#define SCU_SFSPD_2_EHS_Msk                                   (0x01UL << SCU_SFSPD_2_EHS_Pos)
#define SCU_SFSPD_2_EZI_Pos                                   6
#define SCU_SFSPD_2_EZI_Msk                                   (0x01UL << SCU_SFSPD_2_EZI_Pos)
#define SCU_SFSPD_2_EHD_Pos                                   8
#define SCU_SFSPD_2_EHD_Msk                                   (0x03UL << SCU_SFSPD_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_3  ------------------------------------------
#define SCU_SFSPD_3_MODE_Pos                                  0
#define SCU_SFSPD_3_MODE_Msk                                  (0x07UL << SCU_SFSPD_3_MODE_Pos)
#define SCU_SFSPD_3_EPD_Pos                                   3
#define SCU_SFSPD_3_EPD_Msk                                   (0x01UL << SCU_SFSPD_3_EPD_Pos)
#define SCU_SFSPD_3_EPUN_Pos                                  4
#define SCU_SFSPD_3_EPUN_Msk                                  (0x01UL << SCU_SFSPD_3_EPUN_Pos)
#define SCU_SFSPD_3_EHS_Pos                                   5
#define SCU_SFSPD_3_EHS_Msk                                   (0x01UL << SCU_SFSPD_3_EHS_Pos)
#define SCU_SFSPD_3_EZI_Pos                                   6
#define SCU_SFSPD_3_EZI_Msk                                   (0x01UL << SCU_SFSPD_3_EZI_Pos)
#define SCU_SFSPD_3_EHD_Pos                                   8
#define SCU_SFSPD_3_EHD_Msk                                   (0x03UL << SCU_SFSPD_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_4  ------------------------------------------
#define SCU_SFSPD_4_MODE_Pos                                  0
#define SCU_SFSPD_4_MODE_Msk                                  (0x07UL << SCU_SFSPD_4_MODE_Pos)
#define SCU_SFSPD_4_EPD_Pos                                   3
#define SCU_SFSPD_4_EPD_Msk                                   (0x01UL << SCU_SFSPD_4_EPD_Pos)
#define SCU_SFSPD_4_EPUN_Pos                                  4
#define SCU_SFSPD_4_EPUN_Msk                                  (0x01UL << SCU_SFSPD_4_EPUN_Pos)
#define SCU_SFSPD_4_EHS_Pos                                   5
#define SCU_SFSPD_4_EHS_Msk                                   (0x01UL << SCU_SFSPD_4_EHS_Pos)
#define SCU_SFSPD_4_EZI_Pos                                   6
#define SCU_SFSPD_4_EZI_Msk                                   (0x01UL << SCU_SFSPD_4_EZI_Pos)
#define SCU_SFSPD_4_EHD_Pos                                   8
#define SCU_SFSPD_4_EHD_Msk                                   (0x03UL << SCU_SFSPD_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_5  ------------------------------------------
#define SCU_SFSPD_5_MODE_Pos                                  0
#define SCU_SFSPD_5_MODE_Msk                                  (0x07UL << SCU_SFSPD_5_MODE_Pos)
#define SCU_SFSPD_5_EPD_Pos                                   3
#define SCU_SFSPD_5_EPD_Msk                                   (0x01UL << SCU_SFSPD_5_EPD_Pos)
#define SCU_SFSPD_5_EPUN_Pos                                  4
#define SCU_SFSPD_5_EPUN_Msk                                  (0x01UL << SCU_SFSPD_5_EPUN_Pos)
#define SCU_SFSPD_5_EHS_Pos                                   5
#define SCU_SFSPD_5_EHS_Msk                                   (0x01UL << SCU_SFSPD_5_EHS_Pos)
#define SCU_SFSPD_5_EZI_Pos                                   6
#define SCU_SFSPD_5_EZI_Msk                                   (0x01UL << SCU_SFSPD_5_EZI_Pos)
#define SCU_SFSPD_5_EHD_Pos                                   8
#define SCU_SFSPD_5_EHD_Msk                                   (0x03UL << SCU_SFSPD_5_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_6  ------------------------------------------
#define SCU_SFSPD_6_MODE_Pos                                  0
#define SCU_SFSPD_6_MODE_Msk                                  (0x07UL << SCU_SFSPD_6_MODE_Pos)
#define SCU_SFSPD_6_EPD_Pos                                   3
#define SCU_SFSPD_6_EPD_Msk                                   (0x01UL << SCU_SFSPD_6_EPD_Pos)
#define SCU_SFSPD_6_EPUN_Pos                                  4
#define SCU_SFSPD_6_EPUN_Msk                                  (0x01UL << SCU_SFSPD_6_EPUN_Pos)
#define SCU_SFSPD_6_EHS_Pos                                   5
#define SCU_SFSPD_6_EHS_Msk                                   (0x01UL << SCU_SFSPD_6_EHS_Pos)
#define SCU_SFSPD_6_EZI_Pos                                   6
#define SCU_SFSPD_6_EZI_Msk                                   (0x01UL << SCU_SFSPD_6_EZI_Pos)
#define SCU_SFSPD_6_EHD_Pos                                   8
#define SCU_SFSPD_6_EHD_Msk                                   (0x03UL << SCU_SFSPD_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_7  ------------------------------------------
#define SCU_SFSPD_7_MODE_Pos                                  0
#define SCU_SFSPD_7_MODE_Msk                                  (0x07UL << SCU_SFSPD_7_MODE_Pos)
#define SCU_SFSPD_7_EPD_Pos                                   3
#define SCU_SFSPD_7_EPD_Msk                                   (0x01UL << SCU_SFSPD_7_EPD_Pos)
#define SCU_SFSPD_7_EPUN_Pos                                  4
#define SCU_SFSPD_7_EPUN_Msk                                  (0x01UL << SCU_SFSPD_7_EPUN_Pos)
#define SCU_SFSPD_7_EHS_Pos                                   5
#define SCU_SFSPD_7_EHS_Msk                                   (0x01UL << SCU_SFSPD_7_EHS_Pos)
#define SCU_SFSPD_7_EZI_Pos                                   6
#define SCU_SFSPD_7_EZI_Msk                                   (0x01UL << SCU_SFSPD_7_EZI_Pos)
#define SCU_SFSPD_7_EHD_Pos                                   8
#define SCU_SFSPD_7_EHD_Msk                                   (0x03UL << SCU_SFSPD_7_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_8  ------------------------------------------
#define SCU_SFSPD_8_MODE_Pos                                  0
#define SCU_SFSPD_8_MODE_Msk                                  (0x07UL << SCU_SFSPD_8_MODE_Pos)
#define SCU_SFSPD_8_EPD_Pos                                   3
#define SCU_SFSPD_8_EPD_Msk                                   (0x01UL << SCU_SFSPD_8_EPD_Pos)
#define SCU_SFSPD_8_EPUN_Pos                                  4
#define SCU_SFSPD_8_EPUN_Msk                                  (0x01UL << SCU_SFSPD_8_EPUN_Pos)
#define SCU_SFSPD_8_EHS_Pos                                   5
#define SCU_SFSPD_8_EHS_Msk                                   (0x01UL << SCU_SFSPD_8_EHS_Pos)
#define SCU_SFSPD_8_EZI_Pos                                   6
#define SCU_SFSPD_8_EZI_Msk                                   (0x01UL << SCU_SFSPD_8_EZI_Pos)
#define SCU_SFSPD_8_EHD_Pos                                   8
#define SCU_SFSPD_8_EHD_Msk                                   (0x03UL << SCU_SFSPD_8_EHD_Pos)

// ---------------------------------------  SCU_SFSPD_9  ------------------------------------------
#define SCU_SFSPD_9_MODE_Pos                                  0
#define SCU_SFSPD_9_MODE_Msk                                  (0x07UL << SCU_SFSPD_9_MODE_Pos)
#define SCU_SFSPD_9_EPD_Pos                                   3
#define SCU_SFSPD_9_EPD_Msk                                   (0x01UL << SCU_SFSPD_9_EPD_Pos)
#define SCU_SFSPD_9_EPUN_Pos                                  4
#define SCU_SFSPD_9_EPUN_Msk                                  (0x01UL << SCU_SFSPD_9_EPUN_Pos)
#define SCU_SFSPD_9_EHS_Pos                                   5
#define SCU_SFSPD_9_EHS_Msk                                   (0x01UL << SCU_SFSPD_9_EHS_Pos)
#define SCU_SFSPD_9_EZI_Pos                                   6
#define SCU_SFSPD_9_EZI_Msk                                   (0x01UL << SCU_SFSPD_9_EZI_Pos)
#define SCU_SFSPD_9_EHD_Pos                                   8
#define SCU_SFSPD_9_EHD_Msk                                   (0x03UL << SCU_SFSPD_9_EHD_Pos)

// --------------------------------------  SCU_SFSPD_10  ------------------------------------------
#define SCU_SFSPD_10_MODE_Pos                                 0
#define SCU_SFSPD_10_MODE_Msk                                 (0x07UL << SCU_SFSPD_10_MODE_Pos)
#define SCU_SFSPD_10_EPD_Pos                                  3
#define SCU_SFSPD_10_EPD_Msk                                  (0x01UL << SCU_SFSPD_10_EPD_Pos)
#define SCU_SFSPD_10_EPUN_Pos                                 4
#define SCU_SFSPD_10_EPUN_Msk                                 (0x01UL << SCU_SFSPD_10_EPUN_Pos)
#define SCU_SFSPD_10_EHS_Pos                                  5
#define SCU_SFSPD_10_EHS_Msk                                  (0x01UL << SCU_SFSPD_10_EHS_Pos)
#define SCU_SFSPD_10_EZI_Pos                                  6
#define SCU_SFSPD_10_EZI_Msk                                  (0x01UL << SCU_SFSPD_10_EZI_Pos)
#define SCU_SFSPD_10_EHD_Pos                                  8
#define SCU_SFSPD_10_EHD_Msk                                  (0x03UL << SCU_SFSPD_10_EHD_Pos)

// --------------------------------------  SCU_SFSPD_11  ------------------------------------------
#define SCU_SFSPD_11_MODE_Pos                                 0
#define SCU_SFSPD_11_MODE_Msk                                 (0x07UL << SCU_SFSPD_11_MODE_Pos)
#define SCU_SFSPD_11_EPD_Pos                                  3
#define SCU_SFSPD_11_EPD_Msk                                  (0x01UL << SCU_SFSPD_11_EPD_Pos)
#define SCU_SFSPD_11_EPUN_Pos                                 4
#define SCU_SFSPD_11_EPUN_Msk                                 (0x01UL << SCU_SFSPD_11_EPUN_Pos)
#define SCU_SFSPD_11_EHS_Pos                                  5
#define SCU_SFSPD_11_EHS_Msk                                  (0x01UL << SCU_SFSPD_11_EHS_Pos)
#define SCU_SFSPD_11_EZI_Pos                                  6
#define SCU_SFSPD_11_EZI_Msk                                  (0x01UL << SCU_SFSPD_11_EZI_Pos)
#define SCU_SFSPD_11_EHD_Pos                                  8
#define SCU_SFSPD_11_EHD_Msk                                  (0x03UL << SCU_SFSPD_11_EHD_Pos)

// --------------------------------------  SCU_SFSPD_12  ------------------------------------------
#define SCU_SFSPD_12_MODE_Pos                                 0
#define SCU_SFSPD_12_MODE_Msk                                 (0x07UL << SCU_SFSPD_12_MODE_Pos)
#define SCU_SFSPD_12_EPD_Pos                                  3
#define SCU_SFSPD_12_EPD_Msk                                  (0x01UL << SCU_SFSPD_12_EPD_Pos)
#define SCU_SFSPD_12_EPUN_Pos                                 4
#define SCU_SFSPD_12_EPUN_Msk                                 (0x01UL << SCU_SFSPD_12_EPUN_Pos)
#define SCU_SFSPD_12_EHS_Pos                                  5
#define SCU_SFSPD_12_EHS_Msk                                  (0x01UL << SCU_SFSPD_12_EHS_Pos)
#define SCU_SFSPD_12_EZI_Pos                                  6
#define SCU_SFSPD_12_EZI_Msk                                  (0x01UL << SCU_SFSPD_12_EZI_Pos)
#define SCU_SFSPD_12_EHD_Pos                                  8
#define SCU_SFSPD_12_EHD_Msk                                  (0x03UL << SCU_SFSPD_12_EHD_Pos)

// --------------------------------------  SCU_SFSPD_13  ------------------------------------------
#define SCU_SFSPD_13_MODE_Pos                                 0
#define SCU_SFSPD_13_MODE_Msk                                 (0x07UL << SCU_SFSPD_13_MODE_Pos)
#define SCU_SFSPD_13_EPD_Pos                                  3
#define SCU_SFSPD_13_EPD_Msk                                  (0x01UL << SCU_SFSPD_13_EPD_Pos)
#define SCU_SFSPD_13_EPUN_Pos                                 4
#define SCU_SFSPD_13_EPUN_Msk                                 (0x01UL << SCU_SFSPD_13_EPUN_Pos)
#define SCU_SFSPD_13_EHS_Pos                                  5
#define SCU_SFSPD_13_EHS_Msk                                  (0x01UL << SCU_SFSPD_13_EHS_Pos)
#define SCU_SFSPD_13_EZI_Pos                                  6
#define SCU_SFSPD_13_EZI_Msk                                  (0x01UL << SCU_SFSPD_13_EZI_Pos)
#define SCU_SFSPD_13_EHD_Pos                                  8
#define SCU_SFSPD_13_EHD_Msk                                  (0x03UL << SCU_SFSPD_13_EHD_Pos)

// --------------------------------------  SCU_SFSPD_14  ------------------------------------------
#define SCU_SFSPD_14_MODE_Pos                                 0
#define SCU_SFSPD_14_MODE_Msk                                 (0x07UL << SCU_SFSPD_14_MODE_Pos)
#define SCU_SFSPD_14_EPD_Pos                                  3
#define SCU_SFSPD_14_EPD_Msk                                  (0x01UL << SCU_SFSPD_14_EPD_Pos)
#define SCU_SFSPD_14_EPUN_Pos                                 4
#define SCU_SFSPD_14_EPUN_Msk                                 (0x01UL << SCU_SFSPD_14_EPUN_Pos)
#define SCU_SFSPD_14_EHS_Pos                                  5
#define SCU_SFSPD_14_EHS_Msk                                  (0x01UL << SCU_SFSPD_14_EHS_Pos)
#define SCU_SFSPD_14_EZI_Pos                                  6
#define SCU_SFSPD_14_EZI_Msk                                  (0x01UL << SCU_SFSPD_14_EZI_Pos)
#define SCU_SFSPD_14_EHD_Pos                                  8
#define SCU_SFSPD_14_EHD_Msk                                  (0x03UL << SCU_SFSPD_14_EHD_Pos)

// --------------------------------------  SCU_SFSPD_15  ------------------------------------------
#define SCU_SFSPD_15_MODE_Pos                                 0
#define SCU_SFSPD_15_MODE_Msk                                 (0x07UL << SCU_SFSPD_15_MODE_Pos)
#define SCU_SFSPD_15_EPD_Pos                                  3
#define SCU_SFSPD_15_EPD_Msk                                  (0x01UL << SCU_SFSPD_15_EPD_Pos)
#define SCU_SFSPD_15_EPUN_Pos                                 4
#define SCU_SFSPD_15_EPUN_Msk                                 (0x01UL << SCU_SFSPD_15_EPUN_Pos)
#define SCU_SFSPD_15_EHS_Pos                                  5
#define SCU_SFSPD_15_EHS_Msk                                  (0x01UL << SCU_SFSPD_15_EHS_Pos)
#define SCU_SFSPD_15_EZI_Pos                                  6
#define SCU_SFSPD_15_EZI_Msk                                  (0x01UL << SCU_SFSPD_15_EZI_Pos)
#define SCU_SFSPD_15_EHD_Pos                                  8
#define SCU_SFSPD_15_EHD_Msk                                  (0x03UL << SCU_SFSPD_15_EHD_Pos)

// --------------------------------------  SCU_SFSPD_16  ------------------------------------------
#define SCU_SFSPD_16_MODE_Pos                                 0
#define SCU_SFSPD_16_MODE_Msk                                 (0x07UL << SCU_SFSPD_16_MODE_Pos)
#define SCU_SFSPD_16_EPD_Pos                                  3
#define SCU_SFSPD_16_EPD_Msk                                  (0x01UL << SCU_SFSPD_16_EPD_Pos)
#define SCU_SFSPD_16_EPUN_Pos                                 4
#define SCU_SFSPD_16_EPUN_Msk                                 (0x01UL << SCU_SFSPD_16_EPUN_Pos)
#define SCU_SFSPD_16_EHS_Pos                                  5
#define SCU_SFSPD_16_EHS_Msk                                  (0x01UL << SCU_SFSPD_16_EHS_Pos)
#define SCU_SFSPD_16_EZI_Pos                                  6
#define SCU_SFSPD_16_EZI_Msk                                  (0x01UL << SCU_SFSPD_16_EZI_Pos)
#define SCU_SFSPD_16_EHD_Pos                                  8
#define SCU_SFSPD_16_EHD_Msk                                  (0x03UL << SCU_SFSPD_16_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_0  ------------------------------------------
#define SCU_SFSPE_0_MODE_Pos                                  0
#define SCU_SFSPE_0_MODE_Msk                                  (0x07UL << SCU_SFSPE_0_MODE_Pos)
#define SCU_SFSPE_0_EPD_Pos                                   3
#define SCU_SFSPE_0_EPD_Msk                                   (0x01UL << SCU_SFSPE_0_EPD_Pos)
#define SCU_SFSPE_0_EPUN_Pos                                  4
#define SCU_SFSPE_0_EPUN_Msk                                  (0x01UL << SCU_SFSPE_0_EPUN_Pos)
#define SCU_SFSPE_0_EHS_Pos                                   5
#define SCU_SFSPE_0_EHS_Msk                                   (0x01UL << SCU_SFSPE_0_EHS_Pos)
#define SCU_SFSPE_0_EZI_Pos                                   6
#define SCU_SFSPE_0_EZI_Msk                                   (0x01UL << SCU_SFSPE_0_EZI_Pos)
#define SCU_SFSPE_0_EHD_Pos                                   8
#define SCU_SFSPE_0_EHD_Msk                                   (0x03UL << SCU_SFSPE_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_1  ------------------------------------------
#define SCU_SFSPE_1_MODE_Pos                                  0
#define SCU_SFSPE_1_MODE_Msk                                  (0x07UL << SCU_SFSPE_1_MODE_Pos)
#define SCU_SFSPE_1_EPD_Pos                                   3
#define SCU_SFSPE_1_EPD_Msk                                   (0x01UL << SCU_SFSPE_1_EPD_Pos)
#define SCU_SFSPE_1_EPUN_Pos                                  4
#define SCU_SFSPE_1_EPUN_Msk                                  (0x01UL << SCU_SFSPE_1_EPUN_Pos)
#define SCU_SFSPE_1_EHS_Pos                                   5
#define SCU_SFSPE_1_EHS_Msk                                   (0x01UL << SCU_SFSPE_1_EHS_Pos)
#define SCU_SFSPE_1_EZI_Pos                                   6
#define SCU_SFSPE_1_EZI_Msk                                   (0x01UL << SCU_SFSPE_1_EZI_Pos)
#define SCU_SFSPE_1_EHD_Pos                                   8
#define SCU_SFSPE_1_EHD_Msk                                   (0x03UL << SCU_SFSPE_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_2  ------------------------------------------
#define SCU_SFSPE_2_MODE_Pos                                  0
#define SCU_SFSPE_2_MODE_Msk                                  (0x07UL << SCU_SFSPE_2_MODE_Pos)
#define SCU_SFSPE_2_EPD_Pos                                   3
#define SCU_SFSPE_2_EPD_Msk                                   (0x01UL << SCU_SFSPE_2_EPD_Pos)
#define SCU_SFSPE_2_EPUN_Pos                                  4
#define SCU_SFSPE_2_EPUN_Msk                                  (0x01UL << SCU_SFSPE_2_EPUN_Pos)
#define SCU_SFSPE_2_EHS_Pos                                   5
#define SCU_SFSPE_2_EHS_Msk                                   (0x01UL << SCU_SFSPE_2_EHS_Pos)
#define SCU_SFSPE_2_EZI_Pos                                   6
#define SCU_SFSPE_2_EZI_Msk                                   (0x01UL << SCU_SFSPE_2_EZI_Pos)
#define SCU_SFSPE_2_EHD_Pos                                   8
#define SCU_SFSPE_2_EHD_Msk                                   (0x03UL << SCU_SFSPE_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_3  ------------------------------------------
#define SCU_SFSPE_3_MODE_Pos                                  0
#define SCU_SFSPE_3_MODE_Msk                                  (0x07UL << SCU_SFSPE_3_MODE_Pos)
#define SCU_SFSPE_3_EPD_Pos                                   3
#define SCU_SFSPE_3_EPD_Msk                                   (0x01UL << SCU_SFSPE_3_EPD_Pos)
#define SCU_SFSPE_3_EPUN_Pos                                  4
#define SCU_SFSPE_3_EPUN_Msk                                  (0x01UL << SCU_SFSPE_3_EPUN_Pos)
#define SCU_SFSPE_3_EHS_Pos                                   5
#define SCU_SFSPE_3_EHS_Msk                                   (0x01UL << SCU_SFSPE_3_EHS_Pos)
#define SCU_SFSPE_3_EZI_Pos                                   6
#define SCU_SFSPE_3_EZI_Msk                                   (0x01UL << SCU_SFSPE_3_EZI_Pos)
#define SCU_SFSPE_3_EHD_Pos                                   8
#define SCU_SFSPE_3_EHD_Msk                                   (0x03UL << SCU_SFSPE_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_4  ------------------------------------------
#define SCU_SFSPE_4_MODE_Pos                                  0
#define SCU_SFSPE_4_MODE_Msk                                  (0x07UL << SCU_SFSPE_4_MODE_Pos)
#define SCU_SFSPE_4_EPD_Pos                                   3
#define SCU_SFSPE_4_EPD_Msk                                   (0x01UL << SCU_SFSPE_4_EPD_Pos)
#define SCU_SFSPE_4_EPUN_Pos                                  4
#define SCU_SFSPE_4_EPUN_Msk                                  (0x01UL << SCU_SFSPE_4_EPUN_Pos)
#define SCU_SFSPE_4_EHS_Pos                                   5
#define SCU_SFSPE_4_EHS_Msk                                   (0x01UL << SCU_SFSPE_4_EHS_Pos)
#define SCU_SFSPE_4_EZI_Pos                                   6
#define SCU_SFSPE_4_EZI_Msk                                   (0x01UL << SCU_SFSPE_4_EZI_Pos)
#define SCU_SFSPE_4_EHD_Pos                                   8
#define SCU_SFSPE_4_EHD_Msk                                   (0x03UL << SCU_SFSPE_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_5  ------------------------------------------
#define SCU_SFSPE_5_MODE_Pos                                  0
#define SCU_SFSPE_5_MODE_Msk                                  (0x07UL << SCU_SFSPE_5_MODE_Pos)
#define SCU_SFSPE_5_EPD_Pos                                   3
#define SCU_SFSPE_5_EPD_Msk                                   (0x01UL << SCU_SFSPE_5_EPD_Pos)
#define SCU_SFSPE_5_EPUN_Pos                                  4
#define SCU_SFSPE_5_EPUN_Msk                                  (0x01UL << SCU_SFSPE_5_EPUN_Pos)
#define SCU_SFSPE_5_EHS_Pos                                   5
#define SCU_SFSPE_5_EHS_Msk                                   (0x01UL << SCU_SFSPE_5_EHS_Pos)
#define SCU_SFSPE_5_EZI_Pos                                   6
#define SCU_SFSPE_5_EZI_Msk                                   (0x01UL << SCU_SFSPE_5_EZI_Pos)
#define SCU_SFSPE_5_EHD_Pos                                   8
#define SCU_SFSPE_5_EHD_Msk                                   (0x03UL << SCU_SFSPE_5_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_6  ------------------------------------------
#define SCU_SFSPE_6_MODE_Pos                                  0
#define SCU_SFSPE_6_MODE_Msk                                  (0x07UL << SCU_SFSPE_6_MODE_Pos)
#define SCU_SFSPE_6_EPD_Pos                                   3
#define SCU_SFSPE_6_EPD_Msk                                   (0x01UL << SCU_SFSPE_6_EPD_Pos)
#define SCU_SFSPE_6_EPUN_Pos                                  4
#define SCU_SFSPE_6_EPUN_Msk                                  (0x01UL << SCU_SFSPE_6_EPUN_Pos)
#define SCU_SFSPE_6_EHS_Pos                                   5
#define SCU_SFSPE_6_EHS_Msk                                   (0x01UL << SCU_SFSPE_6_EHS_Pos)
#define SCU_SFSPE_6_EZI_Pos                                   6
#define SCU_SFSPE_6_EZI_Msk                                   (0x01UL << SCU_SFSPE_6_EZI_Pos)
#define SCU_SFSPE_6_EHD_Pos                                   8
#define SCU_SFSPE_6_EHD_Msk                                   (0x03UL << SCU_SFSPE_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_7  ------------------------------------------
#define SCU_SFSPE_7_MODE_Pos                                  0
#define SCU_SFSPE_7_MODE_Msk                                  (0x07UL << SCU_SFSPE_7_MODE_Pos)
#define SCU_SFSPE_7_EPD_Pos                                   3
#define SCU_SFSPE_7_EPD_Msk                                   (0x01UL << SCU_SFSPE_7_EPD_Pos)
#define SCU_SFSPE_7_EPUN_Pos                                  4
#define SCU_SFSPE_7_EPUN_Msk                                  (0x01UL << SCU_SFSPE_7_EPUN_Pos)
#define SCU_SFSPE_7_EHS_Pos                                   5
#define SCU_SFSPE_7_EHS_Msk                                   (0x01UL << SCU_SFSPE_7_EHS_Pos)
#define SCU_SFSPE_7_EZI_Pos                                   6
#define SCU_SFSPE_7_EZI_Msk                                   (0x01UL << SCU_SFSPE_7_EZI_Pos)
#define SCU_SFSPE_7_EHD_Pos                                   8
#define SCU_SFSPE_7_EHD_Msk                                   (0x03UL << SCU_SFSPE_7_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_8  ------------------------------------------
#define SCU_SFSPE_8_MODE_Pos                                  0
#define SCU_SFSPE_8_MODE_Msk                                  (0x07UL << SCU_SFSPE_8_MODE_Pos)
#define SCU_SFSPE_8_EPD_Pos                                   3
#define SCU_SFSPE_8_EPD_Msk                                   (0x01UL << SCU_SFSPE_8_EPD_Pos)
#define SCU_SFSPE_8_EPUN_Pos                                  4
#define SCU_SFSPE_8_EPUN_Msk                                  (0x01UL << SCU_SFSPE_8_EPUN_Pos)
#define SCU_SFSPE_8_EHS_Pos                                   5
#define SCU_SFSPE_8_EHS_Msk                                   (0x01UL << SCU_SFSPE_8_EHS_Pos)
#define SCU_SFSPE_8_EZI_Pos                                   6
#define SCU_SFSPE_8_EZI_Msk                                   (0x01UL << SCU_SFSPE_8_EZI_Pos)
#define SCU_SFSPE_8_EHD_Pos                                   8
#define SCU_SFSPE_8_EHD_Msk                                   (0x03UL << SCU_SFSPE_8_EHD_Pos)

// ---------------------------------------  SCU_SFSPE_9  ------------------------------------------
#define SCU_SFSPE_9_MODE_Pos                                  0
#define SCU_SFSPE_9_MODE_Msk                                  (0x07UL << SCU_SFSPE_9_MODE_Pos)
#define SCU_SFSPE_9_EPD_Pos                                   3
#define SCU_SFSPE_9_EPD_Msk                                   (0x01UL << SCU_SFSPE_9_EPD_Pos)
#define SCU_SFSPE_9_EPUN_Pos                                  4
#define SCU_SFSPE_9_EPUN_Msk                                  (0x01UL << SCU_SFSPE_9_EPUN_Pos)
#define SCU_SFSPE_9_EHS_Pos                                   5
#define SCU_SFSPE_9_EHS_Msk                                   (0x01UL << SCU_SFSPE_9_EHS_Pos)
#define SCU_SFSPE_9_EZI_Pos                                   6
#define SCU_SFSPE_9_EZI_Msk                                   (0x01UL << SCU_SFSPE_9_EZI_Pos)
#define SCU_SFSPE_9_EHD_Pos                                   8
#define SCU_SFSPE_9_EHD_Msk                                   (0x03UL << SCU_SFSPE_9_EHD_Pos)

// --------------------------------------  SCU_SFSPE_10  ------------------------------------------
#define SCU_SFSPE_10_MODE_Pos                                 0
#define SCU_SFSPE_10_MODE_Msk                                 (0x07UL << SCU_SFSPE_10_MODE_Pos)
#define SCU_SFSPE_10_EPD_Pos                                  3
#define SCU_SFSPE_10_EPD_Msk                                  (0x01UL << SCU_SFSPE_10_EPD_Pos)
#define SCU_SFSPE_10_EPUN_Pos                                 4
#define SCU_SFSPE_10_EPUN_Msk                                 (0x01UL << SCU_SFSPE_10_EPUN_Pos)
#define SCU_SFSPE_10_EHS_Pos                                  5
#define SCU_SFSPE_10_EHS_Msk                                  (0x01UL << SCU_SFSPE_10_EHS_Pos)
#define SCU_SFSPE_10_EZI_Pos                                  6
#define SCU_SFSPE_10_EZI_Msk                                  (0x01UL << SCU_SFSPE_10_EZI_Pos)
#define SCU_SFSPE_10_EHD_Pos                                  8
#define SCU_SFSPE_10_EHD_Msk                                  (0x03UL << SCU_SFSPE_10_EHD_Pos)

// --------------------------------------  SCU_SFSPE_11  ------------------------------------------
#define SCU_SFSPE_11_MODE_Pos                                 0
#define SCU_SFSPE_11_MODE_Msk                                 (0x07UL << SCU_SFSPE_11_MODE_Pos)
#define SCU_SFSPE_11_EPD_Pos                                  3
#define SCU_SFSPE_11_EPD_Msk                                  (0x01UL << SCU_SFSPE_11_EPD_Pos)
#define SCU_SFSPE_11_EPUN_Pos                                 4
#define SCU_SFSPE_11_EPUN_Msk                                 (0x01UL << SCU_SFSPE_11_EPUN_Pos)
#define SCU_SFSPE_11_EHS_Pos                                  5
#define SCU_SFSPE_11_EHS_Msk                                  (0x01UL << SCU_SFSPE_11_EHS_Pos)
#define SCU_SFSPE_11_EZI_Pos                                  6
#define SCU_SFSPE_11_EZI_Msk                                  (0x01UL << SCU_SFSPE_11_EZI_Pos)
#define SCU_SFSPE_11_EHD_Pos                                  8
#define SCU_SFSPE_11_EHD_Msk                                  (0x03UL << SCU_SFSPE_11_EHD_Pos)

// --------------------------------------  SCU_SFSPE_12  ------------------------------------------
#define SCU_SFSPE_12_MODE_Pos                                 0
#define SCU_SFSPE_12_MODE_Msk                                 (0x07UL << SCU_SFSPE_12_MODE_Pos)
#define SCU_SFSPE_12_EPD_Pos                                  3
#define SCU_SFSPE_12_EPD_Msk                                  (0x01UL << SCU_SFSPE_12_EPD_Pos)
#define SCU_SFSPE_12_EPUN_Pos                                 4
#define SCU_SFSPE_12_EPUN_Msk                                 (0x01UL << SCU_SFSPE_12_EPUN_Pos)
#define SCU_SFSPE_12_EHS_Pos                                  5
#define SCU_SFSPE_12_EHS_Msk                                  (0x01UL << SCU_SFSPE_12_EHS_Pos)
#define SCU_SFSPE_12_EZI_Pos                                  6
#define SCU_SFSPE_12_EZI_Msk                                  (0x01UL << SCU_SFSPE_12_EZI_Pos)
#define SCU_SFSPE_12_EHD_Pos                                  8
#define SCU_SFSPE_12_EHD_Msk                                  (0x03UL << SCU_SFSPE_12_EHD_Pos)

// --------------------------------------  SCU_SFSPE_13  ------------------------------------------
#define SCU_SFSPE_13_MODE_Pos                                 0
#define SCU_SFSPE_13_MODE_Msk                                 (0x07UL << SCU_SFSPE_13_MODE_Pos)
#define SCU_SFSPE_13_EPD_Pos                                  3
#define SCU_SFSPE_13_EPD_Msk                                  (0x01UL << SCU_SFSPE_13_EPD_Pos)
#define SCU_SFSPE_13_EPUN_Pos                                 4
#define SCU_SFSPE_13_EPUN_Msk                                 (0x01UL << SCU_SFSPE_13_EPUN_Pos)
#define SCU_SFSPE_13_EHS_Pos                                  5
#define SCU_SFSPE_13_EHS_Msk                                  (0x01UL << SCU_SFSPE_13_EHS_Pos)
#define SCU_SFSPE_13_EZI_Pos                                  6
#define SCU_SFSPE_13_EZI_Msk                                  (0x01UL << SCU_SFSPE_13_EZI_Pos)
#define SCU_SFSPE_13_EHD_Pos                                  8
#define SCU_SFSPE_13_EHD_Msk                                  (0x03UL << SCU_SFSPE_13_EHD_Pos)

// --------------------------------------  SCU_SFSPE_14  ------------------------------------------
#define SCU_SFSPE_14_MODE_Pos                                 0
#define SCU_SFSPE_14_MODE_Msk                                 (0x07UL << SCU_SFSPE_14_MODE_Pos)
#define SCU_SFSPE_14_EPD_Pos                                  3
#define SCU_SFSPE_14_EPD_Msk                                  (0x01UL << SCU_SFSPE_14_EPD_Pos)
#define SCU_SFSPE_14_EPUN_Pos                                 4
#define SCU_SFSPE_14_EPUN_Msk                                 (0x01UL << SCU_SFSPE_14_EPUN_Pos)
#define SCU_SFSPE_14_EHS_Pos                                  5
#define SCU_SFSPE_14_EHS_Msk                                  (0x01UL << SCU_SFSPE_14_EHS_Pos)
#define SCU_SFSPE_14_EZI_Pos                                  6
#define SCU_SFSPE_14_EZI_Msk                                  (0x01UL << SCU_SFSPE_14_EZI_Pos)
#define SCU_SFSPE_14_EHD_Pos                                  8
#define SCU_SFSPE_14_EHD_Msk                                  (0x03UL << SCU_SFSPE_14_EHD_Pos)

// --------------------------------------  SCU_SFSPE_15  ------------------------------------------
#define SCU_SFSPE_15_MODE_Pos                                 0
#define SCU_SFSPE_15_MODE_Msk                                 (0x07UL << SCU_SFSPE_15_MODE_Pos)
#define SCU_SFSPE_15_EPD_Pos                                  3
#define SCU_SFSPE_15_EPD_Msk                                  (0x01UL << SCU_SFSPE_15_EPD_Pos)
#define SCU_SFSPE_15_EPUN_Pos                                 4
#define SCU_SFSPE_15_EPUN_Msk                                 (0x01UL << SCU_SFSPE_15_EPUN_Pos)
#define SCU_SFSPE_15_EHS_Pos                                  5
#define SCU_SFSPE_15_EHS_Msk                                  (0x01UL << SCU_SFSPE_15_EHS_Pos)
#define SCU_SFSPE_15_EZI_Pos                                  6
#define SCU_SFSPE_15_EZI_Msk                                  (0x01UL << SCU_SFSPE_15_EZI_Pos)
#define SCU_SFSPE_15_EHD_Pos                                  8
#define SCU_SFSPE_15_EHD_Msk                                  (0x03UL << SCU_SFSPE_15_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_0  ------------------------------------------
#define SCU_SFSPF_0_MODE_Pos                                  0
#define SCU_SFSPF_0_MODE_Msk                                  (0x07UL << SCU_SFSPF_0_MODE_Pos)
#define SCU_SFSPF_0_EPD_Pos                                   3
#define SCU_SFSPF_0_EPD_Msk                                   (0x01UL << SCU_SFSPF_0_EPD_Pos)
#define SCU_SFSPF_0_EPUN_Pos                                  4
#define SCU_SFSPF_0_EPUN_Msk                                  (0x01UL << SCU_SFSPF_0_EPUN_Pos)
#define SCU_SFSPF_0_EHS_Pos                                   5
#define SCU_SFSPF_0_EHS_Msk                                   (0x01UL << SCU_SFSPF_0_EHS_Pos)
#define SCU_SFSPF_0_EZI_Pos                                   6
#define SCU_SFSPF_0_EZI_Msk                                   (0x01UL << SCU_SFSPF_0_EZI_Pos)
#define SCU_SFSPF_0_EHD_Pos                                   8
#define SCU_SFSPF_0_EHD_Msk                                   (0x03UL << SCU_SFSPF_0_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_1  ------------------------------------------
#define SCU_SFSPF_1_MODE_Pos                                  0
#define SCU_SFSPF_1_MODE_Msk                                  (0x07UL << SCU_SFSPF_1_MODE_Pos)
#define SCU_SFSPF_1_EPD_Pos                                   3
#define SCU_SFSPF_1_EPD_Msk                                   (0x01UL << SCU_SFSPF_1_EPD_Pos)
#define SCU_SFSPF_1_EPUN_Pos                                  4
#define SCU_SFSPF_1_EPUN_Msk                                  (0x01UL << SCU_SFSPF_1_EPUN_Pos)
#define SCU_SFSPF_1_EHS_Pos                                   5
#define SCU_SFSPF_1_EHS_Msk                                   (0x01UL << SCU_SFSPF_1_EHS_Pos)
#define SCU_SFSPF_1_EZI_Pos                                   6
#define SCU_SFSPF_1_EZI_Msk                                   (0x01UL << SCU_SFSPF_1_EZI_Pos)
#define SCU_SFSPF_1_EHD_Pos                                   8
#define SCU_SFSPF_1_EHD_Msk                                   (0x03UL << SCU_SFSPF_1_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_2  ------------------------------------------
#define SCU_SFSPF_2_MODE_Pos                                  0
#define SCU_SFSPF_2_MODE_Msk                                  (0x07UL << SCU_SFSPF_2_MODE_Pos)
#define SCU_SFSPF_2_EPD_Pos                                   3
#define SCU_SFSPF_2_EPD_Msk                                   (0x01UL << SCU_SFSPF_2_EPD_Pos)
#define SCU_SFSPF_2_EPUN_Pos                                  4
#define SCU_SFSPF_2_EPUN_Msk                                  (0x01UL << SCU_SFSPF_2_EPUN_Pos)
#define SCU_SFSPF_2_EHS_Pos                                   5
#define SCU_SFSPF_2_EHS_Msk                                   (0x01UL << SCU_SFSPF_2_EHS_Pos)
#define SCU_SFSPF_2_EZI_Pos                                   6
#define SCU_SFSPF_2_EZI_Msk                                   (0x01UL << SCU_SFSPF_2_EZI_Pos)
#define SCU_SFSPF_2_EHD_Pos                                   8
#define SCU_SFSPF_2_EHD_Msk                                   (0x03UL << SCU_SFSPF_2_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_3  ------------------------------------------
#define SCU_SFSPF_3_MODE_Pos                                  0
#define SCU_SFSPF_3_MODE_Msk                                  (0x07UL << SCU_SFSPF_3_MODE_Pos)
#define SCU_SFSPF_3_EPD_Pos                                   3
#define SCU_SFSPF_3_EPD_Msk                                   (0x01UL << SCU_SFSPF_3_EPD_Pos)
#define SCU_SFSPF_3_EPUN_Pos                                  4
#define SCU_SFSPF_3_EPUN_Msk                                  (0x01UL << SCU_SFSPF_3_EPUN_Pos)
#define SCU_SFSPF_3_EHS_Pos                                   5
#define SCU_SFSPF_3_EHS_Msk                                   (0x01UL << SCU_SFSPF_3_EHS_Pos)
#define SCU_SFSPF_3_EZI_Pos                                   6
#define SCU_SFSPF_3_EZI_Msk                                   (0x01UL << SCU_SFSPF_3_EZI_Pos)
#define SCU_SFSPF_3_EHD_Pos                                   8
#define SCU_SFSPF_3_EHD_Msk                                   (0x03UL << SCU_SFSPF_3_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_4  ------------------------------------------
#define SCU_SFSPF_4_MODE_Pos                                  0
#define SCU_SFSPF_4_MODE_Msk                                  (0x07UL << SCU_SFSPF_4_MODE_Pos)
#define SCU_SFSPF_4_EPD_Pos                                   3
#define SCU_SFSPF_4_EPD_Msk                                   (0x01UL << SCU_SFSPF_4_EPD_Pos)
#define SCU_SFSPF_4_EPUN_Pos                                  4
#define SCU_SFSPF_4_EPUN_Msk                                  (0x01UL << SCU_SFSPF_4_EPUN_Pos)
#define SCU_SFSPF_4_EHS_Pos                                   5
#define SCU_SFSPF_4_EHS_Msk                                   (0x01UL << SCU_SFSPF_4_EHS_Pos)
#define SCU_SFSPF_4_EZI_Pos                                   6
#define SCU_SFSPF_4_EZI_Msk                                   (0x01UL << SCU_SFSPF_4_EZI_Pos)
#define SCU_SFSPF_4_EHD_Pos                                   8
#define SCU_SFSPF_4_EHD_Msk                                   (0x03UL << SCU_SFSPF_4_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_5  ------------------------------------------
#define SCU_SFSPF_5_MODE_Pos                                  0
#define SCU_SFSPF_5_MODE_Msk                                  (0x07UL << SCU_SFSPF_5_MODE_Pos)
#define SCU_SFSPF_5_EPD_Pos                                   3
#define SCU_SFSPF_5_EPD_Msk                                   (0x01UL << SCU_SFSPF_5_EPD_Pos)
#define SCU_SFSPF_5_EPUN_Pos                                  4
#define SCU_SFSPF_5_EPUN_Msk                                  (0x01UL << SCU_SFSPF_5_EPUN_Pos)
#define SCU_SFSPF_5_EHS_Pos                                   5
#define SCU_SFSPF_5_EHS_Msk                                   (0x01UL << SCU_SFSPF_5_EHS_Pos)
#define SCU_SFSPF_5_EZI_Pos                                   6
#define SCU_SFSPF_5_EZI_Msk                                   (0x01UL << SCU_SFSPF_5_EZI_Pos)
#define SCU_SFSPF_5_EHD_Pos                                   8
#define SCU_SFSPF_5_EHD_Msk                                   (0x03UL << SCU_SFSPF_5_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_6  ------------------------------------------
#define SCU_SFSPF_6_MODE_Pos                                  0
#define SCU_SFSPF_6_MODE_Msk                                  (0x07UL << SCU_SFSPF_6_MODE_Pos)
#define SCU_SFSPF_6_EPD_Pos                                   3
#define SCU_SFSPF_6_EPD_Msk                                   (0x01UL << SCU_SFSPF_6_EPD_Pos)
#define SCU_SFSPF_6_EPUN_Pos                                  4
#define SCU_SFSPF_6_EPUN_Msk                                  (0x01UL << SCU_SFSPF_6_EPUN_Pos)
#define SCU_SFSPF_6_EHS_Pos                                   5
#define SCU_SFSPF_6_EHS_Msk                                   (0x01UL << SCU_SFSPF_6_EHS_Pos)
#define SCU_SFSPF_6_EZI_Pos                                   6
#define SCU_SFSPF_6_EZI_Msk                                   (0x01UL << SCU_SFSPF_6_EZI_Pos)
#define SCU_SFSPF_6_EHD_Pos                                   8
#define SCU_SFSPF_6_EHD_Msk                                   (0x03UL << SCU_SFSPF_6_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_7  ------------------------------------------
#define SCU_SFSPF_7_MODE_Pos                                  0
#define SCU_SFSPF_7_MODE_Msk                                  (0x07UL << SCU_SFSPF_7_MODE_Pos)
#define SCU_SFSPF_7_EPD_Pos                                   3
#define SCU_SFSPF_7_EPD_Msk                                   (0x01UL << SCU_SFSPF_7_EPD_Pos)
#define SCU_SFSPF_7_EPUN_Pos                                  4
#define SCU_SFSPF_7_EPUN_Msk                                  (0x01UL << SCU_SFSPF_7_EPUN_Pos)
#define SCU_SFSPF_7_EHS_Pos                                   5
#define SCU_SFSPF_7_EHS_Msk                                   (0x01UL << SCU_SFSPF_7_EHS_Pos)
#define SCU_SFSPF_7_EZI_Pos                                   6
#define SCU_SFSPF_7_EZI_Msk                                   (0x01UL << SCU_SFSPF_7_EZI_Pos)
#define SCU_SFSPF_7_EHD_Pos                                   8
#define SCU_SFSPF_7_EHD_Msk                                   (0x03UL << SCU_SFSPF_7_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_8  ------------------------------------------
#define SCU_SFSPF_8_MODE_Pos                                  0
#define SCU_SFSPF_8_MODE_Msk                                  (0x07UL << SCU_SFSPF_8_MODE_Pos)
#define SCU_SFSPF_8_EPD_Pos                                   3
#define SCU_SFSPF_8_EPD_Msk                                   (0x01UL << SCU_SFSPF_8_EPD_Pos)
#define SCU_SFSPF_8_EPUN_Pos                                  4
#define SCU_SFSPF_8_EPUN_Msk                                  (0x01UL << SCU_SFSPF_8_EPUN_Pos)
#define SCU_SFSPF_8_EHS_Pos                                   5
#define SCU_SFSPF_8_EHS_Msk                                   (0x01UL << SCU_SFSPF_8_EHS_Pos)
#define SCU_SFSPF_8_EZI_Pos                                   6
#define SCU_SFSPF_8_EZI_Msk                                   (0x01UL << SCU_SFSPF_8_EZI_Pos)
#define SCU_SFSPF_8_EHD_Pos                                   8
#define SCU_SFSPF_8_EHD_Msk                                   (0x03UL << SCU_SFSPF_8_EHD_Pos)

// ---------------------------------------  SCU_SFSPF_9  ------------------------------------------
#define SCU_SFSPF_9_MODE_Pos                                  0
#define SCU_SFSPF_9_MODE_Msk                                  (0x07UL << SCU_SFSPF_9_MODE_Pos)
#define SCU_SFSPF_9_EPD_Pos                                   3
#define SCU_SFSPF_9_EPD_Msk                                   (0x01UL << SCU_SFSPF_9_EPD_Pos)
#define SCU_SFSPF_9_EPUN_Pos                                  4
#define SCU_SFSPF_9_EPUN_Msk                                  (0x01UL << SCU_SFSPF_9_EPUN_Pos)
#define SCU_SFSPF_9_EHS_Pos                                   5
#define SCU_SFSPF_9_EHS_Msk                                   (0x01UL << SCU_SFSPF_9_EHS_Pos)
#define SCU_SFSPF_9_EZI_Pos                                   6
#define SCU_SFSPF_9_EZI_Msk                                   (0x01UL << SCU_SFSPF_9_EZI_Pos)
#define SCU_SFSPF_9_EHD_Pos                                   8
#define SCU_SFSPF_9_EHD_Msk                                   (0x03UL << SCU_SFSPF_9_EHD_Pos)

// --------------------------------------  SCU_SFSPF_10  ------------------------------------------
#define SCU_SFSPF_10_MODE_Pos                                 0
#define SCU_SFSPF_10_MODE_Msk                                 (0x07UL << SCU_SFSPF_10_MODE_Pos)
#define SCU_SFSPF_10_EPD_Pos                                  3
#define SCU_SFSPF_10_EPD_Msk                                  (0x01UL << SCU_SFSPF_10_EPD_Pos)
#define SCU_SFSPF_10_EPUN_Pos                                 4
#define SCU_SFSPF_10_EPUN_Msk                                 (0x01UL << SCU_SFSPF_10_EPUN_Pos)
#define SCU_SFSPF_10_EHS_Pos                                  5
#define SCU_SFSPF_10_EHS_Msk                                  (0x01UL << SCU_SFSPF_10_EHS_Pos)
#define SCU_SFSPF_10_EZI_Pos                                  6
#define SCU_SFSPF_10_EZI_Msk                                  (0x01UL << SCU_SFSPF_10_EZI_Pos)
#define SCU_SFSPF_10_EHD_Pos                                  8
#define SCU_SFSPF_10_EHD_Msk                                  (0x03UL << SCU_SFSPF_10_EHD_Pos)

// --------------------------------------  SCU_SFSPF_11  ------------------------------------------
#define SCU_SFSPF_11_MODE_Pos                                 0
#define SCU_SFSPF_11_MODE_Msk                                 (0x07UL << SCU_SFSPF_11_MODE_Pos)
#define SCU_SFSPF_11_EPD_Pos                                  3
#define SCU_SFSPF_11_EPD_Msk                                  (0x01UL << SCU_SFSPF_11_EPD_Pos)
#define SCU_SFSPF_11_EPUN_Pos                                 4
#define SCU_SFSPF_11_EPUN_Msk                                 (0x01UL << SCU_SFSPF_11_EPUN_Pos)
#define SCU_SFSPF_11_EHS_Pos                                  5
#define SCU_SFSPF_11_EHS_Msk                                  (0x01UL << SCU_SFSPF_11_EHS_Pos)
#define SCU_SFSPF_11_EZI_Pos                                  6
#define SCU_SFSPF_11_EZI_Msk                                  (0x01UL << SCU_SFSPF_11_EZI_Pos)
#define SCU_SFSPF_11_EHD_Pos                                  8
#define SCU_SFSPF_11_EHD_Msk                                  (0x03UL << SCU_SFSPF_11_EHD_Pos)

// --------------------------------------  SCU_SFSCLK_0  ------------------------------------------
#define SCU_SFSCLK_0_MODE_Pos                                 0
#define SCU_SFSCLK_0_MODE_Msk                                 (0x07UL << SCU_SFSCLK_0_MODE_Pos)
#define SCU_SFSCLK_0_EPD_Pos                                  3
#define SCU_SFSCLK_0_EPD_Msk                                  (0x01UL << SCU_SFSCLK_0_EPD_Pos)
#define SCU_SFSCLK_0_EPUN_Pos                                 4
#define SCU_SFSCLK_0_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_0_EPUN_Pos)
#define SCU_SFSCLK_0_EHS_Pos                                  5
#define SCU_SFSCLK_0_EHS_Msk                                  (0x01UL << SCU_SFSCLK_0_EHS_Pos)
#define SCU_SFSCLK_0_EZI_Pos                                  6
#define SCU_SFSCLK_0_EZI_Msk                                  (0x01UL << SCU_SFSCLK_0_EZI_Pos)
#define SCU_SFSCLK_0_EHD_Pos                                  8
#define SCU_SFSCLK_0_EHD_Msk                                  (0x03UL << SCU_SFSCLK_0_EHD_Pos)

// --------------------------------------  SCU_SFSCLK_1  ------------------------------------------
#define SCU_SFSCLK_1_MODE_Pos                                 0
#define SCU_SFSCLK_1_MODE_Msk                                 (0x07UL << SCU_SFSCLK_1_MODE_Pos)
#define SCU_SFSCLK_1_EPD_Pos                                  3
#define SCU_SFSCLK_1_EPD_Msk                                  (0x01UL << SCU_SFSCLK_1_EPD_Pos)
#define SCU_SFSCLK_1_EPUN_Pos                                 4
#define SCU_SFSCLK_1_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_1_EPUN_Pos)
#define SCU_SFSCLK_1_EHS_Pos                                  5
#define SCU_SFSCLK_1_EHS_Msk                                  (0x01UL << SCU_SFSCLK_1_EHS_Pos)
#define SCU_SFSCLK_1_EZI_Pos                                  6
#define SCU_SFSCLK_1_EZI_Msk                                  (0x01UL << SCU_SFSCLK_1_EZI_Pos)
#define SCU_SFSCLK_1_EHD_Pos                                  8
#define SCU_SFSCLK_1_EHD_Msk                                  (0x03UL << SCU_SFSCLK_1_EHD_Pos)

// --------------------------------------  SCU_SFSCLK_2  ------------------------------------------
#define SCU_SFSCLK_2_MODE_Pos                                 0
#define SCU_SFSCLK_2_MODE_Msk                                 (0x07UL << SCU_SFSCLK_2_MODE_Pos)
#define SCU_SFSCLK_2_EPD_Pos                                  3
#define SCU_SFSCLK_2_EPD_Msk                                  (0x01UL << SCU_SFSCLK_2_EPD_Pos)
#define SCU_SFSCLK_2_EPUN_Pos                                 4
#define SCU_SFSCLK_2_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_2_EPUN_Pos)
#define SCU_SFSCLK_2_EHS_Pos                                  5
#define SCU_SFSCLK_2_EHS_Msk                                  (0x01UL << SCU_SFSCLK_2_EHS_Pos)
#define SCU_SFSCLK_2_EZI_Pos                                  6
#define SCU_SFSCLK_2_EZI_Msk                                  (0x01UL << SCU_SFSCLK_2_EZI_Pos)
#define SCU_SFSCLK_2_EHD_Pos                                  8
#define SCU_SFSCLK_2_EHD_Msk                                  (0x03UL << SCU_SFSCLK_2_EHD_Pos)

// --------------------------------------  SCU_SFSCLK_3  ------------------------------------------
#define SCU_SFSCLK_3_MODE_Pos                                 0
#define SCU_SFSCLK_3_MODE_Msk                                 (0x07UL << SCU_SFSCLK_3_MODE_Pos)
#define SCU_SFSCLK_3_EPD_Pos                                  3
#define SCU_SFSCLK_3_EPD_Msk                                  (0x01UL << SCU_SFSCLK_3_EPD_Pos)
#define SCU_SFSCLK_3_EPUN_Pos                                 4
#define SCU_SFSCLK_3_EPUN_Msk                                 (0x01UL << SCU_SFSCLK_3_EPUN_Pos)
#define SCU_SFSCLK_3_EHS_Pos                                  5
#define SCU_SFSCLK_3_EHS_Msk                                  (0x01UL << SCU_SFSCLK_3_EHS_Pos)
#define SCU_SFSCLK_3_EZI_Pos                                  6
#define SCU_SFSCLK_3_EZI_Msk                                  (0x01UL << SCU_SFSCLK_3_EZI_Pos)
#define SCU_SFSCLK_3_EHD_Pos                                  8
#define SCU_SFSCLK_3_EHD_Msk                                  (0x03UL << SCU_SFSCLK_3_EHD_Pos)

// ---------------------------------------  SCU_SFSUSB  -------------------------------------------
#define SCU_SFSUSB_USB_AIM_Pos                                0
#define SCU_SFSUSB_USB_AIM_Msk                                (0x01UL << SCU_SFSUSB_USB_AIM_Pos)
#define SCU_SFSUSB_USB_ESEA_Pos                               1
#define SCU_SFSUSB_USB_ESEA_Msk                               (0x01UL << SCU_SFSUSB_USB_ESEA_Pos)

// ---------------------------------------  SCU_SFSI2C0  ------------------------------------------
#define SCU_SFSI2C0_SDA_EHS_Pos                               0
#define SCU_SFSI2C0_SDA_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos)
#define SCU_SFSI2C0_SCL_EHS_Pos                               1
#define SCU_SFSI2C0_SCL_EHS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos)
#define SCU_SFSI2C0_SCL_ECS_Pos                               2
#define SCU_SFSI2C0_SCL_ECS_Msk                               (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos)

// ---------------------------------------  SCU_ENAIO0  -------------------------------------------
#define SCU_ENAIO0_ADC0_0_Pos                                 0
#define SCU_ENAIO0_ADC0_0_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_0_Pos)
#define SCU_ENAIO0_ADC0_1_Pos                                 1
#define SCU_ENAIO0_ADC0_1_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_1_Pos)
#define SCU_ENAIO0_ADC0_2_Pos                                 2
#define SCU_ENAIO0_ADC0_2_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_2_Pos)
#define SCU_ENAIO0_ADC0_3_Pos                                 3
#define SCU_ENAIO0_ADC0_3_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_3_Pos)
#define SCU_ENAIO0_ADC0_4_Pos                                 4
#define SCU_ENAIO0_ADC0_4_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_4_Pos)
#define SCU_ENAIO0_ADC0_5_Pos                                 5
#define SCU_ENAIO0_ADC0_5_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_5_Pos)
#define SCU_ENAIO0_ADC0_6_Pos                                 6
#define SCU_ENAIO0_ADC0_6_Msk                                 (0x01UL << SCU_ENAIO0_ADC0_6_Pos)

// ---------------------------------------  SCU_ENAIO1  -------------------------------------------
#define SCU_ENAIO1_ADC1_0_Pos                                 0
#define SCU_ENAIO1_ADC1_0_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_0_Pos)
#define SCU_ENAIO1_ADC1_1_Pos                                 1
#define SCU_ENAIO1_ADC1_1_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_1_Pos)
#define SCU_ENAIO1_ADC1_2_Pos                                 2
#define SCU_ENAIO1_ADC1_2_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_2_Pos)
#define SCU_ENAIO1_ADC1_3_Pos                                 3
#define SCU_ENAIO1_ADC1_3_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_3_Pos)
#define SCU_ENAIO1_ADC1_4_Pos                                 4
#define SCU_ENAIO1_ADC1_4_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_4_Pos)
#define SCU_ENAIO1_ADC1_5_Pos                                 5
#define SCU_ENAIO1_ADC1_5_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_5_Pos)
#define SCU_ENAIO1_ADC1_6_Pos                                 6
#define SCU_ENAIO1_ADC1_6_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_6_Pos)
#define SCU_ENAIO1_ADC1_7_Pos                                 7
#define SCU_ENAIO1_ADC1_7_Msk                                 (0x01UL << SCU_ENAIO1_ADC1_7_Pos)

// ---------------------------------------  SCU_ENAIO2  -------------------------------------------
#define SCU_ENAIO2_DAC_Pos                                    0
#define SCU_ENAIO2_DAC_Msk                                    (0x01UL << SCU_ENAIO2_DAC_Pos)
#define SCU_ENAIO2_BG_Pos                                     4
#define SCU_ENAIO2_BG_Msk                                     (0x01UL << SCU_ENAIO2_BG_Pos)

// -------------------------------------  SCU_EMCDELAYCLK  ----------------------------------------
#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos                        0
#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos)
#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos                        4
#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos)
#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos                        8
#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos)
#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos                        12
#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos)
#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos                        16
#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos)
#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos                        20
#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos)
#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos                        24
#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos)
#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos                        28
#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk                        (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos)

// --------------------------------------  SCU_PINTSEL0  ------------------------------------------
#define SCU_PINTSEL0_INTPIN0_Pos                              0
#define SCU_PINTSEL0_INTPIN0_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos)
#define SCU_PINTSEL0_PORTSEL0_Pos                             5
#define SCU_PINTSEL0_PORTSEL0_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos)
#define SCU_PINTSEL0_INTPIN1_Pos                              8
#define SCU_PINTSEL0_INTPIN1_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos)
#define SCU_PINTSEL0_PORTSEL1_Pos                             13
#define SCU_PINTSEL0_PORTSEL1_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos)
#define SCU_PINTSEL0_INTPIN2_Pos                              16
#define SCU_PINTSEL0_INTPIN2_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos)
#define SCU_PINTSEL0_PORTSEL2_Pos                             21
#define SCU_PINTSEL0_PORTSEL2_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos)
#define SCU_PINTSEL0_INTPIN3_Pos                              24
#define SCU_PINTSEL0_INTPIN3_Msk                              (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos)
#define SCU_PINTSEL0_PORTSEL3_Pos                             29
#define SCU_PINTSEL0_PORTSEL3_Msk                             (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos)

// --------------------------------------  SCU_PINTSEL1  ------------------------------------------
#define SCU_PINTSEL1_INTPIN4_Pos                              0
#define SCU_PINTSEL1_INTPIN4_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos)
#define SCU_PINTSEL1_PORTSEL4_Pos                             5
#define SCU_PINTSEL1_PORTSEL4_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos)
#define SCU_PINTSEL1_INTPIN5_Pos                              8
#define SCU_PINTSEL1_INTPIN5_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos)
#define SCU_PINTSEL1_PORTSEL5_Pos                             13
#define SCU_PINTSEL1_PORTSEL5_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos)
#define SCU_PINTSEL1_INTPIN6_Pos                              16
#define SCU_PINTSEL1_INTPIN6_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos)
#define SCU_PINTSEL1_PORTSEL6_Pos                             21
#define SCU_PINTSEL1_PORTSEL6_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos)
#define SCU_PINTSEL1_INTPIN7_Pos                              24
#define SCU_PINTSEL1_INTPIN7_Msk                              (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos)
#define SCU_PINTSEL1_PORTSEL7_Pos                             29
#define SCU_PINTSEL1_PORTSEL7_Msk                             (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos)


// ------------------------------------------------------------------------------------------------
// -----                             GPIO_PIN_INT Position & Mask                             -----
// ------------------------------------------------------------------------------------------------


// ------------------------------------  GPIO_PIN_INT_ISEL  ---------------------------------------
#define GPIO_PIN_INT_ISEL_PMODE0_Pos                          0
#define GPIO_PIN_INT_ISEL_PMODE0_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos)
#define GPIO_PIN_INT_ISEL_PMODE1_Pos                          1
#define GPIO_PIN_INT_ISEL_PMODE1_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos)
#define GPIO_PIN_INT_ISEL_PMODE2_Pos                          2
#define GPIO_PIN_INT_ISEL_PMODE2_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos)
#define GPIO_PIN_INT_ISEL_PMODE3_Pos                          3
#define GPIO_PIN_INT_ISEL_PMODE3_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos)
#define GPIO_PIN_INT_ISEL_PMODE4_Pos                          4
#define GPIO_PIN_INT_ISEL_PMODE4_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos)
#define GPIO_PIN_INT_ISEL_PMODE5_Pos                          5
#define GPIO_PIN_INT_ISEL_PMODE5_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos)
#define GPIO_PIN_INT_ISEL_PMODE6_Pos                          6
#define GPIO_PIN_INT_ISEL_PMODE6_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos)
#define GPIO_PIN_INT_ISEL_PMODE7_Pos                          7
#define GPIO_PIN_INT_ISEL_PMODE7_Msk                          (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos)

// ------------------------------------  GPIO_PIN_INT_IENR  ---------------------------------------
#define GPIO_PIN_INT_IENR_ENRL0_Pos                           0
#define GPIO_PIN_INT_IENR_ENRL0_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos)
#define GPIO_PIN_INT_IENR_ENRL1_Pos                           1
#define GPIO_PIN_INT_IENR_ENRL1_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos)
#define GPIO_PIN_INT_IENR_ENRL2_Pos                           2
#define GPIO_PIN_INT_IENR_ENRL2_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos)
#define GPIO_PIN_INT_IENR_ENRL3_Pos                           3
#define GPIO_PIN_INT_IENR_ENRL3_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos)
#define GPIO_PIN_INT_IENR_ENRL4_Pos                           4
#define GPIO_PIN_INT_IENR_ENRL4_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos)
#define GPIO_PIN_INT_IENR_ENRL5_Pos                           5
#define GPIO_PIN_INT_IENR_ENRL5_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos)
#define GPIO_PIN_INT_IENR_ENRL6_Pos                           6
#define GPIO_PIN_INT_IENR_ENRL6_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos)
#define GPIO_PIN_INT_IENR_ENRL7_Pos                           7
#define GPIO_PIN_INT_IENR_ENRL7_Msk                           (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos)

// -----------------------------------  GPIO_PIN_INT_SIENR  ---------------------------------------
#define GPIO_PIN_INT_SIENR_SETENRL0_Pos                       0
#define GPIO_PIN_INT_SIENR_SETENRL0_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL1_Pos                       1
#define GPIO_PIN_INT_SIENR_SETENRL1_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL2_Pos                       2
#define GPIO_PIN_INT_SIENR_SETENRL2_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL3_Pos                       3
#define GPIO_PIN_INT_SIENR_SETENRL3_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL4_Pos                       4
#define GPIO_PIN_INT_SIENR_SETENRL4_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL5_Pos                       5
#define GPIO_PIN_INT_SIENR_SETENRL5_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL6_Pos                       6
#define GPIO_PIN_INT_SIENR_SETENRL6_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos)
#define GPIO_PIN_INT_SIENR_SETENRL7_Pos                       7
#define GPIO_PIN_INT_SIENR_SETENRL7_Msk                       (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos)

// -----------------------------------  GPIO_PIN_INT_CIENR  ---------------------------------------
#define GPIO_PIN_INT_CIENR_CENRL0_Pos                         0
#define GPIO_PIN_INT_CIENR_CENRL0_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos)
#define GPIO_PIN_INT_CIENR_CENRL1_Pos                         1
#define GPIO_PIN_INT_CIENR_CENRL1_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos)
#define GPIO_PIN_INT_CIENR_CENRL2_Pos                         2
#define GPIO_PIN_INT_CIENR_CENRL2_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos)
#define GPIO_PIN_INT_CIENR_CENRL3_Pos                         3
#define GPIO_PIN_INT_CIENR_CENRL3_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos)
#define GPIO_PIN_INT_CIENR_CENRL4_Pos                         4
#define GPIO_PIN_INT_CIENR_CENRL4_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos)
#define GPIO_PIN_INT_CIENR_CENRL5_Pos                         5
#define GPIO_PIN_INT_CIENR_CENRL5_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos)
#define GPIO_PIN_INT_CIENR_CENRL6_Pos                         6
#define GPIO_PIN_INT_CIENR_CENRL6_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos)
#define GPIO_PIN_INT_CIENR_CENRL7_Pos                         7
#define GPIO_PIN_INT_CIENR_CENRL7_Msk                         (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos)

// ------------------------------------  GPIO_PIN_INT_IENF  ---------------------------------------
#define GPIO_PIN_INT_IENF_ENAF0_Pos                           0
#define GPIO_PIN_INT_IENF_ENAF0_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos)
#define GPIO_PIN_INT_IENF_ENAF1_Pos                           1
#define GPIO_PIN_INT_IENF_ENAF1_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos)
#define GPIO_PIN_INT_IENF_ENAF2_Pos                           2
#define GPIO_PIN_INT_IENF_ENAF2_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos)
#define GPIO_PIN_INT_IENF_ENAF3_Pos                           3
#define GPIO_PIN_INT_IENF_ENAF3_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos)
#define GPIO_PIN_INT_IENF_ENAF4_Pos                           4
#define GPIO_PIN_INT_IENF_ENAF4_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos)
#define GPIO_PIN_INT_IENF_ENAF5_Pos                           5
#define GPIO_PIN_INT_IENF_ENAF5_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos)
#define GPIO_PIN_INT_IENF_ENAF6_Pos                           6
#define GPIO_PIN_INT_IENF_ENAF6_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos)
#define GPIO_PIN_INT_IENF_ENAF7_Pos                           7
#define GPIO_PIN_INT_IENF_ENAF7_Msk                           (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos)

// -----------------------------------  GPIO_PIN_INT_SIENF  ---------------------------------------
#define GPIO_PIN_INT_SIENF_SETENAF0_Pos                       0
#define GPIO_PIN_INT_SIENF_SETENAF0_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF1_Pos                       1
#define GPIO_PIN_INT_SIENF_SETENAF1_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF2_Pos                       2
#define GPIO_PIN_INT_SIENF_SETENAF2_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF3_Pos                       3
#define GPIO_PIN_INT_SIENF_SETENAF3_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF4_Pos                       4
#define GPIO_PIN_INT_SIENF_SETENAF4_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF5_Pos                       5
#define GPIO_PIN_INT_SIENF_SETENAF5_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF6_Pos                       6
#define GPIO_PIN_INT_SIENF_SETENAF6_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos)
#define GPIO_PIN_INT_SIENF_SETENAF7_Pos                       7
#define GPIO_PIN_INT_SIENF_SETENAF7_Msk                       (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos)

// -----------------------------------  GPIO_PIN_INT_CIENF  ---------------------------------------
#define GPIO_PIN_INT_CIENF_CENAF0_Pos                         0
#define GPIO_PIN_INT_CIENF_CENAF0_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos)
#define GPIO_PIN_INT_CIENF_CENAF1_Pos                         1
#define GPIO_PIN_INT_CIENF_CENAF1_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos)
#define GPIO_PIN_INT_CIENF_CENAF2_Pos                         2
#define GPIO_PIN_INT_CIENF_CENAF2_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos)
#define GPIO_PIN_INT_CIENF_CENAF3_Pos                         3
#define GPIO_PIN_INT_CIENF_CENAF3_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos)
#define GPIO_PIN_INT_CIENF_CENAF4_Pos                         4
#define GPIO_PIN_INT_CIENF_CENAF4_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos)
#define GPIO_PIN_INT_CIENF_CENAF5_Pos                         5
#define GPIO_PIN_INT_CIENF_CENAF5_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos)
#define GPIO_PIN_INT_CIENF_CENAF6_Pos                         6
#define GPIO_PIN_INT_CIENF_CENAF6_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos)
#define GPIO_PIN_INT_CIENF_CENAF7_Pos                         7
#define GPIO_PIN_INT_CIENF_CENAF7_Msk                         (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos)

// ------------------------------------  GPIO_PIN_INT_RISE  ---------------------------------------
#define GPIO_PIN_INT_RISE_RDET0_Pos                           0
#define GPIO_PIN_INT_RISE_RDET0_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos)
#define GPIO_PIN_INT_RISE_RDET1_Pos                           1
#define GPIO_PIN_INT_RISE_RDET1_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos)
#define GPIO_PIN_INT_RISE_RDET2_Pos                           2
#define GPIO_PIN_INT_RISE_RDET2_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos)
#define GPIO_PIN_INT_RISE_RDET3_Pos                           3
#define GPIO_PIN_INT_RISE_RDET3_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos)
#define GPIO_PIN_INT_RISE_RDET4_Pos                           4
#define GPIO_PIN_INT_RISE_RDET4_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos)
#define GPIO_PIN_INT_RISE_RDET5_Pos                           5
#define GPIO_PIN_INT_RISE_RDET5_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos)
#define GPIO_PIN_INT_RISE_RDET6_Pos                           6
#define GPIO_PIN_INT_RISE_RDET6_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos)
#define GPIO_PIN_INT_RISE_RDET7_Pos                           7
#define GPIO_PIN_INT_RISE_RDET7_Msk                           (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos)

// ------------------------------------  GPIO_PIN_INT_FALL  ---------------------------------------
#define GPIO_PIN_INT_FALL_FDET0_Pos                           0
#define GPIO_PIN_INT_FALL_FDET0_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos)
#define GPIO_PIN_INT_FALL_FDET1_Pos                           1
#define GPIO_PIN_INT_FALL_FDET1_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos)
#define GPIO_PIN_INT_FALL_FDET2_Pos                           2
#define GPIO_PIN_INT_FALL_FDET2_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos)
#define GPIO_PIN_INT_FALL_FDET3_Pos                           3
#define GPIO_PIN_INT_FALL_FDET3_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos)
#define GPIO_PIN_INT_FALL_FDET4_Pos                           4
#define GPIO_PIN_INT_FALL_FDET4_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos)
#define GPIO_PIN_INT_FALL_FDET5_Pos                           5
#define GPIO_PIN_INT_FALL_FDET5_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos)
#define GPIO_PIN_INT_FALL_FDET6_Pos                           6
#define GPIO_PIN_INT_FALL_FDET6_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos)
#define GPIO_PIN_INT_FALL_FDET7_Pos                           7
#define GPIO_PIN_INT_FALL_FDET7_Msk                           (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos)

// ------------------------------------  GPIO_PIN_INT_IST  ----------------------------------------
#define GPIO_PIN_INT_IST_PSTAT0_Pos                           0
#define GPIO_PIN_INT_IST_PSTAT0_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos)
#define GPIO_PIN_INT_IST_PSTAT1_Pos                           1
#define GPIO_PIN_INT_IST_PSTAT1_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos)
#define GPIO_PIN_INT_IST_PSTAT2_Pos                           2
#define GPIO_PIN_INT_IST_PSTAT2_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos)
#define GPIO_PIN_INT_IST_PSTAT3_Pos                           3
#define GPIO_PIN_INT_IST_PSTAT3_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos)
#define GPIO_PIN_INT_IST_PSTAT4_Pos                           4
#define GPIO_PIN_INT_IST_PSTAT4_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos)
#define GPIO_PIN_INT_IST_PSTAT5_Pos                           5
#define GPIO_PIN_INT_IST_PSTAT5_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos)
#define GPIO_PIN_INT_IST_PSTAT6_Pos                           6
#define GPIO_PIN_INT_IST_PSTAT6_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos)
#define GPIO_PIN_INT_IST_PSTAT7_Pos                           7
#define GPIO_PIN_INT_IST_PSTAT7_Msk                           (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos)


// ------------------------------------------------------------------------------------------------
// -----                            GPIO_GROUP_INTn Position & Mask                           -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  GPIO_GROUP_INTn_CTRL  --------------------------------------
#define GPIO_GROUP_INTn_CTRL_INT_Pos                          0
#define GPIO_GROUP_INTn_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos)
#define GPIO_GROUP_INTn_CTRL_COMB_Pos                         1
#define GPIO_GROUP_INTn_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos)
#define GPIO_GROUP_INTn_CTRL_TRIG_Pos                         2
#define GPIO_GROUP_INTn_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL0  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL1  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL2  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL3  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL4  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL5  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL6  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_POL7  -----------------------------------
#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos)
#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA0  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA1  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA2  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA3  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA4  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA5  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA6  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INTn_PORT_ENA7  -----------------------------------
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos                   0
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos                   1
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos                   2
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos                   3
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos                   4
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos                   5
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos                   6
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos                   7
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos                   8
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos                   9
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos                  10
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos                  11
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos                  12
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos                  13
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos                  14
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos                  15
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos                  16
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos                  17
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos                  18
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos                  19
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos                  20
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos                  21
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos                  22
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos                  23
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos                  24
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos                  25
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos                  26
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos                  27
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos                  28
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos                  29
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos                  30
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos)
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos                  31
#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos)


// ------------------------------------------------------------------------------------------------
// -----                            GPIO_GROUP_INT1 Position & Mask                           -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------  GPIO_GROUP_INT1_CTRL  --------------------------------------
#define GPIO_GROUP_INT1_CTRL_INT_Pos                          0
#define GPIO_GROUP_INT1_CTRL_INT_Msk                          (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos)
#define GPIO_GROUP_INT1_CTRL_COMB_Pos                         1
#define GPIO_GROUP_INT1_CTRL_COMB_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos)
#define GPIO_GROUP_INT1_CTRL_TRIG_Pos                         2
#define GPIO_GROUP_INT1_CTRL_TRIG_Msk                         (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL0  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL1  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL2  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL3  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL4  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL5  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL6  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_POL7  -----------------------------------
#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos)
#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA0  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA1  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA2  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA3  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA4  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA5  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA6  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos)

// --------------------------------  GPIO_GROUP_INT1_PORT_ENA7  -----------------------------------
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos                   0
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos                   1
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos                   2
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos                   3
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos                   4
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos                   5
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos                   6
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos                   7
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos                   8
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos                   9
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk                   (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos                  10
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos                  11
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos                  12
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos                  13
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos                  14
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos                  15
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos                  16
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos                  17
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos                  18
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos                  19
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos                  20
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos                  21
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos                  22
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos                  23
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos                  24
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos                  25
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos                  26
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos                  27
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos                  28
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos                  29
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos                  30
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos)
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos                  31
#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk                  (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 MCPWM Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  MCPWM_CON  -------------------------------------------
#define MCPWM_CON_RUN0_Pos                                    0
#define MCPWM_CON_RUN0_Msk                                    (0x01UL << MCPWM_CON_RUN0_Pos)
#define MCPWM_CON_CENTER0_Pos                                 1
#define MCPWM_CON_CENTER0_Msk                                 (0x01UL << MCPWM_CON_CENTER0_Pos)
#define MCPWM_CON_POLA0_Pos                                   2
#define MCPWM_CON_POLA0_Msk                                   (0x01UL << MCPWM_CON_POLA0_Pos)
#define MCPWM_CON_DTE0_Pos                                    3
#define MCPWM_CON_DTE0_Msk                                    (0x01UL << MCPWM_CON_DTE0_Pos)
#define MCPWM_CON_DISUP0_Pos                                  4
#define MCPWM_CON_DISUP0_Msk                                  (0x01UL << MCPWM_CON_DISUP0_Pos)
#define MCPWM_CON_RUN1_Pos                                    8
#define MCPWM_CON_RUN1_Msk                                    (0x01UL << MCPWM_CON_RUN1_Pos)
#define MCPWM_CON_CENTER1_Pos                                 9
#define MCPWM_CON_CENTER1_Msk                                 (0x01UL << MCPWM_CON_CENTER1_Pos)
#define MCPWM_CON_POLA1_Pos                                   10
#define MCPWM_CON_POLA1_Msk                                   (0x01UL << MCPWM_CON_POLA1_Pos)
#define MCPWM_CON_DTE1_Pos                                    11
#define MCPWM_CON_DTE1_Msk                                    (0x01UL << MCPWM_CON_DTE1_Pos)
#define MCPWM_CON_DISUP1_Pos                                  12
#define MCPWM_CON_DISUP1_Msk                                  (0x01UL << MCPWM_CON_DISUP1_Pos)
#define MCPWM_CON_RUN2_Pos                                    16
#define MCPWM_CON_RUN2_Msk                                    (0x01UL << MCPWM_CON_RUN2_Pos)
#define MCPWM_CON_CENTER2_Pos                                 17
#define MCPWM_CON_CENTER2_Msk                                 (0x01UL << MCPWM_CON_CENTER2_Pos)
#define MCPWM_CON_POLA2_Pos                                   18
#define MCPWM_CON_POLA2_Msk                                   (0x01UL << MCPWM_CON_POLA2_Pos)
#define MCPWM_CON_DTE2_Pos                                    19
#define MCPWM_CON_DTE2_Msk                                    (0x01UL << MCPWM_CON_DTE2_Pos)
#define MCPWM_CON_DISUP2_Pos                                  20
#define MCPWM_CON_DISUP2_Msk                                  (0x01UL << MCPWM_CON_DISUP2_Pos)
#define MCPWM_CON_INVBDC_Pos                                  29
#define MCPWM_CON_INVBDC_Msk                                  (0x01UL << MCPWM_CON_INVBDC_Pos)
#define MCPWM_CON_ACMODE_Pos                                  30
#define MCPWM_CON_ACMODE_Msk                                  (0x01UL << MCPWM_CON_ACMODE_Pos)
#define MCPWM_CON_DCMODE_Pos                                  31
#define MCPWM_CON_DCMODE_Msk                                  (0x01UL << MCPWM_CON_DCMODE_Pos)

// --------------------------------------  MCPWM_CON_SET  -----------------------------------------
#define MCPWM_CON_SET_RUN0_SET_Pos                            0
#define MCPWM_CON_SET_RUN0_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos)
#define MCPWM_CON_SET_CENTER0_SET_Pos                         1
#define MCPWM_CON_SET_CENTER0_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos)
#define MCPWM_CON_SET_POLA0_SET_Pos                           2
#define MCPWM_CON_SET_POLA0_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos)
#define MCPWM_CON_SET_DTE0_SET_Pos                            3
#define MCPWM_CON_SET_DTE0_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos)
#define MCPWM_CON_SET_DISUP0_SET_Pos                          4
#define MCPWM_CON_SET_DISUP0_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos)
#define MCPWM_CON_SET_RUN1_SET_Pos                            8
#define MCPWM_CON_SET_RUN1_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos)
#define MCPWM_CON_SET_CENTER1_SET_Pos                         9
#define MCPWM_CON_SET_CENTER1_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos)
#define MCPWM_CON_SET_POLA1_SET_Pos                           10
#define MCPWM_CON_SET_POLA1_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos)
#define MCPWM_CON_SET_DTE1_SET_Pos                            11
#define MCPWM_CON_SET_DTE1_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos)
#define MCPWM_CON_SET_DISUP1_SET_Pos                          12
#define MCPWM_CON_SET_DISUP1_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos)
#define MCPWM_CON_SET_RUN2_SET_Pos                            16
#define MCPWM_CON_SET_RUN2_SET_Msk                            (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos)
#define MCPWM_CON_SET_CENTER2_SET_Pos                         17
#define MCPWM_CON_SET_CENTER2_SET_Msk                         (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos)
#define MCPWM_CON_SET_POLA2_SET_Pos                           18
#define MCPWM_CON_SET_POLA2_SET_Msk                           (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos)
#define MCPWM_CON_SET_DTE2_SET_Pos                            19
#define MCPWM_CON_SET_DTE2_SET_Msk                            (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos)
#define MCPWM_CON_SET_DISUP2_SET_Pos                          20
#define MCPWM_CON_SET_DISUP2_SET_Msk                          (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos)
#define MCPWM_CON_SET_INVBDC_SET_Pos                          29
#define MCPWM_CON_SET_INVBDC_SET_Msk                          (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos)
#define MCPWM_CON_SET_ACMODE_SET_Pos                          30
#define MCPWM_CON_SET_ACMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos)
#define MCPWM_CON_SET_DCMODE_SET_Pos                          31
#define MCPWM_CON_SET_DCMODE_SET_Msk                          (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos)

// --------------------------------------  MCPWM_CON_CLR  -----------------------------------------
#define MCPWM_CON_CLR_RUN0_CLR_Pos                            0
#define MCPWM_CON_CLR_RUN0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos)
#define MCPWM_CON_CLR_CENTER0_CLR_Pos                         1
#define MCPWM_CON_CLR_CENTER0_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos)
#define MCPWM_CON_CLR_POLA0_CLR_Pos                           2
#define MCPWM_CON_CLR_POLA0_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos)
#define MCPWM_CON_CLR_DTE0_CLR_Pos                            3
#define MCPWM_CON_CLR_DTE0_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos)
#define MCPWM_CON_CLR_DISUP0_CLR_Pos                          4
#define MCPWM_CON_CLR_DISUP0_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos)
#define MCPWM_CON_CLR_RUN1_CLR_Pos                            8
#define MCPWM_CON_CLR_RUN1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos)
#define MCPWM_CON_CLR_CENTER1_CLR_Pos                         9
#define MCPWM_CON_CLR_CENTER1_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos)
#define MCPWM_CON_CLR_POLA1_CLR_Pos                           10
#define MCPWM_CON_CLR_POLA1_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos)
#define MCPWM_CON_CLR_DTE1_CLR_Pos                            11
#define MCPWM_CON_CLR_DTE1_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos)
#define MCPWM_CON_CLR_DISUP1_CLR_Pos                          12
#define MCPWM_CON_CLR_DISUP1_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos)
#define MCPWM_CON_CLR_RUN2_CLR_Pos                            16
#define MCPWM_CON_CLR_RUN2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos)
#define MCPWM_CON_CLR_CENTER2_CLR_Pos                         17
#define MCPWM_CON_CLR_CENTER2_CLR_Msk                         (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos)
#define MCPWM_CON_CLR_POLA2_CLR_Pos                           18
#define MCPWM_CON_CLR_POLA2_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos)
#define MCPWM_CON_CLR_DTE2_CLR_Pos                            19
#define MCPWM_CON_CLR_DTE2_CLR_Msk                            (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos)
#define MCPWM_CON_CLR_DISUP2_CLR_Pos                          20
#define MCPWM_CON_CLR_DISUP2_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos)
#define MCPWM_CON_CLR_INVBDC_CLR_Pos                          29
#define MCPWM_CON_CLR_INVBDC_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos)
#define MCPWM_CON_CLR_ACMOD_CLR_Pos                           30
#define MCPWM_CON_CLR_ACMOD_CLR_Msk                           (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos)
#define MCPWM_CON_CLR_DCMODE_CLR_Pos                          31
#define MCPWM_CON_CLR_DCMODE_CLR_Msk                          (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos)

// --------------------------------------  MCPWM_CAPCON  ------------------------------------------
#define MCPWM_CAPCON_CAP0MCI0_RE_Pos                          0
#define MCPWM_CAPCON_CAP0MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos)
#define MCPWM_CAPCON_CAP0MCI0_FE_Pos                          1
#define MCPWM_CAPCON_CAP0MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos)
#define MCPWM_CAPCON_CAP0MCI1_RE_Pos                          2
#define MCPWM_CAPCON_CAP0MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos)
#define MCPWM_CAPCON_CAP0MCI1_FE_Pos                          3
#define MCPWM_CAPCON_CAP0MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos)
#define MCPWM_CAPCON_CAP0MCI2_RE_Pos                          4
#define MCPWM_CAPCON_CAP0MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos)
#define MCPWM_CAPCON_CAP0MCI2_FE_Pos                          5
#define MCPWM_CAPCON_CAP0MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos)
#define MCPWM_CAPCON_CAP1MCI0_RE_Pos                          6
#define MCPWM_CAPCON_CAP1MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos)
#define MCPWM_CAPCON_CAP1MCI0_FE_Pos                          7
#define MCPWM_CAPCON_CAP1MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos)
#define MCPWM_CAPCON_CAP1MCI1_RE_Pos                          8
#define MCPWM_CAPCON_CAP1MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos)
#define MCPWM_CAPCON_CAP1MCI1_FE_Pos                          9
#define MCPWM_CAPCON_CAP1MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos)
#define MCPWM_CAPCON_CAP1MCI2_RE_Pos                          10
#define MCPWM_CAPCON_CAP1MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos)
#define MCPWM_CAPCON_CAP1MCI2_FE_Pos                          11
#define MCPWM_CAPCON_CAP1MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos)
#define MCPWM_CAPCON_CAP2MCI0_RE_Pos                          12
#define MCPWM_CAPCON_CAP2MCI0_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos)
#define MCPWM_CAPCON_CAP2MCI0_FE_Pos                          13
#define MCPWM_CAPCON_CAP2MCI0_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos)
#define MCPWM_CAPCON_CAP2MCI1_RE_Pos                          14
#define MCPWM_CAPCON_CAP2MCI1_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos)
#define MCPWM_CAPCON_CAP2MCI1_FE_Pos                          15
#define MCPWM_CAPCON_CAP2MCI1_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos)
#define MCPWM_CAPCON_CAP2MCI2_RE_Pos                          16
#define MCPWM_CAPCON_CAP2MCI2_RE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos)
#define MCPWM_CAPCON_CAP2MCI2_FE_Pos                          17
#define MCPWM_CAPCON_CAP2MCI2_FE_Msk                          (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos)
#define MCPWM_CAPCON_RT0_Pos                                  18
#define MCPWM_CAPCON_RT0_Msk                                  (0x01UL << MCPWM_CAPCON_RT0_Pos)
#define MCPWM_CAPCON_RT1_Pos                                  19
#define MCPWM_CAPCON_RT1_Msk                                  (0x01UL << MCPWM_CAPCON_RT1_Pos)
#define MCPWM_CAPCON_RT2_Pos                                  20
#define MCPWM_CAPCON_RT2_Msk                                  (0x01UL << MCPWM_CAPCON_RT2_Pos)
#define MCPWM_CAPCON_HNFCAP0_Pos                              21
#define MCPWM_CAPCON_HNFCAP0_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos)
#define MCPWM_CAPCON_HNFCAP1_Pos                              22
#define MCPWM_CAPCON_HNFCAP1_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos)
#define MCPWM_CAPCON_HNFCAP2_Pos                              23
#define MCPWM_CAPCON_HNFCAP2_Msk                              (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos)

// ------------------------------------  MCPWM_CAPCON_SET  ----------------------------------------
#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos                  0
#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos                  1
#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos                  2
#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos                  3
#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos                  4
#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos                  5
#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos                  6
#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos                  7
#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos                  8
#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos                  9
#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos                  10
#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos                  11
#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos                  12
#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos                  13
#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos                  14
#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos                  15
#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos                  16
#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos)
#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos                  17
#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk                  (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos)
#define MCPWM_CAPCON_SET_RT0_SET_Pos                          18
#define MCPWM_CAPCON_SET_RT0_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos)
#define MCPWM_CAPCON_SET_RT1_SET_Pos                          19
#define MCPWM_CAPCON_SET_RT1_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos)
#define MCPWM_CAPCON_SET_RT2_SET_Pos                          20
#define MCPWM_CAPCON_SET_RT2_SET_Msk                          (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos)
#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos                      21
#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos)
#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos                      22
#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos)
#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos                      23
#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk                      (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos)

// ------------------------------------  MCPWM_CAPCON_CLR  ----------------------------------------
#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos                  0
#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos                  1
#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos                  2
#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos                  3
#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos                  4
#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos                  5
#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos                  6
#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos                  7
#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos                  8
#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos                  9
#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos                  10
#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos                  11
#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos                  12
#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos                  13
#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos                  14
#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos                  15
#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos                  16
#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos)
#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos                  17
#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk                  (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos)
#define MCPWM_CAPCON_CLR_RT0_CLR_Pos                          18
#define MCPWM_CAPCON_CLR_RT0_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos)
#define MCPWM_CAPCON_CLR_RT1_CLR_Pos                          19
#define MCPWM_CAPCON_CLR_RT1_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos)
#define MCPWM_CAPCON_CLR_RT2_CLR_Pos                          20
#define MCPWM_CAPCON_CLR_RT2_CLR_Msk                          (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos)
#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos                      21
#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos)
#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos                      22
#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos)
#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos                      23
#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk                      (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos)

// ----------------------------------------  MCPWM_TC0  -------------------------------------------
#define MCPWM_TC0_MCTC_Pos                                    0
#define MCPWM_TC0_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC0_MCTC_Pos)

// ----------------------------------------  MCPWM_TC1  -------------------------------------------
#define MCPWM_TC1_MCTC_Pos                                    0
#define MCPWM_TC1_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC1_MCTC_Pos)

// ----------------------------------------  MCPWM_TC2  -------------------------------------------
#define MCPWM_TC2_MCTC_Pos                                    0
#define MCPWM_TC2_MCTC_Msk                                    (0xffffffffUL << MCPWM_TC2_MCTC_Pos)

// ---------------------------------------  MCPWM_LIM0  -------------------------------------------
#define MCPWM_LIM0_MCLIM_Pos                                  0
#define MCPWM_LIM0_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos)

// ---------------------------------------  MCPWM_LIM1  -------------------------------------------
#define MCPWM_LIM1_MCLIM_Pos                                  0
#define MCPWM_LIM1_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos)

// ---------------------------------------  MCPWM_LIM2  -------------------------------------------
#define MCPWM_LIM2_MCLIM_Pos                                  0
#define MCPWM_LIM2_MCLIM_Msk                                  (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos)

// ---------------------------------------  MCPWM_MAT0  -------------------------------------------
#define MCPWM_MAT0_MCMAT_Pos                                  0
#define MCPWM_MAT0_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos)

// ---------------------------------------  MCPWM_MAT1  -------------------------------------------
#define MCPWM_MAT1_MCMAT_Pos                                  0
#define MCPWM_MAT1_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos)

// ---------------------------------------  MCPWM_MAT2  -------------------------------------------
#define MCPWM_MAT2_MCMAT_Pos                                  0
#define MCPWM_MAT2_MCMAT_Msk                                  (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos)

// ----------------------------------------  MCPWM_DT  --------------------------------------------
#define MCPWM_DT_DT0_Pos                                      0
#define MCPWM_DT_DT0_Msk                                      (0x000003ffUL << MCPWM_DT_DT0_Pos)
#define MCPWM_DT_DT1_Pos                                      10
#define MCPWM_DT_DT1_Msk                                      (0x000003ffUL << MCPWM_DT_DT1_Pos)
#define MCPWM_DT_DT2_Pos                                      20
#define MCPWM_DT_DT2_Msk                                      (0x000003ffUL << MCPWM_DT_DT2_Pos)

// ----------------------------------------  MCPWM_CCP  -------------------------------------------
#define MCPWM_CCP_CCPA0_Pos                                   0
#define MCPWM_CCP_CCPA0_Msk                                   (0x01UL << MCPWM_CCP_CCPA0_Pos)
#define MCPWM_CCP_CCPB0_Pos                                   1
#define MCPWM_CCP_CCPB0_Msk                                   (0x01UL << MCPWM_CCP_CCPB0_Pos)
#define MCPWM_CCP_CCPA1_Pos                                   2
#define MCPWM_CCP_CCPA1_Msk                                   (0x01UL << MCPWM_CCP_CCPA1_Pos)
#define MCPWM_CCP_CCPB1_Pos                                   3
#define MCPWM_CCP_CCPB1_Msk                                   (0x01UL << MCPWM_CCP_CCPB1_Pos)
#define MCPWM_CCP_CCPA2_Pos                                   4
#define MCPWM_CCP_CCPA2_Msk                                   (0x01UL << MCPWM_CCP_CCPA2_Pos)
#define MCPWM_CCP_CCPB2_Pos                                   5
#define MCPWM_CCP_CCPB2_Msk                                   (0x01UL << MCPWM_CCP_CCPB2_Pos)

// ---------------------------------------  MCPWM_CAP0  -------------------------------------------
#define MCPWM_CAP0_CAP_Pos                                    0
#define MCPWM_CAP0_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP0_CAP_Pos)

// ---------------------------------------  MCPWM_CAP1  -------------------------------------------
#define MCPWM_CAP1_CAP_Pos                                    0
#define MCPWM_CAP1_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP1_CAP_Pos)

// ---------------------------------------  MCPWM_CAP2  -------------------------------------------
#define MCPWM_CAP2_CAP_Pos                                    0
#define MCPWM_CAP2_CAP_Msk                                    (0xffffffffUL << MCPWM_CAP2_CAP_Pos)

// ---------------------------------------  MCPWM_INTEN  ------------------------------------------
#define MCPWM_INTEN_ILIM0_Pos                                 0
#define MCPWM_INTEN_ILIM0_Msk                                 (0x01UL << MCPWM_INTEN_ILIM0_Pos)
#define MCPWM_INTEN_IMAT0_Pos                                 1
#define MCPWM_INTEN_IMAT0_Msk                                 (0x01UL << MCPWM_INTEN_IMAT0_Pos)
#define MCPWM_INTEN_ICAP0_Pos                                 2
#define MCPWM_INTEN_ICAP0_Msk                                 (0x01UL << MCPWM_INTEN_ICAP0_Pos)
#define MCPWM_INTEN_ILIM1_Pos                                 4
#define MCPWM_INTEN_ILIM1_Msk                                 (0x01UL << MCPWM_INTEN_ILIM1_Pos)
#define MCPWM_INTEN_IMAT1_Pos                                 5
#define MCPWM_INTEN_IMAT1_Msk                                 (0x01UL << MCPWM_INTEN_IMAT1_Pos)
#define MCPWM_INTEN_ICAP1_Pos                                 6
#define MCPWM_INTEN_ICAP1_Msk                                 (0x01UL << MCPWM_INTEN_ICAP1_Pos)
#define MCPWM_INTEN_ILIM2_Pos                                 8
#define MCPWM_INTEN_ILIM2_Msk                                 (0x01UL << MCPWM_INTEN_ILIM2_Pos)
#define MCPWM_INTEN_IMAT2_Pos                                 9
#define MCPWM_INTEN_IMAT2_Msk                                 (0x01UL << MCPWM_INTEN_IMAT2_Pos)
#define MCPWM_INTEN_ICAP2_Pos                                 10
#define MCPWM_INTEN_ICAP2_Msk                                 (0x01UL << MCPWM_INTEN_ICAP2_Pos)
#define MCPWM_INTEN_ABORT_Pos                                 15
#define MCPWM_INTEN_ABORT_Msk                                 (0x01UL << MCPWM_INTEN_ABORT_Pos)

// -------------------------------------  MCPWM_INTEN_SET  ----------------------------------------
#define MCPWM_INTEN_SET_ILIM0_SET_Pos                         0
#define MCPWM_INTEN_SET_ILIM0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos)
#define MCPWM_INTEN_SET_IMAT0_SET_Pos                         1
#define MCPWM_INTEN_SET_IMAT0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos)
#define MCPWM_INTEN_SET_ICAP0_SET_Pos                         2
#define MCPWM_INTEN_SET_ICAP0_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos)
#define MCPWM_INTEN_SET_ILIM1_SET_Pos                         4
#define MCPWM_INTEN_SET_ILIM1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos)
#define MCPWM_INTEN_SET_IMAT1_SET_Pos                         5
#define MCPWM_INTEN_SET_IMAT1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos)
#define MCPWM_INTEN_SET_ICAP1_SET_Pos                         6
#define MCPWM_INTEN_SET_ICAP1_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos)
#define MCPWM_INTEN_SET_ILIM2_SET_Pos                         9
#define MCPWM_INTEN_SET_ILIM2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos)
#define MCPWM_INTEN_SET_IMAT2_SET_Pos                         10
#define MCPWM_INTEN_SET_IMAT2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos)
#define MCPWM_INTEN_SET_ICAP2_SET_Pos                         11
#define MCPWM_INTEN_SET_ICAP2_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos)
#define MCPWM_INTEN_SET_ABORT_SET_Pos                         15
#define MCPWM_INTEN_SET_ABORT_SET_Msk                         (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos)

// -------------------------------------  MCPWM_INTEN_CLR  ----------------------------------------
#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos                         0
#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos)
#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos                         1
#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos)
#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos                         2
#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos)
#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos                         4
#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos)
#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos                         5
#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos)
#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos                         6
#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos)
#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos                         8
#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos)
#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos                         9
#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos)
#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos                         10
#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos)
#define MCPWM_INTEN_CLR_ABORT_CLR_Pos                         15
#define MCPWM_INTEN_CLR_ABORT_CLR_Msk                         (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos)

// --------------------------------------  MCPWM_CNTCON  ------------------------------------------
#define MCPWM_CNTCON_TC0MCI0_RE_Pos                           0
#define MCPWM_CNTCON_TC0MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos)
#define MCPWM_CNTCON_TC0MCI0_FE_Pos                           1
#define MCPWM_CNTCON_TC0MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos)
#define MCPWM_CNTCON_TC0MCI1_RE_Pos                           2
#define MCPWM_CNTCON_TC0MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos)
#define MCPWM_CNTCON_TC0MCI1_FE_Pos                           3
#define MCPWM_CNTCON_TC0MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos)
#define MCPWM_CNTCON_TC0MCI2_RE_Pos                           4
#define MCPWM_CNTCON_TC0MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos)
#define MCPWM_CNTCON_TC0MCI2_FE_Pos                           5
#define MCPWM_CNTCON_TC0MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos)
#define MCPWM_CNTCON_TC1MCI0_RE_Pos                           6
#define MCPWM_CNTCON_TC1MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos)
#define MCPWM_CNTCON_TC1MCI0_FE_Pos                           7
#define MCPWM_CNTCON_TC1MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos)
#define MCPWM_CNTCON_TC1MCI1_RE_Pos                           8
#define MCPWM_CNTCON_TC1MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos)
#define MCPWM_CNTCON_TC1MCI1_FE_Pos                           9
#define MCPWM_CNTCON_TC1MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos)
#define MCPWM_CNTCON_TC1MCI2_RE_Pos                           10
#define MCPWM_CNTCON_TC1MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos)
#define MCPWM_CNTCON_TC1MCI2_FE_Pos                           11
#define MCPWM_CNTCON_TC1MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos)
#define MCPWM_CNTCON_TC2MCI0_RE_Pos                           12
#define MCPWM_CNTCON_TC2MCI0_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos)
#define MCPWM_CNTCON_TC2MCI0_FE_Pos                           13
#define MCPWM_CNTCON_TC2MCI0_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos)
#define MCPWM_CNTCON_TC2MCI1_RE_Pos                           14
#define MCPWM_CNTCON_TC2MCI1_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos)
#define MCPWM_CNTCON_TC2MCI1_FE_Pos                           15
#define MCPWM_CNTCON_TC2MCI1_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos)
#define MCPWM_CNTCON_TC2MCI2_RE_Pos                           16
#define MCPWM_CNTCON_TC2MCI2_RE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos)
#define MCPWM_CNTCON_TC2MCI2_FE_Pos                           17
#define MCPWM_CNTCON_TC2MCI2_FE_Msk                           (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos)
#define MCPWM_CNTCON_CNTR0_Pos                                29
#define MCPWM_CNTCON_CNTR0_Msk                                (0x01UL << MCPWM_CNTCON_CNTR0_Pos)
#define MCPWM_CNTCON_CNTR1_Pos                                30
#define MCPWM_CNTCON_CNTR1_Msk                                (0x01UL << MCPWM_CNTCON_CNTR1_Pos)
#define MCPWM_CNTCON_CNTR2_Pos                                31
#define MCPWM_CNTCON_CNTR2_Msk                                (0x01UL << MCPWM_CNTCON_CNTR2_Pos)

// ------------------------------------  MCPWM_CNTCON_SET  ----------------------------------------
#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos                   0
#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos                   1
#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos                   2
#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos                   3
#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos                   4
#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos                   5
#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos                   6
#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos                   7
#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos                   8
#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos                   9
#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos                   10
#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos                   11
#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos                   12
#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos                   13
#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos                   14
#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos                   15
#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos                   16
#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos)
#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos                   17
#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk                   (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos)
#define MCPWM_CNTCON_SET_CNTR0_SET_Pos                        29
#define MCPWM_CNTCON_SET_CNTR0_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos)
#define MCPWM_CNTCON_SET_CNTR1_SET_Pos                        30
#define MCPWM_CNTCON_SET_CNTR1_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos)
#define MCPWM_CNTCON_SET_CNTR2_SET_Pos                        31
#define MCPWM_CNTCON_SET_CNTR2_SET_Msk                        (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos)

// ------------------------------------  MCPWM_CNTCON_CLR  ----------------------------------------
#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos                   0
#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos                   1
#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos                   2
#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos                   3
#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos                       4
#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk                       (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos)
#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos                   5
#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos                   6
#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos                   7
#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos                   8
#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos                   9
#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos                   10
#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos                   11
#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos                   12
#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos                   13
#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos                   14
#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos                   15
#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos                   16
#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos)
#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos                   17
#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk                   (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos)
#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos                        29
#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos)
#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos                        30
#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos)
#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos                        31
#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk                        (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos)

// ---------------------------------------  MCPWM_INTF  -------------------------------------------
#define MCPWM_INTF_ILIM0_F_Pos                                0
#define MCPWM_INTF_ILIM0_F_Msk                                (0x01UL << MCPWM_INTF_ILIM0_F_Pos)
#define MCPWM_INTF_IMAT0_F_Pos                                1
#define MCPWM_INTF_IMAT0_F_Msk                                (0x01UL << MCPWM_INTF_IMAT0_F_Pos)
#define MCPWM_INTF_ICAP0_F_Pos                                2
#define MCPWM_INTF_ICAP0_F_Msk                                (0x01UL << MCPWM_INTF_ICAP0_F_Pos)
#define MCPWM_INTF_ILIM1_F_Pos                                4
#define MCPWM_INTF_ILIM1_F_Msk                                (0x01UL << MCPWM_INTF_ILIM1_F_Pos)
#define MCPWM_INTF_IMAT1_F_Pos                                5
#define MCPWM_INTF_IMAT1_F_Msk                                (0x01UL << MCPWM_INTF_IMAT1_F_Pos)
#define MCPWM_INTF_ICAP1_F_Pos                                6
#define MCPWM_INTF_ICAP1_F_Msk                                (0x01UL << MCPWM_INTF_ICAP1_F_Pos)
#define MCPWM_INTF_ILIM2_F_Pos                                8
#define MCPWM_INTF_ILIM2_F_Msk                                (0x01UL << MCPWM_INTF_ILIM2_F_Pos)
#define MCPWM_INTF_IMAT2_F_Pos                                9
#define MCPWM_INTF_IMAT2_F_Msk                                (0x01UL << MCPWM_INTF_IMAT2_F_Pos)
#define MCPWM_INTF_ICAP2_F_Pos                                10
#define MCPWM_INTF_ICAP2_F_Msk                                (0x01UL << MCPWM_INTF_ICAP2_F_Pos)
#define MCPWM_INTF_ABORT_F_Pos                                15
#define MCPWM_INTF_ABORT_F_Msk                                (0x01UL << MCPWM_INTF_ABORT_F_Pos)

// -------------------------------------  MCPWM_INTF_SET  -----------------------------------------
#define MCPWM_INTF_SET_ILIM0_F_SET_Pos                        0
#define MCPWM_INTF_SET_ILIM0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos)
#define MCPWM_INTF_SET_IMAT0_F_SET_Pos                        1
#define MCPWM_INTF_SET_IMAT0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos)
#define MCPWM_INTF_SET_ICAP0_F_SET_Pos                        2
#define MCPWM_INTF_SET_ICAP0_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos)
#define MCPWM_INTF_SET_ILIM1_F_SET_Pos                        4
#define MCPWM_INTF_SET_ILIM1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos)
#define MCPWM_INTF_SET_IMAT1_F_SET_Pos                        5
#define MCPWM_INTF_SET_IMAT1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos)
#define MCPWM_INTF_SET_ICAP1_F_SET_Pos                        6
#define MCPWM_INTF_SET_ICAP1_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos)
#define MCPWM_INTF_SET_ILIM2_F_SET_Pos                        8
#define MCPWM_INTF_SET_ILIM2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos)
#define MCPWM_INTF_SET_IMAT2_F_SET_Pos                        9
#define MCPWM_INTF_SET_IMAT2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos)
#define MCPWM_INTF_SET_ICAP2_F_SET_Pos                        10
#define MCPWM_INTF_SET_ICAP2_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos)
#define MCPWM_INTF_SET_ABORT_F_SET_Pos                        15
#define MCPWM_INTF_SET_ABORT_F_SET_Msk                        (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos)

// -------------------------------------  MCPWM_INTF_CLR  -----------------------------------------
#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos                        0
#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos)
#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos                        1
#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos)
#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos                        2
#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos)
#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos                        4
#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos)
#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos                        5
#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos)
#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos                        6
#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos)
#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos                        8
#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos)
#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos                        9
#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos)
#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos                        10
#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos)
#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos                        15
#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk                        (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos)

// --------------------------------------  MCPWM_CAP_CLR  -----------------------------------------
#define MCPWM_CAP_CLR_CAP_CLR0_Pos                            0
#define MCPWM_CAP_CLR_CAP_CLR0_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos)
#define MCPWM_CAP_CLR_CAP_CLR1_Pos                            1
#define MCPWM_CAP_CLR_CAP_CLR1_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos)
#define MCPWM_CAP_CLR_CAP_CLR2_Pos                            2
#define MCPWM_CAP_CLR_CAP_CLR2_Msk                            (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 I2C0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  I2C0_CONSET  ------------------------------------------
#define I2C0_CONSET_AA_Pos                                    2
#define I2C0_CONSET_AA_Msk                                    (0x01UL << I2C0_CONSET_AA_Pos)
#define I2C0_CONSET_SI_Pos                                    3
#define I2C0_CONSET_SI_Msk                                    (0x01UL << I2C0_CONSET_SI_Pos)
#define I2C0_CONSET_STO_Pos                                   4
#define I2C0_CONSET_STO_Msk                                   (0x01UL << I2C0_CONSET_STO_Pos)
#define I2C0_CONSET_STA_Pos                                   5
#define I2C0_CONSET_STA_Msk                                   (0x01UL << I2C0_CONSET_STA_Pos)
#define I2C0_CONSET_I2EN_Pos                                  6
#define I2C0_CONSET_I2EN_Msk                                  (0x01UL << I2C0_CONSET_I2EN_Pos)

// ----------------------------------------  I2C0_STAT  -------------------------------------------
#define I2C0_STAT_Status_Pos                                  3
#define I2C0_STAT_Status_Msk                                  (0x1fUL << I2C0_STAT_Status_Pos)

// ----------------------------------------  I2C0_DAT  --------------------------------------------
#define I2C0_DAT_Data_Pos                                     0
#define I2C0_DAT_Data_Msk                                     (0x000000ffUL << I2C0_DAT_Data_Pos)

// ----------------------------------------  I2C0_ADR0  -------------------------------------------
#define I2C0_ADR0_GC_Pos                                      0
#define I2C0_ADR0_GC_Msk                                      (0x01UL << I2C0_ADR0_GC_Pos)
#define I2C0_ADR0_Address_Pos                                 1
#define I2C0_ADR0_Address_Msk                                 (0x7fUL << I2C0_ADR0_Address_Pos)

// ----------------------------------------  I2C0_SCLH  -------------------------------------------
#define I2C0_SCLH_SCLH_Pos                                    0
#define I2C0_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C0_SCLH_SCLH_Pos)

// ----------------------------------------  I2C0_SCLL  -------------------------------------------
#define I2C0_SCLL_SCLL_Pos                                    0
#define I2C0_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C0_SCLL_SCLL_Pos)

// ---------------------------------------  I2C0_CONCLR  ------------------------------------------
#define I2C0_CONCLR_AAC_Pos                                   2
#define I2C0_CONCLR_AAC_Msk                                   (0x01UL << I2C0_CONCLR_AAC_Pos)
#define I2C0_CONCLR_SIC_Pos                                   3
#define I2C0_CONCLR_SIC_Msk                                   (0x01UL << I2C0_CONCLR_SIC_Pos)
#define I2C0_CONCLR_STAC_Pos                                  5
#define I2C0_CONCLR_STAC_Msk                                  (0x01UL << I2C0_CONCLR_STAC_Pos)
#define I2C0_CONCLR_I2ENC_Pos                                 6
#define I2C0_CONCLR_I2ENC_Msk                                 (0x01UL << I2C0_CONCLR_I2ENC_Pos)

// ---------------------------------------  I2C0_MMCTRL  ------------------------------------------
#define I2C0_MMCTRL_MM_ENA_Pos                                0
#define I2C0_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C0_MMCTRL_MM_ENA_Pos)
#define I2C0_MMCTRL_ENA_SCL_Pos                               1
#define I2C0_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos)
#define I2C0_MMCTRL_MATCH_ALL_Pos                             2
#define I2C0_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos)

// ----------------------------------------  I2C0_ADR1  -------------------------------------------
#define I2C0_ADR1_GC_Pos                                      0
#define I2C0_ADR1_GC_Msk                                      (0x01UL << I2C0_ADR1_GC_Pos)
#define I2C0_ADR1_Address_Pos                                 1
#define I2C0_ADR1_Address_Msk                                 (0x7fUL << I2C0_ADR1_Address_Pos)

// ----------------------------------------  I2C0_ADR2  -------------------------------------------
#define I2C0_ADR2_GC_Pos                                      0
#define I2C0_ADR2_GC_Msk                                      (0x01UL << I2C0_ADR2_GC_Pos)
#define I2C0_ADR2_Address_Pos                                 1
#define I2C0_ADR2_Address_Msk                                 (0x7fUL << I2C0_ADR2_Address_Pos)

// ----------------------------------------  I2C0_ADR3  -------------------------------------------
#define I2C0_ADR3_GC_Pos                                      0
#define I2C0_ADR3_GC_Msk                                      (0x01UL << I2C0_ADR3_GC_Pos)
#define I2C0_ADR3_Address_Pos                                 1
#define I2C0_ADR3_Address_Msk                                 (0x7fUL << I2C0_ADR3_Address_Pos)

// ------------------------------------  I2C0_DATA_BUFFER  ----------------------------------------
#define I2C0_DATA_BUFFER_Data_Pos                             0
#define I2C0_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos)

// ---------------------------------------  I2C0_MASK0  -------------------------------------------
#define I2C0_MASK0_MASK_Pos                                   1
#define I2C0_MASK0_MASK_Msk                                   (0x7fUL << I2C0_MASK0_MASK_Pos)

// ---------------------------------------  I2C0_MASK1  -------------------------------------------
#define I2C0_MASK1_MASK_Pos                                   1
#define I2C0_MASK1_MASK_Msk                                   (0x7fUL << I2C0_MASK1_MASK_Pos)

// ---------------------------------------  I2C0_MASK2  -------------------------------------------
#define I2C0_MASK2_MASK_Pos                                   1
#define I2C0_MASK2_MASK_Msk                                   (0x7fUL << I2C0_MASK2_MASK_Pos)

// ---------------------------------------  I2C0_MASK3  -------------------------------------------
#define I2C0_MASK3_MASK_Pos                                   1
#define I2C0_MASK3_MASK_Msk                                   (0x7fUL << I2C0_MASK3_MASK_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 I2C1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  I2C1_CONSET  ------------------------------------------
#define I2C1_CONSET_AA_Pos                                    2
#define I2C1_CONSET_AA_Msk                                    (0x01UL << I2C1_CONSET_AA_Pos)
#define I2C1_CONSET_SI_Pos                                    3
#define I2C1_CONSET_SI_Msk                                    (0x01UL << I2C1_CONSET_SI_Pos)
#define I2C1_CONSET_STO_Pos                                   4
#define I2C1_CONSET_STO_Msk                                   (0x01UL << I2C1_CONSET_STO_Pos)
#define I2C1_CONSET_STA_Pos                                   5
#define I2C1_CONSET_STA_Msk                                   (0x01UL << I2C1_CONSET_STA_Pos)
#define I2C1_CONSET_I2EN_Pos                                  6
#define I2C1_CONSET_I2EN_Msk                                  (0x01UL << I2C1_CONSET_I2EN_Pos)

// ----------------------------------------  I2C1_STAT  -------------------------------------------
#define I2C1_STAT_Status_Pos                                  3
#define I2C1_STAT_Status_Msk                                  (0x1fUL << I2C1_STAT_Status_Pos)

// ----------------------------------------  I2C1_DAT  --------------------------------------------
#define I2C1_DAT_Data_Pos                                     0
#define I2C1_DAT_Data_Msk                                     (0x000000ffUL << I2C1_DAT_Data_Pos)

// ----------------------------------------  I2C1_ADR0  -------------------------------------------
#define I2C1_ADR0_GC_Pos                                      0
#define I2C1_ADR0_GC_Msk                                      (0x01UL << I2C1_ADR0_GC_Pos)
#define I2C1_ADR0_Address_Pos                                 1
#define I2C1_ADR0_Address_Msk                                 (0x7fUL << I2C1_ADR0_Address_Pos)

// ----------------------------------------  I2C1_SCLH  -------------------------------------------
#define I2C1_SCLH_SCLH_Pos                                    0
#define I2C1_SCLH_SCLH_Msk                                    (0x0000ffffUL << I2C1_SCLH_SCLH_Pos)

// ----------------------------------------  I2C1_SCLL  -------------------------------------------
#define I2C1_SCLL_SCLL_Pos                                    0
#define I2C1_SCLL_SCLL_Msk                                    (0x0000ffffUL << I2C1_SCLL_SCLL_Pos)

// ---------------------------------------  I2C1_CONCLR  ------------------------------------------
#define I2C1_CONCLR_AAC_Pos                                   2
#define I2C1_CONCLR_AAC_Msk                                   (0x01UL << I2C1_CONCLR_AAC_Pos)
#define I2C1_CONCLR_SIC_Pos                                   3
#define I2C1_CONCLR_SIC_Msk                                   (0x01UL << I2C1_CONCLR_SIC_Pos)
#define I2C1_CONCLR_STAC_Pos                                  5
#define I2C1_CONCLR_STAC_Msk                                  (0x01UL << I2C1_CONCLR_STAC_Pos)
#define I2C1_CONCLR_I2ENC_Pos                                 6
#define I2C1_CONCLR_I2ENC_Msk                                 (0x01UL << I2C1_CONCLR_I2ENC_Pos)

// ---------------------------------------  I2C1_MMCTRL  ------------------------------------------
#define I2C1_MMCTRL_MM_ENA_Pos                                0
#define I2C1_MMCTRL_MM_ENA_Msk                                (0x01UL << I2C1_MMCTRL_MM_ENA_Pos)
#define I2C1_MMCTRL_ENA_SCL_Pos                               1
#define I2C1_MMCTRL_ENA_SCL_Msk                               (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos)
#define I2C1_MMCTRL_MATCH_ALL_Pos                             2
#define I2C1_MMCTRL_MATCH_ALL_Msk                             (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos)

// ----------------------------------------  I2C1_ADR1  -------------------------------------------
#define I2C1_ADR1_GC_Pos                                      0
#define I2C1_ADR1_GC_Msk                                      (0x01UL << I2C1_ADR1_GC_Pos)
#define I2C1_ADR1_Address_Pos                                 1
#define I2C1_ADR1_Address_Msk                                 (0x7fUL << I2C1_ADR1_Address_Pos)

// ----------------------------------------  I2C1_ADR2  -------------------------------------------
#define I2C1_ADR2_GC_Pos                                      0
#define I2C1_ADR2_GC_Msk                                      (0x01UL << I2C1_ADR2_GC_Pos)
#define I2C1_ADR2_Address_Pos                                 1
#define I2C1_ADR2_Address_Msk                                 (0x7fUL << I2C1_ADR2_Address_Pos)

// ----------------------------------------  I2C1_ADR3  -------------------------------------------
#define I2C1_ADR3_GC_Pos                                      0
#define I2C1_ADR3_GC_Msk                                      (0x01UL << I2C1_ADR3_GC_Pos)
#define I2C1_ADR3_Address_Pos                                 1
#define I2C1_ADR3_Address_Msk                                 (0x7fUL << I2C1_ADR3_Address_Pos)

// ------------------------------------  I2C1_DATA_BUFFER  ----------------------------------------
#define I2C1_DATA_BUFFER_Data_Pos                             0
#define I2C1_DATA_BUFFER_Data_Msk                             (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos)

// ---------------------------------------  I2C1_MASK0  -------------------------------------------
#define I2C1_MASK0_MASK_Pos                                   1
#define I2C1_MASK0_MASK_Msk                                   (0x7fUL << I2C1_MASK0_MASK_Pos)

// ---------------------------------------  I2C1_MASK1  -------------------------------------------
#define I2C1_MASK1_MASK_Pos                                   1
#define I2C1_MASK1_MASK_Msk                                   (0x7fUL << I2C1_MASK1_MASK_Pos)

// ---------------------------------------  I2C1_MASK2  -------------------------------------------
#define I2C1_MASK2_MASK_Pos                                   1
#define I2C1_MASK2_MASK_Msk                                   (0x7fUL << I2C1_MASK2_MASK_Pos)

// ---------------------------------------  I2C1_MASK3  -------------------------------------------
#define I2C1_MASK3_MASK_Pos                                   1
#define I2C1_MASK3_MASK_Msk                                   (0x7fUL << I2C1_MASK3_MASK_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 I2S0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  I2S0_DAO  --------------------------------------------
#define I2S0_DAO_WORDWIDTH_Pos                                0
#define I2S0_DAO_WORDWIDTH_Msk                                (0x03UL << I2S0_DAO_WORDWIDTH_Pos)
#define I2S0_DAO_MONO_Pos                                     2
#define I2S0_DAO_MONO_Msk                                     (0x01UL << I2S0_DAO_MONO_Pos)
#define I2S0_DAO_STOP_Pos                                     3
#define I2S0_DAO_STOP_Msk                                     (0x01UL << I2S0_DAO_STOP_Pos)
#define I2S0_DAO_RESET_Pos                                    4
#define I2S0_DAO_RESET_Msk                                    (0x01UL << I2S0_DAO_RESET_Pos)
#define I2S0_DAO_WS_SEL_Pos                                   5
#define I2S0_DAO_WS_SEL_Msk                                   (0x01UL << I2S0_DAO_WS_SEL_Pos)
#define I2S0_DAO_WS_HALFPERIOD_Pos                            6
#define I2S0_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos)
#define I2S0_DAO_MUTE_Pos                                     15
#define I2S0_DAO_MUTE_Msk                                     (0x01UL << I2S0_DAO_MUTE_Pos)

// ----------------------------------------  I2S0_DAI  --------------------------------------------
#define I2S0_DAI_WORDWIDTH_Pos                                0
#define I2S0_DAI_WORDWIDTH_Msk                                (0x03UL << I2S0_DAI_WORDWIDTH_Pos)
#define I2S0_DAI_MONO_Pos                                     2
#define I2S0_DAI_MONO_Msk                                     (0x01UL << I2S0_DAI_MONO_Pos)
#define I2S0_DAI_STOP_Pos                                     3
#define I2S0_DAI_STOP_Msk                                     (0x01UL << I2S0_DAI_STOP_Pos)
#define I2S0_DAI_RESET_Pos                                    4
#define I2S0_DAI_RESET_Msk                                    (0x01UL << I2S0_DAI_RESET_Pos)
#define I2S0_DAI_WS_SEL_Pos                                   5
#define I2S0_DAI_WS_SEL_Msk                                   (0x01UL << I2S0_DAI_WS_SEL_Pos)
#define I2S0_DAI_WS_HALFPERIOD_Pos                            6
#define I2S0_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos)

// ---------------------------------------  I2S0_TXFIFO  ------------------------------------------
#define I2S0_TXFIFO_I2STXFIFO_Pos                             0
#define I2S0_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos)

// ---------------------------------------  I2S0_RXFIFO  ------------------------------------------
#define I2S0_RXFIFO_I2SRXFIFO_Pos                             0
#define I2S0_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos)

// ---------------------------------------  I2S0_STATE  -------------------------------------------
#define I2S0_STATE_IRQ_Pos                                    0
#define I2S0_STATE_IRQ_Msk                                    (0x01UL << I2S0_STATE_IRQ_Pos)
#define I2S0_STATE_DMAREQ1_Pos                                1
#define I2S0_STATE_DMAREQ1_Msk                                (0x01UL << I2S0_STATE_DMAREQ1_Pos)
#define I2S0_STATE_DMAREQ2_Pos                                2
#define I2S0_STATE_DMAREQ2_Msk                                (0x01UL << I2S0_STATE_DMAREQ2_Pos)
#define I2S0_STATE_RX_LEVEL_Pos                               8
#define I2S0_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_RX_LEVEL_Pos)
#define I2S0_STATE_TX_LEVEL_Pos                               16
#define I2S0_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S0_STATE_TX_LEVEL_Pos)

// ----------------------------------------  I2S0_DMA1  -------------------------------------------
#define I2S0_DMA1_RX_DMA1_ENABLE_Pos                          0
#define I2S0_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos)
#define I2S0_DMA1_TX_DMA1_ENABLE_Pos                          1
#define I2S0_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos)
#define I2S0_DMA1_RX_DEPTH_DMA1_Pos                           8
#define I2S0_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos)
#define I2S0_DMA1_TX_DEPTH_DMA1_Pos                           16
#define I2S0_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos)

// ----------------------------------------  I2S0_DMA2  -------------------------------------------
#define I2S0_DMA2_RX_DMA2_ENABLE_Pos                          0
#define I2S0_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos)
#define I2S0_DMA2_TX_DMA2_ENABLE_Pos                          1
#define I2S0_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos)
#define I2S0_DMA2_RX_DEPTH_DMA2_Pos                           8
#define I2S0_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos)
#define I2S0_DMA2_TX_DEPTH_DMA2_Pos                           16
#define I2S0_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos)

// ----------------------------------------  I2S0_IRQ  --------------------------------------------
#define I2S0_IRQ_RX_IRQ_ENABLE_Pos                            0
#define I2S0_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos)
#define I2S0_IRQ_TX_IRQ_ENABLE_Pos                            1
#define I2S0_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos)
#define I2S0_IRQ_RX_DEPTH_IRQ_Pos                             8
#define I2S0_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos)
#define I2S0_IRQ_TX_DEPTH_IRQ_Pos                             16
#define I2S0_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos)

// ---------------------------------------  I2S0_TXRATE  ------------------------------------------
#define I2S0_TXRATE_Y_DIVIDER_Pos                             0
#define I2S0_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos)
#define I2S0_TXRATE_X_DIVIDER_Pos                             8
#define I2S0_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos)

// ---------------------------------------  I2S0_RXRATE  ------------------------------------------
#define I2S0_RXRATE_Y_DIVIDER_Pos                             0
#define I2S0_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos)
#define I2S0_RXRATE_X_DIVIDER_Pos                             8
#define I2S0_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos)

// -------------------------------------  I2S0_TXBITRATE  -----------------------------------------
#define I2S0_TXBITRATE_TX_BITRATE_Pos                         0
#define I2S0_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos)

// -------------------------------------  I2S0_RXBITRATE  -----------------------------------------
#define I2S0_RXBITRATE_RX_BITRATE_Pos                         0
#define I2S0_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos)

// ---------------------------------------  I2S0_TXMODE  ------------------------------------------
#define I2S0_TXMODE_TXCLKSEL_Pos                              0
#define I2S0_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos)
#define I2S0_TXMODE_TX4PIN_Pos                                2
#define I2S0_TXMODE_TX4PIN_Msk                                (0x01UL << I2S0_TXMODE_TX4PIN_Pos)
#define I2S0_TXMODE_TXMCENA_Pos                               3
#define I2S0_TXMODE_TXMCENA_Msk                               (0x01UL << I2S0_TXMODE_TXMCENA_Pos)

// ---------------------------------------  I2S0_RXMODE  ------------------------------------------
#define I2S0_RXMODE_RXCLKSEL_Pos                              0
#define I2S0_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos)
#define I2S0_RXMODE_RX4PIN_Pos                                2
#define I2S0_RXMODE_RX4PIN_Msk                                (0x01UL << I2S0_RXMODE_RX4PIN_Pos)
#define I2S0_RXMODE_RXMCENA_Pos                               3
#define I2S0_RXMODE_RXMCENA_Msk                               (0x01UL << I2S0_RXMODE_RXMCENA_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 I2S1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// ----------------------------------------  I2S1_DAO  --------------------------------------------
#define I2S1_DAO_WORDWIDTH_Pos                                0
#define I2S1_DAO_WORDWIDTH_Msk                                (0x03UL << I2S1_DAO_WORDWIDTH_Pos)
#define I2S1_DAO_MONO_Pos                                     2
#define I2S1_DAO_MONO_Msk                                     (0x01UL << I2S1_DAO_MONO_Pos)
#define I2S1_DAO_STOP_Pos                                     3
#define I2S1_DAO_STOP_Msk                                     (0x01UL << I2S1_DAO_STOP_Pos)
#define I2S1_DAO_RESET_Pos                                    4
#define I2S1_DAO_RESET_Msk                                    (0x01UL << I2S1_DAO_RESET_Pos)
#define I2S1_DAO_WS_SEL_Pos                                   5
#define I2S1_DAO_WS_SEL_Msk                                   (0x01UL << I2S1_DAO_WS_SEL_Pos)
#define I2S1_DAO_WS_HALFPERIOD_Pos                            6
#define I2S1_DAO_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos)
#define I2S1_DAO_MUTE_Pos                                     15
#define I2S1_DAO_MUTE_Msk                                     (0x01UL << I2S1_DAO_MUTE_Pos)

// ----------------------------------------  I2S1_DAI  --------------------------------------------
#define I2S1_DAI_WORDWIDTH_Pos                                0
#define I2S1_DAI_WORDWIDTH_Msk                                (0x03UL << I2S1_DAI_WORDWIDTH_Pos)
#define I2S1_DAI_MONO_Pos                                     2
#define I2S1_DAI_MONO_Msk                                     (0x01UL << I2S1_DAI_MONO_Pos)
#define I2S1_DAI_STOP_Pos                                     3
#define I2S1_DAI_STOP_Msk                                     (0x01UL << I2S1_DAI_STOP_Pos)
#define I2S1_DAI_RESET_Pos                                    4
#define I2S1_DAI_RESET_Msk                                    (0x01UL << I2S1_DAI_RESET_Pos)
#define I2S1_DAI_WS_SEL_Pos                                   5
#define I2S1_DAI_WS_SEL_Msk                                   (0x01UL << I2S1_DAI_WS_SEL_Pos)
#define I2S1_DAI_WS_HALFPERIOD_Pos                            6
#define I2S1_DAI_WS_HALFPERIOD_Msk                            (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos)

// ---------------------------------------  I2S1_TXFIFO  ------------------------------------------
#define I2S1_TXFIFO_I2STXFIFO_Pos                             0
#define I2S1_TXFIFO_I2STXFIFO_Msk                             (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos)

// ---------------------------------------  I2S1_RXFIFO  ------------------------------------------
#define I2S1_RXFIFO_I2SRXFIFO_Pos                             0
#define I2S1_RXFIFO_I2SRXFIFO_Msk                             (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos)

// ---------------------------------------  I2S1_STATE  -------------------------------------------
#define I2S1_STATE_IRQ_Pos                                    0
#define I2S1_STATE_IRQ_Msk                                    (0x01UL << I2S1_STATE_IRQ_Pos)
#define I2S1_STATE_DMAREQ1_Pos                                1
#define I2S1_STATE_DMAREQ1_Msk                                (0x01UL << I2S1_STATE_DMAREQ1_Pos)
#define I2S1_STATE_DMAREQ2_Pos                                2
#define I2S1_STATE_DMAREQ2_Msk                                (0x01UL << I2S1_STATE_DMAREQ2_Pos)
#define I2S1_STATE_RX_LEVEL_Pos                               8
#define I2S1_STATE_RX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_RX_LEVEL_Pos)
#define I2S1_STATE_TX_LEVEL_Pos                               16
#define I2S1_STATE_TX_LEVEL_Msk                               (0x0fUL << I2S1_STATE_TX_LEVEL_Pos)

// ----------------------------------------  I2S1_DMA1  -------------------------------------------
#define I2S1_DMA1_RX_DMA1_ENABLE_Pos                          0
#define I2S1_DMA1_RX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos)
#define I2S1_DMA1_TX_DMA1_ENABLE_Pos                          1
#define I2S1_DMA1_TX_DMA1_ENABLE_Msk                          (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos)
#define I2S1_DMA1_RX_DEPTH_DMA1_Pos                           8
#define I2S1_DMA1_RX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos)
#define I2S1_DMA1_TX_DEPTH_DMA1_Pos                           16
#define I2S1_DMA1_TX_DEPTH_DMA1_Msk                           (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos)

// ----------------------------------------  I2S1_DMA2  -------------------------------------------
#define I2S1_DMA2_RX_DMA2_ENABLE_Pos                          0
#define I2S1_DMA2_RX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos)
#define I2S1_DMA2_TX_DMA2_ENABLE_Pos                          1
#define I2S1_DMA2_TX_DMA2_ENABLE_Msk                          (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos)
#define I2S1_DMA2_RX_DEPTH_DMA2_Pos                           8
#define I2S1_DMA2_RX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos)
#define I2S1_DMA2_TX_DEPTH_DMA2_Pos                           16
#define I2S1_DMA2_TX_DEPTH_DMA2_Msk                           (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos)

// ----------------------------------------  I2S1_IRQ  --------------------------------------------
#define I2S1_IRQ_RX_IRQ_ENABLE_Pos                            0
#define I2S1_IRQ_RX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos)
#define I2S1_IRQ_TX_IRQ_ENABLE_Pos                            1
#define I2S1_IRQ_TX_IRQ_ENABLE_Msk                            (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos)
#define I2S1_IRQ_RX_DEPTH_IRQ_Pos                             8
#define I2S1_IRQ_RX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos)
#define I2S1_IRQ_TX_DEPTH_IRQ_Pos                             16
#define I2S1_IRQ_TX_DEPTH_IRQ_Msk                             (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos)

// ---------------------------------------  I2S1_TXRATE  ------------------------------------------
#define I2S1_TXRATE_Y_DIVIDER_Pos                             0
#define I2S1_TXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos)
#define I2S1_TXRATE_X_DIVIDER_Pos                             8
#define I2S1_TXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos)

// ---------------------------------------  I2S1_RXRATE  ------------------------------------------
#define I2S1_RXRATE_Y_DIVIDER_Pos                             0
#define I2S1_RXRATE_Y_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos)
#define I2S1_RXRATE_X_DIVIDER_Pos                             8
#define I2S1_RXRATE_X_DIVIDER_Msk                             (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos)

// -------------------------------------  I2S1_TXBITRATE  -----------------------------------------
#define I2S1_TXBITRATE_TX_BITRATE_Pos                         0
#define I2S1_TXBITRATE_TX_BITRATE_Msk                         (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos)

// -------------------------------------  I2S1_RXBITRATE  -----------------------------------------
#define I2S1_RXBITRATE_RX_BITRATE_Pos                         0
#define I2S1_RXBITRATE_RX_BITRATE_Msk                         (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos)

// ---------------------------------------  I2S1_TXMODE  ------------------------------------------
#define I2S1_TXMODE_TXCLKSEL_Pos                              0
#define I2S1_TXMODE_TXCLKSEL_Msk                              (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos)
#define I2S1_TXMODE_TX4PIN_Pos                                2
#define I2S1_TXMODE_TX4PIN_Msk                                (0x01UL << I2S1_TXMODE_TX4PIN_Pos)
#define I2S1_TXMODE_TXMCENA_Pos                               3
#define I2S1_TXMODE_TXMCENA_Msk                               (0x01UL << I2S1_TXMODE_TXMCENA_Pos)

// ---------------------------------------  I2S1_RXMODE  ------------------------------------------
#define I2S1_RXMODE_RXCLKSEL_Pos                              0
#define I2S1_RXMODE_RXCLKSEL_Msk                              (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos)
#define I2S1_RXMODE_RX4PIN_Pos                                2
#define I2S1_RXMODE_RX4PIN_Msk                                (0x01UL << I2S1_RXMODE_RX4PIN_Pos)
#define I2S1_RXMODE_RXMCENA_Pos                               3
#define I2S1_RXMODE_RXMCENA_Msk                               (0x01UL << I2S1_RXMODE_RXMCENA_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                C_CAN1 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  C_CAN1_CNTL  ------------------------------------------
#define C_CAN1_CNTL_INIT_Pos                                  0
#define C_CAN1_CNTL_INIT_Msk                                  (0x01UL << C_CAN1_CNTL_INIT_Pos)
#define C_CAN1_CNTL_IE_Pos                                    1
#define C_CAN1_CNTL_IE_Msk                                    (0x01UL << C_CAN1_CNTL_IE_Pos)
#define C_CAN1_CNTL_SIE_Pos                                   2
#define C_CAN1_CNTL_SIE_Msk                                   (0x01UL << C_CAN1_CNTL_SIE_Pos)
#define C_CAN1_CNTL_EIE_Pos                                   3
#define C_CAN1_CNTL_EIE_Msk                                   (0x01UL << C_CAN1_CNTL_EIE_Pos)
#define C_CAN1_CNTL_DAR_Pos                                   5
#define C_CAN1_CNTL_DAR_Msk                                   (0x01UL << C_CAN1_CNTL_DAR_Pos)
#define C_CAN1_CNTL_CCE_Pos                                   6
#define C_CAN1_CNTL_CCE_Msk                                   (0x01UL << C_CAN1_CNTL_CCE_Pos)
#define C_CAN1_CNTL_TEST_Pos                                  7
#define C_CAN1_CNTL_TEST_Msk                                  (0x01UL << C_CAN1_CNTL_TEST_Pos)

// ---------------------------------------  C_CAN1_STAT  ------------------------------------------
#define C_CAN1_STAT_LEC_Pos                                   0
#define C_CAN1_STAT_LEC_Msk                                   (0x07UL << C_CAN1_STAT_LEC_Pos)
#define C_CAN1_STAT_TXOK_Pos                                  3
#define C_CAN1_STAT_TXOK_Msk                                  (0x01UL << C_CAN1_STAT_TXOK_Pos)
#define C_CAN1_STAT_RXOK_Pos                                  4
#define C_CAN1_STAT_RXOK_Msk                                  (0x01UL << C_CAN1_STAT_RXOK_Pos)
#define C_CAN1_STAT_EPASS_Pos                                 5
#define C_CAN1_STAT_EPASS_Msk                                 (0x01UL << C_CAN1_STAT_EPASS_Pos)
#define C_CAN1_STAT_EWARN_Pos                                 6
#define C_CAN1_STAT_EWARN_Msk                                 (0x01UL << C_CAN1_STAT_EWARN_Pos)
#define C_CAN1_STAT_BOFF_Pos                                  7
#define C_CAN1_STAT_BOFF_Msk                                  (0x01UL << C_CAN1_STAT_BOFF_Pos)

// ----------------------------------------  C_CAN1_EC  -------------------------------------------
#define C_CAN1_EC_TEC_7_0_Pos                                 0
#define C_CAN1_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos)
#define C_CAN1_EC_REC_6_0_Pos                                 8
#define C_CAN1_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN1_EC_REC_6_0_Pos)
#define C_CAN1_EC_RP_Pos                                      15
#define C_CAN1_EC_RP_Msk                                      (0x01UL << C_CAN1_EC_RP_Pos)

// ----------------------------------------  C_CAN1_BT  -------------------------------------------
#define C_CAN1_BT_BRP_Pos                                     0
#define C_CAN1_BT_BRP_Msk                                     (0x3fUL << C_CAN1_BT_BRP_Pos)
#define C_CAN1_BT_SJW_Pos                                     6
#define C_CAN1_BT_SJW_Msk                                     (0x03UL << C_CAN1_BT_SJW_Pos)
#define C_CAN1_BT_TSEG1_Pos                                   8
#define C_CAN1_BT_TSEG1_Msk                                   (0x0fUL << C_CAN1_BT_TSEG1_Pos)
#define C_CAN1_BT_TSEG2_Pos                                   12
#define C_CAN1_BT_TSEG2_Msk                                   (0x07UL << C_CAN1_BT_TSEG2_Pos)

// ---------------------------------------  C_CAN1_INT  -------------------------------------------
#define C_CAN1_INT_INTID15_0_Pos                              0
#define C_CAN1_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos)

// ---------------------------------------  C_CAN1_TEST  ------------------------------------------
#define C_CAN1_TEST_BASIC_Pos                                 2
#define C_CAN1_TEST_BASIC_Msk                                 (0x01UL << C_CAN1_TEST_BASIC_Pos)
#define C_CAN1_TEST_SILENT_Pos                                3
#define C_CAN1_TEST_SILENT_Msk                                (0x01UL << C_CAN1_TEST_SILENT_Pos)
#define C_CAN1_TEST_LBACK_Pos                                 4
#define C_CAN1_TEST_LBACK_Msk                                 (0x01UL << C_CAN1_TEST_LBACK_Pos)
#define C_CAN1_TEST_TX1_0_Pos                                 5
#define C_CAN1_TEST_TX1_0_Msk                                 (0x03UL << C_CAN1_TEST_TX1_0_Pos)
#define C_CAN1_TEST_RX_Pos                                    7
#define C_CAN1_TEST_RX_Msk                                    (0x01UL << C_CAN1_TEST_RX_Pos)

// ---------------------------------------  C_CAN1_BRPE  ------------------------------------------
#define C_CAN1_BRPE_BRPE_Pos                                  0
#define C_CAN1_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN1_BRPE_BRPE_Pos)

// ------------------------------------  C_CAN1_IF1_CMDREQ  ---------------------------------------
#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos                         0
#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos)
#define C_CAN1_IF1_CMDREQ_BUSY_Pos                            15
#define C_CAN1_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos)

// -----------------------------------  C_CAN1_IF1_CMDMSK_W  --------------------------------------
#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos                        0
#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos)
#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos                        1
#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos)
#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos                        2
#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos)
#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos                     3
#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos)
#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos                          4
#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos)
#define C_CAN1_IF1_CMDMSK_W_ARB_Pos                           5
#define C_CAN1_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos)
#define C_CAN1_IF1_CMDMSK_W_MASK_Pos                          6
#define C_CAN1_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos)
#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos                         7
#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos)

// -----------------------------------  C_CAN1_IF1_CMDMSK_R  --------------------------------------
#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos                        0
#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos)
#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos                        1
#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos)
#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos                        2
#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos)
#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos                     3
#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos)
#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos                          4
#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos)
#define C_CAN1_IF1_CMDMSK_R_ARB_Pos                           5
#define C_CAN1_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos)
#define C_CAN1_IF1_CMDMSK_R_MASK_Pos                          6
#define C_CAN1_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos)
#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos                         7
#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos)

// -------------------------------------  C_CAN1_IF1_MSK1  ----------------------------------------
#define C_CAN1_IF1_MSK1_MSK15_0_Pos                           0
#define C_CAN1_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos)

// -------------------------------------  C_CAN1_IF1_MSK2  ----------------------------------------
#define C_CAN1_IF1_MSK2_MSK28_16_Pos                          0
#define C_CAN1_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos)
#define C_CAN1_IF1_MSK2_MDIR_Pos                              14
#define C_CAN1_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos)
#define C_CAN1_IF1_MSK2_MXTD_Pos                              15
#define C_CAN1_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos)

// -------------------------------------  C_CAN1_IF1_ARB1  ----------------------------------------
#define C_CAN1_IF1_ARB1_ID15_0_Pos                            0
#define C_CAN1_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos)

// -------------------------------------  C_CAN1_IF1_ARB2  ----------------------------------------
#define C_CAN1_IF1_ARB2_ID28_16_Pos                           0
#define C_CAN1_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos)
#define C_CAN1_IF1_ARB2_DIR_Pos                               13
#define C_CAN1_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos)
#define C_CAN1_IF1_ARB2_XTD_Pos                               14
#define C_CAN1_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos)
#define C_CAN1_IF1_ARB2_MSGVAL_Pos                            15
#define C_CAN1_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos)

// ------------------------------------  C_CAN1_IF1_MCTRL  ----------------------------------------
#define C_CAN1_IF1_MCTRL_DLC3_0_Pos                           0
#define C_CAN1_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos)
#define C_CAN1_IF1_MCTRL_EOB_Pos                              7
#define C_CAN1_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos)
#define C_CAN1_IF1_MCTRL_TXRQST_Pos                           8
#define C_CAN1_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos)
#define C_CAN1_IF1_MCTRL_RMTEN_Pos                            9
#define C_CAN1_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos)
#define C_CAN1_IF1_MCTRL_RXIE_Pos                             10
#define C_CAN1_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos)
#define C_CAN1_IF1_MCTRL_TXIE_Pos                             11
#define C_CAN1_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos)
#define C_CAN1_IF1_MCTRL_UMASK_Pos                            12
#define C_CAN1_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos)
#define C_CAN1_IF1_MCTRL_INTPND_Pos                           13
#define C_CAN1_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos)
#define C_CAN1_IF1_MCTRL_MSGLST_Pos                           14
#define C_CAN1_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos)
#define C_CAN1_IF1_MCTRL_NEWDAT_Pos                           15
#define C_CAN1_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos)

// -------------------------------------  C_CAN1_IF1_DA1  -----------------------------------------
#define C_CAN1_IF1_DA1_DATA0_Pos                              0
#define C_CAN1_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos)
#define C_CAN1_IF1_DA1_DATA1_Pos                              8
#define C_CAN1_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos)

// -------------------------------------  C_CAN1_IF1_DA2  -----------------------------------------
#define C_CAN1_IF1_DA2_DATA2_Pos                              0
#define C_CAN1_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos)
#define C_CAN1_IF1_DA2_DATA3_Pos                              8
#define C_CAN1_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos)

// -------------------------------------  C_CAN1_IF1_DB1  -----------------------------------------
#define C_CAN1_IF1_DB1_DATA4_Pos                              0
#define C_CAN1_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos)
#define C_CAN1_IF1_DB1_DATA5_Pos                              8
#define C_CAN1_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos)

// -------------------------------------  C_CAN1_IF1_DB2  -----------------------------------------
#define C_CAN1_IF1_DB2_DATA6_Pos                              0
#define C_CAN1_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos)
#define C_CAN1_IF1_DB2_DATA7_Pos                              8
#define C_CAN1_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos)

// ------------------------------------  C_CAN1_IF2_CMDREQ  ---------------------------------------
#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos                         0
#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos)
#define C_CAN1_IF2_CMDREQ_BUSY_Pos                            15
#define C_CAN1_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos)

// -----------------------------------  C_CAN1_IF2_CMDMSK_W  --------------------------------------
#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos                        0
#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos)
#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos                        1
#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos)
#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos                        2
#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos)
#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos                     3
#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos)
#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos                          4
#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos)
#define C_CAN1_IF2_CMDMSK_W_ARB_Pos                           5
#define C_CAN1_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos)
#define C_CAN1_IF2_CMDMSK_W_MASK_Pos                          6
#define C_CAN1_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos)
#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos                         7
#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos)

// -----------------------------------  C_CAN1_IF2_CMDMSK_R  --------------------------------------
#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos                        0
#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos)
#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos                        1
#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos)
#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos                        2
#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos)
#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos                     3
#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos)
#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos                          4
#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos)
#define C_CAN1_IF2_CMDMSK_R_ARB_Pos                           5
#define C_CAN1_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos)
#define C_CAN1_IF2_CMDMSK_R_MASK_Pos                          6
#define C_CAN1_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos)
#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos                         7
#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos)

// -------------------------------------  C_CAN1_IF2_MSK1  ----------------------------------------
#define C_CAN1_IF2_MSK1_MSK15_0_Pos                           0
#define C_CAN1_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos)

// -------------------------------------  C_CAN1_IF2_MSK2  ----------------------------------------
#define C_CAN1_IF2_MSK2_MSK28_16_Pos                          0
#define C_CAN1_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos)
#define C_CAN1_IF2_MSK2_MDIR_Pos                              14
#define C_CAN1_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos)
#define C_CAN1_IF2_MSK2_MXTD_Pos                              15
#define C_CAN1_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos)

// -------------------------------------  C_CAN1_IF2_ARB1  ----------------------------------------
#define C_CAN1_IF2_ARB1_ID15_0_Pos                            0
#define C_CAN1_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos)

// -------------------------------------  C_CAN1_IF2_ARB2  ----------------------------------------
#define C_CAN1_IF2_ARB2_ID28_16_Pos                           0
#define C_CAN1_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos)
#define C_CAN1_IF2_ARB2_DIR_Pos                               13
#define C_CAN1_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos)
#define C_CAN1_IF2_ARB2_XTD_Pos                               14
#define C_CAN1_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos)
#define C_CAN1_IF2_ARB2_MSGVAL_Pos                            15
#define C_CAN1_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos)

// ------------------------------------  C_CAN1_IF2_MCTRL  ----------------------------------------
#define C_CAN1_IF2_MCTRL_DLC3_0_Pos                           0
#define C_CAN1_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos)
#define C_CAN1_IF2_MCTRL_EOB_Pos                              7
#define C_CAN1_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos)
#define C_CAN1_IF2_MCTRL_TXRQST_Pos                           8
#define C_CAN1_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos)
#define C_CAN1_IF2_MCTRL_RMTEN_Pos                            9
#define C_CAN1_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos)
#define C_CAN1_IF2_MCTRL_RXIE_Pos                             10
#define C_CAN1_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos)
#define C_CAN1_IF2_MCTRL_TXIE_Pos                             11
#define C_CAN1_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos)
#define C_CAN1_IF2_MCTRL_UMASK_Pos                            12
#define C_CAN1_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos)
#define C_CAN1_IF2_MCTRL_INTPND_Pos                           13
#define C_CAN1_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos)
#define C_CAN1_IF2_MCTRL_MSGLST_Pos                           14
#define C_CAN1_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos)
#define C_CAN1_IF2_MCTRL_NEWDAT_Pos                           15
#define C_CAN1_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos)

// -------------------------------------  C_CAN1_IF2_DA1  -----------------------------------------
#define C_CAN1_IF2_DA1_DATA0_Pos                              0
#define C_CAN1_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos)
#define C_CAN1_IF2_DA1_DATA1_Pos                              8
#define C_CAN1_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos)

// -------------------------------------  C_CAN1_IF2_DA2  -----------------------------------------
#define C_CAN1_IF2_DA2_DATA2_Pos                              0
#define C_CAN1_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos)
#define C_CAN1_IF2_DA2_DATA3_Pos                              8
#define C_CAN1_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos)

// -------------------------------------  C_CAN1_IF2_DB1  -----------------------------------------
#define C_CAN1_IF2_DB1_DATA4_Pos                              0
#define C_CAN1_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos)
#define C_CAN1_IF2_DB1_DATA5_Pos                              8
#define C_CAN1_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos)

// -------------------------------------  C_CAN1_IF2_DB2  -----------------------------------------
#define C_CAN1_IF2_DB2_DATA6_Pos                              0
#define C_CAN1_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos)
#define C_CAN1_IF2_DB2_DATA7_Pos                              8
#define C_CAN1_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos)

// --------------------------------------  C_CAN1_TXREQ1  -----------------------------------------
#define C_CAN1_TXREQ1_TXRQST16_1_Pos                          0
#define C_CAN1_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos)

// --------------------------------------  C_CAN1_TXREQ2  -----------------------------------------
#define C_CAN1_TXREQ2_TXRQST32_17_Pos                         0
#define C_CAN1_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos)

// ---------------------------------------  C_CAN1_ND1  -------------------------------------------
#define C_CAN1_ND1_NEWDAT16_1_Pos                             0
#define C_CAN1_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos)

// ---------------------------------------  C_CAN1_ND2  -------------------------------------------
#define C_CAN1_ND2_NEWDAT32_17_Pos                            0
#define C_CAN1_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos)

// ---------------------------------------  C_CAN1_IR1  -------------------------------------------
#define C_CAN1_IR1_INTPND16_1_Pos                             0
#define C_CAN1_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos)

// ---------------------------------------  C_CAN1_IR2  -------------------------------------------
#define C_CAN1_IR2_INTPND32_17_Pos                            0
#define C_CAN1_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos)

// --------------------------------------  C_CAN1_MSGV1  ------------------------------------------
#define C_CAN1_MSGV1_MSGVAL16_1_Pos                           0
#define C_CAN1_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos)

// --------------------------------------  C_CAN1_MSGV2  ------------------------------------------
#define C_CAN1_MSGV2_MSGVAL32_17_Pos                          0
#define C_CAN1_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos)

// --------------------------------------  C_CAN1_CLKDIV  -----------------------------------------
#define C_CAN1_CLKDIV_CLKDIVVAL_Pos                           0
#define C_CAN1_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                RITIMER Position & Mask                               -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  RITIMER_COMPVAL  ----------------------------------------
#define RITIMER_COMPVAL_RICOMP_Pos                            0
#define RITIMER_COMPVAL_RICOMP_Msk                            (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos)

// --------------------------------------  RITIMER_MASK  ------------------------------------------
#define RITIMER_MASK_RIMASK_Pos                               0
#define RITIMER_MASK_RIMASK_Msk                               (0xffffffffUL << RITIMER_MASK_RIMASK_Pos)

// --------------------------------------  RITIMER_CTRL  ------------------------------------------
#define RITIMER_CTRL_RITINT_Pos                               0
#define RITIMER_CTRL_RITINT_Msk                               (0x01UL << RITIMER_CTRL_RITINT_Pos)
#define RITIMER_CTRL_RITENCLR_Pos                             1
#define RITIMER_CTRL_RITENCLR_Msk                             (0x01UL << RITIMER_CTRL_RITENCLR_Pos)
#define RITIMER_CTRL_RITENBR_Pos                              2
#define RITIMER_CTRL_RITENBR_Msk                              (0x01UL << RITIMER_CTRL_RITENBR_Pos)
#define RITIMER_CTRL_RITEN_Pos                                3
#define RITIMER_CTRL_RITEN_Msk                                (0x01UL << RITIMER_CTRL_RITEN_Pos)

// -------------------------------------  RITIMER_COUNTER  ----------------------------------------
#define RITIMER_COUNTER_RICOUNTER_Pos                         0
#define RITIMER_COUNTER_RICOUNTER_Msk                         (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  QEI Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  QEI_CON  --------------------------------------------
#define QEI_CON_RESP_Pos                                      0
#define QEI_CON_RESP_Msk                                      (0x01UL << QEI_CON_RESP_Pos)
#define QEI_CON_RESPI_Pos                                     1
#define QEI_CON_RESPI_Msk                                     (0x01UL << QEI_CON_RESPI_Pos)
#define QEI_CON_RESV_Pos                                      2
#define QEI_CON_RESV_Msk                                      (0x01UL << QEI_CON_RESV_Pos)
#define QEI_CON_RESI_Pos                                      3
#define QEI_CON_RESI_Msk                                      (0x01UL << QEI_CON_RESI_Pos)

// ----------------------------------------  QEI_STAT  --------------------------------------------
#define QEI_STAT_DIR_Pos                                      0
#define QEI_STAT_DIR_Msk                                      (0x01UL << QEI_STAT_DIR_Pos)

// ----------------------------------------  QEI_CONF  --------------------------------------------
#define QEI_CONF_DIRINV_Pos                                   0
#define QEI_CONF_DIRINV_Msk                                   (0x01UL << QEI_CONF_DIRINV_Pos)
#define QEI_CONF_SIGMODE_Pos                                  1
#define QEI_CONF_SIGMODE_Msk                                  (0x01UL << QEI_CONF_SIGMODE_Pos)
#define QEI_CONF_CAPMODE_Pos                                  2
#define QEI_CONF_CAPMODE_Msk                                  (0x01UL << QEI_CONF_CAPMODE_Pos)
#define QEI_CONF_INVINX_Pos                                   3
#define QEI_CONF_INVINX_Msk                                   (0x01UL << QEI_CONF_INVINX_Pos)
#define QEI_CONF_CRESPI_Pos                                   4
#define QEI_CONF_CRESPI_Msk                                   (0x01UL << QEI_CONF_CRESPI_Pos)
#define QEI_CONF_INXGATE_Pos                                  16
#define QEI_CONF_INXGATE_Msk                                  (0x0fUL << QEI_CONF_INXGATE_Pos)

// -----------------------------------------  QEI_POS  --------------------------------------------
#define QEI_POS_POS_Pos                                       0
#define QEI_POS_POS_Msk                                       (0xffffffffUL << QEI_POS_POS_Pos)

// ---------------------------------------  QEI_MAXPOS  -------------------------------------------
#define QEI_MAXPOS_MAXPOS_Pos                                 0
#define QEI_MAXPOS_MAXPOS_Msk                                 (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos)

// ---------------------------------------  QEI_CMPOS0  -------------------------------------------
#define QEI_CMPOS0_PCMP0_Pos                                  0
#define QEI_CMPOS0_PCMP0_Msk                                  (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos)

// ---------------------------------------  QEI_CMPOS1  -------------------------------------------
#define QEI_CMPOS1_PCMP1_Pos                                  0
#define QEI_CMPOS1_PCMP1_Msk                                  (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos)

// ---------------------------------------  QEI_CMPOS2  -------------------------------------------
#define QEI_CMPOS2_PCMP2_Pos                                  0
#define QEI_CMPOS2_PCMP2_Msk                                  (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos)

// ---------------------------------------  QEI_INXCNT  -------------------------------------------
#define QEI_INXCNT_ENCPOS_Pos                                 0
#define QEI_INXCNT_ENCPOS_Msk                                 (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos)

// ---------------------------------------  QEI_INXCMP0  ------------------------------------------
#define QEI_INXCMP0_ICMP0_Pos                                 0
#define QEI_INXCMP0_ICMP0_Msk                                 (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos)

// ----------------------------------------  QEI_LOAD  --------------------------------------------
#define QEI_LOAD_VELLOAD_Pos                                  0
#define QEI_LOAD_VELLOAD_Msk                                  (0xffffffffUL << QEI_LOAD_VELLOAD_Pos)

// ----------------------------------------  QEI_TIME  --------------------------------------------
#define QEI_TIME_VELVAL_Pos                                   0
#define QEI_TIME_VELVAL_Msk                                   (0xffffffffUL << QEI_TIME_VELVAL_Pos)

// -----------------------------------------  QEI_VEL  --------------------------------------------
#define QEI_VEL_VELPC_Pos                                     0
#define QEI_VEL_VELPC_Msk                                     (0xffffffffUL << QEI_VEL_VELPC_Pos)

// -----------------------------------------  QEI_CAP  --------------------------------------------
#define QEI_CAP_VELCAP_Pos                                    0
#define QEI_CAP_VELCAP_Msk                                    (0xffffffffUL << QEI_CAP_VELCAP_Pos)

// ---------------------------------------  QEI_VELCOMP  ------------------------------------------
#define QEI_VELCOMP_VELCMP_Pos                                0
#define QEI_VELCOMP_VELCMP_Msk                                (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos)

// --------------------------------------  QEI_FILTERPHA  -----------------------------------------
#define QEI_FILTERPHA_FILTA_Pos                               0
#define QEI_FILTERPHA_FILTA_Msk                               (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos)

// --------------------------------------  QEI_FILTERPHB  -----------------------------------------
#define QEI_FILTERPHB_FILTB_Pos                               0
#define QEI_FILTERPHB_FILTB_Msk                               (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos)

// --------------------------------------  QEI_FILTERINX  -----------------------------------------
#define QEI_FILTERINX_FITLINX_Pos                             0
#define QEI_FILTERINX_FITLINX_Msk                             (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos)

// ---------------------------------------  QEI_WINDOW  -------------------------------------------
#define QEI_WINDOW_WINDOW_Pos                                 0
#define QEI_WINDOW_WINDOW_Msk                                 (0xffffffffUL << QEI_WINDOW_WINDOW_Pos)

// ---------------------------------------  QEI_INXCMP1  ------------------------------------------
#define QEI_INXCMP1_ICMP1_Pos                                 0
#define QEI_INXCMP1_ICMP1_Msk                                 (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos)

// ---------------------------------------  QEI_INXCMP2  ------------------------------------------
#define QEI_INXCMP2_ICMP2_Pos                                 0
#define QEI_INXCMP2_ICMP2_Msk                                 (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos)

// -----------------------------------------  QEI_IEC  --------------------------------------------
#define QEI_IEC_INX_EN_Pos                                    0
#define QEI_IEC_INX_EN_Msk                                    (0x01UL << QEI_IEC_INX_EN_Pos)
#define QEI_IEC_TIM_EN_Pos                                    1
#define QEI_IEC_TIM_EN_Msk                                    (0x01UL << QEI_IEC_TIM_EN_Pos)
#define QEI_IEC_VELC_EN_Pos                                   2
#define QEI_IEC_VELC_EN_Msk                                   (0x01UL << QEI_IEC_VELC_EN_Pos)
#define QEI_IEC_DIR_EN_Pos                                    3
#define QEI_IEC_DIR_EN_Msk                                    (0x01UL << QEI_IEC_DIR_EN_Pos)
#define QEI_IEC_ERR_EN_Pos                                    4
#define QEI_IEC_ERR_EN_Msk                                    (0x01UL << QEI_IEC_ERR_EN_Pos)
#define QEI_IEC_ENCLK_EN_Pos                                  5
#define QEI_IEC_ENCLK_EN_Msk                                  (0x01UL << QEI_IEC_ENCLK_EN_Pos)
#define QEI_IEC_POS0_Int_Pos                                  6
#define QEI_IEC_POS0_Int_Msk                                  (0x01UL << QEI_IEC_POS0_Int_Pos)
#define QEI_IEC_POS1_Int_Pos                                  7
#define QEI_IEC_POS1_Int_Msk                                  (0x01UL << QEI_IEC_POS1_Int_Pos)
#define QEI_IEC_POS2_Int_Pos                                  8
#define QEI_IEC_POS2_Int_Msk                                  (0x01UL << QEI_IEC_POS2_Int_Pos)
#define QEI_IEC_REV_Int_Pos                                   9
#define QEI_IEC_REV_Int_Msk                                   (0x01UL << QEI_IEC_REV_Int_Pos)
#define QEI_IEC_POS0REV_Int_Pos                               10
#define QEI_IEC_POS0REV_Int_Msk                               (0x01UL << QEI_IEC_POS0REV_Int_Pos)
#define QEI_IEC_POS1REV_Int_Pos                               11
#define QEI_IEC_POS1REV_Int_Msk                               (0x01UL << QEI_IEC_POS1REV_Int_Pos)
#define QEI_IEC_POS2REV_Int_Pos                               12
#define QEI_IEC_POS2REV_Int_Msk                               (0x01UL << QEI_IEC_POS2REV_Int_Pos)
#define QEI_IEC_REV1_Int_Pos                                  13
#define QEI_IEC_REV1_Int_Msk                                  (0x01UL << QEI_IEC_REV1_Int_Pos)
#define QEI_IEC_REV2_Int_Pos                                  14
#define QEI_IEC_REV2_Int_Msk                                  (0x01UL << QEI_IEC_REV2_Int_Pos)
#define QEI_IEC_MAXPOS_Int_Pos                                15
#define QEI_IEC_MAXPOS_Int_Msk                                (0x01UL << QEI_IEC_MAXPOS_Int_Pos)

// -----------------------------------------  QEI_IES  --------------------------------------------
#define QEI_IES_INX_EN_Pos                                    0
#define QEI_IES_INX_EN_Msk                                    (0x01UL << QEI_IES_INX_EN_Pos)
#define QEI_IES_TIM_EN_Pos                                    1
#define QEI_IES_TIM_EN_Msk                                    (0x01UL << QEI_IES_TIM_EN_Pos)
#define QEI_IES_VELC_EN_Pos                                   2
#define QEI_IES_VELC_EN_Msk                                   (0x01UL << QEI_IES_VELC_EN_Pos)
#define QEI_IES_DIR_EN_Pos                                    3
#define QEI_IES_DIR_EN_Msk                                    (0x01UL << QEI_IES_DIR_EN_Pos)
#define QEI_IES_ERR_EN_Pos                                    4
#define QEI_IES_ERR_EN_Msk                                    (0x01UL << QEI_IES_ERR_EN_Pos)
#define QEI_IES_ENCLK_EN_Pos                                  5
#define QEI_IES_ENCLK_EN_Msk                                  (0x01UL << QEI_IES_ENCLK_EN_Pos)
#define QEI_IES_POS0_Int_Pos                                  6
#define QEI_IES_POS0_Int_Msk                                  (0x01UL << QEI_IES_POS0_Int_Pos)
#define QEI_IES_POS1_Int_Pos                                  7
#define QEI_IES_POS1_Int_Msk                                  (0x01UL << QEI_IES_POS1_Int_Pos)
#define QEI_IES_POS2_Int_Pos                                  8
#define QEI_IES_POS2_Int_Msk                                  (0x01UL << QEI_IES_POS2_Int_Pos)
#define QEI_IES_REV_Int_Pos                                   9
#define QEI_IES_REV_Int_Msk                                   (0x01UL << QEI_IES_REV_Int_Pos)
#define QEI_IES_POS0REV_Int_Pos                               10
#define QEI_IES_POS0REV_Int_Msk                               (0x01UL << QEI_IES_POS0REV_Int_Pos)
#define QEI_IES_POS1REV_Int_Pos                               11
#define QEI_IES_POS1REV_Int_Msk                               (0x01UL << QEI_IES_POS1REV_Int_Pos)
#define QEI_IES_POS2REV_Int_Pos                               12
#define QEI_IES_POS2REV_Int_Msk                               (0x01UL << QEI_IES_POS2REV_Int_Pos)
#define QEI_IES_REV1_Int_Pos                                  13
#define QEI_IES_REV1_Int_Msk                                  (0x01UL << QEI_IES_REV1_Int_Pos)
#define QEI_IES_REV2_Int_Pos                                  14
#define QEI_IES_REV2_Int_Msk                                  (0x01UL << QEI_IES_REV2_Int_Pos)
#define QEI_IES_MAXPOS_Int_Pos                                15
#define QEI_IES_MAXPOS_Int_Msk                                (0x01UL << QEI_IES_MAXPOS_Int_Pos)

// ---------------------------------------  QEI_INTSTAT  ------------------------------------------
#define QEI_INTSTAT_INX_Int_Pos                               0
#define QEI_INTSTAT_INX_Int_Msk                               (0x01UL << QEI_INTSTAT_INX_Int_Pos)
#define QEI_INTSTAT_TIM_Int_Pos                               1
#define QEI_INTSTAT_TIM_Int_Msk                               (0x01UL << QEI_INTSTAT_TIM_Int_Pos)
#define QEI_INTSTAT_VELC_Int_Pos                              2
#define QEI_INTSTAT_VELC_Int_Msk                              (0x01UL << QEI_INTSTAT_VELC_Int_Pos)
#define QEI_INTSTAT_DIR_Int_Pos                               3
#define QEI_INTSTAT_DIR_Int_Msk                               (0x01UL << QEI_INTSTAT_DIR_Int_Pos)
#define QEI_INTSTAT_ERR_Int_Pos                               4
#define QEI_INTSTAT_ERR_Int_Msk                               (0x01UL << QEI_INTSTAT_ERR_Int_Pos)
#define QEI_INTSTAT_ENCLK_Int_Pos                             5
#define QEI_INTSTAT_ENCLK_Int_Msk                             (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos)
#define QEI_INTSTAT_POS0_Int_Pos                              6
#define QEI_INTSTAT_POS0_Int_Msk                              (0x01UL << QEI_INTSTAT_POS0_Int_Pos)
#define QEI_INTSTAT_POS1_Int_Pos                              7
#define QEI_INTSTAT_POS1_Int_Msk                              (0x01UL << QEI_INTSTAT_POS1_Int_Pos)
#define QEI_INTSTAT_POS2_Int_Pos                              8
#define QEI_INTSTAT_POS2_Int_Msk                              (0x01UL << QEI_INTSTAT_POS2_Int_Pos)
#define QEI_INTSTAT_REV_Int_Pos                               9
#define QEI_INTSTAT_REV_Int_Msk                               (0x01UL << QEI_INTSTAT_REV_Int_Pos)
#define QEI_INTSTAT_POS0REV_Int_Pos                           10
#define QEI_INTSTAT_POS0REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos)
#define QEI_INTSTAT_POS1REV_Int_Pos                           11
#define QEI_INTSTAT_POS1REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos)
#define QEI_INTSTAT_POS2REV_Int_Pos                           12
#define QEI_INTSTAT_POS2REV_Int_Msk                           (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos)
#define QEI_INTSTAT_REV1_Int_Pos                              13
#define QEI_INTSTAT_REV1_Int_Msk                              (0x01UL << QEI_INTSTAT_REV1_Int_Pos)
#define QEI_INTSTAT_REV2_Int_Pos                              14
#define QEI_INTSTAT_REV2_Int_Msk                              (0x01UL << QEI_INTSTAT_REV2_Int_Pos)
#define QEI_INTSTAT_MAXPOS_Int_Pos                            15
#define QEI_INTSTAT_MAXPOS_Int_Msk                            (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos)

// -----------------------------------------  QEI_IE  ---------------------------------------------
#define QEI_IE_INX_Int_Pos                                    0
#define QEI_IE_INX_Int_Msk                                    (0x01UL << QEI_IE_INX_Int_Pos)
#define QEI_IE_TIM_Int_Pos                                    1
#define QEI_IE_TIM_Int_Msk                                    (0x01UL << QEI_IE_TIM_Int_Pos)
#define QEI_IE_VELC_Int_Pos                                   2
#define QEI_IE_VELC_Int_Msk                                   (0x01UL << QEI_IE_VELC_Int_Pos)
#define QEI_IE_DIR_Int_Pos                                    3
#define QEI_IE_DIR_Int_Msk                                    (0x01UL << QEI_IE_DIR_Int_Pos)
#define QEI_IE_ERR_Int_Pos                                    4
#define QEI_IE_ERR_Int_Msk                                    (0x01UL << QEI_IE_ERR_Int_Pos)
#define QEI_IE_ENCLK_Int_Pos                                  5
#define QEI_IE_ENCLK_Int_Msk                                  (0x01UL << QEI_IE_ENCLK_Int_Pos)
#define QEI_IE_POS0_Int_Pos                                   6
#define QEI_IE_POS0_Int_Msk                                   (0x01UL << QEI_IE_POS0_Int_Pos)
#define QEI_IE_POS1_Int_Pos                                   7
#define QEI_IE_POS1_Int_Msk                                   (0x01UL << QEI_IE_POS1_Int_Pos)
#define QEI_IE_POS2_Int_Pos                                   8
#define QEI_IE_POS2_Int_Msk                                   (0x01UL << QEI_IE_POS2_Int_Pos)
#define QEI_IE_REV_Int_Pos                                    9
#define QEI_IE_REV_Int_Msk                                    (0x01UL << QEI_IE_REV_Int_Pos)
#define QEI_IE_POS0REV_Int_Pos                                10
#define QEI_IE_POS0REV_Int_Msk                                (0x01UL << QEI_IE_POS0REV_Int_Pos)
#define QEI_IE_POS1REV_Int_Pos                                11
#define QEI_IE_POS1REV_Int_Msk                                (0x01UL << QEI_IE_POS1REV_Int_Pos)
#define QEI_IE_POS2REV_Int_Pos                                12
#define QEI_IE_POS2REV_Int_Msk                                (0x01UL << QEI_IE_POS2REV_Int_Pos)
#define QEI_IE_REV1_Int_Pos                                   13
#define QEI_IE_REV1_Int_Msk                                   (0x01UL << QEI_IE_REV1_Int_Pos)
#define QEI_IE_REV2_Int_Pos                                   14
#define QEI_IE_REV2_Int_Msk                                   (0x01UL << QEI_IE_REV2_Int_Pos)
#define QEI_IE_MAXPOS_Int_Pos                                 15
#define QEI_IE_MAXPOS_Int_Msk                                 (0x01UL << QEI_IE_MAXPOS_Int_Pos)

// -----------------------------------------  QEI_CLR  --------------------------------------------
#define QEI_CLR_INX_Int_Pos                                   0
#define QEI_CLR_INX_Int_Msk                                   (0x01UL << QEI_CLR_INX_Int_Pos)
#define QEI_CLR_TIM_Int_Pos                                   1
#define QEI_CLR_TIM_Int_Msk                                   (0x01UL << QEI_CLR_TIM_Int_Pos)
#define QEI_CLR_VELC_Int_Pos                                  2
#define QEI_CLR_VELC_Int_Msk                                  (0x01UL << QEI_CLR_VELC_Int_Pos)
#define QEI_CLR_DIR_Int_Pos                                   3
#define QEI_CLR_DIR_Int_Msk                                   (0x01UL << QEI_CLR_DIR_Int_Pos)
#define QEI_CLR_ERR_Int_Pos                                   4
#define QEI_CLR_ERR_Int_Msk                                   (0x01UL << QEI_CLR_ERR_Int_Pos)
#define QEI_CLR_ENCLK_Int_Pos                                 5
#define QEI_CLR_ENCLK_Int_Msk                                 (0x01UL << QEI_CLR_ENCLK_Int_Pos)
#define QEI_CLR_POS0_Int_Pos                                  6
#define QEI_CLR_POS0_Int_Msk                                  (0x01UL << QEI_CLR_POS0_Int_Pos)
#define QEI_CLR_POS1_Int_Pos                                  7
#define QEI_CLR_POS1_Int_Msk                                  (0x01UL << QEI_CLR_POS1_Int_Pos)
#define QEI_CLR_POS2_Int_Pos                                  8
#define QEI_CLR_POS2_Int_Msk                                  (0x01UL << QEI_CLR_POS2_Int_Pos)
#define QEI_CLR_REV_Int_Pos                                   9
#define QEI_CLR_REV_Int_Msk                                   (0x01UL << QEI_CLR_REV_Int_Pos)
#define QEI_CLR_POS0REV_Int_Pos                               10
#define QEI_CLR_POS0REV_Int_Msk                               (0x01UL << QEI_CLR_POS0REV_Int_Pos)
#define QEI_CLR_POS1REV_Int_Pos                               11
#define QEI_CLR_POS1REV_Int_Msk                               (0x01UL << QEI_CLR_POS1REV_Int_Pos)
#define QEI_CLR_REV1_Int_Pos                                  13
#define QEI_CLR_REV1_Int_Msk                                  (0x01UL << QEI_CLR_REV1_Int_Pos)
#define QEI_CLR_REV2_Int_Pos                                  14
#define QEI_CLR_REV2_Int_Msk                                  (0x01UL << QEI_CLR_REV2_Int_Pos)
#define QEI_CLR_MAXPOS_Int_Pos                                15
#define QEI_CLR_MAXPOS_Int_Msk                                (0x01UL << QEI_CLR_MAXPOS_Int_Pos)

// -----------------------------------------  QEI_SET  --------------------------------------------
#define QEI_SET_INX_Int_Pos                                   0
#define QEI_SET_INX_Int_Msk                                   (0x01UL << QEI_SET_INX_Int_Pos)
#define QEI_SET_TIM_Int_Pos                                   1
#define QEI_SET_TIM_Int_Msk                                   (0x01UL << QEI_SET_TIM_Int_Pos)
#define QEI_SET_VELC_Int_Pos                                  2
#define QEI_SET_VELC_Int_Msk                                  (0x01UL << QEI_SET_VELC_Int_Pos)
#define QEI_SET_DIR_Int_Pos                                   3
#define QEI_SET_DIR_Int_Msk                                   (0x01UL << QEI_SET_DIR_Int_Pos)
#define QEI_SET_ERR_Int_Pos                                   4
#define QEI_SET_ERR_Int_Msk                                   (0x01UL << QEI_SET_ERR_Int_Pos)
#define QEI_SET_ENCLK_Int_Pos                                 5
#define QEI_SET_ENCLK_Int_Msk                                 (0x01UL << QEI_SET_ENCLK_Int_Pos)
#define QEI_SET_POS0_Int_Pos                                  6
#define QEI_SET_POS0_Int_Msk                                  (0x01UL << QEI_SET_POS0_Int_Pos)
#define QEI_SET_POS1_Int_Pos                                  7
#define QEI_SET_POS1_Int_Msk                                  (0x01UL << QEI_SET_POS1_Int_Pos)
#define QEI_SET_POS2_Int_Pos                                  8
#define QEI_SET_POS2_Int_Msk                                  (0x01UL << QEI_SET_POS2_Int_Pos)
#define QEI_SET_REV_Int_Pos                                   9
#define QEI_SET_REV_Int_Msk                                   (0x01UL << QEI_SET_REV_Int_Pos)
#define QEI_SET_POS0REV_Int_Pos                               10
#define QEI_SET_POS0REV_Int_Msk                               (0x01UL << QEI_SET_POS0REV_Int_Pos)
#define QEI_SET_POS1REV_Int_Pos                               11
#define QEI_SET_POS1REV_Int_Msk                               (0x01UL << QEI_SET_POS1REV_Int_Pos)
#define QEI_SET_POS2REV_Int_Pos                               12
#define QEI_SET_POS2REV_Int_Msk                               (0x01UL << QEI_SET_POS2REV_Int_Pos)
#define QEI_SET_REV1_Int_Pos                                  13
#define QEI_SET_REV1_Int_Msk                                  (0x01UL << QEI_SET_REV1_Int_Pos)
#define QEI_SET_REV2_Int_Pos                                  14
#define QEI_SET_REV2_Int_Msk                                  (0x01UL << QEI_SET_REV2_Int_Pos)
#define QEI_SET_MAXPOS_Int_Pos                                15
#define QEI_SET_MAXPOS_Int_Msk                                (0x01UL << QEI_SET_MAXPOS_Int_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 GIMA Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -------------------------------------  GIMA_CAP0_0_IN  -----------------------------------------
#define GIMA_CAP0_0_IN_INV_Pos                                0
#define GIMA_CAP0_0_IN_INV_Msk                                (0x01UL << GIMA_CAP0_0_IN_INV_Pos)
#define GIMA_CAP0_0_IN_EDGE_Pos                               1
#define GIMA_CAP0_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos)
#define GIMA_CAP0_0_IN_SYNCH_Pos                              2
#define GIMA_CAP0_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos)
#define GIMA_CAP0_0_IN_PULSE_Pos                              3
#define GIMA_CAP0_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos)
#define GIMA_CAP0_0_IN_SELECT_Pos                             4
#define GIMA_CAP0_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP0_1_IN  -----------------------------------------
#define GIMA_CAP0_1_IN_INV_Pos                                0
#define GIMA_CAP0_1_IN_INV_Msk                                (0x01UL << GIMA_CAP0_1_IN_INV_Pos)
#define GIMA_CAP0_1_IN_EDGE_Pos                               1
#define GIMA_CAP0_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos)
#define GIMA_CAP0_1_IN_SYNCH_Pos                              2
#define GIMA_CAP0_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos)
#define GIMA_CAP0_1_IN_PULSE_Pos                              3
#define GIMA_CAP0_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos)
#define GIMA_CAP0_1_IN_SELECT_Pos                             4
#define GIMA_CAP0_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP0_2_IN  -----------------------------------------
#define GIMA_CAP0_2_IN_INV_Pos                                0
#define GIMA_CAP0_2_IN_INV_Msk                                (0x01UL << GIMA_CAP0_2_IN_INV_Pos)
#define GIMA_CAP0_2_IN_EDGE_Pos                               1
#define GIMA_CAP0_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos)
#define GIMA_CAP0_2_IN_SYNCH_Pos                              2
#define GIMA_CAP0_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos)
#define GIMA_CAP0_2_IN_PULSE_Pos                              3
#define GIMA_CAP0_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos)
#define GIMA_CAP0_2_IN_SELECT_Pos                             4
#define GIMA_CAP0_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP0_3_IN  -----------------------------------------
#define GIMA_CAP0_3_IN_INV_Pos                                0
#define GIMA_CAP0_3_IN_INV_Msk                                (0x01UL << GIMA_CAP0_3_IN_INV_Pos)
#define GIMA_CAP0_3_IN_EDGE_Pos                               1
#define GIMA_CAP0_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos)
#define GIMA_CAP0_3_IN_SYNCH_Pos                              2
#define GIMA_CAP0_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos)
#define GIMA_CAP0_3_IN_PULSE_Pos                              3
#define GIMA_CAP0_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos)
#define GIMA_CAP0_3_IN_SELECT_Pos                             4
#define GIMA_CAP0_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP1_0_IN  -----------------------------------------
#define GIMA_CAP1_0_IN_INV_Pos                                0
#define GIMA_CAP1_0_IN_INV_Msk                                (0x01UL << GIMA_CAP1_0_IN_INV_Pos)
#define GIMA_CAP1_0_IN_EDGE_Pos                               1
#define GIMA_CAP1_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos)
#define GIMA_CAP1_0_IN_SYNCH_Pos                              2
#define GIMA_CAP1_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos)
#define GIMA_CAP1_0_IN_PULSE_Pos                              3
#define GIMA_CAP1_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos)
#define GIMA_CAP1_0_IN_SELECT_Pos                             4
#define GIMA_CAP1_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP1_1_IN  -----------------------------------------
#define GIMA_CAP1_1_IN_INV_Pos                                0
#define GIMA_CAP1_1_IN_INV_Msk                                (0x01UL << GIMA_CAP1_1_IN_INV_Pos)
#define GIMA_CAP1_1_IN_EDGE_Pos                               1
#define GIMA_CAP1_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos)
#define GIMA_CAP1_1_IN_SYNCH_Pos                              2
#define GIMA_CAP1_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos)
#define GIMA_CAP1_1_IN_PULSE_Pos                              3
#define GIMA_CAP1_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos)
#define GIMA_CAP1_1_IN_SELECT_Pos                             4
#define GIMA_CAP1_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP1_2_IN  -----------------------------------------
#define GIMA_CAP1_2_IN_INV_Pos                                0
#define GIMA_CAP1_2_IN_INV_Msk                                (0x01UL << GIMA_CAP1_2_IN_INV_Pos)
#define GIMA_CAP1_2_IN_EDGE_Pos                               1
#define GIMA_CAP1_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos)
#define GIMA_CAP1_2_IN_SYNCH_Pos                              2
#define GIMA_CAP1_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos)
#define GIMA_CAP1_2_IN_PULSE_Pos                              3
#define GIMA_CAP1_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos)
#define GIMA_CAP1_2_IN_SELECT_Pos                             4
#define GIMA_CAP1_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP1_3_IN  -----------------------------------------
#define GIMA_CAP1_3_IN_INV_Pos                                0
#define GIMA_CAP1_3_IN_INV_Msk                                (0x01UL << GIMA_CAP1_3_IN_INV_Pos)
#define GIMA_CAP1_3_IN_EDGE_Pos                               1
#define GIMA_CAP1_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos)
#define GIMA_CAP1_3_IN_SYNCH_Pos                              2
#define GIMA_CAP1_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos)
#define GIMA_CAP1_3_IN_PULSE_Pos                              3
#define GIMA_CAP1_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos)
#define GIMA_CAP1_3_IN_SELECT_Pos                             4
#define GIMA_CAP1_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP2_0_IN  -----------------------------------------
#define GIMA_CAP2_0_IN_INV_Pos                                0
#define GIMA_CAP2_0_IN_INV_Msk                                (0x01UL << GIMA_CAP2_0_IN_INV_Pos)
#define GIMA_CAP2_0_IN_EDGE_Pos                               1
#define GIMA_CAP2_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos)
#define GIMA_CAP2_0_IN_SYNCH_Pos                              2
#define GIMA_CAP2_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos)
#define GIMA_CAP2_0_IN_PULSE_Pos                              3
#define GIMA_CAP2_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos)
#define GIMA_CAP2_0_IN_SELECT_Pos                             4
#define GIMA_CAP2_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP2_1_IN  -----------------------------------------
#define GIMA_CAP2_1_IN_INV_Pos                                0
#define GIMA_CAP2_1_IN_INV_Msk                                (0x01UL << GIMA_CAP2_1_IN_INV_Pos)
#define GIMA_CAP2_1_IN_EDGE_Pos                               1
#define GIMA_CAP2_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos)
#define GIMA_CAP2_1_IN_SYNCH_Pos                              2
#define GIMA_CAP2_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos)
#define GIMA_CAP2_1_IN_PULSE_Pos                              3
#define GIMA_CAP2_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos)
#define GIMA_CAP2_1_IN_SELECT_Pos                             4
#define GIMA_CAP2_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP2_2_IN  -----------------------------------------
#define GIMA_CAP2_2_IN_INV_Pos                                0
#define GIMA_CAP2_2_IN_INV_Msk                                (0x01UL << GIMA_CAP2_2_IN_INV_Pos)
#define GIMA_CAP2_2_IN_EDGE_Pos                               1
#define GIMA_CAP2_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos)
#define GIMA_CAP2_2_IN_SYNCH_Pos                              2
#define GIMA_CAP2_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos)
#define GIMA_CAP2_2_IN_PULSE_Pos                              3
#define GIMA_CAP2_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos)
#define GIMA_CAP2_2_IN_SELECT_Pos                             4
#define GIMA_CAP2_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP2_3_IN  -----------------------------------------
#define GIMA_CAP2_3_IN_INV_Pos                                0
#define GIMA_CAP2_3_IN_INV_Msk                                (0x01UL << GIMA_CAP2_3_IN_INV_Pos)
#define GIMA_CAP2_3_IN_EDGE_Pos                               1
#define GIMA_CAP2_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos)
#define GIMA_CAP2_3_IN_SYNCH_Pos                              2
#define GIMA_CAP2_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos)
#define GIMA_CAP2_3_IN_PULSE_Pos                              3
#define GIMA_CAP2_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos)
#define GIMA_CAP2_3_IN_SELECT_Pos                             4
#define GIMA_CAP2_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP3_0_IN  -----------------------------------------
#define GIMA_CAP3_0_IN_INV_Pos                                0
#define GIMA_CAP3_0_IN_INV_Msk                                (0x01UL << GIMA_CAP3_0_IN_INV_Pos)
#define GIMA_CAP3_0_IN_EDGE_Pos                               1
#define GIMA_CAP3_0_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos)
#define GIMA_CAP3_0_IN_SYNCH_Pos                              2
#define GIMA_CAP3_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos)
#define GIMA_CAP3_0_IN_PULSE_Pos                              3
#define GIMA_CAP3_0_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos)
#define GIMA_CAP3_0_IN_SELECT_Pos                             4
#define GIMA_CAP3_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP3_1_IN  -----------------------------------------
#define GIMA_CAP3_1_IN_INV_Pos                                0
#define GIMA_CAP3_1_IN_INV_Msk                                (0x01UL << GIMA_CAP3_1_IN_INV_Pos)
#define GIMA_CAP3_1_IN_EDGE_Pos                               1
#define GIMA_CAP3_1_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos)
#define GIMA_CAP3_1_IN_SYNCH_Pos                              2
#define GIMA_CAP3_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos)
#define GIMA_CAP3_1_IN_PULSE_Pos                              3
#define GIMA_CAP3_1_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos)
#define GIMA_CAP3_1_IN_SELECT_Pos                             4
#define GIMA_CAP3_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP3_2_IN  -----------------------------------------
#define GIMA_CAP3_2_IN_INV_Pos                                0
#define GIMA_CAP3_2_IN_INV_Msk                                (0x01UL << GIMA_CAP3_2_IN_INV_Pos)
#define GIMA_CAP3_2_IN_EDGE_Pos                               1
#define GIMA_CAP3_2_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos)
#define GIMA_CAP3_2_IN_SYNCH_Pos                              2
#define GIMA_CAP3_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos)
#define GIMA_CAP3_2_IN_PULSE_Pos                              3
#define GIMA_CAP3_2_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos)
#define GIMA_CAP3_2_IN_SELECT_Pos                             4
#define GIMA_CAP3_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos)

// -------------------------------------  GIMA_CAP3_3_IN  -----------------------------------------
#define GIMA_CAP3_3_IN_INV_Pos                                0
#define GIMA_CAP3_3_IN_INV_Msk                                (0x01UL << GIMA_CAP3_3_IN_INV_Pos)
#define GIMA_CAP3_3_IN_EDGE_Pos                               1
#define GIMA_CAP3_3_IN_EDGE_Msk                               (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos)
#define GIMA_CAP3_3_IN_SYNCH_Pos                              2
#define GIMA_CAP3_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos)
#define GIMA_CAP3_3_IN_PULSE_Pos                              3
#define GIMA_CAP3_3_IN_PULSE_Msk                              (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos)
#define GIMA_CAP3_3_IN_SELECT_Pos                             4
#define GIMA_CAP3_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_0_IN  -----------------------------------------
#define GIMA_CTIN_0_IN_INV_Pos                                0
#define GIMA_CTIN_0_IN_INV_Msk                                (0x01UL << GIMA_CTIN_0_IN_INV_Pos)
#define GIMA_CTIN_0_IN_EDGE_Pos                               1
#define GIMA_CTIN_0_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos)
#define GIMA_CTIN_0_IN_SYNCH_Pos                              2
#define GIMA_CTIN_0_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos)
#define GIMA_CTIN_0_IN_PULSE_Pos                              3
#define GIMA_CTIN_0_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos)
#define GIMA_CTIN_0_IN_SELECT_Pos                             4
#define GIMA_CTIN_0_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_1_IN  -----------------------------------------
#define GIMA_CTIN_1_IN_INV_Pos                                0
#define GIMA_CTIN_1_IN_INV_Msk                                (0x01UL << GIMA_CTIN_1_IN_INV_Pos)
#define GIMA_CTIN_1_IN_EDGE_Pos                               1
#define GIMA_CTIN_1_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos)
#define GIMA_CTIN_1_IN_SYNCH_Pos                              2
#define GIMA_CTIN_1_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos)
#define GIMA_CTIN_1_IN_PULSE_Pos                              3
#define GIMA_CTIN_1_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos)
#define GIMA_CTIN_1_IN_SELECT_Pos                             4
#define GIMA_CTIN_1_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_2_IN  -----------------------------------------
#define GIMA_CTIN_2_IN_INV_Pos                                0
#define GIMA_CTIN_2_IN_INV_Msk                                (0x01UL << GIMA_CTIN_2_IN_INV_Pos)
#define GIMA_CTIN_2_IN_EDGE_Pos                               1
#define GIMA_CTIN_2_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos)
#define GIMA_CTIN_2_IN_SYNCH_Pos                              2
#define GIMA_CTIN_2_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos)
#define GIMA_CTIN_2_IN_PULSE_Pos                              3
#define GIMA_CTIN_2_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos)
#define GIMA_CTIN_2_IN_SELECT_Pos                             4
#define GIMA_CTIN_2_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_3_IN  -----------------------------------------
#define GIMA_CTIN_3_IN_INV_Pos                                0
#define GIMA_CTIN_3_IN_INV_Msk                                (0x01UL << GIMA_CTIN_3_IN_INV_Pos)
#define GIMA_CTIN_3_IN_EDGE_Pos                               1
#define GIMA_CTIN_3_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos)
#define GIMA_CTIN_3_IN_SYNCH_Pos                              2
#define GIMA_CTIN_3_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos)
#define GIMA_CTIN_3_IN_PULSE_Pos                              3
#define GIMA_CTIN_3_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos)
#define GIMA_CTIN_3_IN_SELECT_Pos                             4
#define GIMA_CTIN_3_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_4_IN  -----------------------------------------
#define GIMA_CTIN_4_IN_INV_Pos                                0
#define GIMA_CTIN_4_IN_INV_Msk                                (0x01UL << GIMA_CTIN_4_IN_INV_Pos)
#define GIMA_CTIN_4_IN_EDGE_Pos                               1
#define GIMA_CTIN_4_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos)
#define GIMA_CTIN_4_IN_SYNCH_Pos                              2
#define GIMA_CTIN_4_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos)
#define GIMA_CTIN_4_IN_PULSE_Pos                              3
#define GIMA_CTIN_4_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos)
#define GIMA_CTIN_4_IN_SELECT_Pos                             4
#define GIMA_CTIN_4_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_5_IN  -----------------------------------------
#define GIMA_CTIN_5_IN_INV_Pos                                0
#define GIMA_CTIN_5_IN_INV_Msk                                (0x01UL << GIMA_CTIN_5_IN_INV_Pos)
#define GIMA_CTIN_5_IN_EDGE_Pos                               1
#define GIMA_CTIN_5_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos)
#define GIMA_CTIN_5_IN_SYNCH_Pos                              2
#define GIMA_CTIN_5_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos)
#define GIMA_CTIN_5_IN_PULSE_Pos                              3
#define GIMA_CTIN_5_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos)
#define GIMA_CTIN_5_IN_SELECT_Pos                             4
#define GIMA_CTIN_5_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_6_IN  -----------------------------------------
#define GIMA_CTIN_6_IN_INV_Pos                                0
#define GIMA_CTIN_6_IN_INV_Msk                                (0x01UL << GIMA_CTIN_6_IN_INV_Pos)
#define GIMA_CTIN_6_IN_EDGE_Pos                               1
#define GIMA_CTIN_6_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos)
#define GIMA_CTIN_6_IN_SYNCH_Pos                              2
#define GIMA_CTIN_6_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos)
#define GIMA_CTIN_6_IN_PULSE_Pos                              3
#define GIMA_CTIN_6_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos)
#define GIMA_CTIN_6_IN_SELECT_Pos                             4
#define GIMA_CTIN_6_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos)

// -------------------------------------  GIMA_CTIN_7_IN  -----------------------------------------
#define GIMA_CTIN_7_IN_INV_Pos                                0
#define GIMA_CTIN_7_IN_INV_Msk                                (0x01UL << GIMA_CTIN_7_IN_INV_Pos)
#define GIMA_CTIN_7_IN_EDGE_Pos                               1
#define GIMA_CTIN_7_IN_EDGE_Msk                               (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos)
#define GIMA_CTIN_7_IN_SYNCH_Pos                              2
#define GIMA_CTIN_7_IN_SYNCH_Msk                              (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos)
#define GIMA_CTIN_7_IN_PULSE_Pos                              3
#define GIMA_CTIN_7_IN_PULSE_Msk                              (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos)
#define GIMA_CTIN_7_IN_SELECT_Pos                             4
#define GIMA_CTIN_7_IN_SELECT_Msk                             (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos)

// ----------------------------------  GIMA_VADC_TRIGGER_IN  --------------------------------------
#define GIMA_VADC_TRIGGER_IN_INV_Pos                          0
#define GIMA_VADC_TRIGGER_IN_INV_Msk                          (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos)
#define GIMA_VADC_TRIGGER_IN_EDGE_Pos                         1
#define GIMA_VADC_TRIGGER_IN_EDGE_Msk                         (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos)
#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos                        2
#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos)
#define GIMA_VADC_TRIGGER_IN_PULSE_Pos                        3
#define GIMA_VADC_TRIGGER_IN_PULSE_Msk                        (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos)
#define GIMA_VADC_TRIGGER_IN_SELECT_Pos                       4
#define GIMA_VADC_TRIGGER_IN_SELECT_Msk                       (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos)

// ---------------------------------  GIMA_EVENTROUTER_13_IN  -------------------------------------
#define GIMA_EVENTROUTER_13_IN_INV_Pos                        0
#define GIMA_EVENTROUTER_13_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos)
#define GIMA_EVENTROUTER_13_IN_EDGE_Pos                       1
#define GIMA_EVENTROUTER_13_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos)
#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos                      2
#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos)
#define GIMA_EVENTROUTER_13_IN_PULSE_Pos                      3
#define GIMA_EVENTROUTER_13_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos)
#define GIMA_EVENTROUTER_13_IN_SELECT_Pos                     4
#define GIMA_EVENTROUTER_13_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos)

// ---------------------------------  GIMA_EVENTROUTER_14_IN  -------------------------------------
#define GIMA_EVENTROUTER_14_IN_INV_Pos                        0
#define GIMA_EVENTROUTER_14_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos)
#define GIMA_EVENTROUTER_14_IN_EDGE_Pos                       1
#define GIMA_EVENTROUTER_14_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos)
#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos                      2
#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos)
#define GIMA_EVENTROUTER_14_IN_PULSE_Pos                      3
#define GIMA_EVENTROUTER_14_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos)
#define GIMA_EVENTROUTER_14_IN_SELECT_Pos                     4
#define GIMA_EVENTROUTER_14_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos)

// ---------------------------------  GIMA_EVENTROUTER_16_IN  -------------------------------------
#define GIMA_EVENTROUTER_16_IN_INV_Pos                        0
#define GIMA_EVENTROUTER_16_IN_INV_Msk                        (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos)
#define GIMA_EVENTROUTER_16_IN_EDGE_Pos                       1
#define GIMA_EVENTROUTER_16_IN_EDGE_Msk                       (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos)
#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos                      2
#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos)
#define GIMA_EVENTROUTER_16_IN_PULSE_Pos                      3
#define GIMA_EVENTROUTER_16_IN_PULSE_Msk                      (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos)
#define GIMA_EVENTROUTER_16_IN_SELECT_Pos                     4
#define GIMA_EVENTROUTER_16_IN_SELECT_Msk                     (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos)

// ------------------------------------  GIMA_ADCSTART0_IN  ---------------------------------------
#define GIMA_ADCSTART0_IN_INV_Pos                             0
#define GIMA_ADCSTART0_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART0_IN_INV_Pos)
#define GIMA_ADCSTART0_IN_EDGE_Pos                            1
#define GIMA_ADCSTART0_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos)
#define GIMA_ADCSTART0_IN_SYNCH_Pos                           2
#define GIMA_ADCSTART0_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos)
#define GIMA_ADCSTART0_IN_PULSE_Pos                           3
#define GIMA_ADCSTART0_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos)
#define GIMA_ADCSTART0_IN_SELECT_Pos                          4
#define GIMA_ADCSTART0_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos)

// ------------------------------------  GIMA_ADCSTART1_IN  ---------------------------------------
#define GIMA_ADCSTART1_IN_INV_Pos                             0
#define GIMA_ADCSTART1_IN_INV_Msk                             (0x01UL << GIMA_ADCSTART1_IN_INV_Pos)
#define GIMA_ADCSTART1_IN_EDGE_Pos                            1
#define GIMA_ADCSTART1_IN_EDGE_Msk                            (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos)
#define GIMA_ADCSTART1_IN_SYNCH_Pos                           2
#define GIMA_ADCSTART1_IN_SYNCH_Msk                           (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos)
#define GIMA_ADCSTART1_IN_PULSE_Pos                           3
#define GIMA_ADCSTART1_IN_PULSE_Msk                           (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos)
#define GIMA_ADCSTART1_IN_SELECT_Pos                          4
#define GIMA_ADCSTART1_IN_SELECT_Msk                          (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  DAC Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  DAC_CR  ---------------------------------------------
#define DAC_CR_VALUE_Pos                                      6
#define DAC_CR_VALUE_Msk                                      (0x000003ffUL << DAC_CR_VALUE_Pos)
#define DAC_CR_BIAS_Pos                                       16
#define DAC_CR_BIAS_Msk                                       (0x01UL << DAC_CR_BIAS_Pos)

// ----------------------------------------  DAC_CTRL  --------------------------------------------
#define DAC_CTRL_INT_DMA_REQ_Pos                              0
#define DAC_CTRL_INT_DMA_REQ_Msk                              (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos)
#define DAC_CTRL_DBLBUF_ENA_Pos                               1
#define DAC_CTRL_DBLBUF_ENA_Msk                               (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos)
#define DAC_CTRL_CNT_ENA_Pos                                  2
#define DAC_CTRL_CNT_ENA_Msk                                  (0x01UL << DAC_CTRL_CNT_ENA_Pos)
#define DAC_CTRL_DMA_ENA_Pos                                  3
#define DAC_CTRL_DMA_ENA_Msk                                  (0x01UL << DAC_CTRL_DMA_ENA_Pos)

// ---------------------------------------  DAC_CNTVAL  -------------------------------------------
#define DAC_CNTVAL_VALUE_Pos                                  0
#define DAC_CNTVAL_VALUE_Msk                                  (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                C_CAN0 Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// ---------------------------------------  C_CAN0_CNTL  ------------------------------------------
#define C_CAN0_CNTL_INIT_Pos                                  0
#define C_CAN0_CNTL_INIT_Msk                                  (0x01UL << C_CAN0_CNTL_INIT_Pos)
#define C_CAN0_CNTL_IE_Pos                                    1
#define C_CAN0_CNTL_IE_Msk                                    (0x01UL << C_CAN0_CNTL_IE_Pos)
#define C_CAN0_CNTL_SIE_Pos                                   2
#define C_CAN0_CNTL_SIE_Msk                                   (0x01UL << C_CAN0_CNTL_SIE_Pos)
#define C_CAN0_CNTL_EIE_Pos                                   3
#define C_CAN0_CNTL_EIE_Msk                                   (0x01UL << C_CAN0_CNTL_EIE_Pos)
#define C_CAN0_CNTL_DAR_Pos                                   5
#define C_CAN0_CNTL_DAR_Msk                                   (0x01UL << C_CAN0_CNTL_DAR_Pos)
#define C_CAN0_CNTL_CCE_Pos                                   6
#define C_CAN0_CNTL_CCE_Msk                                   (0x01UL << C_CAN0_CNTL_CCE_Pos)
#define C_CAN0_CNTL_TEST_Pos                                  7
#define C_CAN0_CNTL_TEST_Msk                                  (0x01UL << C_CAN0_CNTL_TEST_Pos)

// ---------------------------------------  C_CAN0_STAT  ------------------------------------------
#define C_CAN0_STAT_LEC_Pos                                   0
#define C_CAN0_STAT_LEC_Msk                                   (0x07UL << C_CAN0_STAT_LEC_Pos)
#define C_CAN0_STAT_TXOK_Pos                                  3
#define C_CAN0_STAT_TXOK_Msk                                  (0x01UL << C_CAN0_STAT_TXOK_Pos)
#define C_CAN0_STAT_RXOK_Pos                                  4
#define C_CAN0_STAT_RXOK_Msk                                  (0x01UL << C_CAN0_STAT_RXOK_Pos)
#define C_CAN0_STAT_EPASS_Pos                                 5
#define C_CAN0_STAT_EPASS_Msk                                 (0x01UL << C_CAN0_STAT_EPASS_Pos)
#define C_CAN0_STAT_EWARN_Pos                                 6
#define C_CAN0_STAT_EWARN_Msk                                 (0x01UL << C_CAN0_STAT_EWARN_Pos)
#define C_CAN0_STAT_BOFF_Pos                                  7
#define C_CAN0_STAT_BOFF_Msk                                  (0x01UL << C_CAN0_STAT_BOFF_Pos)

// ----------------------------------------  C_CAN0_EC  -------------------------------------------
#define C_CAN0_EC_TEC_7_0_Pos                                 0
#define C_CAN0_EC_TEC_7_0_Msk                                 (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos)
#define C_CAN0_EC_REC_6_0_Pos                                 8
#define C_CAN0_EC_REC_6_0_Msk                                 (0x7fUL << C_CAN0_EC_REC_6_0_Pos)
#define C_CAN0_EC_RP_Pos                                      15
#define C_CAN0_EC_RP_Msk                                      (0x01UL << C_CAN0_EC_RP_Pos)

// ----------------------------------------  C_CAN0_BT  -------------------------------------------
#define C_CAN0_BT_BRP_Pos                                     0
#define C_CAN0_BT_BRP_Msk                                     (0x3fUL << C_CAN0_BT_BRP_Pos)
#define C_CAN0_BT_SJW_Pos                                     6
#define C_CAN0_BT_SJW_Msk                                     (0x03UL << C_CAN0_BT_SJW_Pos)
#define C_CAN0_BT_TSEG1_Pos                                   8
#define C_CAN0_BT_TSEG1_Msk                                   (0x0fUL << C_CAN0_BT_TSEG1_Pos)
#define C_CAN0_BT_TSEG2_Pos                                   12
#define C_CAN0_BT_TSEG2_Msk                                   (0x07UL << C_CAN0_BT_TSEG2_Pos)

// ---------------------------------------  C_CAN0_INT  -------------------------------------------
#define C_CAN0_INT_INTID15_0_Pos                              0
#define C_CAN0_INT_INTID15_0_Msk                              (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos)

// ---------------------------------------  C_CAN0_TEST  ------------------------------------------
#define C_CAN0_TEST_BASIC_Pos                                 2
#define C_CAN0_TEST_BASIC_Msk                                 (0x01UL << C_CAN0_TEST_BASIC_Pos)
#define C_CAN0_TEST_SILENT_Pos                                3
#define C_CAN0_TEST_SILENT_Msk                                (0x01UL << C_CAN0_TEST_SILENT_Pos)
#define C_CAN0_TEST_LBACK_Pos                                 4
#define C_CAN0_TEST_LBACK_Msk                                 (0x01UL << C_CAN0_TEST_LBACK_Pos)
#define C_CAN0_TEST_TX1_0_Pos                                 5
#define C_CAN0_TEST_TX1_0_Msk                                 (0x03UL << C_CAN0_TEST_TX1_0_Pos)
#define C_CAN0_TEST_RX_Pos                                    7
#define C_CAN0_TEST_RX_Msk                                    (0x01UL << C_CAN0_TEST_RX_Pos)

// ---------------------------------------  C_CAN0_BRPE  ------------------------------------------
#define C_CAN0_BRPE_BRPE_Pos                                  0
#define C_CAN0_BRPE_BRPE_Msk                                  (0x0fUL << C_CAN0_BRPE_BRPE_Pos)

// ------------------------------------  C_CAN0_IF1_CMDREQ  ---------------------------------------
#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos                         0
#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos)
#define C_CAN0_IF1_CMDREQ_BUSY_Pos                            15
#define C_CAN0_IF1_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos)

// -----------------------------------  C_CAN0_IF1_CMDMSK_R  --------------------------------------
#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos                        0
#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos)
#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos                        1
#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos)
#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos                        2
#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos)
#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos                     3
#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos)
#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos                          4
#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos)
#define C_CAN0_IF1_CMDMSK_R_ARB_Pos                           5
#define C_CAN0_IF1_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos)
#define C_CAN0_IF1_CMDMSK_R_MASK_Pos                          6
#define C_CAN0_IF1_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos)
#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos                         7
#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos)

// -----------------------------------  C_CAN0_IF1_CMDMSK_W  --------------------------------------
#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos                        0
#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos)
#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos                        1
#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos)
#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos                        2
#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos)
#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos                     3
#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos)
#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos                          4
#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos)
#define C_CAN0_IF1_CMDMSK_W_ARB_Pos                           5
#define C_CAN0_IF1_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos)
#define C_CAN0_IF1_CMDMSK_W_MASK_Pos                          6
#define C_CAN0_IF1_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos)
#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos                         7
#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos)

// -------------------------------------  C_CAN0_IF1_MSK1  ----------------------------------------
#define C_CAN0_IF1_MSK1_MSK15_0_Pos                           0
#define C_CAN0_IF1_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos)

// -------------------------------------  C_CAN0_IF1_MSK2  ----------------------------------------
#define C_CAN0_IF1_MSK2_MSK28_16_Pos                          0
#define C_CAN0_IF1_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos)
#define C_CAN0_IF1_MSK2_MDIR_Pos                              14
#define C_CAN0_IF1_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos)
#define C_CAN0_IF1_MSK2_MXTD_Pos                              15
#define C_CAN0_IF1_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos)

// -------------------------------------  C_CAN0_IF1_ARB1  ----------------------------------------
#define C_CAN0_IF1_ARB1_ID15_0_Pos                            0
#define C_CAN0_IF1_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos)

// -------------------------------------  C_CAN0_IF1_ARB2  ----------------------------------------
#define C_CAN0_IF1_ARB2_ID28_16_Pos                           0
#define C_CAN0_IF1_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos)
#define C_CAN0_IF1_ARB2_DIR_Pos                               13
#define C_CAN0_IF1_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos)
#define C_CAN0_IF1_ARB2_XTD_Pos                               14
#define C_CAN0_IF1_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos)
#define C_CAN0_IF1_ARB2_MSGVAL_Pos                            15
#define C_CAN0_IF1_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos)

// ------------------------------------  C_CAN0_IF1_MCTRL  ----------------------------------------
#define C_CAN0_IF1_MCTRL_DLC3_0_Pos                           0
#define C_CAN0_IF1_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos)
#define C_CAN0_IF1_MCTRL_EOB_Pos                              7
#define C_CAN0_IF1_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos)
#define C_CAN0_IF1_MCTRL_TXRQST_Pos                           8
#define C_CAN0_IF1_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos)
#define C_CAN0_IF1_MCTRL_RMTEN_Pos                            9
#define C_CAN0_IF1_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos)
#define C_CAN0_IF1_MCTRL_RXIE_Pos                             10
#define C_CAN0_IF1_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos)
#define C_CAN0_IF1_MCTRL_TXIE_Pos                             11
#define C_CAN0_IF1_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos)
#define C_CAN0_IF1_MCTRL_UMASK_Pos                            12
#define C_CAN0_IF1_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos)
#define C_CAN0_IF1_MCTRL_INTPND_Pos                           13
#define C_CAN0_IF1_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos)
#define C_CAN0_IF1_MCTRL_MSGLST_Pos                           14
#define C_CAN0_IF1_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos)
#define C_CAN0_IF1_MCTRL_NEWDAT_Pos                           15
#define C_CAN0_IF1_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos)

// -------------------------------------  C_CAN0_IF1_DA1  -----------------------------------------
#define C_CAN0_IF1_DA1_DATA0_Pos                              0
#define C_CAN0_IF1_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos)
#define C_CAN0_IF1_DA1_DATA1_Pos                              8
#define C_CAN0_IF1_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos)

// -------------------------------------  C_CAN0_IF1_DA2  -----------------------------------------
#define C_CAN0_IF1_DA2_DATA2_Pos                              0
#define C_CAN0_IF1_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos)
#define C_CAN0_IF1_DA2_DATA3_Pos                              8
#define C_CAN0_IF1_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos)

// -------------------------------------  C_CAN0_IF1_DB1  -----------------------------------------
#define C_CAN0_IF1_DB1_DATA4_Pos                              0
#define C_CAN0_IF1_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos)
#define C_CAN0_IF1_DB1_DATA5_Pos                              8
#define C_CAN0_IF1_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos)

// -------------------------------------  C_CAN0_IF1_DB2  -----------------------------------------
#define C_CAN0_IF1_DB2_DATA6_Pos                              0
#define C_CAN0_IF1_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos)
#define C_CAN0_IF1_DB2_DATA7_Pos                              8
#define C_CAN0_IF1_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos)

// ------------------------------------  C_CAN0_IF2_CMDREQ  ---------------------------------------
#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos                         0
#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk                         (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos)
#define C_CAN0_IF2_CMDREQ_BUSY_Pos                            15
#define C_CAN0_IF2_CMDREQ_BUSY_Msk                            (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos)

// -----------------------------------  C_CAN0_IF2_CMDMSK_R  --------------------------------------
#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos                        0
#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos)
#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos                        1
#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos)
#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos                        2
#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos)
#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos                     3
#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos)
#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos                          4
#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos)
#define C_CAN0_IF2_CMDMSK_R_ARB_Pos                           5
#define C_CAN0_IF2_CMDMSK_R_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos)
#define C_CAN0_IF2_CMDMSK_R_MASK_Pos                          6
#define C_CAN0_IF2_CMDMSK_R_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos)
#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos                         7
#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos)

// -----------------------------------  C_CAN0_IF2_CMDMSK_W  --------------------------------------
#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos                        0
#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos)
#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos                        1
#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos)
#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos                        2
#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk                        (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos)
#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos                     3
#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk                     (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos)
#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos                          4
#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos)
#define C_CAN0_IF2_CMDMSK_W_ARB_Pos                           5
#define C_CAN0_IF2_CMDMSK_W_ARB_Msk                           (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos)
#define C_CAN0_IF2_CMDMSK_W_MASK_Pos                          6
#define C_CAN0_IF2_CMDMSK_W_MASK_Msk                          (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos)
#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos                         7
#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk                         (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos)

// -------------------------------------  C_CAN0_IF2_MSK1  ----------------------------------------
#define C_CAN0_IF2_MSK1_MSK15_0_Pos                           0
#define C_CAN0_IF2_MSK1_MSK15_0_Msk                           (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos)

// -------------------------------------  C_CAN0_IF2_MSK2  ----------------------------------------
#define C_CAN0_IF2_MSK2_MSK28_16_Pos                          0
#define C_CAN0_IF2_MSK2_MSK28_16_Msk                          (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos)
#define C_CAN0_IF2_MSK2_MDIR_Pos                              14
#define C_CAN0_IF2_MSK2_MDIR_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos)
#define C_CAN0_IF2_MSK2_MXTD_Pos                              15
#define C_CAN0_IF2_MSK2_MXTD_Msk                              (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos)

// -------------------------------------  C_CAN0_IF2_ARB1  ----------------------------------------
#define C_CAN0_IF2_ARB1_ID15_0_Pos                            0
#define C_CAN0_IF2_ARB1_ID15_0_Msk                            (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos)

// -------------------------------------  C_CAN0_IF2_ARB2  ----------------------------------------
#define C_CAN0_IF2_ARB2_ID28_16_Pos                           0
#define C_CAN0_IF2_ARB2_ID28_16_Msk                           (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos)
#define C_CAN0_IF2_ARB2_DIR_Pos                               13
#define C_CAN0_IF2_ARB2_DIR_Msk                               (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos)
#define C_CAN0_IF2_ARB2_XTD_Pos                               14
#define C_CAN0_IF2_ARB2_XTD_Msk                               (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos)
#define C_CAN0_IF2_ARB2_MSGVAL_Pos                            15
#define C_CAN0_IF2_ARB2_MSGVAL_Msk                            (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos)

// ------------------------------------  C_CAN0_IF2_MCTRL  ----------------------------------------
#define C_CAN0_IF2_MCTRL_DLC3_0_Pos                           0
#define C_CAN0_IF2_MCTRL_DLC3_0_Msk                           (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos)
#define C_CAN0_IF2_MCTRL_EOB_Pos                              7
#define C_CAN0_IF2_MCTRL_EOB_Msk                              (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos)
#define C_CAN0_IF2_MCTRL_TXRQST_Pos                           8
#define C_CAN0_IF2_MCTRL_TXRQST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos)
#define C_CAN0_IF2_MCTRL_RMTEN_Pos                            9
#define C_CAN0_IF2_MCTRL_RMTEN_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos)
#define C_CAN0_IF2_MCTRL_RXIE_Pos                             10
#define C_CAN0_IF2_MCTRL_RXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos)
#define C_CAN0_IF2_MCTRL_TXIE_Pos                             11
#define C_CAN0_IF2_MCTRL_TXIE_Msk                             (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos)
#define C_CAN0_IF2_MCTRL_UMASK_Pos                            12
#define C_CAN0_IF2_MCTRL_UMASK_Msk                            (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos)
#define C_CAN0_IF2_MCTRL_INTPND_Pos                           13
#define C_CAN0_IF2_MCTRL_INTPND_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos)
#define C_CAN0_IF2_MCTRL_MSGLST_Pos                           14
#define C_CAN0_IF2_MCTRL_MSGLST_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos)
#define C_CAN0_IF2_MCTRL_NEWDAT_Pos                           15
#define C_CAN0_IF2_MCTRL_NEWDAT_Msk                           (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos)

// -------------------------------------  C_CAN0_IF2_DA1  -----------------------------------------
#define C_CAN0_IF2_DA1_DATA0_Pos                              0
#define C_CAN0_IF2_DA1_DATA0_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos)
#define C_CAN0_IF2_DA1_DATA1_Pos                              8
#define C_CAN0_IF2_DA1_DATA1_Msk                              (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos)

// -------------------------------------  C_CAN0_IF2_DA2  -----------------------------------------
#define C_CAN0_IF2_DA2_DATA2_Pos                              0
#define C_CAN0_IF2_DA2_DATA2_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos)
#define C_CAN0_IF2_DA2_DATA3_Pos                              8
#define C_CAN0_IF2_DA2_DATA3_Msk                              (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos)

// -------------------------------------  C_CAN0_IF2_DB1  -----------------------------------------
#define C_CAN0_IF2_DB1_DATA4_Pos                              0
#define C_CAN0_IF2_DB1_DATA4_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos)
#define C_CAN0_IF2_DB1_DATA5_Pos                              8
#define C_CAN0_IF2_DB1_DATA5_Msk                              (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos)

// -------------------------------------  C_CAN0_IF2_DB2  -----------------------------------------
#define C_CAN0_IF2_DB2_DATA6_Pos                              0
#define C_CAN0_IF2_DB2_DATA6_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos)
#define C_CAN0_IF2_DB2_DATA7_Pos                              8
#define C_CAN0_IF2_DB2_DATA7_Msk                              (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos)

// --------------------------------------  C_CAN0_TXREQ1  -----------------------------------------
#define C_CAN0_TXREQ1_TXRQST16_1_Pos                          0
#define C_CAN0_TXREQ1_TXRQST16_1_Msk                          (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos)

// --------------------------------------  C_CAN0_TXREQ2  -----------------------------------------
#define C_CAN0_TXREQ2_TXRQST32_17_Pos                         0
#define C_CAN0_TXREQ2_TXRQST32_17_Msk                         (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos)

// ---------------------------------------  C_CAN0_ND1  -------------------------------------------
#define C_CAN0_ND1_NEWDAT16_1_Pos                             0
#define C_CAN0_ND1_NEWDAT16_1_Msk                             (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos)

// ---------------------------------------  C_CAN0_ND2  -------------------------------------------
#define C_CAN0_ND2_NEWDAT32_17_Pos                            0
#define C_CAN0_ND2_NEWDAT32_17_Msk                            (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos)

// ---------------------------------------  C_CAN0_IR1  -------------------------------------------
#define C_CAN0_IR1_INTPND16_1_Pos                             0
#define C_CAN0_IR1_INTPND16_1_Msk                             (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos)

// ---------------------------------------  C_CAN0_IR2  -------------------------------------------
#define C_CAN0_IR2_INTPND32_17_Pos                            0
#define C_CAN0_IR2_INTPND32_17_Msk                            (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos)

// --------------------------------------  C_CAN0_MSGV1  ------------------------------------------
#define C_CAN0_MSGV1_MSGVAL16_1_Pos                           0
#define C_CAN0_MSGV1_MSGVAL16_1_Msk                           (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos)

// --------------------------------------  C_CAN0_MSGV2  ------------------------------------------
#define C_CAN0_MSGV2_MSGVAL32_17_Pos                          0
#define C_CAN0_MSGV2_MSGVAL32_17_Msk                          (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos)

// --------------------------------------  C_CAN0_CLKDIV  -----------------------------------------
#define C_CAN0_CLKDIV_CLKDIVVAL_Pos                           0
#define C_CAN0_CLKDIV_CLKDIVVAL_Msk                           (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 ADC0 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  ADC0_CR  --------------------------------------------
#define ADC0_CR_SEL_Pos                                       0
#define ADC0_CR_SEL_Msk                                       (0x000000ffUL << ADC0_CR_SEL_Pos)
#define ADC0_CR_CLKDIV_Pos                                    8
#define ADC0_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC0_CR_CLKDIV_Pos)
#define ADC0_CR_BURST_Pos                                     16
#define ADC0_CR_BURST_Msk                                     (0x01UL << ADC0_CR_BURST_Pos)
#define ADC0_CR_CLKS_Pos                                      17
#define ADC0_CR_CLKS_Msk                                      (0x07UL << ADC0_CR_CLKS_Pos)
#define ADC0_CR_PDN_Pos                                       21
#define ADC0_CR_PDN_Msk                                       (0x01UL << ADC0_CR_PDN_Pos)
#define ADC0_CR_START_Pos                                     24
#define ADC0_CR_START_Msk                                     (0x07UL << ADC0_CR_START_Pos)
#define ADC0_CR_EDGE_Pos                                      27
#define ADC0_CR_EDGE_Msk                                      (0x01UL << ADC0_CR_EDGE_Pos)

// ----------------------------------------  ADC0_GDR  --------------------------------------------
#define ADC0_GDR_V_VREF_Pos                                   6
#define ADC0_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC0_GDR_V_VREF_Pos)
#define ADC0_GDR_CHN_Pos                                      24
#define ADC0_GDR_CHN_Msk                                      (0x07UL << ADC0_GDR_CHN_Pos)
#define ADC0_GDR_OVERRUN_Pos                                  30
#define ADC0_GDR_OVERRUN_Msk                                  (0x01UL << ADC0_GDR_OVERRUN_Pos)
#define ADC0_GDR_DONE_Pos                                     31
#define ADC0_GDR_DONE_Msk                                     (0x01UL << ADC0_GDR_DONE_Pos)

// ---------------------------------------  ADC0_INTEN  -------------------------------------------
#define ADC0_INTEN_ADINTEN_Pos                                0
#define ADC0_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos)
#define ADC0_INTEN_ADGINTEN_Pos                               8
#define ADC0_INTEN_ADGINTEN_Msk                               (0x01UL << ADC0_INTEN_ADGINTEN_Pos)

// ----------------------------------------  ADC0_DR0  --------------------------------------------
#define ADC0_DR0_V_VREF_Pos                                   6
#define ADC0_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR0_V_VREF_Pos)
#define ADC0_DR0_OVERRUN_Pos                                  30
#define ADC0_DR0_OVERRUN_Msk                                  (0x01UL << ADC0_DR0_OVERRUN_Pos)
#define ADC0_DR0_DONE_Pos                                     31
#define ADC0_DR0_DONE_Msk                                     (0x01UL << ADC0_DR0_DONE_Pos)

// ----------------------------------------  ADC0_DR1  --------------------------------------------
#define ADC0_DR1_V_VREF_Pos                                   6
#define ADC0_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR1_V_VREF_Pos)
#define ADC0_DR1_OVERRUN_Pos                                  30
#define ADC0_DR1_OVERRUN_Msk                                  (0x01UL << ADC0_DR1_OVERRUN_Pos)
#define ADC0_DR1_DONE_Pos                                     31
#define ADC0_DR1_DONE_Msk                                     (0x01UL << ADC0_DR1_DONE_Pos)

// ----------------------------------------  ADC0_DR2  --------------------------------------------
#define ADC0_DR2_V_VREF_Pos                                   6
#define ADC0_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR2_V_VREF_Pos)
#define ADC0_DR2_OVERRUN_Pos                                  30
#define ADC0_DR2_OVERRUN_Msk                                  (0x01UL << ADC0_DR2_OVERRUN_Pos)
#define ADC0_DR2_DONE_Pos                                     31
#define ADC0_DR2_DONE_Msk                                     (0x01UL << ADC0_DR2_DONE_Pos)

// ----------------------------------------  ADC0_DR3  --------------------------------------------
#define ADC0_DR3_V_VREF_Pos                                   6
#define ADC0_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR3_V_VREF_Pos)
#define ADC0_DR3_OVERRUN_Pos                                  30
#define ADC0_DR3_OVERRUN_Msk                                  (0x01UL << ADC0_DR3_OVERRUN_Pos)
#define ADC0_DR3_DONE_Pos                                     31
#define ADC0_DR3_DONE_Msk                                     (0x01UL << ADC0_DR3_DONE_Pos)

// ----------------------------------------  ADC0_DR4  --------------------------------------------
#define ADC0_DR4_V_VREF_Pos                                   6
#define ADC0_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR4_V_VREF_Pos)
#define ADC0_DR4_OVERRUN_Pos                                  30
#define ADC0_DR4_OVERRUN_Msk                                  (0x01UL << ADC0_DR4_OVERRUN_Pos)
#define ADC0_DR4_DONE_Pos                                     31
#define ADC0_DR4_DONE_Msk                                     (0x01UL << ADC0_DR4_DONE_Pos)

// ----------------------------------------  ADC0_DR5  --------------------------------------------
#define ADC0_DR5_V_VREF_Pos                                   6
#define ADC0_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR5_V_VREF_Pos)
#define ADC0_DR5_OVERRUN_Pos                                  30
#define ADC0_DR5_OVERRUN_Msk                                  (0x01UL << ADC0_DR5_OVERRUN_Pos)
#define ADC0_DR5_DONE_Pos                                     31
#define ADC0_DR5_DONE_Msk                                     (0x01UL << ADC0_DR5_DONE_Pos)

// ----------------------------------------  ADC0_DR6  --------------------------------------------
#define ADC0_DR6_V_VREF_Pos                                   6
#define ADC0_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR6_V_VREF_Pos)
#define ADC0_DR6_OVERRUN_Pos                                  30
#define ADC0_DR6_OVERRUN_Msk                                  (0x01UL << ADC0_DR6_OVERRUN_Pos)
#define ADC0_DR6_DONE_Pos                                     31
#define ADC0_DR6_DONE_Msk                                     (0x01UL << ADC0_DR6_DONE_Pos)

// ----------------------------------------  ADC0_DR7  --------------------------------------------
#define ADC0_DR7_V_VREF_Pos                                   6
#define ADC0_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC0_DR7_V_VREF_Pos)
#define ADC0_DR7_OVERRUN_Pos                                  30
#define ADC0_DR7_OVERRUN_Msk                                  (0x01UL << ADC0_DR7_OVERRUN_Pos)
#define ADC0_DR7_DONE_Pos                                     31
#define ADC0_DR7_DONE_Msk                                     (0x01UL << ADC0_DR7_DONE_Pos)

// ----------------------------------------  ADC0_STAT  -------------------------------------------
#define ADC0_STAT_DONE_Pos                                    0
#define ADC0_STAT_DONE_Msk                                    (0x000000ffUL << ADC0_STAT_DONE_Pos)
#define ADC0_STAT_OVERUN_Pos                                  8
#define ADC0_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC0_STAT_OVERUN_Pos)
#define ADC0_STAT_ADINT_Pos                                   16
#define ADC0_STAT_ADINT_Msk                                   (0x01UL << ADC0_STAT_ADINT_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 ADC1 Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  ADC1_CR  --------------------------------------------
#define ADC1_CR_SEL_Pos                                       0
#define ADC1_CR_SEL_Msk                                       (0x000000ffUL << ADC1_CR_SEL_Pos)
#define ADC1_CR_CLKDIV_Pos                                    8
#define ADC1_CR_CLKDIV_Msk                                    (0x000000ffUL << ADC1_CR_CLKDIV_Pos)
#define ADC1_CR_BURST_Pos                                     16
#define ADC1_CR_BURST_Msk                                     (0x01UL << ADC1_CR_BURST_Pos)
#define ADC1_CR_CLKS_Pos                                      17
#define ADC1_CR_CLKS_Msk                                      (0x07UL << ADC1_CR_CLKS_Pos)
#define ADC1_CR_PDN_Pos                                       21
#define ADC1_CR_PDN_Msk                                       (0x01UL << ADC1_CR_PDN_Pos)
#define ADC1_CR_START_Pos                                     24
#define ADC1_CR_START_Msk                                     (0x07UL << ADC1_CR_START_Pos)
#define ADC1_CR_EDGE_Pos                                      27
#define ADC1_CR_EDGE_Msk                                      (0x01UL << ADC1_CR_EDGE_Pos)

// ----------------------------------------  ADC1_GDR  --------------------------------------------
#define ADC1_GDR_V_VREF_Pos                                   6
#define ADC1_GDR_V_VREF_Msk                                   (0x000003ffUL << ADC1_GDR_V_VREF_Pos)
#define ADC1_GDR_CHN_Pos                                      24
#define ADC1_GDR_CHN_Msk                                      (0x07UL << ADC1_GDR_CHN_Pos)
#define ADC1_GDR_OVERRUN_Pos                                  30
#define ADC1_GDR_OVERRUN_Msk                                  (0x01UL << ADC1_GDR_OVERRUN_Pos)
#define ADC1_GDR_DONE_Pos                                     31
#define ADC1_GDR_DONE_Msk                                     (0x01UL << ADC1_GDR_DONE_Pos)

// ---------------------------------------  ADC1_INTEN  -------------------------------------------
#define ADC1_INTEN_ADINTEN_Pos                                0
#define ADC1_INTEN_ADINTEN_Msk                                (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos)
#define ADC1_INTEN_ADGINTEN_Pos                               8
#define ADC1_INTEN_ADGINTEN_Msk                               (0x01UL << ADC1_INTEN_ADGINTEN_Pos)

// ----------------------------------------  ADC1_DR0  --------------------------------------------
#define ADC1_DR0_V_VREF_Pos                                   6
#define ADC1_DR0_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR0_V_VREF_Pos)
#define ADC1_DR0_OVERRUN_Pos                                  30
#define ADC1_DR0_OVERRUN_Msk                                  (0x01UL << ADC1_DR0_OVERRUN_Pos)
#define ADC1_DR0_DONE_Pos                                     31
#define ADC1_DR0_DONE_Msk                                     (0x01UL << ADC1_DR0_DONE_Pos)

// ----------------------------------------  ADC1_DR1  --------------------------------------------
#define ADC1_DR1_V_VREF_Pos                                   6
#define ADC1_DR1_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR1_V_VREF_Pos)
#define ADC1_DR1_OVERRUN_Pos                                  30
#define ADC1_DR1_OVERRUN_Msk                                  (0x01UL << ADC1_DR1_OVERRUN_Pos)
#define ADC1_DR1_DONE_Pos                                     31
#define ADC1_DR1_DONE_Msk                                     (0x01UL << ADC1_DR1_DONE_Pos)

// ----------------------------------------  ADC1_DR2  --------------------------------------------
#define ADC1_DR2_V_VREF_Pos                                   6
#define ADC1_DR2_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR2_V_VREF_Pos)
#define ADC1_DR2_OVERRUN_Pos                                  30
#define ADC1_DR2_OVERRUN_Msk                                  (0x01UL << ADC1_DR2_OVERRUN_Pos)
#define ADC1_DR2_DONE_Pos                                     31
#define ADC1_DR2_DONE_Msk                                     (0x01UL << ADC1_DR2_DONE_Pos)

// ----------------------------------------  ADC1_DR3  --------------------------------------------
#define ADC1_DR3_V_VREF_Pos                                   6
#define ADC1_DR3_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR3_V_VREF_Pos)
#define ADC1_DR3_OVERRUN_Pos                                  30
#define ADC1_DR3_OVERRUN_Msk                                  (0x01UL << ADC1_DR3_OVERRUN_Pos)
#define ADC1_DR3_DONE_Pos                                     31
#define ADC1_DR3_DONE_Msk                                     (0x01UL << ADC1_DR3_DONE_Pos)

// ----------------------------------------  ADC1_DR4  --------------------------------------------
#define ADC1_DR4_V_VREF_Pos                                   6
#define ADC1_DR4_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR4_V_VREF_Pos)
#define ADC1_DR4_OVERRUN_Pos                                  30
#define ADC1_DR4_OVERRUN_Msk                                  (0x01UL << ADC1_DR4_OVERRUN_Pos)
#define ADC1_DR4_DONE_Pos                                     31
#define ADC1_DR4_DONE_Msk                                     (0x01UL << ADC1_DR4_DONE_Pos)

// ----------------------------------------  ADC1_DR5  --------------------------------------------
#define ADC1_DR5_V_VREF_Pos                                   6
#define ADC1_DR5_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR5_V_VREF_Pos)
#define ADC1_DR5_OVERRUN_Pos                                  30
#define ADC1_DR5_OVERRUN_Msk                                  (0x01UL << ADC1_DR5_OVERRUN_Pos)
#define ADC1_DR5_DONE_Pos                                     31
#define ADC1_DR5_DONE_Msk                                     (0x01UL << ADC1_DR5_DONE_Pos)

// ----------------------------------------  ADC1_DR6  --------------------------------------------
#define ADC1_DR6_V_VREF_Pos                                   6
#define ADC1_DR6_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR6_V_VREF_Pos)
#define ADC1_DR6_OVERRUN_Pos                                  30
#define ADC1_DR6_OVERRUN_Msk                                  (0x01UL << ADC1_DR6_OVERRUN_Pos)
#define ADC1_DR6_DONE_Pos                                     31
#define ADC1_DR6_DONE_Msk                                     (0x01UL << ADC1_DR6_DONE_Pos)

// ----------------------------------------  ADC1_DR7  --------------------------------------------
#define ADC1_DR7_V_VREF_Pos                                   6
#define ADC1_DR7_V_VREF_Msk                                   (0x000003ffUL << ADC1_DR7_V_VREF_Pos)
#define ADC1_DR7_OVERRUN_Pos                                  30
#define ADC1_DR7_OVERRUN_Msk                                  (0x01UL << ADC1_DR7_OVERRUN_Pos)
#define ADC1_DR7_DONE_Pos                                     31
#define ADC1_DR7_DONE_Msk                                     (0x01UL << ADC1_DR7_DONE_Pos)

// ----------------------------------------  ADC1_STAT  -------------------------------------------
#define ADC1_STAT_DONE_Pos                                    0
#define ADC1_STAT_DONE_Msk                                    (0x000000ffUL << ADC1_STAT_DONE_Pos)
#define ADC1_STAT_OVERUN_Pos                                  8
#define ADC1_STAT_OVERUN_Msk                                  (0x000000ffUL << ADC1_STAT_OVERUN_Pos)
#define ADC1_STAT_ADINT_Pos                                   16
#define ADC1_STAT_ADINT_Msk                                   (0x01UL << ADC1_STAT_ADINT_Pos)


// ------------------------------------------------------------------------------------------------
// -----                               GPIO_PORT Position & Mask                              -----
// ------------------------------------------------------------------------------------------------


// --------------------------------------  GPIO_PORT_B0  ------------------------------------------
#define GPIO_PORT_B0_PBYTE_Pos                                0
#define GPIO_PORT_B0_PBYTE_Msk                                (0x01UL << GPIO_PORT_B0_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B1  ------------------------------------------
#define GPIO_PORT_B1_PBYTE_Pos                                0
#define GPIO_PORT_B1_PBYTE_Msk                                (0x01UL << GPIO_PORT_B1_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B2  ------------------------------------------
#define GPIO_PORT_B2_PBYTE_Pos                                0
#define GPIO_PORT_B2_PBYTE_Msk                                (0x01UL << GPIO_PORT_B2_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B3  ------------------------------------------
#define GPIO_PORT_B3_PBYTE_Pos                                0
#define GPIO_PORT_B3_PBYTE_Msk                                (0x01UL << GPIO_PORT_B3_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B4  ------------------------------------------
#define GPIO_PORT_B4_PBYTE_Pos                                0
#define GPIO_PORT_B4_PBYTE_Msk                                (0x01UL << GPIO_PORT_B4_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B5  ------------------------------------------
#define GPIO_PORT_B5_PBYTE_Pos                                0
#define GPIO_PORT_B5_PBYTE_Msk                                (0x01UL << GPIO_PORT_B5_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B6  ------------------------------------------
#define GPIO_PORT_B6_PBYTE_Pos                                0
#define GPIO_PORT_B6_PBYTE_Msk                                (0x01UL << GPIO_PORT_B6_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B7  ------------------------------------------
#define GPIO_PORT_B7_PBYTE_Pos                                0
#define GPIO_PORT_B7_PBYTE_Msk                                (0x01UL << GPIO_PORT_B7_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B8  ------------------------------------------
#define GPIO_PORT_B8_PBYTE_Pos                                0
#define GPIO_PORT_B8_PBYTE_Msk                                (0x01UL << GPIO_PORT_B8_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B9  ------------------------------------------
#define GPIO_PORT_B9_PBYTE_Pos                                0
#define GPIO_PORT_B9_PBYTE_Msk                                (0x01UL << GPIO_PORT_B9_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B10  -----------------------------------------
#define GPIO_PORT_B10_PBYTE_Pos                               0
#define GPIO_PORT_B10_PBYTE_Msk                               (0x01UL << GPIO_PORT_B10_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B11  -----------------------------------------
#define GPIO_PORT_B11_PBYTE_Pos                               0
#define GPIO_PORT_B11_PBYTE_Msk                               (0x01UL << GPIO_PORT_B11_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B12  -----------------------------------------
#define GPIO_PORT_B12_PBYTE_Pos                               0
#define GPIO_PORT_B12_PBYTE_Msk                               (0x01UL << GPIO_PORT_B12_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B13  -----------------------------------------
#define GPIO_PORT_B13_PBYTE_Pos                               0
#define GPIO_PORT_B13_PBYTE_Msk                               (0x01UL << GPIO_PORT_B13_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B14  -----------------------------------------
#define GPIO_PORT_B14_PBYTE_Pos                               0
#define GPIO_PORT_B14_PBYTE_Msk                               (0x01UL << GPIO_PORT_B14_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B15  -----------------------------------------
#define GPIO_PORT_B15_PBYTE_Pos                               0
#define GPIO_PORT_B15_PBYTE_Msk                               (0x01UL << GPIO_PORT_B15_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B16  -----------------------------------------
#define GPIO_PORT_B16_PBYTE_Pos                               0
#define GPIO_PORT_B16_PBYTE_Msk                               (0x01UL << GPIO_PORT_B16_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B17  -----------------------------------------
#define GPIO_PORT_B17_PBYTE_Pos                               0
#define GPIO_PORT_B17_PBYTE_Msk                               (0x01UL << GPIO_PORT_B17_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B18  -----------------------------------------
#define GPIO_PORT_B18_PBYTE_Pos                               0
#define GPIO_PORT_B18_PBYTE_Msk                               (0x01UL << GPIO_PORT_B18_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B19  -----------------------------------------
#define GPIO_PORT_B19_PBYTE_Pos                               0
#define GPIO_PORT_B19_PBYTE_Msk                               (0x01UL << GPIO_PORT_B19_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B20  -----------------------------------------
#define GPIO_PORT_B20_PBYTE_Pos                               0
#define GPIO_PORT_B20_PBYTE_Msk                               (0x01UL << GPIO_PORT_B20_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B21  -----------------------------------------
#define GPIO_PORT_B21_PBYTE_Pos                               0
#define GPIO_PORT_B21_PBYTE_Msk                               (0x01UL << GPIO_PORT_B21_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B22  -----------------------------------------
#define GPIO_PORT_B22_PBYTE_Pos                               0
#define GPIO_PORT_B22_PBYTE_Msk                               (0x01UL << GPIO_PORT_B22_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B23  -----------------------------------------
#define GPIO_PORT_B23_PBYTE_Pos                               0
#define GPIO_PORT_B23_PBYTE_Msk                               (0x01UL << GPIO_PORT_B23_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B24  -----------------------------------------
#define GPIO_PORT_B24_PBYTE_Pos                               0
#define GPIO_PORT_B24_PBYTE_Msk                               (0x01UL << GPIO_PORT_B24_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B25  -----------------------------------------
#define GPIO_PORT_B25_PBYTE_Pos                               0
#define GPIO_PORT_B25_PBYTE_Msk                               (0x01UL << GPIO_PORT_B25_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B26  -----------------------------------------
#define GPIO_PORT_B26_PBYTE_Pos                               0
#define GPIO_PORT_B26_PBYTE_Msk                               (0x01UL << GPIO_PORT_B26_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B27  -----------------------------------------
#define GPIO_PORT_B27_PBYTE_Pos                               0
#define GPIO_PORT_B27_PBYTE_Msk                               (0x01UL << GPIO_PORT_B27_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B28  -----------------------------------------
#define GPIO_PORT_B28_PBYTE_Pos                               0
#define GPIO_PORT_B28_PBYTE_Msk                               (0x01UL << GPIO_PORT_B28_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B29  -----------------------------------------
#define GPIO_PORT_B29_PBYTE_Pos                               0
#define GPIO_PORT_B29_PBYTE_Msk                               (0x01UL << GPIO_PORT_B29_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B30  -----------------------------------------
#define GPIO_PORT_B30_PBYTE_Pos                               0
#define GPIO_PORT_B30_PBYTE_Msk                               (0x01UL << GPIO_PORT_B30_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B31  -----------------------------------------
#define GPIO_PORT_B31_PBYTE_Pos                               0
#define GPIO_PORT_B31_PBYTE_Msk                               (0x01UL << GPIO_PORT_B31_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B32  -----------------------------------------
#define GPIO_PORT_B32_PBYTE_Pos                               0
#define GPIO_PORT_B32_PBYTE_Msk                               (0x01UL << GPIO_PORT_B32_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B33  -----------------------------------------
#define GPIO_PORT_B33_PBYTE_Pos                               0
#define GPIO_PORT_B33_PBYTE_Msk                               (0x01UL << GPIO_PORT_B33_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B34  -----------------------------------------
#define GPIO_PORT_B34_PBYTE_Pos                               0
#define GPIO_PORT_B34_PBYTE_Msk                               (0x01UL << GPIO_PORT_B34_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B35  -----------------------------------------
#define GPIO_PORT_B35_PBYTE_Pos                               0
#define GPIO_PORT_B35_PBYTE_Msk                               (0x01UL << GPIO_PORT_B35_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B36  -----------------------------------------
#define GPIO_PORT_B36_PBYTE_Pos                               0
#define GPIO_PORT_B36_PBYTE_Msk                               (0x01UL << GPIO_PORT_B36_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B37  -----------------------------------------
#define GPIO_PORT_B37_PBYTE_Pos                               0
#define GPIO_PORT_B37_PBYTE_Msk                               (0x01UL << GPIO_PORT_B37_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B38  -----------------------------------------
#define GPIO_PORT_B38_PBYTE_Pos                               0
#define GPIO_PORT_B38_PBYTE_Msk                               (0x01UL << GPIO_PORT_B38_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B39  -----------------------------------------
#define GPIO_PORT_B39_PBYTE_Pos                               0
#define GPIO_PORT_B39_PBYTE_Msk                               (0x01UL << GPIO_PORT_B39_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B40  -----------------------------------------
#define GPIO_PORT_B40_PBYTE_Pos                               0
#define GPIO_PORT_B40_PBYTE_Msk                               (0x01UL << GPIO_PORT_B40_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B41  -----------------------------------------
#define GPIO_PORT_B41_PBYTE_Pos                               0
#define GPIO_PORT_B41_PBYTE_Msk                               (0x01UL << GPIO_PORT_B41_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B42  -----------------------------------------
#define GPIO_PORT_B42_PBYTE_Pos                               0
#define GPIO_PORT_B42_PBYTE_Msk                               (0x01UL << GPIO_PORT_B42_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B43  -----------------------------------------
#define GPIO_PORT_B43_PBYTE_Pos                               0
#define GPIO_PORT_B43_PBYTE_Msk                               (0x01UL << GPIO_PORT_B43_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B44  -----------------------------------------
#define GPIO_PORT_B44_PBYTE_Pos                               0
#define GPIO_PORT_B44_PBYTE_Msk                               (0x01UL << GPIO_PORT_B44_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B45  -----------------------------------------
#define GPIO_PORT_B45_PBYTE_Pos                               0
#define GPIO_PORT_B45_PBYTE_Msk                               (0x01UL << GPIO_PORT_B45_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B46  -----------------------------------------
#define GPIO_PORT_B46_PBYTE_Pos                               0
#define GPIO_PORT_B46_PBYTE_Msk                               (0x01UL << GPIO_PORT_B46_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B47  -----------------------------------------
#define GPIO_PORT_B47_PBYTE_Pos                               0
#define GPIO_PORT_B47_PBYTE_Msk                               (0x01UL << GPIO_PORT_B47_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B48  -----------------------------------------
#define GPIO_PORT_B48_PBYTE_Pos                               0
#define GPIO_PORT_B48_PBYTE_Msk                               (0x01UL << GPIO_PORT_B48_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B49  -----------------------------------------
#define GPIO_PORT_B49_PBYTE_Pos                               0
#define GPIO_PORT_B49_PBYTE_Msk                               (0x01UL << GPIO_PORT_B49_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B50  -----------------------------------------
#define GPIO_PORT_B50_PBYTE_Pos                               0
#define GPIO_PORT_B50_PBYTE_Msk                               (0x01UL << GPIO_PORT_B50_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B51  -----------------------------------------
#define GPIO_PORT_B51_PBYTE_Pos                               0
#define GPIO_PORT_B51_PBYTE_Msk                               (0x01UL << GPIO_PORT_B51_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B52  -----------------------------------------
#define GPIO_PORT_B52_PBYTE_Pos                               0
#define GPIO_PORT_B52_PBYTE_Msk                               (0x01UL << GPIO_PORT_B52_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B53  -----------------------------------------
#define GPIO_PORT_B53_PBYTE_Pos                               0
#define GPIO_PORT_B53_PBYTE_Msk                               (0x01UL << GPIO_PORT_B53_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B54  -----------------------------------------
#define GPIO_PORT_B54_PBYTE_Pos                               0
#define GPIO_PORT_B54_PBYTE_Msk                               (0x01UL << GPIO_PORT_B54_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B55  -----------------------------------------
#define GPIO_PORT_B55_PBYTE_Pos                               0
#define GPIO_PORT_B55_PBYTE_Msk                               (0x01UL << GPIO_PORT_B55_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B56  -----------------------------------------
#define GPIO_PORT_B56_PBYTE_Pos                               0
#define GPIO_PORT_B56_PBYTE_Msk                               (0x01UL << GPIO_PORT_B56_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B57  -----------------------------------------
#define GPIO_PORT_B57_PBYTE_Pos                               0
#define GPIO_PORT_B57_PBYTE_Msk                               (0x01UL << GPIO_PORT_B57_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B58  -----------------------------------------
#define GPIO_PORT_B58_PBYTE_Pos                               0
#define GPIO_PORT_B58_PBYTE_Msk                               (0x01UL << GPIO_PORT_B58_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B59  -----------------------------------------
#define GPIO_PORT_B59_PBYTE_Pos                               0
#define GPIO_PORT_B59_PBYTE_Msk                               (0x01UL << GPIO_PORT_B59_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B60  -----------------------------------------
#define GPIO_PORT_B60_PBYTE_Pos                               0
#define GPIO_PORT_B60_PBYTE_Msk                               (0x01UL << GPIO_PORT_B60_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B61  -----------------------------------------
#define GPIO_PORT_B61_PBYTE_Pos                               0
#define GPIO_PORT_B61_PBYTE_Msk                               (0x01UL << GPIO_PORT_B61_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B62  -----------------------------------------
#define GPIO_PORT_B62_PBYTE_Pos                               0
#define GPIO_PORT_B62_PBYTE_Msk                               (0x01UL << GPIO_PORT_B62_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B63  -----------------------------------------
#define GPIO_PORT_B63_PBYTE_Pos                               0
#define GPIO_PORT_B63_PBYTE_Msk                               (0x01UL << GPIO_PORT_B63_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B64  -----------------------------------------
#define GPIO_PORT_B64_PBYTE_Pos                               0
#define GPIO_PORT_B64_PBYTE_Msk                               (0x01UL << GPIO_PORT_B64_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B65  -----------------------------------------
#define GPIO_PORT_B65_PBYTE_Pos                               0
#define GPIO_PORT_B65_PBYTE_Msk                               (0x01UL << GPIO_PORT_B65_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B66  -----------------------------------------
#define GPIO_PORT_B66_PBYTE_Pos                               0
#define GPIO_PORT_B66_PBYTE_Msk                               (0x01UL << GPIO_PORT_B66_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B67  -----------------------------------------
#define GPIO_PORT_B67_PBYTE_Pos                               0
#define GPIO_PORT_B67_PBYTE_Msk                               (0x01UL << GPIO_PORT_B67_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B68  -----------------------------------------
#define GPIO_PORT_B68_PBYTE_Pos                               0
#define GPIO_PORT_B68_PBYTE_Msk                               (0x01UL << GPIO_PORT_B68_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B69  -----------------------------------------
#define GPIO_PORT_B69_PBYTE_Pos                               0
#define GPIO_PORT_B69_PBYTE_Msk                               (0x01UL << GPIO_PORT_B69_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B70  -----------------------------------------
#define GPIO_PORT_B70_PBYTE_Pos                               0
#define GPIO_PORT_B70_PBYTE_Msk                               (0x01UL << GPIO_PORT_B70_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B71  -----------------------------------------
#define GPIO_PORT_B71_PBYTE_Pos                               0
#define GPIO_PORT_B71_PBYTE_Msk                               (0x01UL << GPIO_PORT_B71_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B72  -----------------------------------------
#define GPIO_PORT_B72_PBYTE_Pos                               0
#define GPIO_PORT_B72_PBYTE_Msk                               (0x01UL << GPIO_PORT_B72_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B73  -----------------------------------------
#define GPIO_PORT_B73_PBYTE_Pos                               0
#define GPIO_PORT_B73_PBYTE_Msk                               (0x01UL << GPIO_PORT_B73_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B74  -----------------------------------------
#define GPIO_PORT_B74_PBYTE_Pos                               0
#define GPIO_PORT_B74_PBYTE_Msk                               (0x01UL << GPIO_PORT_B74_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B75  -----------------------------------------
#define GPIO_PORT_B75_PBYTE_Pos                               0
#define GPIO_PORT_B75_PBYTE_Msk                               (0x01UL << GPIO_PORT_B75_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B76  -----------------------------------------
#define GPIO_PORT_B76_PBYTE_Pos                               0
#define GPIO_PORT_B76_PBYTE_Msk                               (0x01UL << GPIO_PORT_B76_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B77  -----------------------------------------
#define GPIO_PORT_B77_PBYTE_Pos                               0
#define GPIO_PORT_B77_PBYTE_Msk                               (0x01UL << GPIO_PORT_B77_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B78  -----------------------------------------
#define GPIO_PORT_B78_PBYTE_Pos                               0
#define GPIO_PORT_B78_PBYTE_Msk                               (0x01UL << GPIO_PORT_B78_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B79  -----------------------------------------
#define GPIO_PORT_B79_PBYTE_Pos                               0
#define GPIO_PORT_B79_PBYTE_Msk                               (0x01UL << GPIO_PORT_B79_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B80  -----------------------------------------
#define GPIO_PORT_B80_PBYTE_Pos                               0
#define GPIO_PORT_B80_PBYTE_Msk                               (0x01UL << GPIO_PORT_B80_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B81  -----------------------------------------
#define GPIO_PORT_B81_PBYTE_Pos                               0
#define GPIO_PORT_B81_PBYTE_Msk                               (0x01UL << GPIO_PORT_B81_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B82  -----------------------------------------
#define GPIO_PORT_B82_PBYTE_Pos                               0
#define GPIO_PORT_B82_PBYTE_Msk                               (0x01UL << GPIO_PORT_B82_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B83  -----------------------------------------
#define GPIO_PORT_B83_PBYTE_Pos                               0
#define GPIO_PORT_B83_PBYTE_Msk                               (0x01UL << GPIO_PORT_B83_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B84  -----------------------------------------
#define GPIO_PORT_B84_PBYTE_Pos                               0
#define GPIO_PORT_B84_PBYTE_Msk                               (0x01UL << GPIO_PORT_B84_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B85  -----------------------------------------
#define GPIO_PORT_B85_PBYTE_Pos                               0
#define GPIO_PORT_B85_PBYTE_Msk                               (0x01UL << GPIO_PORT_B85_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B86  -----------------------------------------
#define GPIO_PORT_B86_PBYTE_Pos                               0
#define GPIO_PORT_B86_PBYTE_Msk                               (0x01UL << GPIO_PORT_B86_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B87  -----------------------------------------
#define GPIO_PORT_B87_PBYTE_Pos                               0
#define GPIO_PORT_B87_PBYTE_Msk                               (0x01UL << GPIO_PORT_B87_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B88  -----------------------------------------
#define GPIO_PORT_B88_PBYTE_Pos                               0
#define GPIO_PORT_B88_PBYTE_Msk                               (0x01UL << GPIO_PORT_B88_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B89  -----------------------------------------
#define GPIO_PORT_B89_PBYTE_Pos                               0
#define GPIO_PORT_B89_PBYTE_Msk                               (0x01UL << GPIO_PORT_B89_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B90  -----------------------------------------
#define GPIO_PORT_B90_PBYTE_Pos                               0
#define GPIO_PORT_B90_PBYTE_Msk                               (0x01UL << GPIO_PORT_B90_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B91  -----------------------------------------
#define GPIO_PORT_B91_PBYTE_Pos                               0
#define GPIO_PORT_B91_PBYTE_Msk                               (0x01UL << GPIO_PORT_B91_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B92  -----------------------------------------
#define GPIO_PORT_B92_PBYTE_Pos                               0
#define GPIO_PORT_B92_PBYTE_Msk                               (0x01UL << GPIO_PORT_B92_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B93  -----------------------------------------
#define GPIO_PORT_B93_PBYTE_Pos                               0
#define GPIO_PORT_B93_PBYTE_Msk                               (0x01UL << GPIO_PORT_B93_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B94  -----------------------------------------
#define GPIO_PORT_B94_PBYTE_Pos                               0
#define GPIO_PORT_B94_PBYTE_Msk                               (0x01UL << GPIO_PORT_B94_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B95  -----------------------------------------
#define GPIO_PORT_B95_PBYTE_Pos                               0
#define GPIO_PORT_B95_PBYTE_Msk                               (0x01UL << GPIO_PORT_B95_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B96  -----------------------------------------
#define GPIO_PORT_B96_PBYTE_Pos                               0
#define GPIO_PORT_B96_PBYTE_Msk                               (0x01UL << GPIO_PORT_B96_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B97  -----------------------------------------
#define GPIO_PORT_B97_PBYTE_Pos                               0
#define GPIO_PORT_B97_PBYTE_Msk                               (0x01UL << GPIO_PORT_B97_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B98  -----------------------------------------
#define GPIO_PORT_B98_PBYTE_Pos                               0
#define GPIO_PORT_B98_PBYTE_Msk                               (0x01UL << GPIO_PORT_B98_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_B99  -----------------------------------------
#define GPIO_PORT_B99_PBYTE_Pos                               0
#define GPIO_PORT_B99_PBYTE_Msk                               (0x01UL << GPIO_PORT_B99_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B100  -----------------------------------------
#define GPIO_PORT_B100_PBYTE_Pos                              0
#define GPIO_PORT_B100_PBYTE_Msk                              (0x01UL << GPIO_PORT_B100_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B101  -----------------------------------------
#define GPIO_PORT_B101_PBYTE_Pos                              0
#define GPIO_PORT_B101_PBYTE_Msk                              (0x01UL << GPIO_PORT_B101_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B102  -----------------------------------------
#define GPIO_PORT_B102_PBYTE_Pos                              0
#define GPIO_PORT_B102_PBYTE_Msk                              (0x01UL << GPIO_PORT_B102_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B103  -----------------------------------------
#define GPIO_PORT_B103_PBYTE_Pos                              0
#define GPIO_PORT_B103_PBYTE_Msk                              (0x01UL << GPIO_PORT_B103_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B104  -----------------------------------------
#define GPIO_PORT_B104_PBYTE_Pos                              0
#define GPIO_PORT_B104_PBYTE_Msk                              (0x01UL << GPIO_PORT_B104_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B105  -----------------------------------------
#define GPIO_PORT_B105_PBYTE_Pos                              0
#define GPIO_PORT_B105_PBYTE_Msk                              (0x01UL << GPIO_PORT_B105_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B106  -----------------------------------------
#define GPIO_PORT_B106_PBYTE_Pos                              0
#define GPIO_PORT_B106_PBYTE_Msk                              (0x01UL << GPIO_PORT_B106_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B107  -----------------------------------------
#define GPIO_PORT_B107_PBYTE_Pos                              0
#define GPIO_PORT_B107_PBYTE_Msk                              (0x01UL << GPIO_PORT_B107_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B108  -----------------------------------------
#define GPIO_PORT_B108_PBYTE_Pos                              0
#define GPIO_PORT_B108_PBYTE_Msk                              (0x01UL << GPIO_PORT_B108_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B109  -----------------------------------------
#define GPIO_PORT_B109_PBYTE_Pos                              0
#define GPIO_PORT_B109_PBYTE_Msk                              (0x01UL << GPIO_PORT_B109_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B110  -----------------------------------------
#define GPIO_PORT_B110_PBYTE_Pos                              0
#define GPIO_PORT_B110_PBYTE_Msk                              (0x01UL << GPIO_PORT_B110_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B111  -----------------------------------------
#define GPIO_PORT_B111_PBYTE_Pos                              0
#define GPIO_PORT_B111_PBYTE_Msk                              (0x01UL << GPIO_PORT_B111_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B112  -----------------------------------------
#define GPIO_PORT_B112_PBYTE_Pos                              0
#define GPIO_PORT_B112_PBYTE_Msk                              (0x01UL << GPIO_PORT_B112_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B113  -----------------------------------------
#define GPIO_PORT_B113_PBYTE_Pos                              0
#define GPIO_PORT_B113_PBYTE_Msk                              (0x01UL << GPIO_PORT_B113_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B114  -----------------------------------------
#define GPIO_PORT_B114_PBYTE_Pos                              0
#define GPIO_PORT_B114_PBYTE_Msk                              (0x01UL << GPIO_PORT_B114_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B115  -----------------------------------------
#define GPIO_PORT_B115_PBYTE_Pos                              0
#define GPIO_PORT_B115_PBYTE_Msk                              (0x01UL << GPIO_PORT_B115_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B116  -----------------------------------------
#define GPIO_PORT_B116_PBYTE_Pos                              0
#define GPIO_PORT_B116_PBYTE_Msk                              (0x01UL << GPIO_PORT_B116_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B117  -----------------------------------------
#define GPIO_PORT_B117_PBYTE_Pos                              0
#define GPIO_PORT_B117_PBYTE_Msk                              (0x01UL << GPIO_PORT_B117_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B118  -----------------------------------------
#define GPIO_PORT_B118_PBYTE_Pos                              0
#define GPIO_PORT_B118_PBYTE_Msk                              (0x01UL << GPIO_PORT_B118_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B119  -----------------------------------------
#define GPIO_PORT_B119_PBYTE_Pos                              0
#define GPIO_PORT_B119_PBYTE_Msk                              (0x01UL << GPIO_PORT_B119_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B120  -----------------------------------------
#define GPIO_PORT_B120_PBYTE_Pos                              0
#define GPIO_PORT_B120_PBYTE_Msk                              (0x01UL << GPIO_PORT_B120_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B121  -----------------------------------------
#define GPIO_PORT_B121_PBYTE_Pos                              0
#define GPIO_PORT_B121_PBYTE_Msk                              (0x01UL << GPIO_PORT_B121_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B122  -----------------------------------------
#define GPIO_PORT_B122_PBYTE_Pos                              0
#define GPIO_PORT_B122_PBYTE_Msk                              (0x01UL << GPIO_PORT_B122_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B123  -----------------------------------------
#define GPIO_PORT_B123_PBYTE_Pos                              0
#define GPIO_PORT_B123_PBYTE_Msk                              (0x01UL << GPIO_PORT_B123_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B124  -----------------------------------------
#define GPIO_PORT_B124_PBYTE_Pos                              0
#define GPIO_PORT_B124_PBYTE_Msk                              (0x01UL << GPIO_PORT_B124_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B125  -----------------------------------------
#define GPIO_PORT_B125_PBYTE_Pos                              0
#define GPIO_PORT_B125_PBYTE_Msk                              (0x01UL << GPIO_PORT_B125_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B126  -----------------------------------------
#define GPIO_PORT_B126_PBYTE_Pos                              0
#define GPIO_PORT_B126_PBYTE_Msk                              (0x01UL << GPIO_PORT_B126_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B127  -----------------------------------------
#define GPIO_PORT_B127_PBYTE_Pos                              0
#define GPIO_PORT_B127_PBYTE_Msk                              (0x01UL << GPIO_PORT_B127_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B128  -----------------------------------------
#define GPIO_PORT_B128_PBYTE_Pos                              0
#define GPIO_PORT_B128_PBYTE_Msk                              (0x01UL << GPIO_PORT_B128_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B129  -----------------------------------------
#define GPIO_PORT_B129_PBYTE_Pos                              0
#define GPIO_PORT_B129_PBYTE_Msk                              (0x01UL << GPIO_PORT_B129_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B130  -----------------------------------------
#define GPIO_PORT_B130_PBYTE_Pos                              0
#define GPIO_PORT_B130_PBYTE_Msk                              (0x01UL << GPIO_PORT_B130_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B131  -----------------------------------------
#define GPIO_PORT_B131_PBYTE_Pos                              0
#define GPIO_PORT_B131_PBYTE_Msk                              (0x01UL << GPIO_PORT_B131_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B132  -----------------------------------------
#define GPIO_PORT_B132_PBYTE_Pos                              0
#define GPIO_PORT_B132_PBYTE_Msk                              (0x01UL << GPIO_PORT_B132_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B133  -----------------------------------------
#define GPIO_PORT_B133_PBYTE_Pos                              0
#define GPIO_PORT_B133_PBYTE_Msk                              (0x01UL << GPIO_PORT_B133_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B134  -----------------------------------------
#define GPIO_PORT_B134_PBYTE_Pos                              0
#define GPIO_PORT_B134_PBYTE_Msk                              (0x01UL << GPIO_PORT_B134_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B135  -----------------------------------------
#define GPIO_PORT_B135_PBYTE_Pos                              0
#define GPIO_PORT_B135_PBYTE_Msk                              (0x01UL << GPIO_PORT_B135_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B136  -----------------------------------------
#define GPIO_PORT_B136_PBYTE_Pos                              0
#define GPIO_PORT_B136_PBYTE_Msk                              (0x01UL << GPIO_PORT_B136_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B137  -----------------------------------------
#define GPIO_PORT_B137_PBYTE_Pos                              0
#define GPIO_PORT_B137_PBYTE_Msk                              (0x01UL << GPIO_PORT_B137_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B138  -----------------------------------------
#define GPIO_PORT_B138_PBYTE_Pos                              0
#define GPIO_PORT_B138_PBYTE_Msk                              (0x01UL << GPIO_PORT_B138_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B139  -----------------------------------------
#define GPIO_PORT_B139_PBYTE_Pos                              0
#define GPIO_PORT_B139_PBYTE_Msk                              (0x01UL << GPIO_PORT_B139_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B140  -----------------------------------------
#define GPIO_PORT_B140_PBYTE_Pos                              0
#define GPIO_PORT_B140_PBYTE_Msk                              (0x01UL << GPIO_PORT_B140_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B141  -----------------------------------------
#define GPIO_PORT_B141_PBYTE_Pos                              0
#define GPIO_PORT_B141_PBYTE_Msk                              (0x01UL << GPIO_PORT_B141_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B142  -----------------------------------------
#define GPIO_PORT_B142_PBYTE_Pos                              0
#define GPIO_PORT_B142_PBYTE_Msk                              (0x01UL << GPIO_PORT_B142_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B143  -----------------------------------------
#define GPIO_PORT_B143_PBYTE_Pos                              0
#define GPIO_PORT_B143_PBYTE_Msk                              (0x01UL << GPIO_PORT_B143_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B144  -----------------------------------------
#define GPIO_PORT_B144_PBYTE_Pos                              0
#define GPIO_PORT_B144_PBYTE_Msk                              (0x01UL << GPIO_PORT_B144_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B145  -----------------------------------------
#define GPIO_PORT_B145_PBYTE_Pos                              0
#define GPIO_PORT_B145_PBYTE_Msk                              (0x01UL << GPIO_PORT_B145_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B146  -----------------------------------------
#define GPIO_PORT_B146_PBYTE_Pos                              0
#define GPIO_PORT_B146_PBYTE_Msk                              (0x01UL << GPIO_PORT_B146_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B147  -----------------------------------------
#define GPIO_PORT_B147_PBYTE_Pos                              0
#define GPIO_PORT_B147_PBYTE_Msk                              (0x01UL << GPIO_PORT_B147_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B148  -----------------------------------------
#define GPIO_PORT_B148_PBYTE_Pos                              0
#define GPIO_PORT_B148_PBYTE_Msk                              (0x01UL << GPIO_PORT_B148_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B149  -----------------------------------------
#define GPIO_PORT_B149_PBYTE_Pos                              0
#define GPIO_PORT_B149_PBYTE_Msk                              (0x01UL << GPIO_PORT_B149_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B150  -----------------------------------------
#define GPIO_PORT_B150_PBYTE_Pos                              0
#define GPIO_PORT_B150_PBYTE_Msk                              (0x01UL << GPIO_PORT_B150_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B151  -----------------------------------------
#define GPIO_PORT_B151_PBYTE_Pos                              0
#define GPIO_PORT_B151_PBYTE_Msk                              (0x01UL << GPIO_PORT_B151_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B152  -----------------------------------------
#define GPIO_PORT_B152_PBYTE_Pos                              0
#define GPIO_PORT_B152_PBYTE_Msk                              (0x01UL << GPIO_PORT_B152_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B153  -----------------------------------------
#define GPIO_PORT_B153_PBYTE_Pos                              0
#define GPIO_PORT_B153_PBYTE_Msk                              (0x01UL << GPIO_PORT_B153_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B154  -----------------------------------------
#define GPIO_PORT_B154_PBYTE_Pos                              0
#define GPIO_PORT_B154_PBYTE_Msk                              (0x01UL << GPIO_PORT_B154_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B155  -----------------------------------------
#define GPIO_PORT_B155_PBYTE_Pos                              0
#define GPIO_PORT_B155_PBYTE_Msk                              (0x01UL << GPIO_PORT_B155_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B156  -----------------------------------------
#define GPIO_PORT_B156_PBYTE_Pos                              0
#define GPIO_PORT_B156_PBYTE_Msk                              (0x01UL << GPIO_PORT_B156_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B157  -----------------------------------------
#define GPIO_PORT_B157_PBYTE_Pos                              0
#define GPIO_PORT_B157_PBYTE_Msk                              (0x01UL << GPIO_PORT_B157_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B158  -----------------------------------------
#define GPIO_PORT_B158_PBYTE_Pos                              0
#define GPIO_PORT_B158_PBYTE_Msk                              (0x01UL << GPIO_PORT_B158_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B159  -----------------------------------------
#define GPIO_PORT_B159_PBYTE_Pos                              0
#define GPIO_PORT_B159_PBYTE_Msk                              (0x01UL << GPIO_PORT_B159_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B160  -----------------------------------------
#define GPIO_PORT_B160_PBYTE_Pos                              0
#define GPIO_PORT_B160_PBYTE_Msk                              (0x01UL << GPIO_PORT_B160_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B161  -----------------------------------------
#define GPIO_PORT_B161_PBYTE_Pos                              0
#define GPIO_PORT_B161_PBYTE_Msk                              (0x01UL << GPIO_PORT_B161_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B162  -----------------------------------------
#define GPIO_PORT_B162_PBYTE_Pos                              0
#define GPIO_PORT_B162_PBYTE_Msk                              (0x01UL << GPIO_PORT_B162_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B163  -----------------------------------------
#define GPIO_PORT_B163_PBYTE_Pos                              0
#define GPIO_PORT_B163_PBYTE_Msk                              (0x01UL << GPIO_PORT_B163_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B164  -----------------------------------------
#define GPIO_PORT_B164_PBYTE_Pos                              0
#define GPIO_PORT_B164_PBYTE_Msk                              (0x01UL << GPIO_PORT_B164_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B165  -----------------------------------------
#define GPIO_PORT_B165_PBYTE_Pos                              0
#define GPIO_PORT_B165_PBYTE_Msk                              (0x01UL << GPIO_PORT_B165_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B166  -----------------------------------------
#define GPIO_PORT_B166_PBYTE_Pos                              0
#define GPIO_PORT_B166_PBYTE_Msk                              (0x01UL << GPIO_PORT_B166_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B167  -----------------------------------------
#define GPIO_PORT_B167_PBYTE_Pos                              0
#define GPIO_PORT_B167_PBYTE_Msk                              (0x01UL << GPIO_PORT_B167_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B168  -----------------------------------------
#define GPIO_PORT_B168_PBYTE_Pos                              0
#define GPIO_PORT_B168_PBYTE_Msk                              (0x01UL << GPIO_PORT_B168_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B169  -----------------------------------------
#define GPIO_PORT_B169_PBYTE_Pos                              0
#define GPIO_PORT_B169_PBYTE_Msk                              (0x01UL << GPIO_PORT_B169_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B170  -----------------------------------------
#define GPIO_PORT_B170_PBYTE_Pos                              0
#define GPIO_PORT_B170_PBYTE_Msk                              (0x01UL << GPIO_PORT_B170_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B171  -----------------------------------------
#define GPIO_PORT_B171_PBYTE_Pos                              0
#define GPIO_PORT_B171_PBYTE_Msk                              (0x01UL << GPIO_PORT_B171_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B172  -----------------------------------------
#define GPIO_PORT_B172_PBYTE_Pos                              0
#define GPIO_PORT_B172_PBYTE_Msk                              (0x01UL << GPIO_PORT_B172_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B173  -----------------------------------------
#define GPIO_PORT_B173_PBYTE_Pos                              0
#define GPIO_PORT_B173_PBYTE_Msk                              (0x01UL << GPIO_PORT_B173_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B174  -----------------------------------------
#define GPIO_PORT_B174_PBYTE_Pos                              0
#define GPIO_PORT_B174_PBYTE_Msk                              (0x01UL << GPIO_PORT_B174_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B175  -----------------------------------------
#define GPIO_PORT_B175_PBYTE_Pos                              0
#define GPIO_PORT_B175_PBYTE_Msk                              (0x01UL << GPIO_PORT_B175_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B176  -----------------------------------------
#define GPIO_PORT_B176_PBYTE_Pos                              0
#define GPIO_PORT_B176_PBYTE_Msk                              (0x01UL << GPIO_PORT_B176_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B177  -----------------------------------------
#define GPIO_PORT_B177_PBYTE_Pos                              0
#define GPIO_PORT_B177_PBYTE_Msk                              (0x01UL << GPIO_PORT_B177_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B178  -----------------------------------------
#define GPIO_PORT_B178_PBYTE_Pos                              0
#define GPIO_PORT_B178_PBYTE_Msk                              (0x01UL << GPIO_PORT_B178_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B179  -----------------------------------------
#define GPIO_PORT_B179_PBYTE_Pos                              0
#define GPIO_PORT_B179_PBYTE_Msk                              (0x01UL << GPIO_PORT_B179_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B180  -----------------------------------------
#define GPIO_PORT_B180_PBYTE_Pos                              0
#define GPIO_PORT_B180_PBYTE_Msk                              (0x01UL << GPIO_PORT_B180_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B181  -----------------------------------------
#define GPIO_PORT_B181_PBYTE_Pos                              0
#define GPIO_PORT_B181_PBYTE_Msk                              (0x01UL << GPIO_PORT_B181_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B182  -----------------------------------------
#define GPIO_PORT_B182_PBYTE_Pos                              0
#define GPIO_PORT_B182_PBYTE_Msk                              (0x01UL << GPIO_PORT_B182_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B183  -----------------------------------------
#define GPIO_PORT_B183_PBYTE_Pos                              0
#define GPIO_PORT_B183_PBYTE_Msk                              (0x01UL << GPIO_PORT_B183_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B184  -----------------------------------------
#define GPIO_PORT_B184_PBYTE_Pos                              0
#define GPIO_PORT_B184_PBYTE_Msk                              (0x01UL << GPIO_PORT_B184_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B185  -----------------------------------------
#define GPIO_PORT_B185_PBYTE_Pos                              0
#define GPIO_PORT_B185_PBYTE_Msk                              (0x01UL << GPIO_PORT_B185_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B186  -----------------------------------------
#define GPIO_PORT_B186_PBYTE_Pos                              0
#define GPIO_PORT_B186_PBYTE_Msk                              (0x01UL << GPIO_PORT_B186_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B187  -----------------------------------------
#define GPIO_PORT_B187_PBYTE_Pos                              0
#define GPIO_PORT_B187_PBYTE_Msk                              (0x01UL << GPIO_PORT_B187_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B188  -----------------------------------------
#define GPIO_PORT_B188_PBYTE_Pos                              0
#define GPIO_PORT_B188_PBYTE_Msk                              (0x01UL << GPIO_PORT_B188_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B189  -----------------------------------------
#define GPIO_PORT_B189_PBYTE_Pos                              0
#define GPIO_PORT_B189_PBYTE_Msk                              (0x01UL << GPIO_PORT_B189_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B190  -----------------------------------------
#define GPIO_PORT_B190_PBYTE_Pos                              0
#define GPIO_PORT_B190_PBYTE_Msk                              (0x01UL << GPIO_PORT_B190_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B191  -----------------------------------------
#define GPIO_PORT_B191_PBYTE_Pos                              0
#define GPIO_PORT_B191_PBYTE_Msk                              (0x01UL << GPIO_PORT_B191_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B192  -----------------------------------------
#define GPIO_PORT_B192_PBYTE_Pos                              0
#define GPIO_PORT_B192_PBYTE_Msk                              (0x01UL << GPIO_PORT_B192_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B193  -----------------------------------------
#define GPIO_PORT_B193_PBYTE_Pos                              0
#define GPIO_PORT_B193_PBYTE_Msk                              (0x01UL << GPIO_PORT_B193_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B194  -----------------------------------------
#define GPIO_PORT_B194_PBYTE_Pos                              0
#define GPIO_PORT_B194_PBYTE_Msk                              (0x01UL << GPIO_PORT_B194_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B195  -----------------------------------------
#define GPIO_PORT_B195_PBYTE_Pos                              0
#define GPIO_PORT_B195_PBYTE_Msk                              (0x01UL << GPIO_PORT_B195_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B196  -----------------------------------------
#define GPIO_PORT_B196_PBYTE_Pos                              0
#define GPIO_PORT_B196_PBYTE_Msk                              (0x01UL << GPIO_PORT_B196_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B197  -----------------------------------------
#define GPIO_PORT_B197_PBYTE_Pos                              0
#define GPIO_PORT_B197_PBYTE_Msk                              (0x01UL << GPIO_PORT_B197_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B198  -----------------------------------------
#define GPIO_PORT_B198_PBYTE_Pos                              0
#define GPIO_PORT_B198_PBYTE_Msk                              (0x01UL << GPIO_PORT_B198_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B199  -----------------------------------------
#define GPIO_PORT_B199_PBYTE_Pos                              0
#define GPIO_PORT_B199_PBYTE_Msk                              (0x01UL << GPIO_PORT_B199_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B200  -----------------------------------------
#define GPIO_PORT_B200_PBYTE_Pos                              0
#define GPIO_PORT_B200_PBYTE_Msk                              (0x01UL << GPIO_PORT_B200_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B201  -----------------------------------------
#define GPIO_PORT_B201_PBYTE_Pos                              0
#define GPIO_PORT_B201_PBYTE_Msk                              (0x01UL << GPIO_PORT_B201_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B202  -----------------------------------------
#define GPIO_PORT_B202_PBYTE_Pos                              0
#define GPIO_PORT_B202_PBYTE_Msk                              (0x01UL << GPIO_PORT_B202_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B203  -----------------------------------------
#define GPIO_PORT_B203_PBYTE_Pos                              0
#define GPIO_PORT_B203_PBYTE_Msk                              (0x01UL << GPIO_PORT_B203_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B204  -----------------------------------------
#define GPIO_PORT_B204_PBYTE_Pos                              0
#define GPIO_PORT_B204_PBYTE_Msk                              (0x01UL << GPIO_PORT_B204_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B205  -----------------------------------------
#define GPIO_PORT_B205_PBYTE_Pos                              0
#define GPIO_PORT_B205_PBYTE_Msk                              (0x01UL << GPIO_PORT_B205_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B206  -----------------------------------------
#define GPIO_PORT_B206_PBYTE_Pos                              0
#define GPIO_PORT_B206_PBYTE_Msk                              (0x01UL << GPIO_PORT_B206_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B207  -----------------------------------------
#define GPIO_PORT_B207_PBYTE_Pos                              0
#define GPIO_PORT_B207_PBYTE_Msk                              (0x01UL << GPIO_PORT_B207_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B208  -----------------------------------------
#define GPIO_PORT_B208_PBYTE_Pos                              0
#define GPIO_PORT_B208_PBYTE_Msk                              (0x01UL << GPIO_PORT_B208_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B209  -----------------------------------------
#define GPIO_PORT_B209_PBYTE_Pos                              0
#define GPIO_PORT_B209_PBYTE_Msk                              (0x01UL << GPIO_PORT_B209_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B210  -----------------------------------------
#define GPIO_PORT_B210_PBYTE_Pos                              0
#define GPIO_PORT_B210_PBYTE_Msk                              (0x01UL << GPIO_PORT_B210_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B211  -----------------------------------------
#define GPIO_PORT_B211_PBYTE_Pos                              0
#define GPIO_PORT_B211_PBYTE_Msk                              (0x01UL << GPIO_PORT_B211_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B212  -----------------------------------------
#define GPIO_PORT_B212_PBYTE_Pos                              0
#define GPIO_PORT_B212_PBYTE_Msk                              (0x01UL << GPIO_PORT_B212_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B213  -----------------------------------------
#define GPIO_PORT_B213_PBYTE_Pos                              0
#define GPIO_PORT_B213_PBYTE_Msk                              (0x01UL << GPIO_PORT_B213_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B214  -----------------------------------------
#define GPIO_PORT_B214_PBYTE_Pos                              0
#define GPIO_PORT_B214_PBYTE_Msk                              (0x01UL << GPIO_PORT_B214_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B215  -----------------------------------------
#define GPIO_PORT_B215_PBYTE_Pos                              0
#define GPIO_PORT_B215_PBYTE_Msk                              (0x01UL << GPIO_PORT_B215_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B216  -----------------------------------------
#define GPIO_PORT_B216_PBYTE_Pos                              0
#define GPIO_PORT_B216_PBYTE_Msk                              (0x01UL << GPIO_PORT_B216_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B217  -----------------------------------------
#define GPIO_PORT_B217_PBYTE_Pos                              0
#define GPIO_PORT_B217_PBYTE_Msk                              (0x01UL << GPIO_PORT_B217_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B218  -----------------------------------------
#define GPIO_PORT_B218_PBYTE_Pos                              0
#define GPIO_PORT_B218_PBYTE_Msk                              (0x01UL << GPIO_PORT_B218_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B219  -----------------------------------------
#define GPIO_PORT_B219_PBYTE_Pos                              0
#define GPIO_PORT_B219_PBYTE_Msk                              (0x01UL << GPIO_PORT_B219_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B220  -----------------------------------------
#define GPIO_PORT_B220_PBYTE_Pos                              0
#define GPIO_PORT_B220_PBYTE_Msk                              (0x01UL << GPIO_PORT_B220_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B221  -----------------------------------------
#define GPIO_PORT_B221_PBYTE_Pos                              0
#define GPIO_PORT_B221_PBYTE_Msk                              (0x01UL << GPIO_PORT_B221_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B222  -----------------------------------------
#define GPIO_PORT_B222_PBYTE_Pos                              0
#define GPIO_PORT_B222_PBYTE_Msk                              (0x01UL << GPIO_PORT_B222_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B223  -----------------------------------------
#define GPIO_PORT_B223_PBYTE_Pos                              0
#define GPIO_PORT_B223_PBYTE_Msk                              (0x01UL << GPIO_PORT_B223_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B224  -----------------------------------------
#define GPIO_PORT_B224_PBYTE_Pos                              0
#define GPIO_PORT_B224_PBYTE_Msk                              (0x01UL << GPIO_PORT_B224_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B225  -----------------------------------------
#define GPIO_PORT_B225_PBYTE_Pos                              0
#define GPIO_PORT_B225_PBYTE_Msk                              (0x01UL << GPIO_PORT_B225_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B226  -----------------------------------------
#define GPIO_PORT_B226_PBYTE_Pos                              0
#define GPIO_PORT_B226_PBYTE_Msk                              (0x01UL << GPIO_PORT_B226_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B227  -----------------------------------------
#define GPIO_PORT_B227_PBYTE_Pos                              0
#define GPIO_PORT_B227_PBYTE_Msk                              (0x01UL << GPIO_PORT_B227_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B228  -----------------------------------------
#define GPIO_PORT_B228_PBYTE_Pos                              0
#define GPIO_PORT_B228_PBYTE_Msk                              (0x01UL << GPIO_PORT_B228_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B229  -----------------------------------------
#define GPIO_PORT_B229_PBYTE_Pos                              0
#define GPIO_PORT_B229_PBYTE_Msk                              (0x01UL << GPIO_PORT_B229_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B230  -----------------------------------------
#define GPIO_PORT_B230_PBYTE_Pos                              0
#define GPIO_PORT_B230_PBYTE_Msk                              (0x01UL << GPIO_PORT_B230_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B231  -----------------------------------------
#define GPIO_PORT_B231_PBYTE_Pos                              0
#define GPIO_PORT_B231_PBYTE_Msk                              (0x01UL << GPIO_PORT_B231_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B232  -----------------------------------------
#define GPIO_PORT_B232_PBYTE_Pos                              0
#define GPIO_PORT_B232_PBYTE_Msk                              (0x01UL << GPIO_PORT_B232_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B233  -----------------------------------------
#define GPIO_PORT_B233_PBYTE_Pos                              0
#define GPIO_PORT_B233_PBYTE_Msk                              (0x01UL << GPIO_PORT_B233_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B234  -----------------------------------------
#define GPIO_PORT_B234_PBYTE_Pos                              0
#define GPIO_PORT_B234_PBYTE_Msk                              (0x01UL << GPIO_PORT_B234_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B235  -----------------------------------------
#define GPIO_PORT_B235_PBYTE_Pos                              0
#define GPIO_PORT_B235_PBYTE_Msk                              (0x01UL << GPIO_PORT_B235_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B236  -----------------------------------------
#define GPIO_PORT_B236_PBYTE_Pos                              0
#define GPIO_PORT_B236_PBYTE_Msk                              (0x01UL << GPIO_PORT_B236_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B237  -----------------------------------------
#define GPIO_PORT_B237_PBYTE_Pos                              0
#define GPIO_PORT_B237_PBYTE_Msk                              (0x01UL << GPIO_PORT_B237_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B238  -----------------------------------------
#define GPIO_PORT_B238_PBYTE_Pos                              0
#define GPIO_PORT_B238_PBYTE_Msk                              (0x01UL << GPIO_PORT_B238_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B239  -----------------------------------------
#define GPIO_PORT_B239_PBYTE_Pos                              0
#define GPIO_PORT_B239_PBYTE_Msk                              (0x01UL << GPIO_PORT_B239_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B240  -----------------------------------------
#define GPIO_PORT_B240_PBYTE_Pos                              0
#define GPIO_PORT_B240_PBYTE_Msk                              (0x01UL << GPIO_PORT_B240_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B241  -----------------------------------------
#define GPIO_PORT_B241_PBYTE_Pos                              0
#define GPIO_PORT_B241_PBYTE_Msk                              (0x01UL << GPIO_PORT_B241_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B242  -----------------------------------------
#define GPIO_PORT_B242_PBYTE_Pos                              0
#define GPIO_PORT_B242_PBYTE_Msk                              (0x01UL << GPIO_PORT_B242_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B243  -----------------------------------------
#define GPIO_PORT_B243_PBYTE_Pos                              0
#define GPIO_PORT_B243_PBYTE_Msk                              (0x01UL << GPIO_PORT_B243_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B244  -----------------------------------------
#define GPIO_PORT_B244_PBYTE_Pos                              0
#define GPIO_PORT_B244_PBYTE_Msk                              (0x01UL << GPIO_PORT_B244_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B245  -----------------------------------------
#define GPIO_PORT_B245_PBYTE_Pos                              0
#define GPIO_PORT_B245_PBYTE_Msk                              (0x01UL << GPIO_PORT_B245_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B246  -----------------------------------------
#define GPIO_PORT_B246_PBYTE_Pos                              0
#define GPIO_PORT_B246_PBYTE_Msk                              (0x01UL << GPIO_PORT_B246_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B247  -----------------------------------------
#define GPIO_PORT_B247_PBYTE_Pos                              0
#define GPIO_PORT_B247_PBYTE_Msk                              (0x01UL << GPIO_PORT_B247_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B248  -----------------------------------------
#define GPIO_PORT_B248_PBYTE_Pos                              0
#define GPIO_PORT_B248_PBYTE_Msk                              (0x01UL << GPIO_PORT_B248_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B249  -----------------------------------------
#define GPIO_PORT_B249_PBYTE_Pos                              0
#define GPIO_PORT_B249_PBYTE_Msk                              (0x01UL << GPIO_PORT_B249_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B250  -----------------------------------------
#define GPIO_PORT_B250_PBYTE_Pos                              0
#define GPIO_PORT_B250_PBYTE_Msk                              (0x01UL << GPIO_PORT_B250_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B251  -----------------------------------------
#define GPIO_PORT_B251_PBYTE_Pos                              0
#define GPIO_PORT_B251_PBYTE_Msk                              (0x01UL << GPIO_PORT_B251_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B252  -----------------------------------------
#define GPIO_PORT_B252_PBYTE_Pos                              0
#define GPIO_PORT_B252_PBYTE_Msk                              (0x01UL << GPIO_PORT_B252_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B253  -----------------------------------------
#define GPIO_PORT_B253_PBYTE_Pos                              0
#define GPIO_PORT_B253_PBYTE_Msk                              (0x01UL << GPIO_PORT_B253_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B254  -----------------------------------------
#define GPIO_PORT_B254_PBYTE_Pos                              0
#define GPIO_PORT_B254_PBYTE_Msk                              (0x01UL << GPIO_PORT_B254_PBYTE_Pos)

// -------------------------------------  GPIO_PORT_B255  -----------------------------------------
#define GPIO_PORT_B255_PBYTE_Pos                              0
#define GPIO_PORT_B255_PBYTE_Msk                              (0x01UL << GPIO_PORT_B255_PBYTE_Pos)

// --------------------------------------  GPIO_PORT_W0  ------------------------------------------
#define GPIO_PORT_W0_PWORD_Pos                                0
#define GPIO_PORT_W0_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W1  ------------------------------------------
#define GPIO_PORT_W1_PWORD_Pos                                0
#define GPIO_PORT_W1_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W2  ------------------------------------------
#define GPIO_PORT_W2_PWORD_Pos                                0
#define GPIO_PORT_W2_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W3  ------------------------------------------
#define GPIO_PORT_W3_PWORD_Pos                                0
#define GPIO_PORT_W3_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W4  ------------------------------------------
#define GPIO_PORT_W4_PWORD_Pos                                0
#define GPIO_PORT_W4_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W5  ------------------------------------------
#define GPIO_PORT_W5_PWORD_Pos                                0
#define GPIO_PORT_W5_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W6  ------------------------------------------
#define GPIO_PORT_W6_PWORD_Pos                                0
#define GPIO_PORT_W6_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W7  ------------------------------------------
#define GPIO_PORT_W7_PWORD_Pos                                0
#define GPIO_PORT_W7_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W8  ------------------------------------------
#define GPIO_PORT_W8_PWORD_Pos                                0
#define GPIO_PORT_W8_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W9  ------------------------------------------
#define GPIO_PORT_W9_PWORD_Pos                                0
#define GPIO_PORT_W9_PWORD_Msk                                (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W10  -----------------------------------------
#define GPIO_PORT_W10_PWORD_Pos                               0
#define GPIO_PORT_W10_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W11  -----------------------------------------
#define GPIO_PORT_W11_PWORD_Pos                               0
#define GPIO_PORT_W11_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W12  -----------------------------------------
#define GPIO_PORT_W12_PWORD_Pos                               0
#define GPIO_PORT_W12_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W13  -----------------------------------------
#define GPIO_PORT_W13_PWORD_Pos                               0
#define GPIO_PORT_W13_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W14  -----------------------------------------
#define GPIO_PORT_W14_PWORD_Pos                               0
#define GPIO_PORT_W14_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W15  -----------------------------------------
#define GPIO_PORT_W15_PWORD_Pos                               0
#define GPIO_PORT_W15_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W16  -----------------------------------------
#define GPIO_PORT_W16_PWORD_Pos                               0
#define GPIO_PORT_W16_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W17  -----------------------------------------
#define GPIO_PORT_W17_PWORD_Pos                               0
#define GPIO_PORT_W17_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W18  -----------------------------------------
#define GPIO_PORT_W18_PWORD_Pos                               0
#define GPIO_PORT_W18_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W19  -----------------------------------------
#define GPIO_PORT_W19_PWORD_Pos                               0
#define GPIO_PORT_W19_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W20  -----------------------------------------
#define GPIO_PORT_W20_PWORD_Pos                               0
#define GPIO_PORT_W20_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W21  -----------------------------------------
#define GPIO_PORT_W21_PWORD_Pos                               0
#define GPIO_PORT_W21_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W22  -----------------------------------------
#define GPIO_PORT_W22_PWORD_Pos                               0
#define GPIO_PORT_W22_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W23  -----------------------------------------
#define GPIO_PORT_W23_PWORD_Pos                               0
#define GPIO_PORT_W23_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W24  -----------------------------------------
#define GPIO_PORT_W24_PWORD_Pos                               0
#define GPIO_PORT_W24_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W25  -----------------------------------------
#define GPIO_PORT_W25_PWORD_Pos                               0
#define GPIO_PORT_W25_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W26  -----------------------------------------
#define GPIO_PORT_W26_PWORD_Pos                               0
#define GPIO_PORT_W26_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W27  -----------------------------------------
#define GPIO_PORT_W27_PWORD_Pos                               0
#define GPIO_PORT_W27_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W28  -----------------------------------------
#define GPIO_PORT_W28_PWORD_Pos                               0
#define GPIO_PORT_W28_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W29  -----------------------------------------
#define GPIO_PORT_W29_PWORD_Pos                               0
#define GPIO_PORT_W29_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W30  -----------------------------------------
#define GPIO_PORT_W30_PWORD_Pos                               0
#define GPIO_PORT_W30_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W31  -----------------------------------------
#define GPIO_PORT_W31_PWORD_Pos                               0
#define GPIO_PORT_W31_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W32  -----------------------------------------
#define GPIO_PORT_W32_PWORD_Pos                               0
#define GPIO_PORT_W32_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W33  -----------------------------------------
#define GPIO_PORT_W33_PWORD_Pos                               0
#define GPIO_PORT_W33_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W34  -----------------------------------------
#define GPIO_PORT_W34_PWORD_Pos                               0
#define GPIO_PORT_W34_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W35  -----------------------------------------
#define GPIO_PORT_W35_PWORD_Pos                               0
#define GPIO_PORT_W35_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W36  -----------------------------------------
#define GPIO_PORT_W36_PWORD_Pos                               0
#define GPIO_PORT_W36_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W37  -----------------------------------------
#define GPIO_PORT_W37_PWORD_Pos                               0
#define GPIO_PORT_W37_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W38  -----------------------------------------
#define GPIO_PORT_W38_PWORD_Pos                               0
#define GPIO_PORT_W38_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W39  -----------------------------------------
#define GPIO_PORT_W39_PWORD_Pos                               0
#define GPIO_PORT_W39_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W40  -----------------------------------------
#define GPIO_PORT_W40_PWORD_Pos                               0
#define GPIO_PORT_W40_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W41  -----------------------------------------
#define GPIO_PORT_W41_PWORD_Pos                               0
#define GPIO_PORT_W41_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W42  -----------------------------------------
#define GPIO_PORT_W42_PWORD_Pos                               0
#define GPIO_PORT_W42_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W43  -----------------------------------------
#define GPIO_PORT_W43_PWORD_Pos                               0
#define GPIO_PORT_W43_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W44  -----------------------------------------
#define GPIO_PORT_W44_PWORD_Pos                               0
#define GPIO_PORT_W44_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W45  -----------------------------------------
#define GPIO_PORT_W45_PWORD_Pos                               0
#define GPIO_PORT_W45_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W46  -----------------------------------------
#define GPIO_PORT_W46_PWORD_Pos                               0
#define GPIO_PORT_W46_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W47  -----------------------------------------
#define GPIO_PORT_W47_PWORD_Pos                               0
#define GPIO_PORT_W47_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W48  -----------------------------------------
#define GPIO_PORT_W48_PWORD_Pos                               0
#define GPIO_PORT_W48_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W49  -----------------------------------------
#define GPIO_PORT_W49_PWORD_Pos                               0
#define GPIO_PORT_W49_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W50  -----------------------------------------
#define GPIO_PORT_W50_PWORD_Pos                               0
#define GPIO_PORT_W50_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W51  -----------------------------------------
#define GPIO_PORT_W51_PWORD_Pos                               0
#define GPIO_PORT_W51_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W52  -----------------------------------------
#define GPIO_PORT_W52_PWORD_Pos                               0
#define GPIO_PORT_W52_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W53  -----------------------------------------
#define GPIO_PORT_W53_PWORD_Pos                               0
#define GPIO_PORT_W53_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W54  -----------------------------------------
#define GPIO_PORT_W54_PWORD_Pos                               0
#define GPIO_PORT_W54_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W55  -----------------------------------------
#define GPIO_PORT_W55_PWORD_Pos                               0
#define GPIO_PORT_W55_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W56  -----------------------------------------
#define GPIO_PORT_W56_PWORD_Pos                               0
#define GPIO_PORT_W56_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W57  -----------------------------------------
#define GPIO_PORT_W57_PWORD_Pos                               0
#define GPIO_PORT_W57_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W58  -----------------------------------------
#define GPIO_PORT_W58_PWORD_Pos                               0
#define GPIO_PORT_W58_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W59  -----------------------------------------
#define GPIO_PORT_W59_PWORD_Pos                               0
#define GPIO_PORT_W59_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W60  -----------------------------------------
#define GPIO_PORT_W60_PWORD_Pos                               0
#define GPIO_PORT_W60_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W61  -----------------------------------------
#define GPIO_PORT_W61_PWORD_Pos                               0
#define GPIO_PORT_W61_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W62  -----------------------------------------
#define GPIO_PORT_W62_PWORD_Pos                               0
#define GPIO_PORT_W62_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W63  -----------------------------------------
#define GPIO_PORT_W63_PWORD_Pos                               0
#define GPIO_PORT_W63_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W64  -----------------------------------------
#define GPIO_PORT_W64_PWORD_Pos                               0
#define GPIO_PORT_W64_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W65  -----------------------------------------
#define GPIO_PORT_W65_PWORD_Pos                               0
#define GPIO_PORT_W65_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W66  -----------------------------------------
#define GPIO_PORT_W66_PWORD_Pos                               0
#define GPIO_PORT_W66_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W67  -----------------------------------------
#define GPIO_PORT_W67_PWORD_Pos                               0
#define GPIO_PORT_W67_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W68  -----------------------------------------
#define GPIO_PORT_W68_PWORD_Pos                               0
#define GPIO_PORT_W68_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W69  -----------------------------------------
#define GPIO_PORT_W69_PWORD_Pos                               0
#define GPIO_PORT_W69_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W70  -----------------------------------------
#define GPIO_PORT_W70_PWORD_Pos                               0
#define GPIO_PORT_W70_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W71  -----------------------------------------
#define GPIO_PORT_W71_PWORD_Pos                               0
#define GPIO_PORT_W71_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W72  -----------------------------------------
#define GPIO_PORT_W72_PWORD_Pos                               0
#define GPIO_PORT_W72_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W73  -----------------------------------------
#define GPIO_PORT_W73_PWORD_Pos                               0
#define GPIO_PORT_W73_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W74  -----------------------------------------
#define GPIO_PORT_W74_PWORD_Pos                               0
#define GPIO_PORT_W74_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W75  -----------------------------------------
#define GPIO_PORT_W75_PWORD_Pos                               0
#define GPIO_PORT_W75_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W76  -----------------------------------------
#define GPIO_PORT_W76_PWORD_Pos                               0
#define GPIO_PORT_W76_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W77  -----------------------------------------
#define GPIO_PORT_W77_PWORD_Pos                               0
#define GPIO_PORT_W77_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W78  -----------------------------------------
#define GPIO_PORT_W78_PWORD_Pos                               0
#define GPIO_PORT_W78_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W79  -----------------------------------------
#define GPIO_PORT_W79_PWORD_Pos                               0
#define GPIO_PORT_W79_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W80  -----------------------------------------
#define GPIO_PORT_W80_PWORD_Pos                               0
#define GPIO_PORT_W80_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W81  -----------------------------------------
#define GPIO_PORT_W81_PWORD_Pos                               0
#define GPIO_PORT_W81_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W82  -----------------------------------------
#define GPIO_PORT_W82_PWORD_Pos                               0
#define GPIO_PORT_W82_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W83  -----------------------------------------
#define GPIO_PORT_W83_PWORD_Pos                               0
#define GPIO_PORT_W83_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W84  -----------------------------------------
#define GPIO_PORT_W84_PWORD_Pos                               0
#define GPIO_PORT_W84_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W85  -----------------------------------------
#define GPIO_PORT_W85_PWORD_Pos                               0
#define GPIO_PORT_W85_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W86  -----------------------------------------
#define GPIO_PORT_W86_PWORD_Pos                               0
#define GPIO_PORT_W86_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W87  -----------------------------------------
#define GPIO_PORT_W87_PWORD_Pos                               0
#define GPIO_PORT_W87_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W88  -----------------------------------------
#define GPIO_PORT_W88_PWORD_Pos                               0
#define GPIO_PORT_W88_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W89  -----------------------------------------
#define GPIO_PORT_W89_PWORD_Pos                               0
#define GPIO_PORT_W89_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W90  -----------------------------------------
#define GPIO_PORT_W90_PWORD_Pos                               0
#define GPIO_PORT_W90_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W91  -----------------------------------------
#define GPIO_PORT_W91_PWORD_Pos                               0
#define GPIO_PORT_W91_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W92  -----------------------------------------
#define GPIO_PORT_W92_PWORD_Pos                               0
#define GPIO_PORT_W92_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W93  -----------------------------------------
#define GPIO_PORT_W93_PWORD_Pos                               0
#define GPIO_PORT_W93_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W94  -----------------------------------------
#define GPIO_PORT_W94_PWORD_Pos                               0
#define GPIO_PORT_W94_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W95  -----------------------------------------
#define GPIO_PORT_W95_PWORD_Pos                               0
#define GPIO_PORT_W95_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W96  -----------------------------------------
#define GPIO_PORT_W96_PWORD_Pos                               0
#define GPIO_PORT_W96_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W97  -----------------------------------------
#define GPIO_PORT_W97_PWORD_Pos                               0
#define GPIO_PORT_W97_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W98  -----------------------------------------
#define GPIO_PORT_W98_PWORD_Pos                               0
#define GPIO_PORT_W98_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos)

// --------------------------------------  GPIO_PORT_W99  -----------------------------------------
#define GPIO_PORT_W99_PWORD_Pos                               0
#define GPIO_PORT_W99_PWORD_Msk                               (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W100  -----------------------------------------
#define GPIO_PORT_W100_PWORD_Pos                              0
#define GPIO_PORT_W100_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W101  -----------------------------------------
#define GPIO_PORT_W101_PWORD_Pos                              0
#define GPIO_PORT_W101_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W102  -----------------------------------------
#define GPIO_PORT_W102_PWORD_Pos                              0
#define GPIO_PORT_W102_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W103  -----------------------------------------
#define GPIO_PORT_W103_PWORD_Pos                              0
#define GPIO_PORT_W103_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W104  -----------------------------------------
#define GPIO_PORT_W104_PWORD_Pos                              0
#define GPIO_PORT_W104_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W105  -----------------------------------------
#define GPIO_PORT_W105_PWORD_Pos                              0
#define GPIO_PORT_W105_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W106  -----------------------------------------
#define GPIO_PORT_W106_PWORD_Pos                              0
#define GPIO_PORT_W106_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W107  -----------------------------------------
#define GPIO_PORT_W107_PWORD_Pos                              0
#define GPIO_PORT_W107_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W108  -----------------------------------------
#define GPIO_PORT_W108_PWORD_Pos                              0
#define GPIO_PORT_W108_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W109  -----------------------------------------
#define GPIO_PORT_W109_PWORD_Pos                              0
#define GPIO_PORT_W109_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W110  -----------------------------------------
#define GPIO_PORT_W110_PWORD_Pos                              0
#define GPIO_PORT_W110_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W111  -----------------------------------------
#define GPIO_PORT_W111_PWORD_Pos                              0
#define GPIO_PORT_W111_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W112  -----------------------------------------
#define GPIO_PORT_W112_PWORD_Pos                              0
#define GPIO_PORT_W112_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W113  -----------------------------------------
#define GPIO_PORT_W113_PWORD_Pos                              0
#define GPIO_PORT_W113_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W114  -----------------------------------------
#define GPIO_PORT_W114_PWORD_Pos                              0
#define GPIO_PORT_W114_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W115  -----------------------------------------
#define GPIO_PORT_W115_PWORD_Pos                              0
#define GPIO_PORT_W115_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W116  -----------------------------------------
#define GPIO_PORT_W116_PWORD_Pos                              0
#define GPIO_PORT_W116_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W117  -----------------------------------------
#define GPIO_PORT_W117_PWORD_Pos                              0
#define GPIO_PORT_W117_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W118  -----------------------------------------
#define GPIO_PORT_W118_PWORD_Pos                              0
#define GPIO_PORT_W118_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W119  -----------------------------------------
#define GPIO_PORT_W119_PWORD_Pos                              0
#define GPIO_PORT_W119_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W120  -----------------------------------------
#define GPIO_PORT_W120_PWORD_Pos                              0
#define GPIO_PORT_W120_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W121  -----------------------------------------
#define GPIO_PORT_W121_PWORD_Pos                              0
#define GPIO_PORT_W121_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W122  -----------------------------------------
#define GPIO_PORT_W122_PWORD_Pos                              0
#define GPIO_PORT_W122_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W123  -----------------------------------------
#define GPIO_PORT_W123_PWORD_Pos                              0
#define GPIO_PORT_W123_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W124  -----------------------------------------
#define GPIO_PORT_W124_PWORD_Pos                              0
#define GPIO_PORT_W124_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W125  -----------------------------------------
#define GPIO_PORT_W125_PWORD_Pos                              0
#define GPIO_PORT_W125_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W126  -----------------------------------------
#define GPIO_PORT_W126_PWORD_Pos                              0
#define GPIO_PORT_W126_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W127  -----------------------------------------
#define GPIO_PORT_W127_PWORD_Pos                              0
#define GPIO_PORT_W127_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W128  -----------------------------------------
#define GPIO_PORT_W128_PWORD_Pos                              0
#define GPIO_PORT_W128_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W129  -----------------------------------------
#define GPIO_PORT_W129_PWORD_Pos                              0
#define GPIO_PORT_W129_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W130  -----------------------------------------
#define GPIO_PORT_W130_PWORD_Pos                              0
#define GPIO_PORT_W130_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W131  -----------------------------------------
#define GPIO_PORT_W131_PWORD_Pos                              0
#define GPIO_PORT_W131_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W132  -----------------------------------------
#define GPIO_PORT_W132_PWORD_Pos                              0
#define GPIO_PORT_W132_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W133  -----------------------------------------
#define GPIO_PORT_W133_PWORD_Pos                              0
#define GPIO_PORT_W133_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W134  -----------------------------------------
#define GPIO_PORT_W134_PWORD_Pos                              0
#define GPIO_PORT_W134_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W135  -----------------------------------------
#define GPIO_PORT_W135_PWORD_Pos                              0
#define GPIO_PORT_W135_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W136  -----------------------------------------
#define GPIO_PORT_W136_PWORD_Pos                              0
#define GPIO_PORT_W136_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W137  -----------------------------------------
#define GPIO_PORT_W137_PWORD_Pos                              0
#define GPIO_PORT_W137_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W138  -----------------------------------------
#define GPIO_PORT_W138_PWORD_Pos                              0
#define GPIO_PORT_W138_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W139  -----------------------------------------
#define GPIO_PORT_W139_PWORD_Pos                              0
#define GPIO_PORT_W139_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W140  -----------------------------------------
#define GPIO_PORT_W140_PWORD_Pos                              0
#define GPIO_PORT_W140_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W141  -----------------------------------------
#define GPIO_PORT_W141_PWORD_Pos                              0
#define GPIO_PORT_W141_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W142  -----------------------------------------
#define GPIO_PORT_W142_PWORD_Pos                              0
#define GPIO_PORT_W142_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W143  -----------------------------------------
#define GPIO_PORT_W143_PWORD_Pos                              0
#define GPIO_PORT_W143_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W144  -----------------------------------------
#define GPIO_PORT_W144_PWORD_Pos                              0
#define GPIO_PORT_W144_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W145  -----------------------------------------
#define GPIO_PORT_W145_PWORD_Pos                              0
#define GPIO_PORT_W145_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W146  -----------------------------------------
#define GPIO_PORT_W146_PWORD_Pos                              0
#define GPIO_PORT_W146_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W147  -----------------------------------------
#define GPIO_PORT_W147_PWORD_Pos                              0
#define GPIO_PORT_W147_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W148  -----------------------------------------
#define GPIO_PORT_W148_PWORD_Pos                              0
#define GPIO_PORT_W148_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W149  -----------------------------------------
#define GPIO_PORT_W149_PWORD_Pos                              0
#define GPIO_PORT_W149_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W150  -----------------------------------------
#define GPIO_PORT_W150_PWORD_Pos                              0
#define GPIO_PORT_W150_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W151  -----------------------------------------
#define GPIO_PORT_W151_PWORD_Pos                              0
#define GPIO_PORT_W151_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W152  -----------------------------------------
#define GPIO_PORT_W152_PWORD_Pos                              0
#define GPIO_PORT_W152_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W153  -----------------------------------------
#define GPIO_PORT_W153_PWORD_Pos                              0
#define GPIO_PORT_W153_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W154  -----------------------------------------
#define GPIO_PORT_W154_PWORD_Pos                              0
#define GPIO_PORT_W154_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W155  -----------------------------------------
#define GPIO_PORT_W155_PWORD_Pos                              0
#define GPIO_PORT_W155_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W156  -----------------------------------------
#define GPIO_PORT_W156_PWORD_Pos                              0
#define GPIO_PORT_W156_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W157  -----------------------------------------
#define GPIO_PORT_W157_PWORD_Pos                              0
#define GPIO_PORT_W157_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W158  -----------------------------------------
#define GPIO_PORT_W158_PWORD_Pos                              0
#define GPIO_PORT_W158_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W159  -----------------------------------------
#define GPIO_PORT_W159_PWORD_Pos                              0
#define GPIO_PORT_W159_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W160  -----------------------------------------
#define GPIO_PORT_W160_PWORD_Pos                              0
#define GPIO_PORT_W160_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W161  -----------------------------------------
#define GPIO_PORT_W161_PWORD_Pos                              0
#define GPIO_PORT_W161_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W162  -----------------------------------------
#define GPIO_PORT_W162_PWORD_Pos                              0
#define GPIO_PORT_W162_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W163  -----------------------------------------
#define GPIO_PORT_W163_PWORD_Pos                              0
#define GPIO_PORT_W163_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W164  -----------------------------------------
#define GPIO_PORT_W164_PWORD_Pos                              0
#define GPIO_PORT_W164_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W165  -----------------------------------------
#define GPIO_PORT_W165_PWORD_Pos                              0
#define GPIO_PORT_W165_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W166  -----------------------------------------
#define GPIO_PORT_W166_PWORD_Pos                              0
#define GPIO_PORT_W166_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W167  -----------------------------------------
#define GPIO_PORT_W167_PWORD_Pos                              0
#define GPIO_PORT_W167_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W168  -----------------------------------------
#define GPIO_PORT_W168_PWORD_Pos                              0
#define GPIO_PORT_W168_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W169  -----------------------------------------
#define GPIO_PORT_W169_PWORD_Pos                              0
#define GPIO_PORT_W169_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W170  -----------------------------------------
#define GPIO_PORT_W170_PWORD_Pos                              0
#define GPIO_PORT_W170_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W171  -----------------------------------------
#define GPIO_PORT_W171_PWORD_Pos                              0
#define GPIO_PORT_W171_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W172  -----------------------------------------
#define GPIO_PORT_W172_PWORD_Pos                              0
#define GPIO_PORT_W172_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W173  -----------------------------------------
#define GPIO_PORT_W173_PWORD_Pos                              0
#define GPIO_PORT_W173_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W174  -----------------------------------------
#define GPIO_PORT_W174_PWORD_Pos                              0
#define GPIO_PORT_W174_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W175  -----------------------------------------
#define GPIO_PORT_W175_PWORD_Pos                              0
#define GPIO_PORT_W175_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W176  -----------------------------------------
#define GPIO_PORT_W176_PWORD_Pos                              0
#define GPIO_PORT_W176_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W177  -----------------------------------------
#define GPIO_PORT_W177_PWORD_Pos                              0
#define GPIO_PORT_W177_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W178  -----------------------------------------
#define GPIO_PORT_W178_PWORD_Pos                              0
#define GPIO_PORT_W178_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W179  -----------------------------------------
#define GPIO_PORT_W179_PWORD_Pos                              0
#define GPIO_PORT_W179_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W180  -----------------------------------------
#define GPIO_PORT_W180_PWORD_Pos                              0
#define GPIO_PORT_W180_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W181  -----------------------------------------
#define GPIO_PORT_W181_PWORD_Pos                              0
#define GPIO_PORT_W181_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W182  -----------------------------------------
#define GPIO_PORT_W182_PWORD_Pos                              0
#define GPIO_PORT_W182_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W183  -----------------------------------------
#define GPIO_PORT_W183_PWORD_Pos                              0
#define GPIO_PORT_W183_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W184  -----------------------------------------
#define GPIO_PORT_W184_PWORD_Pos                              0
#define GPIO_PORT_W184_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W185  -----------------------------------------
#define GPIO_PORT_W185_PWORD_Pos                              0
#define GPIO_PORT_W185_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W186  -----------------------------------------
#define GPIO_PORT_W186_PWORD_Pos                              0
#define GPIO_PORT_W186_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W187  -----------------------------------------
#define GPIO_PORT_W187_PWORD_Pos                              0
#define GPIO_PORT_W187_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W188  -----------------------------------------
#define GPIO_PORT_W188_PWORD_Pos                              0
#define GPIO_PORT_W188_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W189  -----------------------------------------
#define GPIO_PORT_W189_PWORD_Pos                              0
#define GPIO_PORT_W189_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W190  -----------------------------------------
#define GPIO_PORT_W190_PWORD_Pos                              0
#define GPIO_PORT_W190_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W191  -----------------------------------------
#define GPIO_PORT_W191_PWORD_Pos                              0
#define GPIO_PORT_W191_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W192  -----------------------------------------
#define GPIO_PORT_W192_PWORD_Pos                              0
#define GPIO_PORT_W192_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W193  -----------------------------------------
#define GPIO_PORT_W193_PWORD_Pos                              0
#define GPIO_PORT_W193_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W194  -----------------------------------------
#define GPIO_PORT_W194_PWORD_Pos                              0
#define GPIO_PORT_W194_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W195  -----------------------------------------
#define GPIO_PORT_W195_PWORD_Pos                              0
#define GPIO_PORT_W195_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W196  -----------------------------------------
#define GPIO_PORT_W196_PWORD_Pos                              0
#define GPIO_PORT_W196_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W197  -----------------------------------------
#define GPIO_PORT_W197_PWORD_Pos                              0
#define GPIO_PORT_W197_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W198  -----------------------------------------
#define GPIO_PORT_W198_PWORD_Pos                              0
#define GPIO_PORT_W198_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W199  -----------------------------------------
#define GPIO_PORT_W199_PWORD_Pos                              0
#define GPIO_PORT_W199_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W200  -----------------------------------------
#define GPIO_PORT_W200_PWORD_Pos                              0
#define GPIO_PORT_W200_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W201  -----------------------------------------
#define GPIO_PORT_W201_PWORD_Pos                              0
#define GPIO_PORT_W201_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W202  -----------------------------------------
#define GPIO_PORT_W202_PWORD_Pos                              0
#define GPIO_PORT_W202_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W203  -----------------------------------------
#define GPIO_PORT_W203_PWORD_Pos                              0
#define GPIO_PORT_W203_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W204  -----------------------------------------
#define GPIO_PORT_W204_PWORD_Pos                              0
#define GPIO_PORT_W204_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W205  -----------------------------------------
#define GPIO_PORT_W205_PWORD_Pos                              0
#define GPIO_PORT_W205_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W206  -----------------------------------------
#define GPIO_PORT_W206_PWORD_Pos                              0
#define GPIO_PORT_W206_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W207  -----------------------------------------
#define GPIO_PORT_W207_PWORD_Pos                              0
#define GPIO_PORT_W207_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W208  -----------------------------------------
#define GPIO_PORT_W208_PWORD_Pos                              0
#define GPIO_PORT_W208_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W209  -----------------------------------------
#define GPIO_PORT_W209_PWORD_Pos                              0
#define GPIO_PORT_W209_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W210  -----------------------------------------
#define GPIO_PORT_W210_PWORD_Pos                              0
#define GPIO_PORT_W210_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W211  -----------------------------------------
#define GPIO_PORT_W211_PWORD_Pos                              0
#define GPIO_PORT_W211_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W212  -----------------------------------------
#define GPIO_PORT_W212_PWORD_Pos                              0
#define GPIO_PORT_W212_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W213  -----------------------------------------
#define GPIO_PORT_W213_PWORD_Pos                              0
#define GPIO_PORT_W213_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W214  -----------------------------------------
#define GPIO_PORT_W214_PWORD_Pos                              0
#define GPIO_PORT_W214_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W215  -----------------------------------------
#define GPIO_PORT_W215_PWORD_Pos                              0
#define GPIO_PORT_W215_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W216  -----------------------------------------
#define GPIO_PORT_W216_PWORD_Pos                              0
#define GPIO_PORT_W216_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W217  -----------------------------------------
#define GPIO_PORT_W217_PWORD_Pos                              0
#define GPIO_PORT_W217_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W218  -----------------------------------------
#define GPIO_PORT_W218_PWORD_Pos                              0
#define GPIO_PORT_W218_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W219  -----------------------------------------
#define GPIO_PORT_W219_PWORD_Pos                              0
#define GPIO_PORT_W219_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W220  -----------------------------------------
#define GPIO_PORT_W220_PWORD_Pos                              0
#define GPIO_PORT_W220_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W221  -----------------------------------------
#define GPIO_PORT_W221_PWORD_Pos                              0
#define GPIO_PORT_W221_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W222  -----------------------------------------
#define GPIO_PORT_W222_PWORD_Pos                              0
#define GPIO_PORT_W222_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W223  -----------------------------------------
#define GPIO_PORT_W223_PWORD_Pos                              0
#define GPIO_PORT_W223_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W224  -----------------------------------------
#define GPIO_PORT_W224_PWORD_Pos                              0
#define GPIO_PORT_W224_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W225  -----------------------------------------
#define GPIO_PORT_W225_PWORD_Pos                              0
#define GPIO_PORT_W225_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W226  -----------------------------------------
#define GPIO_PORT_W226_PWORD_Pos                              0
#define GPIO_PORT_W226_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W227  -----------------------------------------
#define GPIO_PORT_W227_PWORD_Pos                              0
#define GPIO_PORT_W227_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W228  -----------------------------------------
#define GPIO_PORT_W228_PWORD_Pos                              0
#define GPIO_PORT_W228_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W229  -----------------------------------------
#define GPIO_PORT_W229_PWORD_Pos                              0
#define GPIO_PORT_W229_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W230  -----------------------------------------
#define GPIO_PORT_W230_PWORD_Pos                              0
#define GPIO_PORT_W230_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W231  -----------------------------------------
#define GPIO_PORT_W231_PWORD_Pos                              0
#define GPIO_PORT_W231_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W232  -----------------------------------------
#define GPIO_PORT_W232_PWORD_Pos                              0
#define GPIO_PORT_W232_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W233  -----------------------------------------
#define GPIO_PORT_W233_PWORD_Pos                              0
#define GPIO_PORT_W233_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W234  -----------------------------------------
#define GPIO_PORT_W234_PWORD_Pos                              0
#define GPIO_PORT_W234_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W235  -----------------------------------------
#define GPIO_PORT_W235_PWORD_Pos                              0
#define GPIO_PORT_W235_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W236  -----------------------------------------
#define GPIO_PORT_W236_PWORD_Pos                              0
#define GPIO_PORT_W236_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W237  -----------------------------------------
#define GPIO_PORT_W237_PWORD_Pos                              0
#define GPIO_PORT_W237_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W238  -----------------------------------------
#define GPIO_PORT_W238_PWORD_Pos                              0
#define GPIO_PORT_W238_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W239  -----------------------------------------
#define GPIO_PORT_W239_PWORD_Pos                              0
#define GPIO_PORT_W239_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W240  -----------------------------------------
#define GPIO_PORT_W240_PWORD_Pos                              0
#define GPIO_PORT_W240_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W241  -----------------------------------------
#define GPIO_PORT_W241_PWORD_Pos                              0
#define GPIO_PORT_W241_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W242  -----------------------------------------
#define GPIO_PORT_W242_PWORD_Pos                              0
#define GPIO_PORT_W242_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W243  -----------------------------------------
#define GPIO_PORT_W243_PWORD_Pos                              0
#define GPIO_PORT_W243_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W244  -----------------------------------------
#define GPIO_PORT_W244_PWORD_Pos                              0
#define GPIO_PORT_W244_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W245  -----------------------------------------
#define GPIO_PORT_W245_PWORD_Pos                              0
#define GPIO_PORT_W245_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W246  -----------------------------------------
#define GPIO_PORT_W246_PWORD_Pos                              0
#define GPIO_PORT_W246_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W247  -----------------------------------------
#define GPIO_PORT_W247_PWORD_Pos                              0
#define GPIO_PORT_W247_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W248  -----------------------------------------
#define GPIO_PORT_W248_PWORD_Pos                              0
#define GPIO_PORT_W248_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W249  -----------------------------------------
#define GPIO_PORT_W249_PWORD_Pos                              0
#define GPIO_PORT_W249_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W250  -----------------------------------------
#define GPIO_PORT_W250_PWORD_Pos                              0
#define GPIO_PORT_W250_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W251  -----------------------------------------
#define GPIO_PORT_W251_PWORD_Pos                              0
#define GPIO_PORT_W251_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W252  -----------------------------------------
#define GPIO_PORT_W252_PWORD_Pos                              0
#define GPIO_PORT_W252_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W253  -----------------------------------------
#define GPIO_PORT_W253_PWORD_Pos                              0
#define GPIO_PORT_W253_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W254  -----------------------------------------
#define GPIO_PORT_W254_PWORD_Pos                              0
#define GPIO_PORT_W254_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos)

// -------------------------------------  GPIO_PORT_W255  -----------------------------------------
#define GPIO_PORT_W255_PWORD_Pos                              0
#define GPIO_PORT_W255_PWORD_Msk                              (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos)

// -------------------------------------  GPIO_PORT_DIR0  -----------------------------------------
#define GPIO_PORT_DIR0_DIRP0_Pos                              0
#define GPIO_PORT_DIR0_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos)
#define GPIO_PORT_DIR0_DIRP1_Pos                              1
#define GPIO_PORT_DIR0_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos)
#define GPIO_PORT_DIR0_DIRP2_Pos                              2
#define GPIO_PORT_DIR0_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos)
#define GPIO_PORT_DIR0_DIRP3_Pos                              3
#define GPIO_PORT_DIR0_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos)
#define GPIO_PORT_DIR0_DIRP4_Pos                              4
#define GPIO_PORT_DIR0_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos)
#define GPIO_PORT_DIR0_DIRP5_Pos                              5
#define GPIO_PORT_DIR0_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos)
#define GPIO_PORT_DIR0_DIRP6_Pos                              6
#define GPIO_PORT_DIR0_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos)
#define GPIO_PORT_DIR0_DIRP7_Pos                              7
#define GPIO_PORT_DIR0_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos)
#define GPIO_PORT_DIR0_DIRP8_Pos                              8
#define GPIO_PORT_DIR0_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos)
#define GPIO_PORT_DIR0_DIRP9_Pos                              9
#define GPIO_PORT_DIR0_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos)
#define GPIO_PORT_DIR0_DIRP10_Pos                             10
#define GPIO_PORT_DIR0_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos)
#define GPIO_PORT_DIR0_DIRP11_Pos                             11
#define GPIO_PORT_DIR0_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos)
#define GPIO_PORT_DIR0_DIRP12_Pos                             12
#define GPIO_PORT_DIR0_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos)
#define GPIO_PORT_DIR0_DIRP13_Pos                             13
#define GPIO_PORT_DIR0_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos)
#define GPIO_PORT_DIR0_DIRP14_Pos                             14
#define GPIO_PORT_DIR0_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos)
#define GPIO_PORT_DIR0_DIRP15_Pos                             15
#define GPIO_PORT_DIR0_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos)
#define GPIO_PORT_DIR0_DIRP16_Pos                             16
#define GPIO_PORT_DIR0_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos)
#define GPIO_PORT_DIR0_DIRP17_Pos                             17
#define GPIO_PORT_DIR0_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos)
#define GPIO_PORT_DIR0_DIRP18_Pos                             18
#define GPIO_PORT_DIR0_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos)
#define GPIO_PORT_DIR0_DIRP19_Pos                             19
#define GPIO_PORT_DIR0_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos)
#define GPIO_PORT_DIR0_DIRP20_Pos                             20
#define GPIO_PORT_DIR0_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos)
#define GPIO_PORT_DIR0_DIRP21_Pos                             21
#define GPIO_PORT_DIR0_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos)
#define GPIO_PORT_DIR0_DIRP22_Pos                             22
#define GPIO_PORT_DIR0_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos)
#define GPIO_PORT_DIR0_DIRP23_Pos                             23
#define GPIO_PORT_DIR0_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos)
#define GPIO_PORT_DIR0_DIRP24_Pos                             24
#define GPIO_PORT_DIR0_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos)
#define GPIO_PORT_DIR0_DIRP25_Pos                             25
#define GPIO_PORT_DIR0_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos)
#define GPIO_PORT_DIR0_DIRP26_Pos                             26
#define GPIO_PORT_DIR0_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos)
#define GPIO_PORT_DIR0_DIRP27_Pos                             27
#define GPIO_PORT_DIR0_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos)
#define GPIO_PORT_DIR0_DIRP28_Pos                             28
#define GPIO_PORT_DIR0_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos)
#define GPIO_PORT_DIR0_DIRP29_Pos                             29
#define GPIO_PORT_DIR0_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos)
#define GPIO_PORT_DIR0_DIRP30_Pos                             30
#define GPIO_PORT_DIR0_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos)
#define GPIO_PORT_DIR0_DIRP31_Pos                             31
#define GPIO_PORT_DIR0_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR1  -----------------------------------------
#define GPIO_PORT_DIR1_DIRP0_Pos                              0
#define GPIO_PORT_DIR1_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos)
#define GPIO_PORT_DIR1_DIRP1_Pos                              1
#define GPIO_PORT_DIR1_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos)
#define GPIO_PORT_DIR1_DIRP2_Pos                              2
#define GPIO_PORT_DIR1_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos)
#define GPIO_PORT_DIR1_DIRP3_Pos                              3
#define GPIO_PORT_DIR1_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos)
#define GPIO_PORT_DIR1_DIRP4_Pos                              4
#define GPIO_PORT_DIR1_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos)
#define GPIO_PORT_DIR1_DIRP5_Pos                              5
#define GPIO_PORT_DIR1_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos)
#define GPIO_PORT_DIR1_DIRP6_Pos                              6
#define GPIO_PORT_DIR1_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos)
#define GPIO_PORT_DIR1_DIRP7_Pos                              7
#define GPIO_PORT_DIR1_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos)
#define GPIO_PORT_DIR1_DIRP8_Pos                              8
#define GPIO_PORT_DIR1_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos)
#define GPIO_PORT_DIR1_DIRP9_Pos                              9
#define GPIO_PORT_DIR1_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos)
#define GPIO_PORT_DIR1_DIRP10_Pos                             10
#define GPIO_PORT_DIR1_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos)
#define GPIO_PORT_DIR1_DIRP11_Pos                             11
#define GPIO_PORT_DIR1_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos)
#define GPIO_PORT_DIR1_DIRP12_Pos                             12
#define GPIO_PORT_DIR1_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos)
#define GPIO_PORT_DIR1_DIRP13_Pos                             13
#define GPIO_PORT_DIR1_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos)
#define GPIO_PORT_DIR1_DIRP14_Pos                             14
#define GPIO_PORT_DIR1_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos)
#define GPIO_PORT_DIR1_DIRP15_Pos                             15
#define GPIO_PORT_DIR1_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos)
#define GPIO_PORT_DIR1_DIRP16_Pos                             16
#define GPIO_PORT_DIR1_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos)
#define GPIO_PORT_DIR1_DIRP17_Pos                             17
#define GPIO_PORT_DIR1_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos)
#define GPIO_PORT_DIR1_DIRP18_Pos                             18
#define GPIO_PORT_DIR1_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos)
#define GPIO_PORT_DIR1_DIRP19_Pos                             19
#define GPIO_PORT_DIR1_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos)
#define GPIO_PORT_DIR1_DIRP20_Pos                             20
#define GPIO_PORT_DIR1_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos)
#define GPIO_PORT_DIR1_DIRP21_Pos                             21
#define GPIO_PORT_DIR1_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos)
#define GPIO_PORT_DIR1_DIRP22_Pos                             22
#define GPIO_PORT_DIR1_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos)
#define GPIO_PORT_DIR1_DIRP23_Pos                             23
#define GPIO_PORT_DIR1_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos)
#define GPIO_PORT_DIR1_DIRP24_Pos                             24
#define GPIO_PORT_DIR1_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos)
#define GPIO_PORT_DIR1_DIRP25_Pos                             25
#define GPIO_PORT_DIR1_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos)
#define GPIO_PORT_DIR1_DIRP26_Pos                             26
#define GPIO_PORT_DIR1_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos)
#define GPIO_PORT_DIR1_DIRP27_Pos                             27
#define GPIO_PORT_DIR1_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos)
#define GPIO_PORT_DIR1_DIRP28_Pos                             28
#define GPIO_PORT_DIR1_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos)
#define GPIO_PORT_DIR1_DIRP29_Pos                             29
#define GPIO_PORT_DIR1_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos)
#define GPIO_PORT_DIR1_DIRP30_Pos                             30
#define GPIO_PORT_DIR1_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos)
#define GPIO_PORT_DIR1_DIRP31_Pos                             31
#define GPIO_PORT_DIR1_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR2  -----------------------------------------
#define GPIO_PORT_DIR2_DIRP0_Pos                              0
#define GPIO_PORT_DIR2_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos)
#define GPIO_PORT_DIR2_DIRP1_Pos                              1
#define GPIO_PORT_DIR2_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos)
#define GPIO_PORT_DIR2_DIRP2_Pos                              2
#define GPIO_PORT_DIR2_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos)
#define GPIO_PORT_DIR2_DIRP3_Pos                              3
#define GPIO_PORT_DIR2_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos)
#define GPIO_PORT_DIR2_DIRP4_Pos                              4
#define GPIO_PORT_DIR2_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos)
#define GPIO_PORT_DIR2_DIRP5_Pos                              5
#define GPIO_PORT_DIR2_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos)
#define GPIO_PORT_DIR2_DIRP6_Pos                              6
#define GPIO_PORT_DIR2_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos)
#define GPIO_PORT_DIR2_DIRP7_Pos                              7
#define GPIO_PORT_DIR2_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos)
#define GPIO_PORT_DIR2_DIRP8_Pos                              8
#define GPIO_PORT_DIR2_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos)
#define GPIO_PORT_DIR2_DIRP9_Pos                              9
#define GPIO_PORT_DIR2_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos)
#define GPIO_PORT_DIR2_DIRP10_Pos                             10
#define GPIO_PORT_DIR2_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos)
#define GPIO_PORT_DIR2_DIRP11_Pos                             11
#define GPIO_PORT_DIR2_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos)
#define GPIO_PORT_DIR2_DIRP12_Pos                             12
#define GPIO_PORT_DIR2_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos)
#define GPIO_PORT_DIR2_DIRP13_Pos                             13
#define GPIO_PORT_DIR2_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos)
#define GPIO_PORT_DIR2_DIRP14_Pos                             14
#define GPIO_PORT_DIR2_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos)
#define GPIO_PORT_DIR2_DIRP15_Pos                             15
#define GPIO_PORT_DIR2_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos)
#define GPIO_PORT_DIR2_DIRP16_Pos                             16
#define GPIO_PORT_DIR2_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos)
#define GPIO_PORT_DIR2_DIRP17_Pos                             17
#define GPIO_PORT_DIR2_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos)
#define GPIO_PORT_DIR2_DIRP18_Pos                             18
#define GPIO_PORT_DIR2_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos)
#define GPIO_PORT_DIR2_DIRP19_Pos                             19
#define GPIO_PORT_DIR2_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos)
#define GPIO_PORT_DIR2_DIRP20_Pos                             20
#define GPIO_PORT_DIR2_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos)
#define GPIO_PORT_DIR2_DIRP21_Pos                             21
#define GPIO_PORT_DIR2_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos)
#define GPIO_PORT_DIR2_DIRP22_Pos                             22
#define GPIO_PORT_DIR2_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos)
#define GPIO_PORT_DIR2_DIRP23_Pos                             23
#define GPIO_PORT_DIR2_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos)
#define GPIO_PORT_DIR2_DIRP24_Pos                             24
#define GPIO_PORT_DIR2_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos)
#define GPIO_PORT_DIR2_DIRP25_Pos                             25
#define GPIO_PORT_DIR2_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos)
#define GPIO_PORT_DIR2_DIRP26_Pos                             26
#define GPIO_PORT_DIR2_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos)
#define GPIO_PORT_DIR2_DIRP27_Pos                             27
#define GPIO_PORT_DIR2_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos)
#define GPIO_PORT_DIR2_DIRP28_Pos                             28
#define GPIO_PORT_DIR2_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos)
#define GPIO_PORT_DIR2_DIRP29_Pos                             29
#define GPIO_PORT_DIR2_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos)
#define GPIO_PORT_DIR2_DIRP30_Pos                             30
#define GPIO_PORT_DIR2_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos)
#define GPIO_PORT_DIR2_DIRP31_Pos                             31
#define GPIO_PORT_DIR2_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR3  -----------------------------------------
#define GPIO_PORT_DIR3_DIRP0_Pos                              0
#define GPIO_PORT_DIR3_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos)
#define GPIO_PORT_DIR3_DIRP1_Pos                              1
#define GPIO_PORT_DIR3_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos)
#define GPIO_PORT_DIR3_DIRP2_Pos                              2
#define GPIO_PORT_DIR3_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos)
#define GPIO_PORT_DIR3_DIRP3_Pos                              3
#define GPIO_PORT_DIR3_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos)
#define GPIO_PORT_DIR3_DIRP4_Pos                              4
#define GPIO_PORT_DIR3_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos)
#define GPIO_PORT_DIR3_DIRP5_Pos                              5
#define GPIO_PORT_DIR3_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos)
#define GPIO_PORT_DIR3_DIRP6_Pos                              6
#define GPIO_PORT_DIR3_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos)
#define GPIO_PORT_DIR3_DIRP7_Pos                              7
#define GPIO_PORT_DIR3_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos)
#define GPIO_PORT_DIR3_DIRP8_Pos                              8
#define GPIO_PORT_DIR3_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos)
#define GPIO_PORT_DIR3_DIRP9_Pos                              9
#define GPIO_PORT_DIR3_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos)
#define GPIO_PORT_DIR3_DIRP10_Pos                             10
#define GPIO_PORT_DIR3_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos)
#define GPIO_PORT_DIR3_DIRP11_Pos                             11
#define GPIO_PORT_DIR3_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos)
#define GPIO_PORT_DIR3_DIRP12_Pos                             12
#define GPIO_PORT_DIR3_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos)
#define GPIO_PORT_DIR3_DIRP13_Pos                             13
#define GPIO_PORT_DIR3_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos)
#define GPIO_PORT_DIR3_DIRP14_Pos                             14
#define GPIO_PORT_DIR3_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos)
#define GPIO_PORT_DIR3_DIRP15_Pos                             15
#define GPIO_PORT_DIR3_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos)
#define GPIO_PORT_DIR3_DIRP16_Pos                             16
#define GPIO_PORT_DIR3_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos)
#define GPIO_PORT_DIR3_DIRP17_Pos                             17
#define GPIO_PORT_DIR3_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos)
#define GPIO_PORT_DIR3_DIRP18_Pos                             18
#define GPIO_PORT_DIR3_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos)
#define GPIO_PORT_DIR3_DIRP19_Pos                             19
#define GPIO_PORT_DIR3_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos)
#define GPIO_PORT_DIR3_DIRP20_Pos                             20
#define GPIO_PORT_DIR3_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos)
#define GPIO_PORT_DIR3_DIRP21_Pos                             21
#define GPIO_PORT_DIR3_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos)
#define GPIO_PORT_DIR3_DIRP22_Pos                             22
#define GPIO_PORT_DIR3_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos)
#define GPIO_PORT_DIR3_DIRP23_Pos                             23
#define GPIO_PORT_DIR3_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos)
#define GPIO_PORT_DIR3_DIRP24_Pos                             24
#define GPIO_PORT_DIR3_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos)
#define GPIO_PORT_DIR3_DIRP25_Pos                             25
#define GPIO_PORT_DIR3_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos)
#define GPIO_PORT_DIR3_DIRP26_Pos                             26
#define GPIO_PORT_DIR3_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos)
#define GPIO_PORT_DIR3_DIRP27_Pos                             27
#define GPIO_PORT_DIR3_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos)
#define GPIO_PORT_DIR3_DIRP28_Pos                             28
#define GPIO_PORT_DIR3_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos)
#define GPIO_PORT_DIR3_DIRP29_Pos                             29
#define GPIO_PORT_DIR3_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos)
#define GPIO_PORT_DIR3_DIRP30_Pos                             30
#define GPIO_PORT_DIR3_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos)
#define GPIO_PORT_DIR3_DIRP31_Pos                             31
#define GPIO_PORT_DIR3_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR4  -----------------------------------------
#define GPIO_PORT_DIR4_DIRP0_Pos                              0
#define GPIO_PORT_DIR4_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos)
#define GPIO_PORT_DIR4_DIRP1_Pos                              1
#define GPIO_PORT_DIR4_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos)
#define GPIO_PORT_DIR4_DIRP2_Pos                              2
#define GPIO_PORT_DIR4_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos)
#define GPIO_PORT_DIR4_DIRP3_Pos                              3
#define GPIO_PORT_DIR4_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos)
#define GPIO_PORT_DIR4_DIRP4_Pos                              4
#define GPIO_PORT_DIR4_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos)
#define GPIO_PORT_DIR4_DIRP5_Pos                              5
#define GPIO_PORT_DIR4_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos)
#define GPIO_PORT_DIR4_DIRP6_Pos                              6
#define GPIO_PORT_DIR4_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos)
#define GPIO_PORT_DIR4_DIRP7_Pos                              7
#define GPIO_PORT_DIR4_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos)
#define GPIO_PORT_DIR4_DIRP8_Pos                              8
#define GPIO_PORT_DIR4_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos)
#define GPIO_PORT_DIR4_DIRP9_Pos                              9
#define GPIO_PORT_DIR4_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos)
#define GPIO_PORT_DIR4_DIRP10_Pos                             10
#define GPIO_PORT_DIR4_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos)
#define GPIO_PORT_DIR4_DIRP11_Pos                             11
#define GPIO_PORT_DIR4_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos)
#define GPIO_PORT_DIR4_DIRP12_Pos                             12
#define GPIO_PORT_DIR4_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos)
#define GPIO_PORT_DIR4_DIRP13_Pos                             13
#define GPIO_PORT_DIR4_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos)
#define GPIO_PORT_DIR4_DIRP14_Pos                             14
#define GPIO_PORT_DIR4_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos)
#define GPIO_PORT_DIR4_DIRP15_Pos                             15
#define GPIO_PORT_DIR4_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos)
#define GPIO_PORT_DIR4_DIRP16_Pos                             16
#define GPIO_PORT_DIR4_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos)
#define GPIO_PORT_DIR4_DIRP17_Pos                             17
#define GPIO_PORT_DIR4_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos)
#define GPIO_PORT_DIR4_DIRP18_Pos                             18
#define GPIO_PORT_DIR4_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos)
#define GPIO_PORT_DIR4_DIRP19_Pos                             19
#define GPIO_PORT_DIR4_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos)
#define GPIO_PORT_DIR4_DIRP20_Pos                             20
#define GPIO_PORT_DIR4_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos)
#define GPIO_PORT_DIR4_DIRP21_Pos                             21
#define GPIO_PORT_DIR4_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos)
#define GPIO_PORT_DIR4_DIRP22_Pos                             22
#define GPIO_PORT_DIR4_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos)
#define GPIO_PORT_DIR4_DIRP23_Pos                             23
#define GPIO_PORT_DIR4_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos)
#define GPIO_PORT_DIR4_DIRP24_Pos                             24
#define GPIO_PORT_DIR4_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos)
#define GPIO_PORT_DIR4_DIRP25_Pos                             25
#define GPIO_PORT_DIR4_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos)
#define GPIO_PORT_DIR4_DIRP26_Pos                             26
#define GPIO_PORT_DIR4_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos)
#define GPIO_PORT_DIR4_DIRP27_Pos                             27
#define GPIO_PORT_DIR4_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos)
#define GPIO_PORT_DIR4_DIRP28_Pos                             28
#define GPIO_PORT_DIR4_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos)
#define GPIO_PORT_DIR4_DIRP29_Pos                             29
#define GPIO_PORT_DIR4_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos)
#define GPIO_PORT_DIR4_DIRP30_Pos                             30
#define GPIO_PORT_DIR4_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos)
#define GPIO_PORT_DIR4_DIRP31_Pos                             31
#define GPIO_PORT_DIR4_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR5  -----------------------------------------
#define GPIO_PORT_DIR5_DIRP0_Pos                              0
#define GPIO_PORT_DIR5_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos)
#define GPIO_PORT_DIR5_DIRP1_Pos                              1
#define GPIO_PORT_DIR5_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos)
#define GPIO_PORT_DIR5_DIRP2_Pos                              2
#define GPIO_PORT_DIR5_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos)
#define GPIO_PORT_DIR5_DIRP3_Pos                              3
#define GPIO_PORT_DIR5_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos)
#define GPIO_PORT_DIR5_DIRP4_Pos                              4
#define GPIO_PORT_DIR5_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos)
#define GPIO_PORT_DIR5_DIRP5_Pos                              5
#define GPIO_PORT_DIR5_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos)
#define GPIO_PORT_DIR5_DIRP6_Pos                              6
#define GPIO_PORT_DIR5_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos)
#define GPIO_PORT_DIR5_DIRP7_Pos                              7
#define GPIO_PORT_DIR5_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos)
#define GPIO_PORT_DIR5_DIRP8_Pos                              8
#define GPIO_PORT_DIR5_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos)
#define GPIO_PORT_DIR5_DIRP9_Pos                              9
#define GPIO_PORT_DIR5_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos)
#define GPIO_PORT_DIR5_DIRP10_Pos                             10
#define GPIO_PORT_DIR5_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos)
#define GPIO_PORT_DIR5_DIRP11_Pos                             11
#define GPIO_PORT_DIR5_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos)
#define GPIO_PORT_DIR5_DIRP12_Pos                             12
#define GPIO_PORT_DIR5_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos)
#define GPIO_PORT_DIR5_DIRP13_Pos                             13
#define GPIO_PORT_DIR5_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos)
#define GPIO_PORT_DIR5_DIRP14_Pos                             14
#define GPIO_PORT_DIR5_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos)
#define GPIO_PORT_DIR5_DIRP15_Pos                             15
#define GPIO_PORT_DIR5_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos)
#define GPIO_PORT_DIR5_DIRP16_Pos                             16
#define GPIO_PORT_DIR5_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos)
#define GPIO_PORT_DIR5_DIRP17_Pos                             17
#define GPIO_PORT_DIR5_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos)
#define GPIO_PORT_DIR5_DIRP18_Pos                             18
#define GPIO_PORT_DIR5_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos)
#define GPIO_PORT_DIR5_DIRP19_Pos                             19
#define GPIO_PORT_DIR5_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos)
#define GPIO_PORT_DIR5_DIRP20_Pos                             20
#define GPIO_PORT_DIR5_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos)
#define GPIO_PORT_DIR5_DIRP21_Pos                             21
#define GPIO_PORT_DIR5_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos)
#define GPIO_PORT_DIR5_DIRP22_Pos                             22
#define GPIO_PORT_DIR5_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos)
#define GPIO_PORT_DIR5_DIRP23_Pos                             23
#define GPIO_PORT_DIR5_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos)
#define GPIO_PORT_DIR5_DIRP24_Pos                             24
#define GPIO_PORT_DIR5_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos)
#define GPIO_PORT_DIR5_DIRP25_Pos                             25
#define GPIO_PORT_DIR5_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos)
#define GPIO_PORT_DIR5_DIRP26_Pos                             26
#define GPIO_PORT_DIR5_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos)
#define GPIO_PORT_DIR5_DIRP27_Pos                             27
#define GPIO_PORT_DIR5_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos)
#define GPIO_PORT_DIR5_DIRP28_Pos                             28
#define GPIO_PORT_DIR5_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos)
#define GPIO_PORT_DIR5_DIRP29_Pos                             29
#define GPIO_PORT_DIR5_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos)
#define GPIO_PORT_DIR5_DIRP30_Pos                             30
#define GPIO_PORT_DIR5_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos)
#define GPIO_PORT_DIR5_DIRP31_Pos                             31
#define GPIO_PORT_DIR5_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR6  -----------------------------------------
#define GPIO_PORT_DIR6_DIRP0_Pos                              0
#define GPIO_PORT_DIR6_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos)
#define GPIO_PORT_DIR6_DIRP1_Pos                              1
#define GPIO_PORT_DIR6_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos)
#define GPIO_PORT_DIR6_DIRP2_Pos                              2
#define GPIO_PORT_DIR6_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos)
#define GPIO_PORT_DIR6_DIRP3_Pos                              3
#define GPIO_PORT_DIR6_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos)
#define GPIO_PORT_DIR6_DIRP4_Pos                              4
#define GPIO_PORT_DIR6_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos)
#define GPIO_PORT_DIR6_DIRP5_Pos                              5
#define GPIO_PORT_DIR6_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos)
#define GPIO_PORT_DIR6_DIRP6_Pos                              6
#define GPIO_PORT_DIR6_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos)
#define GPIO_PORT_DIR6_DIRP7_Pos                              7
#define GPIO_PORT_DIR6_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos)
#define GPIO_PORT_DIR6_DIRP8_Pos                              8
#define GPIO_PORT_DIR6_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos)
#define GPIO_PORT_DIR6_DIRP9_Pos                              9
#define GPIO_PORT_DIR6_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos)
#define GPIO_PORT_DIR6_DIRP10_Pos                             10
#define GPIO_PORT_DIR6_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos)
#define GPIO_PORT_DIR6_DIRP11_Pos                             11
#define GPIO_PORT_DIR6_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos)
#define GPIO_PORT_DIR6_DIRP12_Pos                             12
#define GPIO_PORT_DIR6_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos)
#define GPIO_PORT_DIR6_DIRP13_Pos                             13
#define GPIO_PORT_DIR6_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos)
#define GPIO_PORT_DIR6_DIRP14_Pos                             14
#define GPIO_PORT_DIR6_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos)
#define GPIO_PORT_DIR6_DIRP15_Pos                             15
#define GPIO_PORT_DIR6_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos)
#define GPIO_PORT_DIR6_DIRP16_Pos                             16
#define GPIO_PORT_DIR6_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos)
#define GPIO_PORT_DIR6_DIRP17_Pos                             17
#define GPIO_PORT_DIR6_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos)
#define GPIO_PORT_DIR6_DIRP18_Pos                             18
#define GPIO_PORT_DIR6_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos)
#define GPIO_PORT_DIR6_DIRP19_Pos                             19
#define GPIO_PORT_DIR6_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos)
#define GPIO_PORT_DIR6_DIRP20_Pos                             20
#define GPIO_PORT_DIR6_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos)
#define GPIO_PORT_DIR6_DIRP21_Pos                             21
#define GPIO_PORT_DIR6_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos)
#define GPIO_PORT_DIR6_DIRP22_Pos                             22
#define GPIO_PORT_DIR6_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos)
#define GPIO_PORT_DIR6_DIRP23_Pos                             23
#define GPIO_PORT_DIR6_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos)
#define GPIO_PORT_DIR6_DIRP24_Pos                             24
#define GPIO_PORT_DIR6_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos)
#define GPIO_PORT_DIR6_DIRP25_Pos                             25
#define GPIO_PORT_DIR6_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos)
#define GPIO_PORT_DIR6_DIRP26_Pos                             26
#define GPIO_PORT_DIR6_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos)
#define GPIO_PORT_DIR6_DIRP27_Pos                             27
#define GPIO_PORT_DIR6_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos)
#define GPIO_PORT_DIR6_DIRP28_Pos                             28
#define GPIO_PORT_DIR6_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos)
#define GPIO_PORT_DIR6_DIRP29_Pos                             29
#define GPIO_PORT_DIR6_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos)
#define GPIO_PORT_DIR6_DIRP30_Pos                             30
#define GPIO_PORT_DIR6_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos)
#define GPIO_PORT_DIR6_DIRP31_Pos                             31
#define GPIO_PORT_DIR6_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_DIR7  -----------------------------------------
#define GPIO_PORT_DIR7_DIRP0_Pos                              0
#define GPIO_PORT_DIR7_DIRP0_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos)
#define GPIO_PORT_DIR7_DIRP1_Pos                              1
#define GPIO_PORT_DIR7_DIRP1_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos)
#define GPIO_PORT_DIR7_DIRP2_Pos                              2
#define GPIO_PORT_DIR7_DIRP2_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos)
#define GPIO_PORT_DIR7_DIRP3_Pos                              3
#define GPIO_PORT_DIR7_DIRP3_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos)
#define GPIO_PORT_DIR7_DIRP4_Pos                              4
#define GPIO_PORT_DIR7_DIRP4_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos)
#define GPIO_PORT_DIR7_DIRP5_Pos                              5
#define GPIO_PORT_DIR7_DIRP5_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos)
#define GPIO_PORT_DIR7_DIRP6_Pos                              6
#define GPIO_PORT_DIR7_DIRP6_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos)
#define GPIO_PORT_DIR7_DIRP7_Pos                              7
#define GPIO_PORT_DIR7_DIRP7_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos)
#define GPIO_PORT_DIR7_DIRP8_Pos                              8
#define GPIO_PORT_DIR7_DIRP8_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos)
#define GPIO_PORT_DIR7_DIRP9_Pos                              9
#define GPIO_PORT_DIR7_DIRP9_Msk                              (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos)
#define GPIO_PORT_DIR7_DIRP10_Pos                             10
#define GPIO_PORT_DIR7_DIRP10_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos)
#define GPIO_PORT_DIR7_DIRP11_Pos                             11
#define GPIO_PORT_DIR7_DIRP11_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos)
#define GPIO_PORT_DIR7_DIRP12_Pos                             12
#define GPIO_PORT_DIR7_DIRP12_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos)
#define GPIO_PORT_DIR7_DIRP13_Pos                             13
#define GPIO_PORT_DIR7_DIRP13_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos)
#define GPIO_PORT_DIR7_DIRP14_Pos                             14
#define GPIO_PORT_DIR7_DIRP14_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos)
#define GPIO_PORT_DIR7_DIRP15_Pos                             15
#define GPIO_PORT_DIR7_DIRP15_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos)
#define GPIO_PORT_DIR7_DIRP16_Pos                             16
#define GPIO_PORT_DIR7_DIRP16_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos)
#define GPIO_PORT_DIR7_DIRP17_Pos                             17
#define GPIO_PORT_DIR7_DIRP17_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos)
#define GPIO_PORT_DIR7_DIRP18_Pos                             18
#define GPIO_PORT_DIR7_DIRP18_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos)
#define GPIO_PORT_DIR7_DIRP19_Pos                             19
#define GPIO_PORT_DIR7_DIRP19_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos)
#define GPIO_PORT_DIR7_DIRP20_Pos                             20
#define GPIO_PORT_DIR7_DIRP20_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos)
#define GPIO_PORT_DIR7_DIRP21_Pos                             21
#define GPIO_PORT_DIR7_DIRP21_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos)
#define GPIO_PORT_DIR7_DIRP22_Pos                             22
#define GPIO_PORT_DIR7_DIRP22_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos)
#define GPIO_PORT_DIR7_DIRP23_Pos                             23
#define GPIO_PORT_DIR7_DIRP23_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos)
#define GPIO_PORT_DIR7_DIRP24_Pos                             24
#define GPIO_PORT_DIR7_DIRP24_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos)
#define GPIO_PORT_DIR7_DIRP25_Pos                             25
#define GPIO_PORT_DIR7_DIRP25_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos)
#define GPIO_PORT_DIR7_DIRP26_Pos                             26
#define GPIO_PORT_DIR7_DIRP26_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos)
#define GPIO_PORT_DIR7_DIRP27_Pos                             27
#define GPIO_PORT_DIR7_DIRP27_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos)
#define GPIO_PORT_DIR7_DIRP28_Pos                             28
#define GPIO_PORT_DIR7_DIRP28_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos)
#define GPIO_PORT_DIR7_DIRP29_Pos                             29
#define GPIO_PORT_DIR7_DIRP29_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos)
#define GPIO_PORT_DIR7_DIRP30_Pos                             30
#define GPIO_PORT_DIR7_DIRP30_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos)
#define GPIO_PORT_DIR7_DIRP31_Pos                             31
#define GPIO_PORT_DIR7_DIRP31_Msk                             (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos)

// -------------------------------------  GPIO_PORT_MASK0  ----------------------------------------
#define GPIO_PORT_MASK0_MASKP0_Pos                            0
#define GPIO_PORT_MASK0_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos)
#define GPIO_PORT_MASK0_MASKP1_Pos                            1
#define GPIO_PORT_MASK0_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos)
#define GPIO_PORT_MASK0_MASKP2_Pos                            2
#define GPIO_PORT_MASK0_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos)
#define GPIO_PORT_MASK0_MASKP3_Pos                            3
#define GPIO_PORT_MASK0_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos)
#define GPIO_PORT_MASK0_MASKP4_Pos                            4
#define GPIO_PORT_MASK0_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos)
#define GPIO_PORT_MASK0_MASKP5_Pos                            5
#define GPIO_PORT_MASK0_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos)
#define GPIO_PORT_MASK0_MASKP6_Pos                            6
#define GPIO_PORT_MASK0_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos)
#define GPIO_PORT_MASK0_MASKP7_Pos                            7
#define GPIO_PORT_MASK0_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos)
#define GPIO_PORT_MASK0_MASKP8_Pos                            8
#define GPIO_PORT_MASK0_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos)
#define GPIO_PORT_MASK0_MASKP9_Pos                            9
#define GPIO_PORT_MASK0_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos)
#define GPIO_PORT_MASK0_MASKP10_Pos                           10
#define GPIO_PORT_MASK0_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos)
#define GPIO_PORT_MASK0_MASKP11_Pos                           11
#define GPIO_PORT_MASK0_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos)
#define GPIO_PORT_MASK0_MASKP12_Pos                           12
#define GPIO_PORT_MASK0_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos)
#define GPIO_PORT_MASK0_MASKP13_Pos                           13
#define GPIO_PORT_MASK0_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos)
#define GPIO_PORT_MASK0_MASKP14_Pos                           14
#define GPIO_PORT_MASK0_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos)
#define GPIO_PORT_MASK0_MASKP15_Pos                           15
#define GPIO_PORT_MASK0_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos)
#define GPIO_PORT_MASK0_MASKP16_Pos                           16
#define GPIO_PORT_MASK0_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos)
#define GPIO_PORT_MASK0_MASKP17_Pos                           17
#define GPIO_PORT_MASK0_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos)
#define GPIO_PORT_MASK0_MASKP18_Pos                           18
#define GPIO_PORT_MASK0_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos)
#define GPIO_PORT_MASK0_MASKP19_Pos                           19
#define GPIO_PORT_MASK0_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos)
#define GPIO_PORT_MASK0_MASKP20_Pos                           20
#define GPIO_PORT_MASK0_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos)
#define GPIO_PORT_MASK0_MASKP21_Pos                           21
#define GPIO_PORT_MASK0_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos)
#define GPIO_PORT_MASK0_MASKP22_Pos                           22
#define GPIO_PORT_MASK0_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos)
#define GPIO_PORT_MASK0_MASKP23_Pos                           23
#define GPIO_PORT_MASK0_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos)
#define GPIO_PORT_MASK0_MASKP24_Pos                           24
#define GPIO_PORT_MASK0_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos)
#define GPIO_PORT_MASK0_MASKP25_Pos                           25
#define GPIO_PORT_MASK0_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos)
#define GPIO_PORT_MASK0_MASKP26_Pos                           26
#define GPIO_PORT_MASK0_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos)
#define GPIO_PORT_MASK0_MASKP27_Pos                           27
#define GPIO_PORT_MASK0_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos)
#define GPIO_PORT_MASK0_MASKP28_Pos                           28
#define GPIO_PORT_MASK0_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos)
#define GPIO_PORT_MASK0_MASKP29_Pos                           29
#define GPIO_PORT_MASK0_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos)
#define GPIO_PORT_MASK0_MASKP30_Pos                           30
#define GPIO_PORT_MASK0_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos)
#define GPIO_PORT_MASK0_MASKP31_Pos                           31
#define GPIO_PORT_MASK0_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK1  ----------------------------------------
#define GPIO_PORT_MASK1_MASKP0_Pos                            0
#define GPIO_PORT_MASK1_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos)
#define GPIO_PORT_MASK1_MASKP1_Pos                            1
#define GPIO_PORT_MASK1_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos)
#define GPIO_PORT_MASK1_MASKP2_Pos                            2
#define GPIO_PORT_MASK1_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos)
#define GPIO_PORT_MASK1_MASKP3_Pos                            3
#define GPIO_PORT_MASK1_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos)
#define GPIO_PORT_MASK1_MASKP4_Pos                            4
#define GPIO_PORT_MASK1_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos)
#define GPIO_PORT_MASK1_MASKP5_Pos                            5
#define GPIO_PORT_MASK1_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos)
#define GPIO_PORT_MASK1_MASKP6_Pos                            6
#define GPIO_PORT_MASK1_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos)
#define GPIO_PORT_MASK1_MASKP7_Pos                            7
#define GPIO_PORT_MASK1_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos)
#define GPIO_PORT_MASK1_MASKP8_Pos                            8
#define GPIO_PORT_MASK1_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos)
#define GPIO_PORT_MASK1_MASKP9_Pos                            9
#define GPIO_PORT_MASK1_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos)
#define GPIO_PORT_MASK1_MASKP10_Pos                           10
#define GPIO_PORT_MASK1_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos)
#define GPIO_PORT_MASK1_MASKP11_Pos                           11
#define GPIO_PORT_MASK1_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos)
#define GPIO_PORT_MASK1_MASKP12_Pos                           12
#define GPIO_PORT_MASK1_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos)
#define GPIO_PORT_MASK1_MASKP13_Pos                           13
#define GPIO_PORT_MASK1_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos)
#define GPIO_PORT_MASK1_MASKP14_Pos                           14
#define GPIO_PORT_MASK1_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos)
#define GPIO_PORT_MASK1_MASKP15_Pos                           15
#define GPIO_PORT_MASK1_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos)
#define GPIO_PORT_MASK1_MASKP16_Pos                           16
#define GPIO_PORT_MASK1_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos)
#define GPIO_PORT_MASK1_MASKP17_Pos                           17
#define GPIO_PORT_MASK1_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos)
#define GPIO_PORT_MASK1_MASKP18_Pos                           18
#define GPIO_PORT_MASK1_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos)
#define GPIO_PORT_MASK1_MASKP19_Pos                           19
#define GPIO_PORT_MASK1_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos)
#define GPIO_PORT_MASK1_MASKP20_Pos                           20
#define GPIO_PORT_MASK1_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos)
#define GPIO_PORT_MASK1_MASKP21_Pos                           21
#define GPIO_PORT_MASK1_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos)
#define GPIO_PORT_MASK1_MASKP22_Pos                           22
#define GPIO_PORT_MASK1_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos)
#define GPIO_PORT_MASK1_MASKP23_Pos                           23
#define GPIO_PORT_MASK1_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos)
#define GPIO_PORT_MASK1_MASKP24_Pos                           24
#define GPIO_PORT_MASK1_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos)
#define GPIO_PORT_MASK1_MASKP25_Pos                           25
#define GPIO_PORT_MASK1_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos)
#define GPIO_PORT_MASK1_MASKP26_Pos                           26
#define GPIO_PORT_MASK1_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos)
#define GPIO_PORT_MASK1_MASKP27_Pos                           27
#define GPIO_PORT_MASK1_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos)
#define GPIO_PORT_MASK1_MASKP28_Pos                           28
#define GPIO_PORT_MASK1_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos)
#define GPIO_PORT_MASK1_MASKP29_Pos                           29
#define GPIO_PORT_MASK1_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos)
#define GPIO_PORT_MASK1_MASKP30_Pos                           30
#define GPIO_PORT_MASK1_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos)
#define GPIO_PORT_MASK1_MASKP31_Pos                           31
#define GPIO_PORT_MASK1_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK2  ----------------------------------------
#define GPIO_PORT_MASK2_MASKP0_Pos                            0
#define GPIO_PORT_MASK2_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos)
#define GPIO_PORT_MASK2_MASKP1_Pos                            1
#define GPIO_PORT_MASK2_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos)
#define GPIO_PORT_MASK2_MASKP2_Pos                            2
#define GPIO_PORT_MASK2_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos)
#define GPIO_PORT_MASK2_MASKP3_Pos                            3
#define GPIO_PORT_MASK2_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos)
#define GPIO_PORT_MASK2_MASKP4_Pos                            4
#define GPIO_PORT_MASK2_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos)
#define GPIO_PORT_MASK2_MASKP5_Pos                            5
#define GPIO_PORT_MASK2_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos)
#define GPIO_PORT_MASK2_MASKP6_Pos                            6
#define GPIO_PORT_MASK2_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos)
#define GPIO_PORT_MASK2_MASKP7_Pos                            7
#define GPIO_PORT_MASK2_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos)
#define GPIO_PORT_MASK2_MASKP8_Pos                            8
#define GPIO_PORT_MASK2_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos)
#define GPIO_PORT_MASK2_MASKP9_Pos                            9
#define GPIO_PORT_MASK2_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos)
#define GPIO_PORT_MASK2_MASKP10_Pos                           10
#define GPIO_PORT_MASK2_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos)
#define GPIO_PORT_MASK2_MASKP11_Pos                           11
#define GPIO_PORT_MASK2_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos)
#define GPIO_PORT_MASK2_MASKP12_Pos                           12
#define GPIO_PORT_MASK2_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos)
#define GPIO_PORT_MASK2_MASKP13_Pos                           13
#define GPIO_PORT_MASK2_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos)
#define GPIO_PORT_MASK2_MASKP14_Pos                           14
#define GPIO_PORT_MASK2_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos)
#define GPIO_PORT_MASK2_MASKP15_Pos                           15
#define GPIO_PORT_MASK2_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos)
#define GPIO_PORT_MASK2_MASKP16_Pos                           16
#define GPIO_PORT_MASK2_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos)
#define GPIO_PORT_MASK2_MASKP17_Pos                           17
#define GPIO_PORT_MASK2_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos)
#define GPIO_PORT_MASK2_MASKP18_Pos                           18
#define GPIO_PORT_MASK2_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos)
#define GPIO_PORT_MASK2_MASKP19_Pos                           19
#define GPIO_PORT_MASK2_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos)
#define GPIO_PORT_MASK2_MASKP20_Pos                           20
#define GPIO_PORT_MASK2_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos)
#define GPIO_PORT_MASK2_MASKP21_Pos                           21
#define GPIO_PORT_MASK2_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos)
#define GPIO_PORT_MASK2_MASKP22_Pos                           22
#define GPIO_PORT_MASK2_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos)
#define GPIO_PORT_MASK2_MASKP23_Pos                           23
#define GPIO_PORT_MASK2_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos)
#define GPIO_PORT_MASK2_MASKP24_Pos                           24
#define GPIO_PORT_MASK2_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos)
#define GPIO_PORT_MASK2_MASKP25_Pos                           25
#define GPIO_PORT_MASK2_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos)
#define GPIO_PORT_MASK2_MASKP26_Pos                           26
#define GPIO_PORT_MASK2_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos)
#define GPIO_PORT_MASK2_MASKP27_Pos                           27
#define GPIO_PORT_MASK2_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos)
#define GPIO_PORT_MASK2_MASKP28_Pos                           28
#define GPIO_PORT_MASK2_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos)
#define GPIO_PORT_MASK2_MASKP29_Pos                           29
#define GPIO_PORT_MASK2_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos)
#define GPIO_PORT_MASK2_MASKP30_Pos                           30
#define GPIO_PORT_MASK2_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos)
#define GPIO_PORT_MASK2_MASKP31_Pos                           31
#define GPIO_PORT_MASK2_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK3  ----------------------------------------
#define GPIO_PORT_MASK3_MASKP0_Pos                            0
#define GPIO_PORT_MASK3_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos)
#define GPIO_PORT_MASK3_MASKP1_Pos                            1
#define GPIO_PORT_MASK3_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos)
#define GPIO_PORT_MASK3_MASKP2_Pos                            2
#define GPIO_PORT_MASK3_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos)
#define GPIO_PORT_MASK3_MASKP3_Pos                            3
#define GPIO_PORT_MASK3_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos)
#define GPIO_PORT_MASK3_MASKP4_Pos                            4
#define GPIO_PORT_MASK3_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos)
#define GPIO_PORT_MASK3_MASKP5_Pos                            5
#define GPIO_PORT_MASK3_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos)
#define GPIO_PORT_MASK3_MASKP6_Pos                            6
#define GPIO_PORT_MASK3_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos)
#define GPIO_PORT_MASK3_MASKP7_Pos                            7
#define GPIO_PORT_MASK3_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos)
#define GPIO_PORT_MASK3_MASKP8_Pos                            8
#define GPIO_PORT_MASK3_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos)
#define GPIO_PORT_MASK3_MASKP9_Pos                            9
#define GPIO_PORT_MASK3_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos)
#define GPIO_PORT_MASK3_MASKP10_Pos                           10
#define GPIO_PORT_MASK3_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos)
#define GPIO_PORT_MASK3_MASKP11_Pos                           11
#define GPIO_PORT_MASK3_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos)
#define GPIO_PORT_MASK3_MASKP12_Pos                           12
#define GPIO_PORT_MASK3_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos)
#define GPIO_PORT_MASK3_MASKP13_Pos                           13
#define GPIO_PORT_MASK3_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos)
#define GPIO_PORT_MASK3_MASKP14_Pos                           14
#define GPIO_PORT_MASK3_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos)
#define GPIO_PORT_MASK3_MASKP15_Pos                           15
#define GPIO_PORT_MASK3_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos)
#define GPIO_PORT_MASK3_MASKP16_Pos                           16
#define GPIO_PORT_MASK3_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos)
#define GPIO_PORT_MASK3_MASKP17_Pos                           17
#define GPIO_PORT_MASK3_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos)
#define GPIO_PORT_MASK3_MASKP18_Pos                           18
#define GPIO_PORT_MASK3_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos)
#define GPIO_PORT_MASK3_MASKP19_Pos                           19
#define GPIO_PORT_MASK3_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos)
#define GPIO_PORT_MASK3_MASKP20_Pos                           20
#define GPIO_PORT_MASK3_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos)
#define GPIO_PORT_MASK3_MASKP21_Pos                           21
#define GPIO_PORT_MASK3_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos)
#define GPIO_PORT_MASK3_MASKP22_Pos                           22
#define GPIO_PORT_MASK3_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos)
#define GPIO_PORT_MASK3_MASKP23_Pos                           23
#define GPIO_PORT_MASK3_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos)
#define GPIO_PORT_MASK3_MASKP24_Pos                           24
#define GPIO_PORT_MASK3_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos)
#define GPIO_PORT_MASK3_MASKP25_Pos                           25
#define GPIO_PORT_MASK3_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos)
#define GPIO_PORT_MASK3_MASKP26_Pos                           26
#define GPIO_PORT_MASK3_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos)
#define GPIO_PORT_MASK3_MASKP27_Pos                           27
#define GPIO_PORT_MASK3_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos)
#define GPIO_PORT_MASK3_MASKP28_Pos                           28
#define GPIO_PORT_MASK3_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos)
#define GPIO_PORT_MASK3_MASKP29_Pos                           29
#define GPIO_PORT_MASK3_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos)
#define GPIO_PORT_MASK3_MASKP30_Pos                           30
#define GPIO_PORT_MASK3_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos)
#define GPIO_PORT_MASK3_MASKP31_Pos                           31
#define GPIO_PORT_MASK3_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK4  ----------------------------------------
#define GPIO_PORT_MASK4_MASKP0_Pos                            0
#define GPIO_PORT_MASK4_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos)
#define GPIO_PORT_MASK4_MASKP1_Pos                            1
#define GPIO_PORT_MASK4_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos)
#define GPIO_PORT_MASK4_MASKP2_Pos                            2
#define GPIO_PORT_MASK4_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos)
#define GPIO_PORT_MASK4_MASKP3_Pos                            3
#define GPIO_PORT_MASK4_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos)
#define GPIO_PORT_MASK4_MASKP4_Pos                            4
#define GPIO_PORT_MASK4_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos)
#define GPIO_PORT_MASK4_MASKP5_Pos                            5
#define GPIO_PORT_MASK4_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos)
#define GPIO_PORT_MASK4_MASKP6_Pos                            6
#define GPIO_PORT_MASK4_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos)
#define GPIO_PORT_MASK4_MASKP7_Pos                            7
#define GPIO_PORT_MASK4_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos)
#define GPIO_PORT_MASK4_MASKP8_Pos                            8
#define GPIO_PORT_MASK4_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos)
#define GPIO_PORT_MASK4_MASKP9_Pos                            9
#define GPIO_PORT_MASK4_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos)
#define GPIO_PORT_MASK4_MASKP10_Pos                           10
#define GPIO_PORT_MASK4_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos)
#define GPIO_PORT_MASK4_MASKP11_Pos                           11
#define GPIO_PORT_MASK4_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos)
#define GPIO_PORT_MASK4_MASKP12_Pos                           12
#define GPIO_PORT_MASK4_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos)
#define GPIO_PORT_MASK4_MASKP13_Pos                           13
#define GPIO_PORT_MASK4_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos)
#define GPIO_PORT_MASK4_MASKP14_Pos                           14
#define GPIO_PORT_MASK4_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos)
#define GPIO_PORT_MASK4_MASKP15_Pos                           15
#define GPIO_PORT_MASK4_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos)
#define GPIO_PORT_MASK4_MASKP16_Pos                           16
#define GPIO_PORT_MASK4_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos)
#define GPIO_PORT_MASK4_MASKP17_Pos                           17
#define GPIO_PORT_MASK4_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos)
#define GPIO_PORT_MASK4_MASKP18_Pos                           18
#define GPIO_PORT_MASK4_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos)
#define GPIO_PORT_MASK4_MASKP19_Pos                           19
#define GPIO_PORT_MASK4_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos)
#define GPIO_PORT_MASK4_MASKP20_Pos                           20
#define GPIO_PORT_MASK4_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos)
#define GPIO_PORT_MASK4_MASKP21_Pos                           21
#define GPIO_PORT_MASK4_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos)
#define GPIO_PORT_MASK4_MASKP22_Pos                           22
#define GPIO_PORT_MASK4_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos)
#define GPIO_PORT_MASK4_MASKP23_Pos                           23
#define GPIO_PORT_MASK4_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos)
#define GPIO_PORT_MASK4_MASKP24_Pos                           24
#define GPIO_PORT_MASK4_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos)
#define GPIO_PORT_MASK4_MASKP25_Pos                           25
#define GPIO_PORT_MASK4_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos)
#define GPIO_PORT_MASK4_MASKP26_Pos                           26
#define GPIO_PORT_MASK4_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos)
#define GPIO_PORT_MASK4_MASKP27_Pos                           27
#define GPIO_PORT_MASK4_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos)
#define GPIO_PORT_MASK4_MASKP28_Pos                           28
#define GPIO_PORT_MASK4_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos)
#define GPIO_PORT_MASK4_MASKP29_Pos                           29
#define GPIO_PORT_MASK4_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos)
#define GPIO_PORT_MASK4_MASKP30_Pos                           30
#define GPIO_PORT_MASK4_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos)
#define GPIO_PORT_MASK4_MASKP31_Pos                           31
#define GPIO_PORT_MASK4_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK5  ----------------------------------------
#define GPIO_PORT_MASK5_MASKP0_Pos                            0
#define GPIO_PORT_MASK5_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos)
#define GPIO_PORT_MASK5_MASKP1_Pos                            1
#define GPIO_PORT_MASK5_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos)
#define GPIO_PORT_MASK5_MASKP2_Pos                            2
#define GPIO_PORT_MASK5_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos)
#define GPIO_PORT_MASK5_MASKP3_Pos                            3
#define GPIO_PORT_MASK5_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos)
#define GPIO_PORT_MASK5_MASKP4_Pos                            4
#define GPIO_PORT_MASK5_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos)
#define GPIO_PORT_MASK5_MASKP5_Pos                            5
#define GPIO_PORT_MASK5_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos)
#define GPIO_PORT_MASK5_MASKP6_Pos                            6
#define GPIO_PORT_MASK5_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos)
#define GPIO_PORT_MASK5_MASKP7_Pos                            7
#define GPIO_PORT_MASK5_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos)
#define GPIO_PORT_MASK5_MASKP8_Pos                            8
#define GPIO_PORT_MASK5_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos)
#define GPIO_PORT_MASK5_MASKP9_Pos                            9
#define GPIO_PORT_MASK5_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos)
#define GPIO_PORT_MASK5_MASKP10_Pos                           10
#define GPIO_PORT_MASK5_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos)
#define GPIO_PORT_MASK5_MASKP11_Pos                           11
#define GPIO_PORT_MASK5_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos)
#define GPIO_PORT_MASK5_MASKP12_Pos                           12
#define GPIO_PORT_MASK5_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos)
#define GPIO_PORT_MASK5_MASKP13_Pos                           13
#define GPIO_PORT_MASK5_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos)
#define GPIO_PORT_MASK5_MASKP14_Pos                           14
#define GPIO_PORT_MASK5_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos)
#define GPIO_PORT_MASK5_MASKP15_Pos                           15
#define GPIO_PORT_MASK5_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos)
#define GPIO_PORT_MASK5_MASKP16_Pos                           16
#define GPIO_PORT_MASK5_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos)
#define GPIO_PORT_MASK5_MASKP17_Pos                           17
#define GPIO_PORT_MASK5_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos)
#define GPIO_PORT_MASK5_MASKP18_Pos                           18
#define GPIO_PORT_MASK5_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos)
#define GPIO_PORT_MASK5_MASKP19_Pos                           19
#define GPIO_PORT_MASK5_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos)
#define GPIO_PORT_MASK5_MASKP20_Pos                           20
#define GPIO_PORT_MASK5_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos)
#define GPIO_PORT_MASK5_MASKP21_Pos                           21
#define GPIO_PORT_MASK5_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos)
#define GPIO_PORT_MASK5_MASKP22_Pos                           22
#define GPIO_PORT_MASK5_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos)
#define GPIO_PORT_MASK5_MASKP23_Pos                           23
#define GPIO_PORT_MASK5_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos)
#define GPIO_PORT_MASK5_MASKP24_Pos                           24
#define GPIO_PORT_MASK5_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos)
#define GPIO_PORT_MASK5_MASKP25_Pos                           25
#define GPIO_PORT_MASK5_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos)
#define GPIO_PORT_MASK5_MASKP26_Pos                           26
#define GPIO_PORT_MASK5_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos)
#define GPIO_PORT_MASK5_MASKP27_Pos                           27
#define GPIO_PORT_MASK5_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos)
#define GPIO_PORT_MASK5_MASKP28_Pos                           28
#define GPIO_PORT_MASK5_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos)
#define GPIO_PORT_MASK5_MASKP29_Pos                           29
#define GPIO_PORT_MASK5_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos)
#define GPIO_PORT_MASK5_MASKP30_Pos                           30
#define GPIO_PORT_MASK5_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos)
#define GPIO_PORT_MASK5_MASKP31_Pos                           31
#define GPIO_PORT_MASK5_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK6  ----------------------------------------
#define GPIO_PORT_MASK6_MASKP0_Pos                            0
#define GPIO_PORT_MASK6_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos)
#define GPIO_PORT_MASK6_MASKP1_Pos                            1
#define GPIO_PORT_MASK6_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos)
#define GPIO_PORT_MASK6_MASKP2_Pos                            2
#define GPIO_PORT_MASK6_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos)
#define GPIO_PORT_MASK6_MASKP3_Pos                            3
#define GPIO_PORT_MASK6_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos)
#define GPIO_PORT_MASK6_MASKP4_Pos                            4
#define GPIO_PORT_MASK6_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos)
#define GPIO_PORT_MASK6_MASKP5_Pos                            5
#define GPIO_PORT_MASK6_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos)
#define GPIO_PORT_MASK6_MASKP6_Pos                            6
#define GPIO_PORT_MASK6_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos)
#define GPIO_PORT_MASK6_MASKP7_Pos                            7
#define GPIO_PORT_MASK6_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos)
#define GPIO_PORT_MASK6_MASKP8_Pos                            8
#define GPIO_PORT_MASK6_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos)
#define GPIO_PORT_MASK6_MASKP9_Pos                            9
#define GPIO_PORT_MASK6_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos)
#define GPIO_PORT_MASK6_MASKP10_Pos                           10
#define GPIO_PORT_MASK6_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos)
#define GPIO_PORT_MASK6_MASKP11_Pos                           11
#define GPIO_PORT_MASK6_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos)
#define GPIO_PORT_MASK6_MASKP12_Pos                           12
#define GPIO_PORT_MASK6_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos)
#define GPIO_PORT_MASK6_MASKP13_Pos                           13
#define GPIO_PORT_MASK6_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos)
#define GPIO_PORT_MASK6_MASKP14_Pos                           14
#define GPIO_PORT_MASK6_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos)
#define GPIO_PORT_MASK6_MASKP15_Pos                           15
#define GPIO_PORT_MASK6_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos)
#define GPIO_PORT_MASK6_MASKP16_Pos                           16
#define GPIO_PORT_MASK6_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos)
#define GPIO_PORT_MASK6_MASKP17_Pos                           17
#define GPIO_PORT_MASK6_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos)
#define GPIO_PORT_MASK6_MASKP18_Pos                           18
#define GPIO_PORT_MASK6_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos)
#define GPIO_PORT_MASK6_MASKP19_Pos                           19
#define GPIO_PORT_MASK6_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos)
#define GPIO_PORT_MASK6_MASKP20_Pos                           20
#define GPIO_PORT_MASK6_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos)
#define GPIO_PORT_MASK6_MASKP21_Pos                           21
#define GPIO_PORT_MASK6_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos)
#define GPIO_PORT_MASK6_MASKP22_Pos                           22
#define GPIO_PORT_MASK6_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos)
#define GPIO_PORT_MASK6_MASKP23_Pos                           23
#define GPIO_PORT_MASK6_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos)
#define GPIO_PORT_MASK6_MASKP24_Pos                           24
#define GPIO_PORT_MASK6_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos)
#define GPIO_PORT_MASK6_MASKP25_Pos                           25
#define GPIO_PORT_MASK6_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos)
#define GPIO_PORT_MASK6_MASKP26_Pos                           26
#define GPIO_PORT_MASK6_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos)
#define GPIO_PORT_MASK6_MASKP27_Pos                           27
#define GPIO_PORT_MASK6_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos)
#define GPIO_PORT_MASK6_MASKP28_Pos                           28
#define GPIO_PORT_MASK6_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos)
#define GPIO_PORT_MASK6_MASKP29_Pos                           29
#define GPIO_PORT_MASK6_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos)
#define GPIO_PORT_MASK6_MASKP30_Pos                           30
#define GPIO_PORT_MASK6_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos)
#define GPIO_PORT_MASK6_MASKP31_Pos                           31
#define GPIO_PORT_MASK6_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_MASK7  ----------------------------------------
#define GPIO_PORT_MASK7_MASKP0_Pos                            0
#define GPIO_PORT_MASK7_MASKP0_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos)
#define GPIO_PORT_MASK7_MASKP1_Pos                            1
#define GPIO_PORT_MASK7_MASKP1_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos)
#define GPIO_PORT_MASK7_MASKP2_Pos                            2
#define GPIO_PORT_MASK7_MASKP2_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos)
#define GPIO_PORT_MASK7_MASKP3_Pos                            3
#define GPIO_PORT_MASK7_MASKP3_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos)
#define GPIO_PORT_MASK7_MASKP4_Pos                            4
#define GPIO_PORT_MASK7_MASKP4_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos)
#define GPIO_PORT_MASK7_MASKP5_Pos                            5
#define GPIO_PORT_MASK7_MASKP5_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos)
#define GPIO_PORT_MASK7_MASKP6_Pos                            6
#define GPIO_PORT_MASK7_MASKP6_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos)
#define GPIO_PORT_MASK7_MASKP7_Pos                            7
#define GPIO_PORT_MASK7_MASKP7_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos)
#define GPIO_PORT_MASK7_MASKP8_Pos                            8
#define GPIO_PORT_MASK7_MASKP8_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos)
#define GPIO_PORT_MASK7_MASKP9_Pos                            9
#define GPIO_PORT_MASK7_MASKP9_Msk                            (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos)
#define GPIO_PORT_MASK7_MASKP10_Pos                           10
#define GPIO_PORT_MASK7_MASKP10_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos)
#define GPIO_PORT_MASK7_MASKP11_Pos                           11
#define GPIO_PORT_MASK7_MASKP11_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos)
#define GPIO_PORT_MASK7_MASKP12_Pos                           12
#define GPIO_PORT_MASK7_MASKP12_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos)
#define GPIO_PORT_MASK7_MASKP13_Pos                           13
#define GPIO_PORT_MASK7_MASKP13_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos)
#define GPIO_PORT_MASK7_MASKP14_Pos                           14
#define GPIO_PORT_MASK7_MASKP14_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos)
#define GPIO_PORT_MASK7_MASKP15_Pos                           15
#define GPIO_PORT_MASK7_MASKP15_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos)
#define GPIO_PORT_MASK7_MASKP16_Pos                           16
#define GPIO_PORT_MASK7_MASKP16_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos)
#define GPIO_PORT_MASK7_MASKP17_Pos                           17
#define GPIO_PORT_MASK7_MASKP17_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos)
#define GPIO_PORT_MASK7_MASKP18_Pos                           18
#define GPIO_PORT_MASK7_MASKP18_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos)
#define GPIO_PORT_MASK7_MASKP19_Pos                           19
#define GPIO_PORT_MASK7_MASKP19_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos)
#define GPIO_PORT_MASK7_MASKP20_Pos                           20
#define GPIO_PORT_MASK7_MASKP20_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos)
#define GPIO_PORT_MASK7_MASKP21_Pos                           21
#define GPIO_PORT_MASK7_MASKP21_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos)
#define GPIO_PORT_MASK7_MASKP22_Pos                           22
#define GPIO_PORT_MASK7_MASKP22_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos)
#define GPIO_PORT_MASK7_MASKP23_Pos                           23
#define GPIO_PORT_MASK7_MASKP23_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos)
#define GPIO_PORT_MASK7_MASKP24_Pos                           24
#define GPIO_PORT_MASK7_MASKP24_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos)
#define GPIO_PORT_MASK7_MASKP25_Pos                           25
#define GPIO_PORT_MASK7_MASKP25_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos)
#define GPIO_PORT_MASK7_MASKP26_Pos                           26
#define GPIO_PORT_MASK7_MASKP26_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos)
#define GPIO_PORT_MASK7_MASKP27_Pos                           27
#define GPIO_PORT_MASK7_MASKP27_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos)
#define GPIO_PORT_MASK7_MASKP28_Pos                           28
#define GPIO_PORT_MASK7_MASKP28_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos)
#define GPIO_PORT_MASK7_MASKP29_Pos                           29
#define GPIO_PORT_MASK7_MASKP29_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos)
#define GPIO_PORT_MASK7_MASKP30_Pos                           30
#define GPIO_PORT_MASK7_MASKP30_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos)
#define GPIO_PORT_MASK7_MASKP31_Pos                           31
#define GPIO_PORT_MASK7_MASKP31_Msk                           (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos)

// -------------------------------------  GPIO_PORT_PIN0  -----------------------------------------
#define GPIO_PORT_PIN0_PORT0_Pos                              0
#define GPIO_PORT_PIN0_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT0_Pos)
#define GPIO_PORT_PIN0_PORT1_Pos                              1
#define GPIO_PORT_PIN0_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT1_Pos)
#define GPIO_PORT_PIN0_PORT2_Pos                              2
#define GPIO_PORT_PIN0_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT2_Pos)
#define GPIO_PORT_PIN0_PORT3_Pos                              3
#define GPIO_PORT_PIN0_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT3_Pos)
#define GPIO_PORT_PIN0_PORT4_Pos                              4
#define GPIO_PORT_PIN0_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT4_Pos)
#define GPIO_PORT_PIN0_PORT5_Pos                              5
#define GPIO_PORT_PIN0_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT5_Pos)
#define GPIO_PORT_PIN0_PORT6_Pos                              6
#define GPIO_PORT_PIN0_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT6_Pos)
#define GPIO_PORT_PIN0_PORT7_Pos                              7
#define GPIO_PORT_PIN0_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT7_Pos)
#define GPIO_PORT_PIN0_PORT8_Pos                              8
#define GPIO_PORT_PIN0_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT8_Pos)
#define GPIO_PORT_PIN0_PORT9_Pos                              9
#define GPIO_PORT_PIN0_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN0_PORT9_Pos)
#define GPIO_PORT_PIN0_PORT10_Pos                             10
#define GPIO_PORT_PIN0_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT10_Pos)
#define GPIO_PORT_PIN0_PORT11_Pos                             11
#define GPIO_PORT_PIN0_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT11_Pos)
#define GPIO_PORT_PIN0_PORT12_Pos                             12
#define GPIO_PORT_PIN0_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT12_Pos)
#define GPIO_PORT_PIN0_PORT13_Pos                             13
#define GPIO_PORT_PIN0_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT13_Pos)
#define GPIO_PORT_PIN0_PORT14_Pos                             14
#define GPIO_PORT_PIN0_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT14_Pos)
#define GPIO_PORT_PIN0_PORT15_Pos                             15
#define GPIO_PORT_PIN0_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT15_Pos)
#define GPIO_PORT_PIN0_PORT16_Pos                             16
#define GPIO_PORT_PIN0_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT16_Pos)
#define GPIO_PORT_PIN0_PORT17_Pos                             17
#define GPIO_PORT_PIN0_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT17_Pos)
#define GPIO_PORT_PIN0_PORT18_Pos                             18
#define GPIO_PORT_PIN0_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT18_Pos)
#define GPIO_PORT_PIN0_PORT19_Pos                             19
#define GPIO_PORT_PIN0_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT19_Pos)
#define GPIO_PORT_PIN0_PORT20_Pos                             20
#define GPIO_PORT_PIN0_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT20_Pos)
#define GPIO_PORT_PIN0_PORT21_Pos                             21
#define GPIO_PORT_PIN0_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT21_Pos)
#define GPIO_PORT_PIN0_PORT22_Pos                             22
#define GPIO_PORT_PIN0_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT22_Pos)
#define GPIO_PORT_PIN0_PORT23_Pos                             23
#define GPIO_PORT_PIN0_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT23_Pos)
#define GPIO_PORT_PIN0_PORT24_Pos                             24
#define GPIO_PORT_PIN0_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT24_Pos)
#define GPIO_PORT_PIN0_PORT25_Pos                             25
#define GPIO_PORT_PIN0_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT25_Pos)
#define GPIO_PORT_PIN0_PORT26_Pos                             26
#define GPIO_PORT_PIN0_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT26_Pos)
#define GPIO_PORT_PIN0_PORT27_Pos                             27
#define GPIO_PORT_PIN0_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT27_Pos)
#define GPIO_PORT_PIN0_PORT28_Pos                             28
#define GPIO_PORT_PIN0_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT28_Pos)
#define GPIO_PORT_PIN0_PORT29_Pos                             29
#define GPIO_PORT_PIN0_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT29_Pos)
#define GPIO_PORT_PIN0_PORT30_Pos                             30
#define GPIO_PORT_PIN0_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT30_Pos)
#define GPIO_PORT_PIN0_PORT31_Pos                             31
#define GPIO_PORT_PIN0_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN0_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN1  -----------------------------------------
#define GPIO_PORT_PIN1_PORT0_Pos                              0
#define GPIO_PORT_PIN1_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT0_Pos)
#define GPIO_PORT_PIN1_PORT1_Pos                              1
#define GPIO_PORT_PIN1_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT1_Pos)
#define GPIO_PORT_PIN1_PORT2_Pos                              2
#define GPIO_PORT_PIN1_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT2_Pos)
#define GPIO_PORT_PIN1_PORT3_Pos                              3
#define GPIO_PORT_PIN1_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT3_Pos)
#define GPIO_PORT_PIN1_PORT4_Pos                              4
#define GPIO_PORT_PIN1_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT4_Pos)
#define GPIO_PORT_PIN1_PORT5_Pos                              5
#define GPIO_PORT_PIN1_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT5_Pos)
#define GPIO_PORT_PIN1_PORT6_Pos                              6
#define GPIO_PORT_PIN1_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT6_Pos)
#define GPIO_PORT_PIN1_PORT7_Pos                              7
#define GPIO_PORT_PIN1_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT7_Pos)
#define GPIO_PORT_PIN1_PORT8_Pos                              8
#define GPIO_PORT_PIN1_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT8_Pos)
#define GPIO_PORT_PIN1_PORT9_Pos                              9
#define GPIO_PORT_PIN1_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN1_PORT9_Pos)
#define GPIO_PORT_PIN1_PORT10_Pos                             10
#define GPIO_PORT_PIN1_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT10_Pos)
#define GPIO_PORT_PIN1_PORT11_Pos                             11
#define GPIO_PORT_PIN1_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT11_Pos)
#define GPIO_PORT_PIN1_PORT12_Pos                             12
#define GPIO_PORT_PIN1_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT12_Pos)
#define GPIO_PORT_PIN1_PORT13_Pos                             13
#define GPIO_PORT_PIN1_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT13_Pos)
#define GPIO_PORT_PIN1_PORT14_Pos                             14
#define GPIO_PORT_PIN1_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT14_Pos)
#define GPIO_PORT_PIN1_PORT15_Pos                             15
#define GPIO_PORT_PIN1_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT15_Pos)
#define GPIO_PORT_PIN1_PORT16_Pos                             16
#define GPIO_PORT_PIN1_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT16_Pos)
#define GPIO_PORT_PIN1_PORT17_Pos                             17
#define GPIO_PORT_PIN1_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT17_Pos)
#define GPIO_PORT_PIN1_PORT18_Pos                             18
#define GPIO_PORT_PIN1_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT18_Pos)
#define GPIO_PORT_PIN1_PORT19_Pos                             19
#define GPIO_PORT_PIN1_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT19_Pos)
#define GPIO_PORT_PIN1_PORT20_Pos                             20
#define GPIO_PORT_PIN1_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT20_Pos)
#define GPIO_PORT_PIN1_PORT21_Pos                             21
#define GPIO_PORT_PIN1_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT21_Pos)
#define GPIO_PORT_PIN1_PORT22_Pos                             22
#define GPIO_PORT_PIN1_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT22_Pos)
#define GPIO_PORT_PIN1_PORT23_Pos                             23
#define GPIO_PORT_PIN1_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT23_Pos)
#define GPIO_PORT_PIN1_PORT24_Pos                             24
#define GPIO_PORT_PIN1_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT24_Pos)
#define GPIO_PORT_PIN1_PORT25_Pos                             25
#define GPIO_PORT_PIN1_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT25_Pos)
#define GPIO_PORT_PIN1_PORT26_Pos                             26
#define GPIO_PORT_PIN1_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT26_Pos)
#define GPIO_PORT_PIN1_PORT27_Pos                             27
#define GPIO_PORT_PIN1_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT27_Pos)
#define GPIO_PORT_PIN1_PORT28_Pos                             28
#define GPIO_PORT_PIN1_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT28_Pos)
#define GPIO_PORT_PIN1_PORT29_Pos                             29
#define GPIO_PORT_PIN1_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT29_Pos)
#define GPIO_PORT_PIN1_PORT30_Pos                             30
#define GPIO_PORT_PIN1_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT30_Pos)
#define GPIO_PORT_PIN1_PORT31_Pos                             31
#define GPIO_PORT_PIN1_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN1_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN2  -----------------------------------------
#define GPIO_PORT_PIN2_PORT0_Pos                              0
#define GPIO_PORT_PIN2_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT0_Pos)
#define GPIO_PORT_PIN2_PORT1_Pos                              1
#define GPIO_PORT_PIN2_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT1_Pos)
#define GPIO_PORT_PIN2_PORT2_Pos                              2
#define GPIO_PORT_PIN2_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT2_Pos)
#define GPIO_PORT_PIN2_PORT3_Pos                              3
#define GPIO_PORT_PIN2_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT3_Pos)
#define GPIO_PORT_PIN2_PORT4_Pos                              4
#define GPIO_PORT_PIN2_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT4_Pos)
#define GPIO_PORT_PIN2_PORT5_Pos                              5
#define GPIO_PORT_PIN2_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT5_Pos)
#define GPIO_PORT_PIN2_PORT6_Pos                              6
#define GPIO_PORT_PIN2_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT6_Pos)
#define GPIO_PORT_PIN2_PORT7_Pos                              7
#define GPIO_PORT_PIN2_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT7_Pos)
#define GPIO_PORT_PIN2_PORT8_Pos                              8
#define GPIO_PORT_PIN2_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT8_Pos)
#define GPIO_PORT_PIN2_PORT9_Pos                              9
#define GPIO_PORT_PIN2_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN2_PORT9_Pos)
#define GPIO_PORT_PIN2_PORT10_Pos                             10
#define GPIO_PORT_PIN2_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT10_Pos)
#define GPIO_PORT_PIN2_PORT11_Pos                             11
#define GPIO_PORT_PIN2_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT11_Pos)
#define GPIO_PORT_PIN2_PORT12_Pos                             12
#define GPIO_PORT_PIN2_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT12_Pos)
#define GPIO_PORT_PIN2_PORT13_Pos                             13
#define GPIO_PORT_PIN2_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT13_Pos)
#define GPIO_PORT_PIN2_PORT14_Pos                             14
#define GPIO_PORT_PIN2_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT14_Pos)
#define GPIO_PORT_PIN2_PORT15_Pos                             15
#define GPIO_PORT_PIN2_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT15_Pos)
#define GPIO_PORT_PIN2_PORT16_Pos                             16
#define GPIO_PORT_PIN2_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT16_Pos)
#define GPIO_PORT_PIN2_PORT17_Pos                             17
#define GPIO_PORT_PIN2_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT17_Pos)
#define GPIO_PORT_PIN2_PORT18_Pos                             18
#define GPIO_PORT_PIN2_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT18_Pos)
#define GPIO_PORT_PIN2_PORT19_Pos                             19
#define GPIO_PORT_PIN2_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT19_Pos)
#define GPIO_PORT_PIN2_PORT20_Pos                             20
#define GPIO_PORT_PIN2_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT20_Pos)
#define GPIO_PORT_PIN2_PORT21_Pos                             21
#define GPIO_PORT_PIN2_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT21_Pos)
#define GPIO_PORT_PIN2_PORT22_Pos                             22
#define GPIO_PORT_PIN2_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT22_Pos)
#define GPIO_PORT_PIN2_PORT23_Pos                             23
#define GPIO_PORT_PIN2_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT23_Pos)
#define GPIO_PORT_PIN2_PORT24_Pos                             24
#define GPIO_PORT_PIN2_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT24_Pos)
#define GPIO_PORT_PIN2_PORT25_Pos                             25
#define GPIO_PORT_PIN2_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT25_Pos)
#define GPIO_PORT_PIN2_PORT26_Pos                             26
#define GPIO_PORT_PIN2_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT26_Pos)
#define GPIO_PORT_PIN2_PORT27_Pos                             27
#define GPIO_PORT_PIN2_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT27_Pos)
#define GPIO_PORT_PIN2_PORT28_Pos                             28
#define GPIO_PORT_PIN2_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT28_Pos)
#define GPIO_PORT_PIN2_PORT29_Pos                             29
#define GPIO_PORT_PIN2_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT29_Pos)
#define GPIO_PORT_PIN2_PORT30_Pos                             30
#define GPIO_PORT_PIN2_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT30_Pos)
#define GPIO_PORT_PIN2_PORT31_Pos                             31
#define GPIO_PORT_PIN2_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN2_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN3  -----------------------------------------
#define GPIO_PORT_PIN3_PORT0_Pos                              0
#define GPIO_PORT_PIN3_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT0_Pos)
#define GPIO_PORT_PIN3_PORT1_Pos                              1
#define GPIO_PORT_PIN3_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT1_Pos)
#define GPIO_PORT_PIN3_PORT2_Pos                              2
#define GPIO_PORT_PIN3_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT2_Pos)
#define GPIO_PORT_PIN3_PORT3_Pos                              3
#define GPIO_PORT_PIN3_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT3_Pos)
#define GPIO_PORT_PIN3_PORT4_Pos                              4
#define GPIO_PORT_PIN3_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT4_Pos)
#define GPIO_PORT_PIN3_PORT5_Pos                              5
#define GPIO_PORT_PIN3_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT5_Pos)
#define GPIO_PORT_PIN3_PORT6_Pos                              6
#define GPIO_PORT_PIN3_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT6_Pos)
#define GPIO_PORT_PIN3_PORT7_Pos                              7
#define GPIO_PORT_PIN3_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT7_Pos)
#define GPIO_PORT_PIN3_PORT8_Pos                              8
#define GPIO_PORT_PIN3_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT8_Pos)
#define GPIO_PORT_PIN3_PORT9_Pos                              9
#define GPIO_PORT_PIN3_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN3_PORT9_Pos)
#define GPIO_PORT_PIN3_PORT10_Pos                             10
#define GPIO_PORT_PIN3_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT10_Pos)
#define GPIO_PORT_PIN3_PORT11_Pos                             11
#define GPIO_PORT_PIN3_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT11_Pos)
#define GPIO_PORT_PIN3_PORT12_Pos                             12
#define GPIO_PORT_PIN3_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT12_Pos)
#define GPIO_PORT_PIN3_PORT13_Pos                             13
#define GPIO_PORT_PIN3_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT13_Pos)
#define GPIO_PORT_PIN3_PORT14_Pos                             14
#define GPIO_PORT_PIN3_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT14_Pos)
#define GPIO_PORT_PIN3_PORT15_Pos                             15
#define GPIO_PORT_PIN3_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT15_Pos)
#define GPIO_PORT_PIN3_PORT16_Pos                             16
#define GPIO_PORT_PIN3_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT16_Pos)
#define GPIO_PORT_PIN3_PORT17_Pos                             17
#define GPIO_PORT_PIN3_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT17_Pos)
#define GPIO_PORT_PIN3_PORT18_Pos                             18
#define GPIO_PORT_PIN3_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT18_Pos)
#define GPIO_PORT_PIN3_PORT19_Pos                             19
#define GPIO_PORT_PIN3_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT19_Pos)
#define GPIO_PORT_PIN3_PORT20_Pos                             20
#define GPIO_PORT_PIN3_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT20_Pos)
#define GPIO_PORT_PIN3_PORT21_Pos                             21
#define GPIO_PORT_PIN3_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT21_Pos)
#define GPIO_PORT_PIN3_PORT22_Pos                             22
#define GPIO_PORT_PIN3_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT22_Pos)
#define GPIO_PORT_PIN3_PORT23_Pos                             23
#define GPIO_PORT_PIN3_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT23_Pos)
#define GPIO_PORT_PIN3_PORT24_Pos                             24
#define GPIO_PORT_PIN3_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT24_Pos)
#define GPIO_PORT_PIN3_PORT25_Pos                             25
#define GPIO_PORT_PIN3_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT25_Pos)
#define GPIO_PORT_PIN3_PORT26_Pos                             26
#define GPIO_PORT_PIN3_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT26_Pos)
#define GPIO_PORT_PIN3_PORT27_Pos                             27
#define GPIO_PORT_PIN3_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT27_Pos)
#define GPIO_PORT_PIN3_PORT28_Pos                             28
#define GPIO_PORT_PIN3_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT28_Pos)
#define GPIO_PORT_PIN3_PORT29_Pos                             29
#define GPIO_PORT_PIN3_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT29_Pos)
#define GPIO_PORT_PIN3_PORT30_Pos                             30
#define GPIO_PORT_PIN3_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT30_Pos)
#define GPIO_PORT_PIN3_PORT31_Pos                             31
#define GPIO_PORT_PIN3_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN3_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN4  -----------------------------------------
#define GPIO_PORT_PIN4_PORT0_Pos                              0
#define GPIO_PORT_PIN4_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT0_Pos)
#define GPIO_PORT_PIN4_PORT1_Pos                              1
#define GPIO_PORT_PIN4_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT1_Pos)
#define GPIO_PORT_PIN4_PORT2_Pos                              2
#define GPIO_PORT_PIN4_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT2_Pos)
#define GPIO_PORT_PIN4_PORT3_Pos                              3
#define GPIO_PORT_PIN4_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT3_Pos)
#define GPIO_PORT_PIN4_PORT4_Pos                              4
#define GPIO_PORT_PIN4_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT4_Pos)
#define GPIO_PORT_PIN4_PORT5_Pos                              5
#define GPIO_PORT_PIN4_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT5_Pos)
#define GPIO_PORT_PIN4_PORT6_Pos                              6
#define GPIO_PORT_PIN4_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT6_Pos)
#define GPIO_PORT_PIN4_PORT7_Pos                              7
#define GPIO_PORT_PIN4_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT7_Pos)
#define GPIO_PORT_PIN4_PORT8_Pos                              8
#define GPIO_PORT_PIN4_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT8_Pos)
#define GPIO_PORT_PIN4_PORT9_Pos                              9
#define GPIO_PORT_PIN4_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN4_PORT9_Pos)
#define GPIO_PORT_PIN4_PORT10_Pos                             10
#define GPIO_PORT_PIN4_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT10_Pos)
#define GPIO_PORT_PIN4_PORT11_Pos                             11
#define GPIO_PORT_PIN4_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT11_Pos)
#define GPIO_PORT_PIN4_PORT12_Pos                             12
#define GPIO_PORT_PIN4_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT12_Pos)
#define GPIO_PORT_PIN4_PORT13_Pos                             13
#define GPIO_PORT_PIN4_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT13_Pos)
#define GPIO_PORT_PIN4_PORT14_Pos                             14
#define GPIO_PORT_PIN4_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT14_Pos)
#define GPIO_PORT_PIN4_PORT15_Pos                             15
#define GPIO_PORT_PIN4_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT15_Pos)
#define GPIO_PORT_PIN4_PORT16_Pos                             16
#define GPIO_PORT_PIN4_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT16_Pos)
#define GPIO_PORT_PIN4_PORT17_Pos                             17
#define GPIO_PORT_PIN4_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT17_Pos)
#define GPIO_PORT_PIN4_PORT18_Pos                             18
#define GPIO_PORT_PIN4_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT18_Pos)
#define GPIO_PORT_PIN4_PORT19_Pos                             19
#define GPIO_PORT_PIN4_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT19_Pos)
#define GPIO_PORT_PIN4_PORT20_Pos                             20
#define GPIO_PORT_PIN4_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT20_Pos)
#define GPIO_PORT_PIN4_PORT21_Pos                             21
#define GPIO_PORT_PIN4_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT21_Pos)
#define GPIO_PORT_PIN4_PORT22_Pos                             22
#define GPIO_PORT_PIN4_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT22_Pos)
#define GPIO_PORT_PIN4_PORT23_Pos                             23
#define GPIO_PORT_PIN4_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT23_Pos)
#define GPIO_PORT_PIN4_PORT24_Pos                             24
#define GPIO_PORT_PIN4_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT24_Pos)
#define GPIO_PORT_PIN4_PORT25_Pos                             25
#define GPIO_PORT_PIN4_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT25_Pos)
#define GPIO_PORT_PIN4_PORT26_Pos                             26
#define GPIO_PORT_PIN4_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT26_Pos)
#define GPIO_PORT_PIN4_PORT27_Pos                             27
#define GPIO_PORT_PIN4_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT27_Pos)
#define GPIO_PORT_PIN4_PORT28_Pos                             28
#define GPIO_PORT_PIN4_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT28_Pos)
#define GPIO_PORT_PIN4_PORT29_Pos                             29
#define GPIO_PORT_PIN4_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT29_Pos)
#define GPIO_PORT_PIN4_PORT30_Pos                             30
#define GPIO_PORT_PIN4_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT30_Pos)
#define GPIO_PORT_PIN4_PORT31_Pos                             31
#define GPIO_PORT_PIN4_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN4_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN5  -----------------------------------------
#define GPIO_PORT_PIN5_PORT0_Pos                              0
#define GPIO_PORT_PIN5_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT0_Pos)
#define GPIO_PORT_PIN5_PORT1_Pos                              1
#define GPIO_PORT_PIN5_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT1_Pos)
#define GPIO_PORT_PIN5_PORT2_Pos                              2
#define GPIO_PORT_PIN5_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT2_Pos)
#define GPIO_PORT_PIN5_PORT3_Pos                              3
#define GPIO_PORT_PIN5_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT3_Pos)
#define GPIO_PORT_PIN5_PORT4_Pos                              4
#define GPIO_PORT_PIN5_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT4_Pos)
#define GPIO_PORT_PIN5_PORT5_Pos                              5
#define GPIO_PORT_PIN5_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT5_Pos)
#define GPIO_PORT_PIN5_PORT6_Pos                              6
#define GPIO_PORT_PIN5_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT6_Pos)
#define GPIO_PORT_PIN5_PORT7_Pos                              7
#define GPIO_PORT_PIN5_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT7_Pos)
#define GPIO_PORT_PIN5_PORT8_Pos                              8
#define GPIO_PORT_PIN5_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT8_Pos)
#define GPIO_PORT_PIN5_PORT9_Pos                              9
#define GPIO_PORT_PIN5_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN5_PORT9_Pos)
#define GPIO_PORT_PIN5_PORT10_Pos                             10
#define GPIO_PORT_PIN5_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT10_Pos)
#define GPIO_PORT_PIN5_PORT11_Pos                             11
#define GPIO_PORT_PIN5_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT11_Pos)
#define GPIO_PORT_PIN5_PORT12_Pos                             12
#define GPIO_PORT_PIN5_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT12_Pos)
#define GPIO_PORT_PIN5_PORT13_Pos                             13
#define GPIO_PORT_PIN5_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT13_Pos)
#define GPIO_PORT_PIN5_PORT14_Pos                             14
#define GPIO_PORT_PIN5_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT14_Pos)
#define GPIO_PORT_PIN5_PORT15_Pos                             15
#define GPIO_PORT_PIN5_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT15_Pos)
#define GPIO_PORT_PIN5_PORT16_Pos                             16
#define GPIO_PORT_PIN5_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT16_Pos)
#define GPIO_PORT_PIN5_PORT17_Pos                             17
#define GPIO_PORT_PIN5_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT17_Pos)
#define GPIO_PORT_PIN5_PORT18_Pos                             18
#define GPIO_PORT_PIN5_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT18_Pos)
#define GPIO_PORT_PIN5_PORT19_Pos                             19
#define GPIO_PORT_PIN5_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT19_Pos)
#define GPIO_PORT_PIN5_PORT20_Pos                             20
#define GPIO_PORT_PIN5_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT20_Pos)
#define GPIO_PORT_PIN5_PORT21_Pos                             21
#define GPIO_PORT_PIN5_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT21_Pos)
#define GPIO_PORT_PIN5_PORT22_Pos                             22
#define GPIO_PORT_PIN5_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT22_Pos)
#define GPIO_PORT_PIN5_PORT23_Pos                             23
#define GPIO_PORT_PIN5_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT23_Pos)
#define GPIO_PORT_PIN5_PORT24_Pos                             24
#define GPIO_PORT_PIN5_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT24_Pos)
#define GPIO_PORT_PIN5_PORT25_Pos                             25
#define GPIO_PORT_PIN5_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT25_Pos)
#define GPIO_PORT_PIN5_PORT26_Pos                             26
#define GPIO_PORT_PIN5_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT26_Pos)
#define GPIO_PORT_PIN5_PORT27_Pos                             27
#define GPIO_PORT_PIN5_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT27_Pos)
#define GPIO_PORT_PIN5_PORT28_Pos                             28
#define GPIO_PORT_PIN5_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT28_Pos)
#define GPIO_PORT_PIN5_PORT29_Pos                             29
#define GPIO_PORT_PIN5_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT29_Pos)
#define GPIO_PORT_PIN5_PORT30_Pos                             30
#define GPIO_PORT_PIN5_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT30_Pos)
#define GPIO_PORT_PIN5_PORT31_Pos                             31
#define GPIO_PORT_PIN5_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN5_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN6  -----------------------------------------
#define GPIO_PORT_PIN6_PORT0_Pos                              0
#define GPIO_PORT_PIN6_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT0_Pos)
#define GPIO_PORT_PIN6_PORT1_Pos                              1
#define GPIO_PORT_PIN6_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT1_Pos)
#define GPIO_PORT_PIN6_PORT2_Pos                              2
#define GPIO_PORT_PIN6_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT2_Pos)
#define GPIO_PORT_PIN6_PORT3_Pos                              3
#define GPIO_PORT_PIN6_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT3_Pos)
#define GPIO_PORT_PIN6_PORT4_Pos                              4
#define GPIO_PORT_PIN6_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT4_Pos)
#define GPIO_PORT_PIN6_PORT5_Pos                              5
#define GPIO_PORT_PIN6_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT5_Pos)
#define GPIO_PORT_PIN6_PORT6_Pos                              6
#define GPIO_PORT_PIN6_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT6_Pos)
#define GPIO_PORT_PIN6_PORT7_Pos                              7
#define GPIO_PORT_PIN6_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT7_Pos)
#define GPIO_PORT_PIN6_PORT8_Pos                              8
#define GPIO_PORT_PIN6_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT8_Pos)
#define GPIO_PORT_PIN6_PORT9_Pos                              9
#define GPIO_PORT_PIN6_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN6_PORT9_Pos)
#define GPIO_PORT_PIN6_PORT10_Pos                             10
#define GPIO_PORT_PIN6_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT10_Pos)
#define GPIO_PORT_PIN6_PORT11_Pos                             11
#define GPIO_PORT_PIN6_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT11_Pos)
#define GPIO_PORT_PIN6_PORT12_Pos                             12
#define GPIO_PORT_PIN6_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT12_Pos)
#define GPIO_PORT_PIN6_PORT13_Pos                             13
#define GPIO_PORT_PIN6_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT13_Pos)
#define GPIO_PORT_PIN6_PORT14_Pos                             14
#define GPIO_PORT_PIN6_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT14_Pos)
#define GPIO_PORT_PIN6_PORT15_Pos                             15
#define GPIO_PORT_PIN6_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT15_Pos)
#define GPIO_PORT_PIN6_PORT16_Pos                             16
#define GPIO_PORT_PIN6_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT16_Pos)
#define GPIO_PORT_PIN6_PORT17_Pos                             17
#define GPIO_PORT_PIN6_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT17_Pos)
#define GPIO_PORT_PIN6_PORT18_Pos                             18
#define GPIO_PORT_PIN6_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT18_Pos)
#define GPIO_PORT_PIN6_PORT19_Pos                             19
#define GPIO_PORT_PIN6_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT19_Pos)
#define GPIO_PORT_PIN6_PORT20_Pos                             20
#define GPIO_PORT_PIN6_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT20_Pos)
#define GPIO_PORT_PIN6_PORT21_Pos                             21
#define GPIO_PORT_PIN6_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT21_Pos)
#define GPIO_PORT_PIN6_PORT22_Pos                             22
#define GPIO_PORT_PIN6_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT22_Pos)
#define GPIO_PORT_PIN6_PORT23_Pos                             23
#define GPIO_PORT_PIN6_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT23_Pos)
#define GPIO_PORT_PIN6_PORT24_Pos                             24
#define GPIO_PORT_PIN6_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT24_Pos)
#define GPIO_PORT_PIN6_PORT25_Pos                             25
#define GPIO_PORT_PIN6_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT25_Pos)
#define GPIO_PORT_PIN6_PORT26_Pos                             26
#define GPIO_PORT_PIN6_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT26_Pos)
#define GPIO_PORT_PIN6_PORT27_Pos                             27
#define GPIO_PORT_PIN6_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT27_Pos)
#define GPIO_PORT_PIN6_PORT28_Pos                             28
#define GPIO_PORT_PIN6_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT28_Pos)
#define GPIO_PORT_PIN6_PORT29_Pos                             29
#define GPIO_PORT_PIN6_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT29_Pos)
#define GPIO_PORT_PIN6_PORT30_Pos                             30
#define GPIO_PORT_PIN6_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT30_Pos)
#define GPIO_PORT_PIN6_PORT31_Pos                             31
#define GPIO_PORT_PIN6_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN6_PORT31_Pos)

// -------------------------------------  GPIO_PORT_PIN7  -----------------------------------------
#define GPIO_PORT_PIN7_PORT0_Pos                              0
#define GPIO_PORT_PIN7_PORT0_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT0_Pos)
#define GPIO_PORT_PIN7_PORT1_Pos                              1
#define GPIO_PORT_PIN7_PORT1_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT1_Pos)
#define GPIO_PORT_PIN7_PORT2_Pos                              2
#define GPIO_PORT_PIN7_PORT2_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT2_Pos)
#define GPIO_PORT_PIN7_PORT3_Pos                              3
#define GPIO_PORT_PIN7_PORT3_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT3_Pos)
#define GPIO_PORT_PIN7_PORT4_Pos                              4
#define GPIO_PORT_PIN7_PORT4_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT4_Pos)
#define GPIO_PORT_PIN7_PORT5_Pos                              5
#define GPIO_PORT_PIN7_PORT5_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT5_Pos)
#define GPIO_PORT_PIN7_PORT6_Pos                              6
#define GPIO_PORT_PIN7_PORT6_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT6_Pos)
#define GPIO_PORT_PIN7_PORT7_Pos                              7
#define GPIO_PORT_PIN7_PORT7_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT7_Pos)
#define GPIO_PORT_PIN7_PORT8_Pos                              8
#define GPIO_PORT_PIN7_PORT8_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT8_Pos)
#define GPIO_PORT_PIN7_PORT9_Pos                              9
#define GPIO_PORT_PIN7_PORT9_Msk                              (0x01UL << GPIO_PORT_PIN7_PORT9_Pos)
#define GPIO_PORT_PIN7_PORT10_Pos                             10
#define GPIO_PORT_PIN7_PORT10_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT10_Pos)
#define GPIO_PORT_PIN7_PORT11_Pos                             11
#define GPIO_PORT_PIN7_PORT11_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT11_Pos)
#define GPIO_PORT_PIN7_PORT12_Pos                             12
#define GPIO_PORT_PIN7_PORT12_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT12_Pos)
#define GPIO_PORT_PIN7_PORT13_Pos                             13
#define GPIO_PORT_PIN7_PORT13_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT13_Pos)
#define GPIO_PORT_PIN7_PORT14_Pos                             14
#define GPIO_PORT_PIN7_PORT14_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT14_Pos)
#define GPIO_PORT_PIN7_PORT15_Pos                             15
#define GPIO_PORT_PIN7_PORT15_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT15_Pos)
#define GPIO_PORT_PIN7_PORT16_Pos                             16
#define GPIO_PORT_PIN7_PORT16_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT16_Pos)
#define GPIO_PORT_PIN7_PORT17_Pos                             17
#define GPIO_PORT_PIN7_PORT17_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT17_Pos)
#define GPIO_PORT_PIN7_PORT18_Pos                             18
#define GPIO_PORT_PIN7_PORT18_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT18_Pos)
#define GPIO_PORT_PIN7_PORT19_Pos                             19
#define GPIO_PORT_PIN7_PORT19_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT19_Pos)
#define GPIO_PORT_PIN7_PORT20_Pos                             20
#define GPIO_PORT_PIN7_PORT20_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT20_Pos)
#define GPIO_PORT_PIN7_PORT21_Pos                             21
#define GPIO_PORT_PIN7_PORT21_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT21_Pos)
#define GPIO_PORT_PIN7_PORT22_Pos                             22
#define GPIO_PORT_PIN7_PORT22_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT22_Pos)
#define GPIO_PORT_PIN7_PORT23_Pos                             23
#define GPIO_PORT_PIN7_PORT23_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT23_Pos)
#define GPIO_PORT_PIN7_PORT24_Pos                             24
#define GPIO_PORT_PIN7_PORT24_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT24_Pos)
#define GPIO_PORT_PIN7_PORT25_Pos                             25
#define GPIO_PORT_PIN7_PORT25_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT25_Pos)
#define GPIO_PORT_PIN7_PORT26_Pos                             26
#define GPIO_PORT_PIN7_PORT26_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT26_Pos)
#define GPIO_PORT_PIN7_PORT27_Pos                             27
#define GPIO_PORT_PIN7_PORT27_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT27_Pos)
#define GPIO_PORT_PIN7_PORT28_Pos                             28
#define GPIO_PORT_PIN7_PORT28_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT28_Pos)
#define GPIO_PORT_PIN7_PORT29_Pos                             29
#define GPIO_PORT_PIN7_PORT29_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT29_Pos)
#define GPIO_PORT_PIN7_PORT30_Pos                             30
#define GPIO_PORT_PIN7_PORT30_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT30_Pos)
#define GPIO_PORT_PIN7_PORT31_Pos                             31
#define GPIO_PORT_PIN7_PORT31_Msk                             (0x01UL << GPIO_PORT_PIN7_PORT31_Pos)

// -------------------------------------  GPIO_PORT_MPIN0  ----------------------------------------
#define GPIO_PORT_MPIN0_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN0_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos)
#define GPIO_PORT_MPIN0_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN0_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos)
#define GPIO_PORT_MPIN0_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN0_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos)
#define GPIO_PORT_MPIN0_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN0_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos)
#define GPIO_PORT_MPIN0_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN0_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos)
#define GPIO_PORT_MPIN0_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN0_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos)
#define GPIO_PORT_MPIN0_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN0_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos)
#define GPIO_PORT_MPIN0_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN0_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos)
#define GPIO_PORT_MPIN0_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN0_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos)
#define GPIO_PORT_MPIN0_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN0_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos)
#define GPIO_PORT_MPIN0_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN0_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos)
#define GPIO_PORT_MPIN0_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN0_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos)
#define GPIO_PORT_MPIN0_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN0_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos)
#define GPIO_PORT_MPIN0_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN0_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos)
#define GPIO_PORT_MPIN0_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN0_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos)
#define GPIO_PORT_MPIN0_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN0_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos)
#define GPIO_PORT_MPIN0_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN0_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos)
#define GPIO_PORT_MPIN0_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN0_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos)
#define GPIO_PORT_MPIN0_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN0_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos)
#define GPIO_PORT_MPIN0_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN0_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos)
#define GPIO_PORT_MPIN0_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN0_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos)
#define GPIO_PORT_MPIN0_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN0_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos)
#define GPIO_PORT_MPIN0_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN0_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos)
#define GPIO_PORT_MPIN0_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN0_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos)
#define GPIO_PORT_MPIN0_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN0_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos)
#define GPIO_PORT_MPIN0_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN0_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos)
#define GPIO_PORT_MPIN0_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN0_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos)
#define GPIO_PORT_MPIN0_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN0_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos)
#define GPIO_PORT_MPIN0_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN0_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos)
#define GPIO_PORT_MPIN0_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN0_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos)
#define GPIO_PORT_MPIN0_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN0_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos)
#define GPIO_PORT_MPIN0_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN0_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN1  ----------------------------------------
#define GPIO_PORT_MPIN1_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN1_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos)
#define GPIO_PORT_MPIN1_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN1_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos)
#define GPIO_PORT_MPIN1_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN1_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos)
#define GPIO_PORT_MPIN1_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN1_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos)
#define GPIO_PORT_MPIN1_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN1_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos)
#define GPIO_PORT_MPIN1_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN1_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos)
#define GPIO_PORT_MPIN1_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN1_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos)
#define GPIO_PORT_MPIN1_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN1_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos)
#define GPIO_PORT_MPIN1_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN1_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos)
#define GPIO_PORT_MPIN1_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN1_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos)
#define GPIO_PORT_MPIN1_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN1_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos)
#define GPIO_PORT_MPIN1_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN1_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos)
#define GPIO_PORT_MPIN1_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN1_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos)
#define GPIO_PORT_MPIN1_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN1_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos)
#define GPIO_PORT_MPIN1_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN1_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos)
#define GPIO_PORT_MPIN1_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN1_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos)
#define GPIO_PORT_MPIN1_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN1_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos)
#define GPIO_PORT_MPIN1_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN1_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos)
#define GPIO_PORT_MPIN1_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN1_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos)
#define GPIO_PORT_MPIN1_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN1_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos)
#define GPIO_PORT_MPIN1_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN1_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos)
#define GPIO_PORT_MPIN1_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN1_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos)
#define GPIO_PORT_MPIN1_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN1_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos)
#define GPIO_PORT_MPIN1_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN1_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos)
#define GPIO_PORT_MPIN1_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN1_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos)
#define GPIO_PORT_MPIN1_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN1_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos)
#define GPIO_PORT_MPIN1_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN1_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos)
#define GPIO_PORT_MPIN1_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN1_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos)
#define GPIO_PORT_MPIN1_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN1_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos)
#define GPIO_PORT_MPIN1_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN1_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos)
#define GPIO_PORT_MPIN1_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN1_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos)
#define GPIO_PORT_MPIN1_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN1_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN2  ----------------------------------------
#define GPIO_PORT_MPIN2_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN2_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos)
#define GPIO_PORT_MPIN2_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN2_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos)
#define GPIO_PORT_MPIN2_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN2_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos)
#define GPIO_PORT_MPIN2_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN2_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos)
#define GPIO_PORT_MPIN2_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN2_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos)
#define GPIO_PORT_MPIN2_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN2_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos)
#define GPIO_PORT_MPIN2_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN2_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos)
#define GPIO_PORT_MPIN2_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN2_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos)
#define GPIO_PORT_MPIN2_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN2_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos)
#define GPIO_PORT_MPIN2_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN2_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos)
#define GPIO_PORT_MPIN2_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN2_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos)
#define GPIO_PORT_MPIN2_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN2_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos)
#define GPIO_PORT_MPIN2_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN2_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos)
#define GPIO_PORT_MPIN2_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN2_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos)
#define GPIO_PORT_MPIN2_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN2_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos)
#define GPIO_PORT_MPIN2_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN2_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos)
#define GPIO_PORT_MPIN2_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN2_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos)
#define GPIO_PORT_MPIN2_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN2_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos)
#define GPIO_PORT_MPIN2_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN2_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos)
#define GPIO_PORT_MPIN2_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN2_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos)
#define GPIO_PORT_MPIN2_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN2_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos)
#define GPIO_PORT_MPIN2_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN2_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos)
#define GPIO_PORT_MPIN2_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN2_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos)
#define GPIO_PORT_MPIN2_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN2_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos)
#define GPIO_PORT_MPIN2_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN2_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos)
#define GPIO_PORT_MPIN2_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN2_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos)
#define GPIO_PORT_MPIN2_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN2_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos)
#define GPIO_PORT_MPIN2_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN2_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos)
#define GPIO_PORT_MPIN2_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN2_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos)
#define GPIO_PORT_MPIN2_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN2_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos)
#define GPIO_PORT_MPIN2_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN2_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos)
#define GPIO_PORT_MPIN2_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN2_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN3  ----------------------------------------
#define GPIO_PORT_MPIN3_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN3_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos)
#define GPIO_PORT_MPIN3_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN3_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos)
#define GPIO_PORT_MPIN3_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN3_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos)
#define GPIO_PORT_MPIN3_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN3_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos)
#define GPIO_PORT_MPIN3_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN3_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos)
#define GPIO_PORT_MPIN3_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN3_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos)
#define GPIO_PORT_MPIN3_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN3_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos)
#define GPIO_PORT_MPIN3_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN3_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos)
#define GPIO_PORT_MPIN3_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN3_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos)
#define GPIO_PORT_MPIN3_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN3_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos)
#define GPIO_PORT_MPIN3_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN3_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos)
#define GPIO_PORT_MPIN3_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN3_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos)
#define GPIO_PORT_MPIN3_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN3_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos)
#define GPIO_PORT_MPIN3_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN3_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos)
#define GPIO_PORT_MPIN3_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN3_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos)
#define GPIO_PORT_MPIN3_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN3_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos)
#define GPIO_PORT_MPIN3_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN3_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos)
#define GPIO_PORT_MPIN3_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN3_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos)
#define GPIO_PORT_MPIN3_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN3_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos)
#define GPIO_PORT_MPIN3_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN3_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos)
#define GPIO_PORT_MPIN3_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN3_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos)
#define GPIO_PORT_MPIN3_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN3_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos)
#define GPIO_PORT_MPIN3_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN3_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos)
#define GPIO_PORT_MPIN3_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN3_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos)
#define GPIO_PORT_MPIN3_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN3_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos)
#define GPIO_PORT_MPIN3_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN3_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos)
#define GPIO_PORT_MPIN3_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN3_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos)
#define GPIO_PORT_MPIN3_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN3_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos)
#define GPIO_PORT_MPIN3_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN3_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos)
#define GPIO_PORT_MPIN3_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN3_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos)
#define GPIO_PORT_MPIN3_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN3_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos)
#define GPIO_PORT_MPIN3_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN3_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN4  ----------------------------------------
#define GPIO_PORT_MPIN4_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN4_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos)
#define GPIO_PORT_MPIN4_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN4_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos)
#define GPIO_PORT_MPIN4_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN4_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos)
#define GPIO_PORT_MPIN4_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN4_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos)
#define GPIO_PORT_MPIN4_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN4_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos)
#define GPIO_PORT_MPIN4_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN4_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos)
#define GPIO_PORT_MPIN4_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN4_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos)
#define GPIO_PORT_MPIN4_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN4_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos)
#define GPIO_PORT_MPIN4_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN4_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos)
#define GPIO_PORT_MPIN4_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN4_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos)
#define GPIO_PORT_MPIN4_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN4_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos)
#define GPIO_PORT_MPIN4_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN4_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos)
#define GPIO_PORT_MPIN4_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN4_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos)
#define GPIO_PORT_MPIN4_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN4_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos)
#define GPIO_PORT_MPIN4_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN4_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos)
#define GPIO_PORT_MPIN4_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN4_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos)
#define GPIO_PORT_MPIN4_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN4_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos)
#define GPIO_PORT_MPIN4_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN4_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos)
#define GPIO_PORT_MPIN4_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN4_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos)
#define GPIO_PORT_MPIN4_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN4_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos)
#define GPIO_PORT_MPIN4_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN4_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos)
#define GPIO_PORT_MPIN4_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN4_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos)
#define GPIO_PORT_MPIN4_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN4_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos)
#define GPIO_PORT_MPIN4_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN4_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos)
#define GPIO_PORT_MPIN4_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN4_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos)
#define GPIO_PORT_MPIN4_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN4_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos)
#define GPIO_PORT_MPIN4_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN4_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos)
#define GPIO_PORT_MPIN4_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN4_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos)
#define GPIO_PORT_MPIN4_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN4_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos)
#define GPIO_PORT_MPIN4_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN4_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos)
#define GPIO_PORT_MPIN4_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN4_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos)
#define GPIO_PORT_MPIN4_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN4_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN5  ----------------------------------------
#define GPIO_PORT_MPIN5_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN5_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos)
#define GPIO_PORT_MPIN5_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN5_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos)
#define GPIO_PORT_MPIN5_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN5_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos)
#define GPIO_PORT_MPIN5_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN5_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos)
#define GPIO_PORT_MPIN5_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN5_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos)
#define GPIO_PORT_MPIN5_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN5_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos)
#define GPIO_PORT_MPIN5_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN5_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos)
#define GPIO_PORT_MPIN5_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN5_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos)
#define GPIO_PORT_MPIN5_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN5_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos)
#define GPIO_PORT_MPIN5_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN5_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos)
#define GPIO_PORT_MPIN5_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN5_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos)
#define GPIO_PORT_MPIN5_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN5_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos)
#define GPIO_PORT_MPIN5_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN5_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos)
#define GPIO_PORT_MPIN5_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN5_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos)
#define GPIO_PORT_MPIN5_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN5_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos)
#define GPIO_PORT_MPIN5_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN5_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos)
#define GPIO_PORT_MPIN5_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN5_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos)
#define GPIO_PORT_MPIN5_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN5_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos)
#define GPIO_PORT_MPIN5_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN5_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos)
#define GPIO_PORT_MPIN5_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN5_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos)
#define GPIO_PORT_MPIN5_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN5_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos)
#define GPIO_PORT_MPIN5_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN5_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos)
#define GPIO_PORT_MPIN5_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN5_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos)
#define GPIO_PORT_MPIN5_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN5_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos)
#define GPIO_PORT_MPIN5_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN5_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos)
#define GPIO_PORT_MPIN5_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN5_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos)
#define GPIO_PORT_MPIN5_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN5_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos)
#define GPIO_PORT_MPIN5_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN5_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos)
#define GPIO_PORT_MPIN5_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN5_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos)
#define GPIO_PORT_MPIN5_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN5_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos)
#define GPIO_PORT_MPIN5_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN5_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos)
#define GPIO_PORT_MPIN5_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN5_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN6  ----------------------------------------
#define GPIO_PORT_MPIN6_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN6_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos)
#define GPIO_PORT_MPIN6_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN6_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos)
#define GPIO_PORT_MPIN6_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN6_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos)
#define GPIO_PORT_MPIN6_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN6_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos)
#define GPIO_PORT_MPIN6_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN6_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos)
#define GPIO_PORT_MPIN6_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN6_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos)
#define GPIO_PORT_MPIN6_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN6_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos)
#define GPIO_PORT_MPIN6_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN6_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos)
#define GPIO_PORT_MPIN6_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN6_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos)
#define GPIO_PORT_MPIN6_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN6_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos)
#define GPIO_PORT_MPIN6_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN6_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos)
#define GPIO_PORT_MPIN6_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN6_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos)
#define GPIO_PORT_MPIN6_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN6_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos)
#define GPIO_PORT_MPIN6_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN6_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos)
#define GPIO_PORT_MPIN6_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN6_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos)
#define GPIO_PORT_MPIN6_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN6_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos)
#define GPIO_PORT_MPIN6_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN6_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos)
#define GPIO_PORT_MPIN6_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN6_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos)
#define GPIO_PORT_MPIN6_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN6_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos)
#define GPIO_PORT_MPIN6_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN6_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos)
#define GPIO_PORT_MPIN6_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN6_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos)
#define GPIO_PORT_MPIN6_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN6_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos)
#define GPIO_PORT_MPIN6_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN6_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos)
#define GPIO_PORT_MPIN6_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN6_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos)
#define GPIO_PORT_MPIN6_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN6_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos)
#define GPIO_PORT_MPIN6_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN6_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos)
#define GPIO_PORT_MPIN6_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN6_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos)
#define GPIO_PORT_MPIN6_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN6_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos)
#define GPIO_PORT_MPIN6_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN6_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos)
#define GPIO_PORT_MPIN6_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN6_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos)
#define GPIO_PORT_MPIN6_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN6_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos)
#define GPIO_PORT_MPIN6_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN6_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_MPIN7  ----------------------------------------
#define GPIO_PORT_MPIN7_MPORTP0_Pos                           0
#define GPIO_PORT_MPIN7_MPORTP0_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos)
#define GPIO_PORT_MPIN7_MPORTP1_Pos                           1
#define GPIO_PORT_MPIN7_MPORTP1_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos)
#define GPIO_PORT_MPIN7_MPORTP2_Pos                           2
#define GPIO_PORT_MPIN7_MPORTP2_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos)
#define GPIO_PORT_MPIN7_MPORTP3_Pos                           3
#define GPIO_PORT_MPIN7_MPORTP3_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos)
#define GPIO_PORT_MPIN7_MPORTP4_Pos                           4
#define GPIO_PORT_MPIN7_MPORTP4_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos)
#define GPIO_PORT_MPIN7_MPORTP5_Pos                           5
#define GPIO_PORT_MPIN7_MPORTP5_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos)
#define GPIO_PORT_MPIN7_MPORTP6_Pos                           6
#define GPIO_PORT_MPIN7_MPORTP6_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos)
#define GPIO_PORT_MPIN7_MPORTP7_Pos                           7
#define GPIO_PORT_MPIN7_MPORTP7_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos)
#define GPIO_PORT_MPIN7_MPORTP8_Pos                           8
#define GPIO_PORT_MPIN7_MPORTP8_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos)
#define GPIO_PORT_MPIN7_MPORTP9_Pos                           9
#define GPIO_PORT_MPIN7_MPORTP9_Msk                           (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos)
#define GPIO_PORT_MPIN7_MPORTP10_Pos                          10
#define GPIO_PORT_MPIN7_MPORTP10_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos)
#define GPIO_PORT_MPIN7_MPORTP11_Pos                          11
#define GPIO_PORT_MPIN7_MPORTP11_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos)
#define GPIO_PORT_MPIN7_MPORTP12_Pos                          12
#define GPIO_PORT_MPIN7_MPORTP12_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos)
#define GPIO_PORT_MPIN7_MPORTP13_Pos                          13
#define GPIO_PORT_MPIN7_MPORTP13_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos)
#define GPIO_PORT_MPIN7_MPORTP14_Pos                          14
#define GPIO_PORT_MPIN7_MPORTP14_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos)
#define GPIO_PORT_MPIN7_MPORTP15_Pos                          15
#define GPIO_PORT_MPIN7_MPORTP15_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos)
#define GPIO_PORT_MPIN7_MPORTP16_Pos                          16
#define GPIO_PORT_MPIN7_MPORTP16_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos)
#define GPIO_PORT_MPIN7_MPORTP17_Pos                          17
#define GPIO_PORT_MPIN7_MPORTP17_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos)
#define GPIO_PORT_MPIN7_MPORTP18_Pos                          18
#define GPIO_PORT_MPIN7_MPORTP18_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos)
#define GPIO_PORT_MPIN7_MPORTP19_Pos                          19
#define GPIO_PORT_MPIN7_MPORTP19_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos)
#define GPIO_PORT_MPIN7_MPORTP20_Pos                          20
#define GPIO_PORT_MPIN7_MPORTP20_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos)
#define GPIO_PORT_MPIN7_MPORTP21_Pos                          21
#define GPIO_PORT_MPIN7_MPORTP21_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos)
#define GPIO_PORT_MPIN7_MPORTP22_Pos                          22
#define GPIO_PORT_MPIN7_MPORTP22_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos)
#define GPIO_PORT_MPIN7_MPORTP23_Pos                          23
#define GPIO_PORT_MPIN7_MPORTP23_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos)
#define GPIO_PORT_MPIN7_MPORTP24_Pos                          24
#define GPIO_PORT_MPIN7_MPORTP24_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos)
#define GPIO_PORT_MPIN7_MPORTP25_Pos                          25
#define GPIO_PORT_MPIN7_MPORTP25_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos)
#define GPIO_PORT_MPIN7_MPORTP26_Pos                          26
#define GPIO_PORT_MPIN7_MPORTP26_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos)
#define GPIO_PORT_MPIN7_MPORTP27_Pos                          27
#define GPIO_PORT_MPIN7_MPORTP27_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos)
#define GPIO_PORT_MPIN7_MPORTP28_Pos                          28
#define GPIO_PORT_MPIN7_MPORTP28_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos)
#define GPIO_PORT_MPIN7_MPORTP29_Pos                          29
#define GPIO_PORT_MPIN7_MPORTP29_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos)
#define GPIO_PORT_MPIN7_MPORTP30_Pos                          30
#define GPIO_PORT_MPIN7_MPORTP30_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos)
#define GPIO_PORT_MPIN7_MPORTP31_Pos                          31
#define GPIO_PORT_MPIN7_MPORTP31_Msk                          (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos)

// -------------------------------------  GPIO_PORT_SET0  -----------------------------------------
#define GPIO_PORT_SET0_SETP0_Pos                              0
#define GPIO_PORT_SET0_SETP0_Msk                              (0x01UL << GPIO_PORT_SET0_SETP0_Pos)
#define GPIO_PORT_SET0_SETP1_Pos                              1
#define GPIO_PORT_SET0_SETP1_Msk                              (0x01UL << GPIO_PORT_SET0_SETP1_Pos)
#define GPIO_PORT_SET0_SETP2_Pos                              2
#define GPIO_PORT_SET0_SETP2_Msk                              (0x01UL << GPIO_PORT_SET0_SETP2_Pos)
#define GPIO_PORT_SET0_SETP3_Pos                              3
#define GPIO_PORT_SET0_SETP3_Msk                              (0x01UL << GPIO_PORT_SET0_SETP3_Pos)
#define GPIO_PORT_SET0_SETP4_Pos                              4
#define GPIO_PORT_SET0_SETP4_Msk                              (0x01UL << GPIO_PORT_SET0_SETP4_Pos)
#define GPIO_PORT_SET0_SETP5_Pos                              5
#define GPIO_PORT_SET0_SETP5_Msk                              (0x01UL << GPIO_PORT_SET0_SETP5_Pos)
#define GPIO_PORT_SET0_SETP6_Pos                              6
#define GPIO_PORT_SET0_SETP6_Msk                              (0x01UL << GPIO_PORT_SET0_SETP6_Pos)
#define GPIO_PORT_SET0_SETP7_Pos                              7
#define GPIO_PORT_SET0_SETP7_Msk                              (0x01UL << GPIO_PORT_SET0_SETP7_Pos)
#define GPIO_PORT_SET0_SETP8_Pos                              8
#define GPIO_PORT_SET0_SETP8_Msk                              (0x01UL << GPIO_PORT_SET0_SETP8_Pos)
#define GPIO_PORT_SET0_SETP9_Pos                              9
#define GPIO_PORT_SET0_SETP9_Msk                              (0x01UL << GPIO_PORT_SET0_SETP9_Pos)
#define GPIO_PORT_SET0_SETP10_Pos                             10
#define GPIO_PORT_SET0_SETP10_Msk                             (0x01UL << GPIO_PORT_SET0_SETP10_Pos)
#define GPIO_PORT_SET0_SETP11_Pos                             11
#define GPIO_PORT_SET0_SETP11_Msk                             (0x01UL << GPIO_PORT_SET0_SETP11_Pos)
#define GPIO_PORT_SET0_SETP12_Pos                             12
#define GPIO_PORT_SET0_SETP12_Msk                             (0x01UL << GPIO_PORT_SET0_SETP12_Pos)
#define GPIO_PORT_SET0_SETP13_Pos                             13
#define GPIO_PORT_SET0_SETP13_Msk                             (0x01UL << GPIO_PORT_SET0_SETP13_Pos)
#define GPIO_PORT_SET0_SETP14_Pos                             14
#define GPIO_PORT_SET0_SETP14_Msk                             (0x01UL << GPIO_PORT_SET0_SETP14_Pos)
#define GPIO_PORT_SET0_SETP15_Pos                             15
#define GPIO_PORT_SET0_SETP15_Msk                             (0x01UL << GPIO_PORT_SET0_SETP15_Pos)
#define GPIO_PORT_SET0_SETP16_Pos                             16
#define GPIO_PORT_SET0_SETP16_Msk                             (0x01UL << GPIO_PORT_SET0_SETP16_Pos)
#define GPIO_PORT_SET0_SETP17_Pos                             17
#define GPIO_PORT_SET0_SETP17_Msk                             (0x01UL << GPIO_PORT_SET0_SETP17_Pos)
#define GPIO_PORT_SET0_SETP18_Pos                             18
#define GPIO_PORT_SET0_SETP18_Msk                             (0x01UL << GPIO_PORT_SET0_SETP18_Pos)
#define GPIO_PORT_SET0_SETP19_Pos                             19
#define GPIO_PORT_SET0_SETP19_Msk                             (0x01UL << GPIO_PORT_SET0_SETP19_Pos)
#define GPIO_PORT_SET0_SETP20_Pos                             20
#define GPIO_PORT_SET0_SETP20_Msk                             (0x01UL << GPIO_PORT_SET0_SETP20_Pos)
#define GPIO_PORT_SET0_SETP21_Pos                             21
#define GPIO_PORT_SET0_SETP21_Msk                             (0x01UL << GPIO_PORT_SET0_SETP21_Pos)
#define GPIO_PORT_SET0_SETP22_Pos                             22
#define GPIO_PORT_SET0_SETP22_Msk                             (0x01UL << GPIO_PORT_SET0_SETP22_Pos)
#define GPIO_PORT_SET0_SETP23_Pos                             23
#define GPIO_PORT_SET0_SETP23_Msk                             (0x01UL << GPIO_PORT_SET0_SETP23_Pos)
#define GPIO_PORT_SET0_SETP24_Pos                             24
#define GPIO_PORT_SET0_SETP24_Msk                             (0x01UL << GPIO_PORT_SET0_SETP24_Pos)
#define GPIO_PORT_SET0_SETP25_Pos                             25
#define GPIO_PORT_SET0_SETP25_Msk                             (0x01UL << GPIO_PORT_SET0_SETP25_Pos)
#define GPIO_PORT_SET0_SETP26_Pos                             26
#define GPIO_PORT_SET0_SETP26_Msk                             (0x01UL << GPIO_PORT_SET0_SETP26_Pos)
#define GPIO_PORT_SET0_SETP27_Pos                             27
#define GPIO_PORT_SET0_SETP27_Msk                             (0x01UL << GPIO_PORT_SET0_SETP27_Pos)
#define GPIO_PORT_SET0_SETP28_Pos                             28
#define GPIO_PORT_SET0_SETP28_Msk                             (0x01UL << GPIO_PORT_SET0_SETP28_Pos)
#define GPIO_PORT_SET0_SETP29_Pos                             29
#define GPIO_PORT_SET0_SETP29_Msk                             (0x01UL << GPIO_PORT_SET0_SETP29_Pos)
#define GPIO_PORT_SET0_SETP30_Pos                             30
#define GPIO_PORT_SET0_SETP30_Msk                             (0x01UL << GPIO_PORT_SET0_SETP30_Pos)
#define GPIO_PORT_SET0_SETP31_Pos                             31
#define GPIO_PORT_SET0_SETP31_Msk                             (0x01UL << GPIO_PORT_SET0_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET1  -----------------------------------------
#define GPIO_PORT_SET1_SETP0_Pos                              0
#define GPIO_PORT_SET1_SETP0_Msk                              (0x01UL << GPIO_PORT_SET1_SETP0_Pos)
#define GPIO_PORT_SET1_SETP1_Pos                              1
#define GPIO_PORT_SET1_SETP1_Msk                              (0x01UL << GPIO_PORT_SET1_SETP1_Pos)
#define GPIO_PORT_SET1_SETP2_Pos                              2
#define GPIO_PORT_SET1_SETP2_Msk                              (0x01UL << GPIO_PORT_SET1_SETP2_Pos)
#define GPIO_PORT_SET1_SETP3_Pos                              3
#define GPIO_PORT_SET1_SETP3_Msk                              (0x01UL << GPIO_PORT_SET1_SETP3_Pos)
#define GPIO_PORT_SET1_SETP4_Pos                              4
#define GPIO_PORT_SET1_SETP4_Msk                              (0x01UL << GPIO_PORT_SET1_SETP4_Pos)
#define GPIO_PORT_SET1_SETP5_Pos                              5
#define GPIO_PORT_SET1_SETP5_Msk                              (0x01UL << GPIO_PORT_SET1_SETP5_Pos)
#define GPIO_PORT_SET1_SETP6_Pos                              6
#define GPIO_PORT_SET1_SETP6_Msk                              (0x01UL << GPIO_PORT_SET1_SETP6_Pos)
#define GPIO_PORT_SET1_SETP7_Pos                              7
#define GPIO_PORT_SET1_SETP7_Msk                              (0x01UL << GPIO_PORT_SET1_SETP7_Pos)
#define GPIO_PORT_SET1_SETP8_Pos                              8
#define GPIO_PORT_SET1_SETP8_Msk                              (0x01UL << GPIO_PORT_SET1_SETP8_Pos)
#define GPIO_PORT_SET1_SETP9_Pos                              9
#define GPIO_PORT_SET1_SETP9_Msk                              (0x01UL << GPIO_PORT_SET1_SETP9_Pos)
#define GPIO_PORT_SET1_SETP10_Pos                             10
#define GPIO_PORT_SET1_SETP10_Msk                             (0x01UL << GPIO_PORT_SET1_SETP10_Pos)
#define GPIO_PORT_SET1_SETP11_Pos                             11
#define GPIO_PORT_SET1_SETP11_Msk                             (0x01UL << GPIO_PORT_SET1_SETP11_Pos)
#define GPIO_PORT_SET1_SETP12_Pos                             12
#define GPIO_PORT_SET1_SETP12_Msk                             (0x01UL << GPIO_PORT_SET1_SETP12_Pos)
#define GPIO_PORT_SET1_SETP13_Pos                             13
#define GPIO_PORT_SET1_SETP13_Msk                             (0x01UL << GPIO_PORT_SET1_SETP13_Pos)
#define GPIO_PORT_SET1_SETP14_Pos                             14
#define GPIO_PORT_SET1_SETP14_Msk                             (0x01UL << GPIO_PORT_SET1_SETP14_Pos)
#define GPIO_PORT_SET1_SETP15_Pos                             15
#define GPIO_PORT_SET1_SETP15_Msk                             (0x01UL << GPIO_PORT_SET1_SETP15_Pos)
#define GPIO_PORT_SET1_SETP16_Pos                             16
#define GPIO_PORT_SET1_SETP16_Msk                             (0x01UL << GPIO_PORT_SET1_SETP16_Pos)
#define GPIO_PORT_SET1_SETP17_Pos                             17
#define GPIO_PORT_SET1_SETP17_Msk                             (0x01UL << GPIO_PORT_SET1_SETP17_Pos)
#define GPIO_PORT_SET1_SETP18_Pos                             18
#define GPIO_PORT_SET1_SETP18_Msk                             (0x01UL << GPIO_PORT_SET1_SETP18_Pos)
#define GPIO_PORT_SET1_SETP19_Pos                             19
#define GPIO_PORT_SET1_SETP19_Msk                             (0x01UL << GPIO_PORT_SET1_SETP19_Pos)
#define GPIO_PORT_SET1_SETP20_Pos                             20
#define GPIO_PORT_SET1_SETP20_Msk                             (0x01UL << GPIO_PORT_SET1_SETP20_Pos)
#define GPIO_PORT_SET1_SETP21_Pos                             21
#define GPIO_PORT_SET1_SETP21_Msk                             (0x01UL << GPIO_PORT_SET1_SETP21_Pos)
#define GPIO_PORT_SET1_SETP22_Pos                             22
#define GPIO_PORT_SET1_SETP22_Msk                             (0x01UL << GPIO_PORT_SET1_SETP22_Pos)
#define GPIO_PORT_SET1_SETP23_Pos                             23
#define GPIO_PORT_SET1_SETP23_Msk                             (0x01UL << GPIO_PORT_SET1_SETP23_Pos)
#define GPIO_PORT_SET1_SETP24_Pos                             24
#define GPIO_PORT_SET1_SETP24_Msk                             (0x01UL << GPIO_PORT_SET1_SETP24_Pos)
#define GPIO_PORT_SET1_SETP25_Pos                             25
#define GPIO_PORT_SET1_SETP25_Msk                             (0x01UL << GPIO_PORT_SET1_SETP25_Pos)
#define GPIO_PORT_SET1_SETP26_Pos                             26
#define GPIO_PORT_SET1_SETP26_Msk                             (0x01UL << GPIO_PORT_SET1_SETP26_Pos)
#define GPIO_PORT_SET1_SETP27_Pos                             27
#define GPIO_PORT_SET1_SETP27_Msk                             (0x01UL << GPIO_PORT_SET1_SETP27_Pos)
#define GPIO_PORT_SET1_SETP28_Pos                             28
#define GPIO_PORT_SET1_SETP28_Msk                             (0x01UL << GPIO_PORT_SET1_SETP28_Pos)
#define GPIO_PORT_SET1_SETP29_Pos                             29
#define GPIO_PORT_SET1_SETP29_Msk                             (0x01UL << GPIO_PORT_SET1_SETP29_Pos)
#define GPIO_PORT_SET1_SETP30_Pos                             30
#define GPIO_PORT_SET1_SETP30_Msk                             (0x01UL << GPIO_PORT_SET1_SETP30_Pos)
#define GPIO_PORT_SET1_SETP31_Pos                             31
#define GPIO_PORT_SET1_SETP31_Msk                             (0x01UL << GPIO_PORT_SET1_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET2  -----------------------------------------
#define GPIO_PORT_SET2_SETP0_Pos                              0
#define GPIO_PORT_SET2_SETP0_Msk                              (0x01UL << GPIO_PORT_SET2_SETP0_Pos)
#define GPIO_PORT_SET2_SETP1_Pos                              1
#define GPIO_PORT_SET2_SETP1_Msk                              (0x01UL << GPIO_PORT_SET2_SETP1_Pos)
#define GPIO_PORT_SET2_SETP2_Pos                              2
#define GPIO_PORT_SET2_SETP2_Msk                              (0x01UL << GPIO_PORT_SET2_SETP2_Pos)
#define GPIO_PORT_SET2_SETP3_Pos                              3
#define GPIO_PORT_SET2_SETP3_Msk                              (0x01UL << GPIO_PORT_SET2_SETP3_Pos)
#define GPIO_PORT_SET2_SETP4_Pos                              4
#define GPIO_PORT_SET2_SETP4_Msk                              (0x01UL << GPIO_PORT_SET2_SETP4_Pos)
#define GPIO_PORT_SET2_SETP5_Pos                              5
#define GPIO_PORT_SET2_SETP5_Msk                              (0x01UL << GPIO_PORT_SET2_SETP5_Pos)
#define GPIO_PORT_SET2_SETP6_Pos                              6
#define GPIO_PORT_SET2_SETP6_Msk                              (0x01UL << GPIO_PORT_SET2_SETP6_Pos)
#define GPIO_PORT_SET2_SETP7_Pos                              7
#define GPIO_PORT_SET2_SETP7_Msk                              (0x01UL << GPIO_PORT_SET2_SETP7_Pos)
#define GPIO_PORT_SET2_SETP8_Pos                              8
#define GPIO_PORT_SET2_SETP8_Msk                              (0x01UL << GPIO_PORT_SET2_SETP8_Pos)
#define GPIO_PORT_SET2_SETP9_Pos                              9
#define GPIO_PORT_SET2_SETP9_Msk                              (0x01UL << GPIO_PORT_SET2_SETP9_Pos)
#define GPIO_PORT_SET2_SETP10_Pos                             10
#define GPIO_PORT_SET2_SETP10_Msk                             (0x01UL << GPIO_PORT_SET2_SETP10_Pos)
#define GPIO_PORT_SET2_SETP11_Pos                             11
#define GPIO_PORT_SET2_SETP11_Msk                             (0x01UL << GPIO_PORT_SET2_SETP11_Pos)
#define GPIO_PORT_SET2_SETP12_Pos                             12
#define GPIO_PORT_SET2_SETP12_Msk                             (0x01UL << GPIO_PORT_SET2_SETP12_Pos)
#define GPIO_PORT_SET2_SETP13_Pos                             13
#define GPIO_PORT_SET2_SETP13_Msk                             (0x01UL << GPIO_PORT_SET2_SETP13_Pos)
#define GPIO_PORT_SET2_SETP14_Pos                             14
#define GPIO_PORT_SET2_SETP14_Msk                             (0x01UL << GPIO_PORT_SET2_SETP14_Pos)
#define GPIO_PORT_SET2_SETP15_Pos                             15
#define GPIO_PORT_SET2_SETP15_Msk                             (0x01UL << GPIO_PORT_SET2_SETP15_Pos)
#define GPIO_PORT_SET2_SETP16_Pos                             16
#define GPIO_PORT_SET2_SETP16_Msk                             (0x01UL << GPIO_PORT_SET2_SETP16_Pos)
#define GPIO_PORT_SET2_SETP17_Pos                             17
#define GPIO_PORT_SET2_SETP17_Msk                             (0x01UL << GPIO_PORT_SET2_SETP17_Pos)
#define GPIO_PORT_SET2_SETP18_Pos                             18
#define GPIO_PORT_SET2_SETP18_Msk                             (0x01UL << GPIO_PORT_SET2_SETP18_Pos)
#define GPIO_PORT_SET2_SETP19_Pos                             19
#define GPIO_PORT_SET2_SETP19_Msk                             (0x01UL << GPIO_PORT_SET2_SETP19_Pos)
#define GPIO_PORT_SET2_SETP20_Pos                             20
#define GPIO_PORT_SET2_SETP20_Msk                             (0x01UL << GPIO_PORT_SET2_SETP20_Pos)
#define GPIO_PORT_SET2_SETP21_Pos                             21
#define GPIO_PORT_SET2_SETP21_Msk                             (0x01UL << GPIO_PORT_SET2_SETP21_Pos)
#define GPIO_PORT_SET2_SETP22_Pos                             22
#define GPIO_PORT_SET2_SETP22_Msk                             (0x01UL << GPIO_PORT_SET2_SETP22_Pos)
#define GPIO_PORT_SET2_SETP23_Pos                             23
#define GPIO_PORT_SET2_SETP23_Msk                             (0x01UL << GPIO_PORT_SET2_SETP23_Pos)
#define GPIO_PORT_SET2_SETP24_Pos                             24
#define GPIO_PORT_SET2_SETP24_Msk                             (0x01UL << GPIO_PORT_SET2_SETP24_Pos)
#define GPIO_PORT_SET2_SETP25_Pos                             25
#define GPIO_PORT_SET2_SETP25_Msk                             (0x01UL << GPIO_PORT_SET2_SETP25_Pos)
#define GPIO_PORT_SET2_SETP26_Pos                             26
#define GPIO_PORT_SET2_SETP26_Msk                             (0x01UL << GPIO_PORT_SET2_SETP26_Pos)
#define GPIO_PORT_SET2_SETP27_Pos                             27
#define GPIO_PORT_SET2_SETP27_Msk                             (0x01UL << GPIO_PORT_SET2_SETP27_Pos)
#define GPIO_PORT_SET2_SETP28_Pos                             28
#define GPIO_PORT_SET2_SETP28_Msk                             (0x01UL << GPIO_PORT_SET2_SETP28_Pos)
#define GPIO_PORT_SET2_SETP29_Pos                             29
#define GPIO_PORT_SET2_SETP29_Msk                             (0x01UL << GPIO_PORT_SET2_SETP29_Pos)
#define GPIO_PORT_SET2_SETP30_Pos                             30
#define GPIO_PORT_SET2_SETP30_Msk                             (0x01UL << GPIO_PORT_SET2_SETP30_Pos)
#define GPIO_PORT_SET2_SETP31_Pos                             31
#define GPIO_PORT_SET2_SETP31_Msk                             (0x01UL << GPIO_PORT_SET2_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET3  -----------------------------------------
#define GPIO_PORT_SET3_SETP0_Pos                              0
#define GPIO_PORT_SET3_SETP0_Msk                              (0x01UL << GPIO_PORT_SET3_SETP0_Pos)
#define GPIO_PORT_SET3_SETP1_Pos                              1
#define GPIO_PORT_SET3_SETP1_Msk                              (0x01UL << GPIO_PORT_SET3_SETP1_Pos)
#define GPIO_PORT_SET3_SETP2_Pos                              2
#define GPIO_PORT_SET3_SETP2_Msk                              (0x01UL << GPIO_PORT_SET3_SETP2_Pos)
#define GPIO_PORT_SET3_SETP3_Pos                              3
#define GPIO_PORT_SET3_SETP3_Msk                              (0x01UL << GPIO_PORT_SET3_SETP3_Pos)
#define GPIO_PORT_SET3_SETP4_Pos                              4
#define GPIO_PORT_SET3_SETP4_Msk                              (0x01UL << GPIO_PORT_SET3_SETP4_Pos)
#define GPIO_PORT_SET3_SETP5_Pos                              5
#define GPIO_PORT_SET3_SETP5_Msk                              (0x01UL << GPIO_PORT_SET3_SETP5_Pos)
#define GPIO_PORT_SET3_SETP6_Pos                              6
#define GPIO_PORT_SET3_SETP6_Msk                              (0x01UL << GPIO_PORT_SET3_SETP6_Pos)
#define GPIO_PORT_SET3_SETP7_Pos                              7
#define GPIO_PORT_SET3_SETP7_Msk                              (0x01UL << GPIO_PORT_SET3_SETP7_Pos)
#define GPIO_PORT_SET3_SETP8_Pos                              8
#define GPIO_PORT_SET3_SETP8_Msk                              (0x01UL << GPIO_PORT_SET3_SETP8_Pos)
#define GPIO_PORT_SET3_SETP9_Pos                              9
#define GPIO_PORT_SET3_SETP9_Msk                              (0x01UL << GPIO_PORT_SET3_SETP9_Pos)
#define GPIO_PORT_SET3_SETP10_Pos                             10
#define GPIO_PORT_SET3_SETP10_Msk                             (0x01UL << GPIO_PORT_SET3_SETP10_Pos)
#define GPIO_PORT_SET3_SETP11_Pos                             11
#define GPIO_PORT_SET3_SETP11_Msk                             (0x01UL << GPIO_PORT_SET3_SETP11_Pos)
#define GPIO_PORT_SET3_SETP12_Pos                             12
#define GPIO_PORT_SET3_SETP12_Msk                             (0x01UL << GPIO_PORT_SET3_SETP12_Pos)
#define GPIO_PORT_SET3_SETP13_Pos                             13
#define GPIO_PORT_SET3_SETP13_Msk                             (0x01UL << GPIO_PORT_SET3_SETP13_Pos)
#define GPIO_PORT_SET3_SETP14_Pos                             14
#define GPIO_PORT_SET3_SETP14_Msk                             (0x01UL << GPIO_PORT_SET3_SETP14_Pos)
#define GPIO_PORT_SET3_SETP15_Pos                             15
#define GPIO_PORT_SET3_SETP15_Msk                             (0x01UL << GPIO_PORT_SET3_SETP15_Pos)
#define GPIO_PORT_SET3_SETP16_Pos                             16
#define GPIO_PORT_SET3_SETP16_Msk                             (0x01UL << GPIO_PORT_SET3_SETP16_Pos)
#define GPIO_PORT_SET3_SETP17_Pos                             17
#define GPIO_PORT_SET3_SETP17_Msk                             (0x01UL << GPIO_PORT_SET3_SETP17_Pos)
#define GPIO_PORT_SET3_SETP18_Pos                             18
#define GPIO_PORT_SET3_SETP18_Msk                             (0x01UL << GPIO_PORT_SET3_SETP18_Pos)
#define GPIO_PORT_SET3_SETP19_Pos                             19
#define GPIO_PORT_SET3_SETP19_Msk                             (0x01UL << GPIO_PORT_SET3_SETP19_Pos)
#define GPIO_PORT_SET3_SETP20_Pos                             20
#define GPIO_PORT_SET3_SETP20_Msk                             (0x01UL << GPIO_PORT_SET3_SETP20_Pos)
#define GPIO_PORT_SET3_SETP21_Pos                             21
#define GPIO_PORT_SET3_SETP21_Msk                             (0x01UL << GPIO_PORT_SET3_SETP21_Pos)
#define GPIO_PORT_SET3_SETP22_Pos                             22
#define GPIO_PORT_SET3_SETP22_Msk                             (0x01UL << GPIO_PORT_SET3_SETP22_Pos)
#define GPIO_PORT_SET3_SETP23_Pos                             23
#define GPIO_PORT_SET3_SETP23_Msk                             (0x01UL << GPIO_PORT_SET3_SETP23_Pos)
#define GPIO_PORT_SET3_SETP24_Pos                             24
#define GPIO_PORT_SET3_SETP24_Msk                             (0x01UL << GPIO_PORT_SET3_SETP24_Pos)
#define GPIO_PORT_SET3_SETP25_Pos                             25
#define GPIO_PORT_SET3_SETP25_Msk                             (0x01UL << GPIO_PORT_SET3_SETP25_Pos)
#define GPIO_PORT_SET3_SETP26_Pos                             26
#define GPIO_PORT_SET3_SETP26_Msk                             (0x01UL << GPIO_PORT_SET3_SETP26_Pos)
#define GPIO_PORT_SET3_SETP27_Pos                             27
#define GPIO_PORT_SET3_SETP27_Msk                             (0x01UL << GPIO_PORT_SET3_SETP27_Pos)
#define GPIO_PORT_SET3_SETP28_Pos                             28
#define GPIO_PORT_SET3_SETP28_Msk                             (0x01UL << GPIO_PORT_SET3_SETP28_Pos)
#define GPIO_PORT_SET3_SETP29_Pos                             29
#define GPIO_PORT_SET3_SETP29_Msk                             (0x01UL << GPIO_PORT_SET3_SETP29_Pos)
#define GPIO_PORT_SET3_SETP30_Pos                             30
#define GPIO_PORT_SET3_SETP30_Msk                             (0x01UL << GPIO_PORT_SET3_SETP30_Pos)
#define GPIO_PORT_SET3_SETP31_Pos                             31
#define GPIO_PORT_SET3_SETP31_Msk                             (0x01UL << GPIO_PORT_SET3_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET4  -----------------------------------------
#define GPIO_PORT_SET4_SETP0_Pos                              0
#define GPIO_PORT_SET4_SETP0_Msk                              (0x01UL << GPIO_PORT_SET4_SETP0_Pos)
#define GPIO_PORT_SET4_SETP1_Pos                              1
#define GPIO_PORT_SET4_SETP1_Msk                              (0x01UL << GPIO_PORT_SET4_SETP1_Pos)
#define GPIO_PORT_SET4_SETP2_Pos                              2
#define GPIO_PORT_SET4_SETP2_Msk                              (0x01UL << GPIO_PORT_SET4_SETP2_Pos)
#define GPIO_PORT_SET4_SETP3_Pos                              3
#define GPIO_PORT_SET4_SETP3_Msk                              (0x01UL << GPIO_PORT_SET4_SETP3_Pos)
#define GPIO_PORT_SET4_SETP4_Pos                              4
#define GPIO_PORT_SET4_SETP4_Msk                              (0x01UL << GPIO_PORT_SET4_SETP4_Pos)
#define GPIO_PORT_SET4_SETP5_Pos                              5
#define GPIO_PORT_SET4_SETP5_Msk                              (0x01UL << GPIO_PORT_SET4_SETP5_Pos)
#define GPIO_PORT_SET4_SETP6_Pos                              6
#define GPIO_PORT_SET4_SETP6_Msk                              (0x01UL << GPIO_PORT_SET4_SETP6_Pos)
#define GPIO_PORT_SET4_SETP7_Pos                              7
#define GPIO_PORT_SET4_SETP7_Msk                              (0x01UL << GPIO_PORT_SET4_SETP7_Pos)
#define GPIO_PORT_SET4_SETP8_Pos                              8
#define GPIO_PORT_SET4_SETP8_Msk                              (0x01UL << GPIO_PORT_SET4_SETP8_Pos)
#define GPIO_PORT_SET4_SETP9_Pos                              9
#define GPIO_PORT_SET4_SETP9_Msk                              (0x01UL << GPIO_PORT_SET4_SETP9_Pos)
#define GPIO_PORT_SET4_SETP10_Pos                             10
#define GPIO_PORT_SET4_SETP10_Msk                             (0x01UL << GPIO_PORT_SET4_SETP10_Pos)
#define GPIO_PORT_SET4_SETP11_Pos                             11
#define GPIO_PORT_SET4_SETP11_Msk                             (0x01UL << GPIO_PORT_SET4_SETP11_Pos)
#define GPIO_PORT_SET4_SETP12_Pos                             12
#define GPIO_PORT_SET4_SETP12_Msk                             (0x01UL << GPIO_PORT_SET4_SETP12_Pos)
#define GPIO_PORT_SET4_SETP13_Pos                             13
#define GPIO_PORT_SET4_SETP13_Msk                             (0x01UL << GPIO_PORT_SET4_SETP13_Pos)
#define GPIO_PORT_SET4_SETP14_Pos                             14
#define GPIO_PORT_SET4_SETP14_Msk                             (0x01UL << GPIO_PORT_SET4_SETP14_Pos)
#define GPIO_PORT_SET4_SETP15_Pos                             15
#define GPIO_PORT_SET4_SETP15_Msk                             (0x01UL << GPIO_PORT_SET4_SETP15_Pos)
#define GPIO_PORT_SET4_SETP16_Pos                             16
#define GPIO_PORT_SET4_SETP16_Msk                             (0x01UL << GPIO_PORT_SET4_SETP16_Pos)
#define GPIO_PORT_SET4_SETP17_Pos                             17
#define GPIO_PORT_SET4_SETP17_Msk                             (0x01UL << GPIO_PORT_SET4_SETP17_Pos)
#define GPIO_PORT_SET4_SETP18_Pos                             18
#define GPIO_PORT_SET4_SETP18_Msk                             (0x01UL << GPIO_PORT_SET4_SETP18_Pos)
#define GPIO_PORT_SET4_SETP19_Pos                             19
#define GPIO_PORT_SET4_SETP19_Msk                             (0x01UL << GPIO_PORT_SET4_SETP19_Pos)
#define GPIO_PORT_SET4_SETP20_Pos                             20
#define GPIO_PORT_SET4_SETP20_Msk                             (0x01UL << GPIO_PORT_SET4_SETP20_Pos)
#define GPIO_PORT_SET4_SETP21_Pos                             21
#define GPIO_PORT_SET4_SETP21_Msk                             (0x01UL << GPIO_PORT_SET4_SETP21_Pos)
#define GPIO_PORT_SET4_SETP22_Pos                             22
#define GPIO_PORT_SET4_SETP22_Msk                             (0x01UL << GPIO_PORT_SET4_SETP22_Pos)
#define GPIO_PORT_SET4_SETP23_Pos                             23
#define GPIO_PORT_SET4_SETP23_Msk                             (0x01UL << GPIO_PORT_SET4_SETP23_Pos)
#define GPIO_PORT_SET4_SETP24_Pos                             24
#define GPIO_PORT_SET4_SETP24_Msk                             (0x01UL << GPIO_PORT_SET4_SETP24_Pos)
#define GPIO_PORT_SET4_SETP25_Pos                             25
#define GPIO_PORT_SET4_SETP25_Msk                             (0x01UL << GPIO_PORT_SET4_SETP25_Pos)
#define GPIO_PORT_SET4_SETP26_Pos                             26
#define GPIO_PORT_SET4_SETP26_Msk                             (0x01UL << GPIO_PORT_SET4_SETP26_Pos)
#define GPIO_PORT_SET4_SETP27_Pos                             27
#define GPIO_PORT_SET4_SETP27_Msk                             (0x01UL << GPIO_PORT_SET4_SETP27_Pos)
#define GPIO_PORT_SET4_SETP28_Pos                             28
#define GPIO_PORT_SET4_SETP28_Msk                             (0x01UL << GPIO_PORT_SET4_SETP28_Pos)
#define GPIO_PORT_SET4_SETP29_Pos                             29
#define GPIO_PORT_SET4_SETP29_Msk                             (0x01UL << GPIO_PORT_SET4_SETP29_Pos)
#define GPIO_PORT_SET4_SETP30_Pos                             30
#define GPIO_PORT_SET4_SETP30_Msk                             (0x01UL << GPIO_PORT_SET4_SETP30_Pos)
#define GPIO_PORT_SET4_SETP31_Pos                             31
#define GPIO_PORT_SET4_SETP31_Msk                             (0x01UL << GPIO_PORT_SET4_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET5  -----------------------------------------
#define GPIO_PORT_SET5_SETP0_Pos                              0
#define GPIO_PORT_SET5_SETP0_Msk                              (0x01UL << GPIO_PORT_SET5_SETP0_Pos)
#define GPIO_PORT_SET5_SETP1_Pos                              1
#define GPIO_PORT_SET5_SETP1_Msk                              (0x01UL << GPIO_PORT_SET5_SETP1_Pos)
#define GPIO_PORT_SET5_SETP2_Pos                              2
#define GPIO_PORT_SET5_SETP2_Msk                              (0x01UL << GPIO_PORT_SET5_SETP2_Pos)
#define GPIO_PORT_SET5_SETP3_Pos                              3
#define GPIO_PORT_SET5_SETP3_Msk                              (0x01UL << GPIO_PORT_SET5_SETP3_Pos)
#define GPIO_PORT_SET5_SETP4_Pos                              4
#define GPIO_PORT_SET5_SETP4_Msk                              (0x01UL << GPIO_PORT_SET5_SETP4_Pos)
#define GPIO_PORT_SET5_SETP5_Pos                              5
#define GPIO_PORT_SET5_SETP5_Msk                              (0x01UL << GPIO_PORT_SET5_SETP5_Pos)
#define GPIO_PORT_SET5_SETP6_Pos                              6
#define GPIO_PORT_SET5_SETP6_Msk                              (0x01UL << GPIO_PORT_SET5_SETP6_Pos)
#define GPIO_PORT_SET5_SETP7_Pos                              7
#define GPIO_PORT_SET5_SETP7_Msk                              (0x01UL << GPIO_PORT_SET5_SETP7_Pos)
#define GPIO_PORT_SET5_SETP8_Pos                              8
#define GPIO_PORT_SET5_SETP8_Msk                              (0x01UL << GPIO_PORT_SET5_SETP8_Pos)
#define GPIO_PORT_SET5_SETP9_Pos                              9
#define GPIO_PORT_SET5_SETP9_Msk                              (0x01UL << GPIO_PORT_SET5_SETP9_Pos)
#define GPIO_PORT_SET5_SETP10_Pos                             10
#define GPIO_PORT_SET5_SETP10_Msk                             (0x01UL << GPIO_PORT_SET5_SETP10_Pos)
#define GPIO_PORT_SET5_SETP11_Pos                             11
#define GPIO_PORT_SET5_SETP11_Msk                             (0x01UL << GPIO_PORT_SET5_SETP11_Pos)
#define GPIO_PORT_SET5_SETP12_Pos                             12
#define GPIO_PORT_SET5_SETP12_Msk                             (0x01UL << GPIO_PORT_SET5_SETP12_Pos)
#define GPIO_PORT_SET5_SETP13_Pos                             13
#define GPIO_PORT_SET5_SETP13_Msk                             (0x01UL << GPIO_PORT_SET5_SETP13_Pos)
#define GPIO_PORT_SET5_SETP14_Pos                             14
#define GPIO_PORT_SET5_SETP14_Msk                             (0x01UL << GPIO_PORT_SET5_SETP14_Pos)
#define GPIO_PORT_SET5_SETP15_Pos                             15
#define GPIO_PORT_SET5_SETP15_Msk                             (0x01UL << GPIO_PORT_SET5_SETP15_Pos)
#define GPIO_PORT_SET5_SETP16_Pos                             16
#define GPIO_PORT_SET5_SETP16_Msk                             (0x01UL << GPIO_PORT_SET5_SETP16_Pos)
#define GPIO_PORT_SET5_SETP17_Pos                             17
#define GPIO_PORT_SET5_SETP17_Msk                             (0x01UL << GPIO_PORT_SET5_SETP17_Pos)
#define GPIO_PORT_SET5_SETP18_Pos                             18
#define GPIO_PORT_SET5_SETP18_Msk                             (0x01UL << GPIO_PORT_SET5_SETP18_Pos)
#define GPIO_PORT_SET5_SETP19_Pos                             19
#define GPIO_PORT_SET5_SETP19_Msk                             (0x01UL << GPIO_PORT_SET5_SETP19_Pos)
#define GPIO_PORT_SET5_SETP20_Pos                             20
#define GPIO_PORT_SET5_SETP20_Msk                             (0x01UL << GPIO_PORT_SET5_SETP20_Pos)
#define GPIO_PORT_SET5_SETP21_Pos                             21
#define GPIO_PORT_SET5_SETP21_Msk                             (0x01UL << GPIO_PORT_SET5_SETP21_Pos)
#define GPIO_PORT_SET5_SETP22_Pos                             22
#define GPIO_PORT_SET5_SETP22_Msk                             (0x01UL << GPIO_PORT_SET5_SETP22_Pos)
#define GPIO_PORT_SET5_SETP23_Pos                             23
#define GPIO_PORT_SET5_SETP23_Msk                             (0x01UL << GPIO_PORT_SET5_SETP23_Pos)
#define GPIO_PORT_SET5_SETP24_Pos                             24
#define GPIO_PORT_SET5_SETP24_Msk                             (0x01UL << GPIO_PORT_SET5_SETP24_Pos)
#define GPIO_PORT_SET5_SETP25_Pos                             25
#define GPIO_PORT_SET5_SETP25_Msk                             (0x01UL << GPIO_PORT_SET5_SETP25_Pos)
#define GPIO_PORT_SET5_SETP26_Pos                             26
#define GPIO_PORT_SET5_SETP26_Msk                             (0x01UL << GPIO_PORT_SET5_SETP26_Pos)
#define GPIO_PORT_SET5_SETP27_Pos                             27
#define GPIO_PORT_SET5_SETP27_Msk                             (0x01UL << GPIO_PORT_SET5_SETP27_Pos)
#define GPIO_PORT_SET5_SETP28_Pos                             28
#define GPIO_PORT_SET5_SETP28_Msk                             (0x01UL << GPIO_PORT_SET5_SETP28_Pos)
#define GPIO_PORT_SET5_SETP29_Pos                             29
#define GPIO_PORT_SET5_SETP29_Msk                             (0x01UL << GPIO_PORT_SET5_SETP29_Pos)
#define GPIO_PORT_SET5_SETP30_Pos                             30
#define GPIO_PORT_SET5_SETP30_Msk                             (0x01UL << GPIO_PORT_SET5_SETP30_Pos)
#define GPIO_PORT_SET5_SETP31_Pos                             31
#define GPIO_PORT_SET5_SETP31_Msk                             (0x01UL << GPIO_PORT_SET5_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET6  -----------------------------------------
#define GPIO_PORT_SET6_SETP0_Pos                              0
#define GPIO_PORT_SET6_SETP0_Msk                              (0x01UL << GPIO_PORT_SET6_SETP0_Pos)
#define GPIO_PORT_SET6_SETP1_Pos                              1
#define GPIO_PORT_SET6_SETP1_Msk                              (0x01UL << GPIO_PORT_SET6_SETP1_Pos)
#define GPIO_PORT_SET6_SETP2_Pos                              2
#define GPIO_PORT_SET6_SETP2_Msk                              (0x01UL << GPIO_PORT_SET6_SETP2_Pos)
#define GPIO_PORT_SET6_SETP3_Pos                              3
#define GPIO_PORT_SET6_SETP3_Msk                              (0x01UL << GPIO_PORT_SET6_SETP3_Pos)
#define GPIO_PORT_SET6_SETP4_Pos                              4
#define GPIO_PORT_SET6_SETP4_Msk                              (0x01UL << GPIO_PORT_SET6_SETP4_Pos)
#define GPIO_PORT_SET6_SETP5_Pos                              5
#define GPIO_PORT_SET6_SETP5_Msk                              (0x01UL << GPIO_PORT_SET6_SETP5_Pos)
#define GPIO_PORT_SET6_SETP6_Pos                              6
#define GPIO_PORT_SET6_SETP6_Msk                              (0x01UL << GPIO_PORT_SET6_SETP6_Pos)
#define GPIO_PORT_SET6_SETP7_Pos                              7
#define GPIO_PORT_SET6_SETP7_Msk                              (0x01UL << GPIO_PORT_SET6_SETP7_Pos)
#define GPIO_PORT_SET6_SETP8_Pos                              8
#define GPIO_PORT_SET6_SETP8_Msk                              (0x01UL << GPIO_PORT_SET6_SETP8_Pos)
#define GPIO_PORT_SET6_SETP9_Pos                              9
#define GPIO_PORT_SET6_SETP9_Msk                              (0x01UL << GPIO_PORT_SET6_SETP9_Pos)
#define GPIO_PORT_SET6_SETP10_Pos                             10
#define GPIO_PORT_SET6_SETP10_Msk                             (0x01UL << GPIO_PORT_SET6_SETP10_Pos)
#define GPIO_PORT_SET6_SETP11_Pos                             11
#define GPIO_PORT_SET6_SETP11_Msk                             (0x01UL << GPIO_PORT_SET6_SETP11_Pos)
#define GPIO_PORT_SET6_SETP12_Pos                             12
#define GPIO_PORT_SET6_SETP12_Msk                             (0x01UL << GPIO_PORT_SET6_SETP12_Pos)
#define GPIO_PORT_SET6_SETP13_Pos                             13
#define GPIO_PORT_SET6_SETP13_Msk                             (0x01UL << GPIO_PORT_SET6_SETP13_Pos)
#define GPIO_PORT_SET6_SETP14_Pos                             14
#define GPIO_PORT_SET6_SETP14_Msk                             (0x01UL << GPIO_PORT_SET6_SETP14_Pos)
#define GPIO_PORT_SET6_SETP15_Pos                             15
#define GPIO_PORT_SET6_SETP15_Msk                             (0x01UL << GPIO_PORT_SET6_SETP15_Pos)
#define GPIO_PORT_SET6_SETP16_Pos                             16
#define GPIO_PORT_SET6_SETP16_Msk                             (0x01UL << GPIO_PORT_SET6_SETP16_Pos)
#define GPIO_PORT_SET6_SETP17_Pos                             17
#define GPIO_PORT_SET6_SETP17_Msk                             (0x01UL << GPIO_PORT_SET6_SETP17_Pos)
#define GPIO_PORT_SET6_SETP18_Pos                             18
#define GPIO_PORT_SET6_SETP18_Msk                             (0x01UL << GPIO_PORT_SET6_SETP18_Pos)
#define GPIO_PORT_SET6_SETP19_Pos                             19
#define GPIO_PORT_SET6_SETP19_Msk                             (0x01UL << GPIO_PORT_SET6_SETP19_Pos)
#define GPIO_PORT_SET6_SETP20_Pos                             20
#define GPIO_PORT_SET6_SETP20_Msk                             (0x01UL << GPIO_PORT_SET6_SETP20_Pos)
#define GPIO_PORT_SET6_SETP21_Pos                             21
#define GPIO_PORT_SET6_SETP21_Msk                             (0x01UL << GPIO_PORT_SET6_SETP21_Pos)
#define GPIO_PORT_SET6_SETP22_Pos                             22
#define GPIO_PORT_SET6_SETP22_Msk                             (0x01UL << GPIO_PORT_SET6_SETP22_Pos)
#define GPIO_PORT_SET6_SETP23_Pos                             23
#define GPIO_PORT_SET6_SETP23_Msk                             (0x01UL << GPIO_PORT_SET6_SETP23_Pos)
#define GPIO_PORT_SET6_SETP24_Pos                             24
#define GPIO_PORT_SET6_SETP24_Msk                             (0x01UL << GPIO_PORT_SET6_SETP24_Pos)
#define GPIO_PORT_SET6_SETP25_Pos                             25
#define GPIO_PORT_SET6_SETP25_Msk                             (0x01UL << GPIO_PORT_SET6_SETP25_Pos)
#define GPIO_PORT_SET6_SETP26_Pos                             26
#define GPIO_PORT_SET6_SETP26_Msk                             (0x01UL << GPIO_PORT_SET6_SETP26_Pos)
#define GPIO_PORT_SET6_SETP27_Pos                             27
#define GPIO_PORT_SET6_SETP27_Msk                             (0x01UL << GPIO_PORT_SET6_SETP27_Pos)
#define GPIO_PORT_SET6_SETP28_Pos                             28
#define GPIO_PORT_SET6_SETP28_Msk                             (0x01UL << GPIO_PORT_SET6_SETP28_Pos)
#define GPIO_PORT_SET6_SETP29_Pos                             29
#define GPIO_PORT_SET6_SETP29_Msk                             (0x01UL << GPIO_PORT_SET6_SETP29_Pos)
#define GPIO_PORT_SET6_SETP30_Pos                             30
#define GPIO_PORT_SET6_SETP30_Msk                             (0x01UL << GPIO_PORT_SET6_SETP30_Pos)
#define GPIO_PORT_SET6_SETP31_Pos                             31
#define GPIO_PORT_SET6_SETP31_Msk                             (0x01UL << GPIO_PORT_SET6_SETP31_Pos)

// -------------------------------------  GPIO_PORT_SET7  -----------------------------------------
#define GPIO_PORT_SET7_SETP0_Pos                              0
#define GPIO_PORT_SET7_SETP0_Msk                              (0x01UL << GPIO_PORT_SET7_SETP0_Pos)
#define GPIO_PORT_SET7_SETP1_Pos                              1
#define GPIO_PORT_SET7_SETP1_Msk                              (0x01UL << GPIO_PORT_SET7_SETP1_Pos)
#define GPIO_PORT_SET7_SETP2_Pos                              2
#define GPIO_PORT_SET7_SETP2_Msk                              (0x01UL << GPIO_PORT_SET7_SETP2_Pos)
#define GPIO_PORT_SET7_SETP3_Pos                              3
#define GPIO_PORT_SET7_SETP3_Msk                              (0x01UL << GPIO_PORT_SET7_SETP3_Pos)
#define GPIO_PORT_SET7_SETP4_Pos                              4
#define GPIO_PORT_SET7_SETP4_Msk                              (0x01UL << GPIO_PORT_SET7_SETP4_Pos)
#define GPIO_PORT_SET7_SETP5_Pos                              5
#define GPIO_PORT_SET7_SETP5_Msk                              (0x01UL << GPIO_PORT_SET7_SETP5_Pos)
#define GPIO_PORT_SET7_SETP6_Pos                              6
#define GPIO_PORT_SET7_SETP6_Msk                              (0x01UL << GPIO_PORT_SET7_SETP6_Pos)
#define GPIO_PORT_SET7_SETP7_Pos                              7
#define GPIO_PORT_SET7_SETP7_Msk                              (0x01UL << GPIO_PORT_SET7_SETP7_Pos)
#define GPIO_PORT_SET7_SETP8_Pos                              8
#define GPIO_PORT_SET7_SETP8_Msk                              (0x01UL << GPIO_PORT_SET7_SETP8_Pos)
#define GPIO_PORT_SET7_SETP9_Pos                              9
#define GPIO_PORT_SET7_SETP9_Msk                              (0x01UL << GPIO_PORT_SET7_SETP9_Pos)
#define GPIO_PORT_SET7_SETP10_Pos                             10
#define GPIO_PORT_SET7_SETP10_Msk                             (0x01UL << GPIO_PORT_SET7_SETP10_Pos)
#define GPIO_PORT_SET7_SETP11_Pos                             11
#define GPIO_PORT_SET7_SETP11_Msk                             (0x01UL << GPIO_PORT_SET7_SETP11_Pos)
#define GPIO_PORT_SET7_SETP12_Pos                             12
#define GPIO_PORT_SET7_SETP12_Msk                             (0x01UL << GPIO_PORT_SET7_SETP12_Pos)
#define GPIO_PORT_SET7_SETP13_Pos                             13
#define GPIO_PORT_SET7_SETP13_Msk                             (0x01UL << GPIO_PORT_SET7_SETP13_Pos)
#define GPIO_PORT_SET7_SETP14_Pos                             14
#define GPIO_PORT_SET7_SETP14_Msk                             (0x01UL << GPIO_PORT_SET7_SETP14_Pos)
#define GPIO_PORT_SET7_SETP15_Pos                             15
#define GPIO_PORT_SET7_SETP15_Msk                             (0x01UL << GPIO_PORT_SET7_SETP15_Pos)
#define GPIO_PORT_SET7_SETP16_Pos                             16
#define GPIO_PORT_SET7_SETP16_Msk                             (0x01UL << GPIO_PORT_SET7_SETP16_Pos)
#define GPIO_PORT_SET7_SETP17_Pos                             17
#define GPIO_PORT_SET7_SETP17_Msk                             (0x01UL << GPIO_PORT_SET7_SETP17_Pos)
#define GPIO_PORT_SET7_SETP18_Pos                             18
#define GPIO_PORT_SET7_SETP18_Msk                             (0x01UL << GPIO_PORT_SET7_SETP18_Pos)
#define GPIO_PORT_SET7_SETP19_Pos                             19
#define GPIO_PORT_SET7_SETP19_Msk                             (0x01UL << GPIO_PORT_SET7_SETP19_Pos)
#define GPIO_PORT_SET7_SETP20_Pos                             20
#define GPIO_PORT_SET7_SETP20_Msk                             (0x01UL << GPIO_PORT_SET7_SETP20_Pos)
#define GPIO_PORT_SET7_SETP21_Pos                             21
#define GPIO_PORT_SET7_SETP21_Msk                             (0x01UL << GPIO_PORT_SET7_SETP21_Pos)
#define GPIO_PORT_SET7_SETP22_Pos                             22
#define GPIO_PORT_SET7_SETP22_Msk                             (0x01UL << GPIO_PORT_SET7_SETP22_Pos)
#define GPIO_PORT_SET7_SETP23_Pos                             23
#define GPIO_PORT_SET7_SETP23_Msk                             (0x01UL << GPIO_PORT_SET7_SETP23_Pos)
#define GPIO_PORT_SET7_SETP24_Pos                             24
#define GPIO_PORT_SET7_SETP24_Msk                             (0x01UL << GPIO_PORT_SET7_SETP24_Pos)
#define GPIO_PORT_SET7_SETP25_Pos                             25
#define GPIO_PORT_SET7_SETP25_Msk                             (0x01UL << GPIO_PORT_SET7_SETP25_Pos)
#define GPIO_PORT_SET7_SETP26_Pos                             26
#define GPIO_PORT_SET7_SETP26_Msk                             (0x01UL << GPIO_PORT_SET7_SETP26_Pos)
#define GPIO_PORT_SET7_SETP27_Pos                             27
#define GPIO_PORT_SET7_SETP27_Msk                             (0x01UL << GPIO_PORT_SET7_SETP27_Pos)
#define GPIO_PORT_SET7_SETP28_Pos                             28
#define GPIO_PORT_SET7_SETP28_Msk                             (0x01UL << GPIO_PORT_SET7_SETP28_Pos)
#define GPIO_PORT_SET7_SETP29_Pos                             29
#define GPIO_PORT_SET7_SETP29_Msk                             (0x01UL << GPIO_PORT_SET7_SETP29_Pos)
#define GPIO_PORT_SET7_SETP30_Pos                             30
#define GPIO_PORT_SET7_SETP30_Msk                             (0x01UL << GPIO_PORT_SET7_SETP30_Pos)
#define GPIO_PORT_SET7_SETP31_Pos                             31
#define GPIO_PORT_SET7_SETP31_Msk                             (0x01UL << GPIO_PORT_SET7_SETP31_Pos)

// -------------------------------------  GPIO_PORT_CLR0  -----------------------------------------
#define GPIO_PORT_CLR0_CLRP00_Pos                             0
#define GPIO_PORT_CLR0_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos)
#define GPIO_PORT_CLR0_CLRP01_Pos                             1
#define GPIO_PORT_CLR0_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos)
#define GPIO_PORT_CLR0_CLRP02_Pos                             2
#define GPIO_PORT_CLR0_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos)
#define GPIO_PORT_CLR0_CLRP03_Pos                             3
#define GPIO_PORT_CLR0_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos)
#define GPIO_PORT_CLR0_CLRP04_Pos                             4
#define GPIO_PORT_CLR0_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos)
#define GPIO_PORT_CLR0_CLRP05_Pos                             5
#define GPIO_PORT_CLR0_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos)
#define GPIO_PORT_CLR0_CLRP06_Pos                             6
#define GPIO_PORT_CLR0_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos)
#define GPIO_PORT_CLR0_CLRP07_Pos                             7
#define GPIO_PORT_CLR0_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos)
#define GPIO_PORT_CLR0_CLRP08_Pos                             8
#define GPIO_PORT_CLR0_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos)
#define GPIO_PORT_CLR0_CLRP09_Pos                             9
#define GPIO_PORT_CLR0_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos)
#define GPIO_PORT_CLR0_CLRP010_Pos                            10
#define GPIO_PORT_CLR0_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos)
#define GPIO_PORT_CLR0_CLRP011_Pos                            11
#define GPIO_PORT_CLR0_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos)
#define GPIO_PORT_CLR0_CLRP012_Pos                            12
#define GPIO_PORT_CLR0_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos)
#define GPIO_PORT_CLR0_CLRP013_Pos                            13
#define GPIO_PORT_CLR0_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos)
#define GPIO_PORT_CLR0_CLRP014_Pos                            14
#define GPIO_PORT_CLR0_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos)
#define GPIO_PORT_CLR0_CLRP015_Pos                            15
#define GPIO_PORT_CLR0_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos)
#define GPIO_PORT_CLR0_CLRP016_Pos                            16
#define GPIO_PORT_CLR0_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos)
#define GPIO_PORT_CLR0_CLRP017_Pos                            17
#define GPIO_PORT_CLR0_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos)
#define GPIO_PORT_CLR0_CLRP018_Pos                            18
#define GPIO_PORT_CLR0_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos)
#define GPIO_PORT_CLR0_CLRP019_Pos                            19
#define GPIO_PORT_CLR0_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos)
#define GPIO_PORT_CLR0_CLRP020_Pos                            20
#define GPIO_PORT_CLR0_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos)
#define GPIO_PORT_CLR0_CLRP021_Pos                            21
#define GPIO_PORT_CLR0_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos)
#define GPIO_PORT_CLR0_CLRP022_Pos                            22
#define GPIO_PORT_CLR0_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos)
#define GPIO_PORT_CLR0_CLRP023_Pos                            23
#define GPIO_PORT_CLR0_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos)
#define GPIO_PORT_CLR0_CLRP024_Pos                            24
#define GPIO_PORT_CLR0_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos)
#define GPIO_PORT_CLR0_CLRP025_Pos                            25
#define GPIO_PORT_CLR0_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos)
#define GPIO_PORT_CLR0_CLRP026_Pos                            26
#define GPIO_PORT_CLR0_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos)
#define GPIO_PORT_CLR0_CLRP027_Pos                            27
#define GPIO_PORT_CLR0_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos)
#define GPIO_PORT_CLR0_CLRP028_Pos                            28
#define GPIO_PORT_CLR0_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos)
#define GPIO_PORT_CLR0_CLRP029_Pos                            29
#define GPIO_PORT_CLR0_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos)
#define GPIO_PORT_CLR0_CLRP030_Pos                            30
#define GPIO_PORT_CLR0_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos)
#define GPIO_PORT_CLR0_CLRP031_Pos                            31
#define GPIO_PORT_CLR0_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR1  -----------------------------------------
#define GPIO_PORT_CLR1_CLRP00_Pos                             0
#define GPIO_PORT_CLR1_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos)
#define GPIO_PORT_CLR1_CLRP01_Pos                             1
#define GPIO_PORT_CLR1_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos)
#define GPIO_PORT_CLR1_CLRP02_Pos                             2
#define GPIO_PORT_CLR1_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos)
#define GPIO_PORT_CLR1_CLRP03_Pos                             3
#define GPIO_PORT_CLR1_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos)
#define GPIO_PORT_CLR1_CLRP04_Pos                             4
#define GPIO_PORT_CLR1_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos)
#define GPIO_PORT_CLR1_CLRP05_Pos                             5
#define GPIO_PORT_CLR1_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos)
#define GPIO_PORT_CLR1_CLRP06_Pos                             6
#define GPIO_PORT_CLR1_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos)
#define GPIO_PORT_CLR1_CLRP07_Pos                             7
#define GPIO_PORT_CLR1_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos)
#define GPIO_PORT_CLR1_CLRP08_Pos                             8
#define GPIO_PORT_CLR1_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos)
#define GPIO_PORT_CLR1_CLRP09_Pos                             9
#define GPIO_PORT_CLR1_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos)
#define GPIO_PORT_CLR1_CLRP010_Pos                            10
#define GPIO_PORT_CLR1_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos)
#define GPIO_PORT_CLR1_CLRP011_Pos                            11
#define GPIO_PORT_CLR1_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos)
#define GPIO_PORT_CLR1_CLRP012_Pos                            12
#define GPIO_PORT_CLR1_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos)
#define GPIO_PORT_CLR1_CLRP013_Pos                            13
#define GPIO_PORT_CLR1_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos)
#define GPIO_PORT_CLR1_CLRP014_Pos                            14
#define GPIO_PORT_CLR1_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos)
#define GPIO_PORT_CLR1_CLRP015_Pos                            15
#define GPIO_PORT_CLR1_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos)
#define GPIO_PORT_CLR1_CLRP016_Pos                            16
#define GPIO_PORT_CLR1_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos)
#define GPIO_PORT_CLR1_CLRP017_Pos                            17
#define GPIO_PORT_CLR1_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos)
#define GPIO_PORT_CLR1_CLRP018_Pos                            18
#define GPIO_PORT_CLR1_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos)
#define GPIO_PORT_CLR1_CLRP019_Pos                            19
#define GPIO_PORT_CLR1_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos)
#define GPIO_PORT_CLR1_CLRP020_Pos                            20
#define GPIO_PORT_CLR1_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos)
#define GPIO_PORT_CLR1_CLRP021_Pos                            21
#define GPIO_PORT_CLR1_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos)
#define GPIO_PORT_CLR1_CLRP022_Pos                            22
#define GPIO_PORT_CLR1_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos)
#define GPIO_PORT_CLR1_CLRP023_Pos                            23
#define GPIO_PORT_CLR1_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos)
#define GPIO_PORT_CLR1_CLRP024_Pos                            24
#define GPIO_PORT_CLR1_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos)
#define GPIO_PORT_CLR1_CLRP025_Pos                            25
#define GPIO_PORT_CLR1_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos)
#define GPIO_PORT_CLR1_CLRP026_Pos                            26
#define GPIO_PORT_CLR1_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos)
#define GPIO_PORT_CLR1_CLRP027_Pos                            27
#define GPIO_PORT_CLR1_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos)
#define GPIO_PORT_CLR1_CLRP028_Pos                            28
#define GPIO_PORT_CLR1_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos)
#define GPIO_PORT_CLR1_CLRP029_Pos                            29
#define GPIO_PORT_CLR1_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos)
#define GPIO_PORT_CLR1_CLRP030_Pos                            30
#define GPIO_PORT_CLR1_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos)
#define GPIO_PORT_CLR1_CLRP031_Pos                            31
#define GPIO_PORT_CLR1_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR2  -----------------------------------------
#define GPIO_PORT_CLR2_CLRP00_Pos                             0
#define GPIO_PORT_CLR2_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos)
#define GPIO_PORT_CLR2_CLRP01_Pos                             1
#define GPIO_PORT_CLR2_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos)
#define GPIO_PORT_CLR2_CLRP02_Pos                             2
#define GPIO_PORT_CLR2_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos)
#define GPIO_PORT_CLR2_CLRP03_Pos                             3
#define GPIO_PORT_CLR2_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos)
#define GPIO_PORT_CLR2_CLRP04_Pos                             4
#define GPIO_PORT_CLR2_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos)
#define GPIO_PORT_CLR2_CLRP05_Pos                             5
#define GPIO_PORT_CLR2_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos)
#define GPIO_PORT_CLR2_CLRP06_Pos                             6
#define GPIO_PORT_CLR2_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos)
#define GPIO_PORT_CLR2_CLRP07_Pos                             7
#define GPIO_PORT_CLR2_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos)
#define GPIO_PORT_CLR2_CLRP08_Pos                             8
#define GPIO_PORT_CLR2_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos)
#define GPIO_PORT_CLR2_CLRP09_Pos                             9
#define GPIO_PORT_CLR2_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos)
#define GPIO_PORT_CLR2_CLRP010_Pos                            10
#define GPIO_PORT_CLR2_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos)
#define GPIO_PORT_CLR2_CLRP011_Pos                            11
#define GPIO_PORT_CLR2_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos)
#define GPIO_PORT_CLR2_CLRP012_Pos                            12
#define GPIO_PORT_CLR2_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos)
#define GPIO_PORT_CLR2_CLRP013_Pos                            13
#define GPIO_PORT_CLR2_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos)
#define GPIO_PORT_CLR2_CLRP014_Pos                            14
#define GPIO_PORT_CLR2_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos)
#define GPIO_PORT_CLR2_CLRP015_Pos                            15
#define GPIO_PORT_CLR2_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos)
#define GPIO_PORT_CLR2_CLRP016_Pos                            16
#define GPIO_PORT_CLR2_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos)
#define GPIO_PORT_CLR2_CLRP017_Pos                            17
#define GPIO_PORT_CLR2_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos)
#define GPIO_PORT_CLR2_CLRP018_Pos                            18
#define GPIO_PORT_CLR2_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos)
#define GPIO_PORT_CLR2_CLRP019_Pos                            19
#define GPIO_PORT_CLR2_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos)
#define GPIO_PORT_CLR2_CLRP020_Pos                            20
#define GPIO_PORT_CLR2_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos)
#define GPIO_PORT_CLR2_CLRP021_Pos                            21
#define GPIO_PORT_CLR2_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos)
#define GPIO_PORT_CLR2_CLRP022_Pos                            22
#define GPIO_PORT_CLR2_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos)
#define GPIO_PORT_CLR2_CLRP023_Pos                            23
#define GPIO_PORT_CLR2_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos)
#define GPIO_PORT_CLR2_CLRP024_Pos                            24
#define GPIO_PORT_CLR2_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos)
#define GPIO_PORT_CLR2_CLRP025_Pos                            25
#define GPIO_PORT_CLR2_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos)
#define GPIO_PORT_CLR2_CLRP026_Pos                            26
#define GPIO_PORT_CLR2_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos)
#define GPIO_PORT_CLR2_CLRP027_Pos                            27
#define GPIO_PORT_CLR2_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos)
#define GPIO_PORT_CLR2_CLRP028_Pos                            28
#define GPIO_PORT_CLR2_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos)
#define GPIO_PORT_CLR2_CLRP029_Pos                            29
#define GPIO_PORT_CLR2_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos)
#define GPIO_PORT_CLR2_CLRP030_Pos                            30
#define GPIO_PORT_CLR2_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos)
#define GPIO_PORT_CLR2_CLRP031_Pos                            31
#define GPIO_PORT_CLR2_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR3  -----------------------------------------
#define GPIO_PORT_CLR3_CLRP00_Pos                             0
#define GPIO_PORT_CLR3_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos)
#define GPIO_PORT_CLR3_CLRP01_Pos                             1
#define GPIO_PORT_CLR3_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos)
#define GPIO_PORT_CLR3_CLRP02_Pos                             2
#define GPIO_PORT_CLR3_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos)
#define GPIO_PORT_CLR3_CLRP03_Pos                             3
#define GPIO_PORT_CLR3_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos)
#define GPIO_PORT_CLR3_CLRP04_Pos                             4
#define GPIO_PORT_CLR3_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos)
#define GPIO_PORT_CLR3_CLRP05_Pos                             5
#define GPIO_PORT_CLR3_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos)
#define GPIO_PORT_CLR3_CLRP06_Pos                             6
#define GPIO_PORT_CLR3_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos)
#define GPIO_PORT_CLR3_CLRP07_Pos                             7
#define GPIO_PORT_CLR3_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos)
#define GPIO_PORT_CLR3_CLRP08_Pos                             8
#define GPIO_PORT_CLR3_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos)
#define GPIO_PORT_CLR3_CLRP09_Pos                             9
#define GPIO_PORT_CLR3_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos)
#define GPIO_PORT_CLR3_CLRP010_Pos                            10
#define GPIO_PORT_CLR3_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos)
#define GPIO_PORT_CLR3_CLRP011_Pos                            11
#define GPIO_PORT_CLR3_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos)
#define GPIO_PORT_CLR3_CLRP012_Pos                            12
#define GPIO_PORT_CLR3_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos)
#define GPIO_PORT_CLR3_CLRP013_Pos                            13
#define GPIO_PORT_CLR3_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos)
#define GPIO_PORT_CLR3_CLRP014_Pos                            14
#define GPIO_PORT_CLR3_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos)
#define GPIO_PORT_CLR3_CLRP015_Pos                            15
#define GPIO_PORT_CLR3_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos)
#define GPIO_PORT_CLR3_CLRP016_Pos                            16
#define GPIO_PORT_CLR3_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos)
#define GPIO_PORT_CLR3_CLRP017_Pos                            17
#define GPIO_PORT_CLR3_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos)
#define GPIO_PORT_CLR3_CLRP018_Pos                            18
#define GPIO_PORT_CLR3_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos)
#define GPIO_PORT_CLR3_CLRP019_Pos                            19
#define GPIO_PORT_CLR3_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos)
#define GPIO_PORT_CLR3_CLRP020_Pos                            20
#define GPIO_PORT_CLR3_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos)
#define GPIO_PORT_CLR3_CLRP021_Pos                            21
#define GPIO_PORT_CLR3_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos)
#define GPIO_PORT_CLR3_CLRP022_Pos                            22
#define GPIO_PORT_CLR3_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos)
#define GPIO_PORT_CLR3_CLRP023_Pos                            23
#define GPIO_PORT_CLR3_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos)
#define GPIO_PORT_CLR3_CLRP024_Pos                            24
#define GPIO_PORT_CLR3_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos)
#define GPIO_PORT_CLR3_CLRP025_Pos                            25
#define GPIO_PORT_CLR3_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos)
#define GPIO_PORT_CLR3_CLRP026_Pos                            26
#define GPIO_PORT_CLR3_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos)
#define GPIO_PORT_CLR3_CLRP027_Pos                            27
#define GPIO_PORT_CLR3_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos)
#define GPIO_PORT_CLR3_CLRP028_Pos                            28
#define GPIO_PORT_CLR3_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos)
#define GPIO_PORT_CLR3_CLRP029_Pos                            29
#define GPIO_PORT_CLR3_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos)
#define GPIO_PORT_CLR3_CLRP030_Pos                            30
#define GPIO_PORT_CLR3_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos)
#define GPIO_PORT_CLR3_CLRP031_Pos                            31
#define GPIO_PORT_CLR3_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR4  -----------------------------------------
#define GPIO_PORT_CLR4_CLRP00_Pos                             0
#define GPIO_PORT_CLR4_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos)
#define GPIO_PORT_CLR4_CLRP01_Pos                             1
#define GPIO_PORT_CLR4_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos)
#define GPIO_PORT_CLR4_CLRP02_Pos                             2
#define GPIO_PORT_CLR4_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos)
#define GPIO_PORT_CLR4_CLRP03_Pos                             3
#define GPIO_PORT_CLR4_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos)
#define GPIO_PORT_CLR4_CLRP04_Pos                             4
#define GPIO_PORT_CLR4_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos)
#define GPIO_PORT_CLR4_CLRP05_Pos                             5
#define GPIO_PORT_CLR4_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos)
#define GPIO_PORT_CLR4_CLRP06_Pos                             6
#define GPIO_PORT_CLR4_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos)
#define GPIO_PORT_CLR4_CLRP07_Pos                             7
#define GPIO_PORT_CLR4_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos)
#define GPIO_PORT_CLR4_CLRP08_Pos                             8
#define GPIO_PORT_CLR4_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos)
#define GPIO_PORT_CLR4_CLRP09_Pos                             9
#define GPIO_PORT_CLR4_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos)
#define GPIO_PORT_CLR4_CLRP010_Pos                            10
#define GPIO_PORT_CLR4_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos)
#define GPIO_PORT_CLR4_CLRP011_Pos                            11
#define GPIO_PORT_CLR4_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos)
#define GPIO_PORT_CLR4_CLRP012_Pos                            12
#define GPIO_PORT_CLR4_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos)
#define GPIO_PORT_CLR4_CLRP013_Pos                            13
#define GPIO_PORT_CLR4_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos)
#define GPIO_PORT_CLR4_CLRP014_Pos                            14
#define GPIO_PORT_CLR4_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos)
#define GPIO_PORT_CLR4_CLRP015_Pos                            15
#define GPIO_PORT_CLR4_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos)
#define GPIO_PORT_CLR4_CLRP016_Pos                            16
#define GPIO_PORT_CLR4_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos)
#define GPIO_PORT_CLR4_CLRP017_Pos                            17
#define GPIO_PORT_CLR4_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos)
#define GPIO_PORT_CLR4_CLRP018_Pos                            18
#define GPIO_PORT_CLR4_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos)
#define GPIO_PORT_CLR4_CLRP019_Pos                            19
#define GPIO_PORT_CLR4_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos)
#define GPIO_PORT_CLR4_CLRP020_Pos                            20
#define GPIO_PORT_CLR4_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos)
#define GPIO_PORT_CLR4_CLRP021_Pos                            21
#define GPIO_PORT_CLR4_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos)
#define GPIO_PORT_CLR4_CLRP022_Pos                            22
#define GPIO_PORT_CLR4_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos)
#define GPIO_PORT_CLR4_CLRP023_Pos                            23
#define GPIO_PORT_CLR4_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos)
#define GPIO_PORT_CLR4_CLRP024_Pos                            24
#define GPIO_PORT_CLR4_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos)
#define GPIO_PORT_CLR4_CLRP025_Pos                            25
#define GPIO_PORT_CLR4_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos)
#define GPIO_PORT_CLR4_CLRP026_Pos                            26
#define GPIO_PORT_CLR4_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos)
#define GPIO_PORT_CLR4_CLRP027_Pos                            27
#define GPIO_PORT_CLR4_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos)
#define GPIO_PORT_CLR4_CLRP028_Pos                            28
#define GPIO_PORT_CLR4_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos)
#define GPIO_PORT_CLR4_CLRP029_Pos                            29
#define GPIO_PORT_CLR4_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos)
#define GPIO_PORT_CLR4_CLRP030_Pos                            30
#define GPIO_PORT_CLR4_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos)
#define GPIO_PORT_CLR4_CLRP031_Pos                            31
#define GPIO_PORT_CLR4_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR5  -----------------------------------------
#define GPIO_PORT_CLR5_CLRP00_Pos                             0
#define GPIO_PORT_CLR5_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos)
#define GPIO_PORT_CLR5_CLRP01_Pos                             1
#define GPIO_PORT_CLR5_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos)
#define GPIO_PORT_CLR5_CLRP02_Pos                             2
#define GPIO_PORT_CLR5_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos)
#define GPIO_PORT_CLR5_CLRP03_Pos                             3
#define GPIO_PORT_CLR5_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos)
#define GPIO_PORT_CLR5_CLRP04_Pos                             4
#define GPIO_PORT_CLR5_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos)
#define GPIO_PORT_CLR5_CLRP05_Pos                             5
#define GPIO_PORT_CLR5_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos)
#define GPIO_PORT_CLR5_CLRP06_Pos                             6
#define GPIO_PORT_CLR5_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos)
#define GPIO_PORT_CLR5_CLRP07_Pos                             7
#define GPIO_PORT_CLR5_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos)
#define GPIO_PORT_CLR5_CLRP08_Pos                             8
#define GPIO_PORT_CLR5_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos)
#define GPIO_PORT_CLR5_CLRP09_Pos                             9
#define GPIO_PORT_CLR5_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos)
#define GPIO_PORT_CLR5_CLRP010_Pos                            10
#define GPIO_PORT_CLR5_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos)
#define GPIO_PORT_CLR5_CLRP011_Pos                            11
#define GPIO_PORT_CLR5_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos)
#define GPIO_PORT_CLR5_CLRP012_Pos                            12
#define GPIO_PORT_CLR5_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos)
#define GPIO_PORT_CLR5_CLRP013_Pos                            13
#define GPIO_PORT_CLR5_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos)
#define GPIO_PORT_CLR5_CLRP014_Pos                            14
#define GPIO_PORT_CLR5_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos)
#define GPIO_PORT_CLR5_CLRP015_Pos                            15
#define GPIO_PORT_CLR5_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos)
#define GPIO_PORT_CLR5_CLRP016_Pos                            16
#define GPIO_PORT_CLR5_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos)
#define GPIO_PORT_CLR5_CLRP017_Pos                            17
#define GPIO_PORT_CLR5_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos)
#define GPIO_PORT_CLR5_CLRP018_Pos                            18
#define GPIO_PORT_CLR5_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos)
#define GPIO_PORT_CLR5_CLRP019_Pos                            19
#define GPIO_PORT_CLR5_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos)
#define GPIO_PORT_CLR5_CLRP020_Pos                            20
#define GPIO_PORT_CLR5_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos)
#define GPIO_PORT_CLR5_CLRP021_Pos                            21
#define GPIO_PORT_CLR5_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos)
#define GPIO_PORT_CLR5_CLRP022_Pos                            22
#define GPIO_PORT_CLR5_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos)
#define GPIO_PORT_CLR5_CLRP023_Pos                            23
#define GPIO_PORT_CLR5_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos)
#define GPIO_PORT_CLR5_CLRP024_Pos                            24
#define GPIO_PORT_CLR5_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos)
#define GPIO_PORT_CLR5_CLRP025_Pos                            25
#define GPIO_PORT_CLR5_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos)
#define GPIO_PORT_CLR5_CLRP026_Pos                            26
#define GPIO_PORT_CLR5_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos)
#define GPIO_PORT_CLR5_CLRP027_Pos                            27
#define GPIO_PORT_CLR5_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos)
#define GPIO_PORT_CLR5_CLRP028_Pos                            28
#define GPIO_PORT_CLR5_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos)
#define GPIO_PORT_CLR5_CLRP029_Pos                            29
#define GPIO_PORT_CLR5_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos)
#define GPIO_PORT_CLR5_CLRP030_Pos                            30
#define GPIO_PORT_CLR5_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos)
#define GPIO_PORT_CLR5_CLRP031_Pos                            31
#define GPIO_PORT_CLR5_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR6  -----------------------------------------
#define GPIO_PORT_CLR6_CLRP00_Pos                             0
#define GPIO_PORT_CLR6_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos)
#define GPIO_PORT_CLR6_CLRP01_Pos                             1
#define GPIO_PORT_CLR6_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos)
#define GPIO_PORT_CLR6_CLRP02_Pos                             2
#define GPIO_PORT_CLR6_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos)
#define GPIO_PORT_CLR6_CLRP03_Pos                             3
#define GPIO_PORT_CLR6_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos)
#define GPIO_PORT_CLR6_CLRP04_Pos                             4
#define GPIO_PORT_CLR6_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos)
#define GPIO_PORT_CLR6_CLRP05_Pos                             5
#define GPIO_PORT_CLR6_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos)
#define GPIO_PORT_CLR6_CLRP06_Pos                             6
#define GPIO_PORT_CLR6_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos)
#define GPIO_PORT_CLR6_CLRP07_Pos                             7
#define GPIO_PORT_CLR6_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos)
#define GPIO_PORT_CLR6_CLRP08_Pos                             8
#define GPIO_PORT_CLR6_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos)
#define GPIO_PORT_CLR6_CLRP09_Pos                             9
#define GPIO_PORT_CLR6_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos)
#define GPIO_PORT_CLR6_CLRP010_Pos                            10
#define GPIO_PORT_CLR6_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos)
#define GPIO_PORT_CLR6_CLRP011_Pos                            11
#define GPIO_PORT_CLR6_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos)
#define GPIO_PORT_CLR6_CLRP012_Pos                            12
#define GPIO_PORT_CLR6_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos)
#define GPIO_PORT_CLR6_CLRP013_Pos                            13
#define GPIO_PORT_CLR6_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos)
#define GPIO_PORT_CLR6_CLRP014_Pos                            14
#define GPIO_PORT_CLR6_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos)
#define GPIO_PORT_CLR6_CLRP015_Pos                            15
#define GPIO_PORT_CLR6_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos)
#define GPIO_PORT_CLR6_CLRP016_Pos                            16
#define GPIO_PORT_CLR6_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos)
#define GPIO_PORT_CLR6_CLRP017_Pos                            17
#define GPIO_PORT_CLR6_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos)
#define GPIO_PORT_CLR6_CLRP018_Pos                            18
#define GPIO_PORT_CLR6_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos)
#define GPIO_PORT_CLR6_CLRP019_Pos                            19
#define GPIO_PORT_CLR6_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos)
#define GPIO_PORT_CLR6_CLRP020_Pos                            20
#define GPIO_PORT_CLR6_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos)
#define GPIO_PORT_CLR6_CLRP021_Pos                            21
#define GPIO_PORT_CLR6_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos)
#define GPIO_PORT_CLR6_CLRP022_Pos                            22
#define GPIO_PORT_CLR6_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos)
#define GPIO_PORT_CLR6_CLRP023_Pos                            23
#define GPIO_PORT_CLR6_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos)
#define GPIO_PORT_CLR6_CLRP024_Pos                            24
#define GPIO_PORT_CLR6_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos)
#define GPIO_PORT_CLR6_CLRP025_Pos                            25
#define GPIO_PORT_CLR6_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos)
#define GPIO_PORT_CLR6_CLRP026_Pos                            26
#define GPIO_PORT_CLR6_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos)
#define GPIO_PORT_CLR6_CLRP027_Pos                            27
#define GPIO_PORT_CLR6_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos)
#define GPIO_PORT_CLR6_CLRP028_Pos                            28
#define GPIO_PORT_CLR6_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos)
#define GPIO_PORT_CLR6_CLRP029_Pos                            29
#define GPIO_PORT_CLR6_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos)
#define GPIO_PORT_CLR6_CLRP030_Pos                            30
#define GPIO_PORT_CLR6_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos)
#define GPIO_PORT_CLR6_CLRP031_Pos                            31
#define GPIO_PORT_CLR6_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_CLR7  -----------------------------------------
#define GPIO_PORT_CLR7_CLRP00_Pos                             0
#define GPIO_PORT_CLR7_CLRP00_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos)
#define GPIO_PORT_CLR7_CLRP01_Pos                             1
#define GPIO_PORT_CLR7_CLRP01_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos)
#define GPIO_PORT_CLR7_CLRP02_Pos                             2
#define GPIO_PORT_CLR7_CLRP02_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos)
#define GPIO_PORT_CLR7_CLRP03_Pos                             3
#define GPIO_PORT_CLR7_CLRP03_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos)
#define GPIO_PORT_CLR7_CLRP04_Pos                             4
#define GPIO_PORT_CLR7_CLRP04_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos)
#define GPIO_PORT_CLR7_CLRP05_Pos                             5
#define GPIO_PORT_CLR7_CLRP05_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos)
#define GPIO_PORT_CLR7_CLRP06_Pos                             6
#define GPIO_PORT_CLR7_CLRP06_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos)
#define GPIO_PORT_CLR7_CLRP07_Pos                             7
#define GPIO_PORT_CLR7_CLRP07_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos)
#define GPIO_PORT_CLR7_CLRP08_Pos                             8
#define GPIO_PORT_CLR7_CLRP08_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos)
#define GPIO_PORT_CLR7_CLRP09_Pos                             9
#define GPIO_PORT_CLR7_CLRP09_Msk                             (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos)
#define GPIO_PORT_CLR7_CLRP010_Pos                            10
#define GPIO_PORT_CLR7_CLRP010_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos)
#define GPIO_PORT_CLR7_CLRP011_Pos                            11
#define GPIO_PORT_CLR7_CLRP011_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos)
#define GPIO_PORT_CLR7_CLRP012_Pos                            12
#define GPIO_PORT_CLR7_CLRP012_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos)
#define GPIO_PORT_CLR7_CLRP013_Pos                            13
#define GPIO_PORT_CLR7_CLRP013_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos)
#define GPIO_PORT_CLR7_CLRP014_Pos                            14
#define GPIO_PORT_CLR7_CLRP014_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos)
#define GPIO_PORT_CLR7_CLRP015_Pos                            15
#define GPIO_PORT_CLR7_CLRP015_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos)
#define GPIO_PORT_CLR7_CLRP016_Pos                            16
#define GPIO_PORT_CLR7_CLRP016_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos)
#define GPIO_PORT_CLR7_CLRP017_Pos                            17
#define GPIO_PORT_CLR7_CLRP017_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos)
#define GPIO_PORT_CLR7_CLRP018_Pos                            18
#define GPIO_PORT_CLR7_CLRP018_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos)
#define GPIO_PORT_CLR7_CLRP019_Pos                            19
#define GPIO_PORT_CLR7_CLRP019_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos)
#define GPIO_PORT_CLR7_CLRP020_Pos                            20
#define GPIO_PORT_CLR7_CLRP020_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos)
#define GPIO_PORT_CLR7_CLRP021_Pos                            21
#define GPIO_PORT_CLR7_CLRP021_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos)
#define GPIO_PORT_CLR7_CLRP022_Pos                            22
#define GPIO_PORT_CLR7_CLRP022_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos)
#define GPIO_PORT_CLR7_CLRP023_Pos                            23
#define GPIO_PORT_CLR7_CLRP023_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos)
#define GPIO_PORT_CLR7_CLRP024_Pos                            24
#define GPIO_PORT_CLR7_CLRP024_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos)
#define GPIO_PORT_CLR7_CLRP025_Pos                            25
#define GPIO_PORT_CLR7_CLRP025_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos)
#define GPIO_PORT_CLR7_CLRP026_Pos                            26
#define GPIO_PORT_CLR7_CLRP026_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos)
#define GPIO_PORT_CLR7_CLRP027_Pos                            27
#define GPIO_PORT_CLR7_CLRP027_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos)
#define GPIO_PORT_CLR7_CLRP028_Pos                            28
#define GPIO_PORT_CLR7_CLRP028_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos)
#define GPIO_PORT_CLR7_CLRP029_Pos                            29
#define GPIO_PORT_CLR7_CLRP029_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos)
#define GPIO_PORT_CLR7_CLRP030_Pos                            30
#define GPIO_PORT_CLR7_CLRP030_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos)
#define GPIO_PORT_CLR7_CLRP031_Pos                            31
#define GPIO_PORT_CLR7_CLRP031_Msk                            (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos)

// -------------------------------------  GPIO_PORT_NOT0  -----------------------------------------
#define GPIO_PORT_NOT0_NOTP0_Pos                              0
#define GPIO_PORT_NOT0_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos)
#define GPIO_PORT_NOT0_NOTP1_Pos                              1
#define GPIO_PORT_NOT0_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos)
#define GPIO_PORT_NOT0_NOTP2_Pos                              2
#define GPIO_PORT_NOT0_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos)
#define GPIO_PORT_NOT0_NOTP3_Pos                              3
#define GPIO_PORT_NOT0_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos)
#define GPIO_PORT_NOT0_NOTP4_Pos                              4
#define GPIO_PORT_NOT0_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos)
#define GPIO_PORT_NOT0_NOTP5_Pos                              5
#define GPIO_PORT_NOT0_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos)
#define GPIO_PORT_NOT0_NOTP6_Pos                              6
#define GPIO_PORT_NOT0_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos)
#define GPIO_PORT_NOT0_NOTP7_Pos                              7
#define GPIO_PORT_NOT0_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos)
#define GPIO_PORT_NOT0_NOTP8_Pos                              8
#define GPIO_PORT_NOT0_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos)
#define GPIO_PORT_NOT0_NOTP9_Pos                              9
#define GPIO_PORT_NOT0_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos)
#define GPIO_PORT_NOT0_NOTP10_Pos                             10
#define GPIO_PORT_NOT0_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos)
#define GPIO_PORT_NOT0_NOTP11_Pos                             11
#define GPIO_PORT_NOT0_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos)
#define GPIO_PORT_NOT0_NOTP12_Pos                             12
#define GPIO_PORT_NOT0_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos)
#define GPIO_PORT_NOT0_NOTP13_Pos                             13
#define GPIO_PORT_NOT0_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos)
#define GPIO_PORT_NOT0_NOTP14_Pos                             14
#define GPIO_PORT_NOT0_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos)
#define GPIO_PORT_NOT0_NOTP15_Pos                             15
#define GPIO_PORT_NOT0_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos)
#define GPIO_PORT_NOT0_NOTP16_Pos                             16
#define GPIO_PORT_NOT0_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos)
#define GPIO_PORT_NOT0_NOTP17_Pos                             17
#define GPIO_PORT_NOT0_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos)
#define GPIO_PORT_NOT0_NOTP18_Pos                             18
#define GPIO_PORT_NOT0_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos)
#define GPIO_PORT_NOT0_NOTP19_Pos                             19
#define GPIO_PORT_NOT0_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos)
#define GPIO_PORT_NOT0_NOTP20_Pos                             20
#define GPIO_PORT_NOT0_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos)
#define GPIO_PORT_NOT0_NOTP21_Pos                             21
#define GPIO_PORT_NOT0_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos)
#define GPIO_PORT_NOT0_NOTP22_Pos                             22
#define GPIO_PORT_NOT0_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos)
#define GPIO_PORT_NOT0_NOTP23_Pos                             23
#define GPIO_PORT_NOT0_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos)
#define GPIO_PORT_NOT0_NOTP24_Pos                             24
#define GPIO_PORT_NOT0_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos)
#define GPIO_PORT_NOT0_NOTP25_Pos                             25
#define GPIO_PORT_NOT0_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos)
#define GPIO_PORT_NOT0_NOTP26_Pos                             26
#define GPIO_PORT_NOT0_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos)
#define GPIO_PORT_NOT0_NOTP27_Pos                             27
#define GPIO_PORT_NOT0_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos)
#define GPIO_PORT_NOT0_NOTP28_Pos                             28
#define GPIO_PORT_NOT0_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos)
#define GPIO_PORT_NOT0_NOTP29_Pos                             29
#define GPIO_PORT_NOT0_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos)
#define GPIO_PORT_NOT0_NOTP30_Pos                             30
#define GPIO_PORT_NOT0_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos)
#define GPIO_PORT_NOT0_NOTP31_Pos                             31
#define GPIO_PORT_NOT0_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT1  -----------------------------------------
#define GPIO_PORT_NOT1_NOTP0_Pos                              0
#define GPIO_PORT_NOT1_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos)
#define GPIO_PORT_NOT1_NOTP1_Pos                              1
#define GPIO_PORT_NOT1_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos)
#define GPIO_PORT_NOT1_NOTP2_Pos                              2
#define GPIO_PORT_NOT1_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos)
#define GPIO_PORT_NOT1_NOTP3_Pos                              3
#define GPIO_PORT_NOT1_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos)
#define GPIO_PORT_NOT1_NOTP4_Pos                              4
#define GPIO_PORT_NOT1_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos)
#define GPIO_PORT_NOT1_NOTP5_Pos                              5
#define GPIO_PORT_NOT1_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos)
#define GPIO_PORT_NOT1_NOTP6_Pos                              6
#define GPIO_PORT_NOT1_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos)
#define GPIO_PORT_NOT1_NOTP7_Pos                              7
#define GPIO_PORT_NOT1_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos)
#define GPIO_PORT_NOT1_NOTP8_Pos                              8
#define GPIO_PORT_NOT1_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos)
#define GPIO_PORT_NOT1_NOTP9_Pos                              9
#define GPIO_PORT_NOT1_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos)
#define GPIO_PORT_NOT1_NOTP10_Pos                             10
#define GPIO_PORT_NOT1_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos)
#define GPIO_PORT_NOT1_NOTP11_Pos                             11
#define GPIO_PORT_NOT1_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos)
#define GPIO_PORT_NOT1_NOTP12_Pos                             12
#define GPIO_PORT_NOT1_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos)
#define GPIO_PORT_NOT1_NOTP13_Pos                             13
#define GPIO_PORT_NOT1_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos)
#define GPIO_PORT_NOT1_NOTP14_Pos                             14
#define GPIO_PORT_NOT1_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos)
#define GPIO_PORT_NOT1_NOTP15_Pos                             15
#define GPIO_PORT_NOT1_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos)
#define GPIO_PORT_NOT1_NOTP16_Pos                             16
#define GPIO_PORT_NOT1_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos)
#define GPIO_PORT_NOT1_NOTP17_Pos                             17
#define GPIO_PORT_NOT1_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos)
#define GPIO_PORT_NOT1_NOTP18_Pos                             18
#define GPIO_PORT_NOT1_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos)
#define GPIO_PORT_NOT1_NOTP19_Pos                             19
#define GPIO_PORT_NOT1_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos)
#define GPIO_PORT_NOT1_NOTP20_Pos                             20
#define GPIO_PORT_NOT1_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos)
#define GPIO_PORT_NOT1_NOTP21_Pos                             21
#define GPIO_PORT_NOT1_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos)
#define GPIO_PORT_NOT1_NOTP22_Pos                             22
#define GPIO_PORT_NOT1_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos)
#define GPIO_PORT_NOT1_NOTP23_Pos                             23
#define GPIO_PORT_NOT1_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos)
#define GPIO_PORT_NOT1_NOTP24_Pos                             24
#define GPIO_PORT_NOT1_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos)
#define GPIO_PORT_NOT1_NOTP25_Pos                             25
#define GPIO_PORT_NOT1_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos)
#define GPIO_PORT_NOT1_NOTP26_Pos                             26
#define GPIO_PORT_NOT1_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos)
#define GPIO_PORT_NOT1_NOTP27_Pos                             27
#define GPIO_PORT_NOT1_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos)
#define GPIO_PORT_NOT1_NOTP28_Pos                             28
#define GPIO_PORT_NOT1_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos)
#define GPIO_PORT_NOT1_NOTP29_Pos                             29
#define GPIO_PORT_NOT1_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos)
#define GPIO_PORT_NOT1_NOTP30_Pos                             30
#define GPIO_PORT_NOT1_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos)
#define GPIO_PORT_NOT1_NOTP31_Pos                             31
#define GPIO_PORT_NOT1_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT2  -----------------------------------------
#define GPIO_PORT_NOT2_NOTP0_Pos                              0
#define GPIO_PORT_NOT2_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos)
#define GPIO_PORT_NOT2_NOTP1_Pos                              1
#define GPIO_PORT_NOT2_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos)
#define GPIO_PORT_NOT2_NOTP2_Pos                              2
#define GPIO_PORT_NOT2_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos)
#define GPIO_PORT_NOT2_NOTP3_Pos                              3
#define GPIO_PORT_NOT2_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos)
#define GPIO_PORT_NOT2_NOTP4_Pos                              4
#define GPIO_PORT_NOT2_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos)
#define GPIO_PORT_NOT2_NOTP5_Pos                              5
#define GPIO_PORT_NOT2_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos)
#define GPIO_PORT_NOT2_NOTP6_Pos                              6
#define GPIO_PORT_NOT2_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos)
#define GPIO_PORT_NOT2_NOTP7_Pos                              7
#define GPIO_PORT_NOT2_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos)
#define GPIO_PORT_NOT2_NOTP8_Pos                              8
#define GPIO_PORT_NOT2_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos)
#define GPIO_PORT_NOT2_NOTP9_Pos                              9
#define GPIO_PORT_NOT2_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos)
#define GPIO_PORT_NOT2_NOTP10_Pos                             10
#define GPIO_PORT_NOT2_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos)
#define GPIO_PORT_NOT2_NOTP11_Pos                             11
#define GPIO_PORT_NOT2_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos)
#define GPIO_PORT_NOT2_NOTP12_Pos                             12
#define GPIO_PORT_NOT2_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos)
#define GPIO_PORT_NOT2_NOTP13_Pos                             13
#define GPIO_PORT_NOT2_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos)
#define GPIO_PORT_NOT2_NOTP14_Pos                             14
#define GPIO_PORT_NOT2_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos)
#define GPIO_PORT_NOT2_NOTP15_Pos                             15
#define GPIO_PORT_NOT2_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos)
#define GPIO_PORT_NOT2_NOTP16_Pos                             16
#define GPIO_PORT_NOT2_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos)
#define GPIO_PORT_NOT2_NOTP17_Pos                             17
#define GPIO_PORT_NOT2_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos)
#define GPIO_PORT_NOT2_NOTP18_Pos                             18
#define GPIO_PORT_NOT2_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos)
#define GPIO_PORT_NOT2_NOTP19_Pos                             19
#define GPIO_PORT_NOT2_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos)
#define GPIO_PORT_NOT2_NOTP20_Pos                             20
#define GPIO_PORT_NOT2_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos)
#define GPIO_PORT_NOT2_NOTP21_Pos                             21
#define GPIO_PORT_NOT2_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos)
#define GPIO_PORT_NOT2_NOTP22_Pos                             22
#define GPIO_PORT_NOT2_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos)
#define GPIO_PORT_NOT2_NOTP23_Pos                             23
#define GPIO_PORT_NOT2_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos)
#define GPIO_PORT_NOT2_NOTP24_Pos                             24
#define GPIO_PORT_NOT2_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos)
#define GPIO_PORT_NOT2_NOTP25_Pos                             25
#define GPIO_PORT_NOT2_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos)
#define GPIO_PORT_NOT2_NOTP26_Pos                             26
#define GPIO_PORT_NOT2_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos)
#define GPIO_PORT_NOT2_NOTP27_Pos                             27
#define GPIO_PORT_NOT2_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos)
#define GPIO_PORT_NOT2_NOTP28_Pos                             28
#define GPIO_PORT_NOT2_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos)
#define GPIO_PORT_NOT2_NOTP29_Pos                             29
#define GPIO_PORT_NOT2_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos)
#define GPIO_PORT_NOT2_NOTP30_Pos                             30
#define GPIO_PORT_NOT2_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos)
#define GPIO_PORT_NOT2_NOTP31_Pos                             31
#define GPIO_PORT_NOT2_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT3  -----------------------------------------
#define GPIO_PORT_NOT3_NOTP0_Pos                              0
#define GPIO_PORT_NOT3_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos)
#define GPIO_PORT_NOT3_NOTP1_Pos                              1
#define GPIO_PORT_NOT3_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos)
#define GPIO_PORT_NOT3_NOTP2_Pos                              2
#define GPIO_PORT_NOT3_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos)
#define GPIO_PORT_NOT3_NOTP3_Pos                              3
#define GPIO_PORT_NOT3_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos)
#define GPIO_PORT_NOT3_NOTP4_Pos                              4
#define GPIO_PORT_NOT3_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos)
#define GPIO_PORT_NOT3_NOTP5_Pos                              5
#define GPIO_PORT_NOT3_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos)
#define GPIO_PORT_NOT3_NOTP6_Pos                              6
#define GPIO_PORT_NOT3_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos)
#define GPIO_PORT_NOT3_NOTP7_Pos                              7
#define GPIO_PORT_NOT3_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos)
#define GPIO_PORT_NOT3_NOTP8_Pos                              8
#define GPIO_PORT_NOT3_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos)
#define GPIO_PORT_NOT3_NOTP9_Pos                              9
#define GPIO_PORT_NOT3_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos)
#define GPIO_PORT_NOT3_NOTP10_Pos                             10
#define GPIO_PORT_NOT3_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos)
#define GPIO_PORT_NOT3_NOTP11_Pos                             11
#define GPIO_PORT_NOT3_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos)
#define GPIO_PORT_NOT3_NOTP12_Pos                             12
#define GPIO_PORT_NOT3_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos)
#define GPIO_PORT_NOT3_NOTP13_Pos                             13
#define GPIO_PORT_NOT3_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos)
#define GPIO_PORT_NOT3_NOTP14_Pos                             14
#define GPIO_PORT_NOT3_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos)
#define GPIO_PORT_NOT3_NOTP15_Pos                             15
#define GPIO_PORT_NOT3_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos)
#define GPIO_PORT_NOT3_NOTP16_Pos                             16
#define GPIO_PORT_NOT3_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos)
#define GPIO_PORT_NOT3_NOTP17_Pos                             17
#define GPIO_PORT_NOT3_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos)
#define GPIO_PORT_NOT3_NOTP18_Pos                             18
#define GPIO_PORT_NOT3_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos)
#define GPIO_PORT_NOT3_NOTP19_Pos                             19
#define GPIO_PORT_NOT3_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos)
#define GPIO_PORT_NOT3_NOTP20_Pos                             20
#define GPIO_PORT_NOT3_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos)
#define GPIO_PORT_NOT3_NOTP21_Pos                             21
#define GPIO_PORT_NOT3_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos)
#define GPIO_PORT_NOT3_NOTP22_Pos                             22
#define GPIO_PORT_NOT3_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos)
#define GPIO_PORT_NOT3_NOTP23_Pos                             23
#define GPIO_PORT_NOT3_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos)
#define GPIO_PORT_NOT3_NOTP24_Pos                             24
#define GPIO_PORT_NOT3_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos)
#define GPIO_PORT_NOT3_NOTP25_Pos                             25
#define GPIO_PORT_NOT3_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos)
#define GPIO_PORT_NOT3_NOTP26_Pos                             26
#define GPIO_PORT_NOT3_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos)
#define GPIO_PORT_NOT3_NOTP27_Pos                             27
#define GPIO_PORT_NOT3_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos)
#define GPIO_PORT_NOT3_NOTP28_Pos                             28
#define GPIO_PORT_NOT3_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos)
#define GPIO_PORT_NOT3_NOTP29_Pos                             29
#define GPIO_PORT_NOT3_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos)
#define GPIO_PORT_NOT3_NOTP30_Pos                             30
#define GPIO_PORT_NOT3_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos)
#define GPIO_PORT_NOT3_NOTP31_Pos                             31
#define GPIO_PORT_NOT3_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT4  -----------------------------------------
#define GPIO_PORT_NOT4_NOTP0_Pos                              0
#define GPIO_PORT_NOT4_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos)
#define GPIO_PORT_NOT4_NOTP1_Pos                              1
#define GPIO_PORT_NOT4_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos)
#define GPIO_PORT_NOT4_NOTP2_Pos                              2
#define GPIO_PORT_NOT4_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos)
#define GPIO_PORT_NOT4_NOTP3_Pos                              3
#define GPIO_PORT_NOT4_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos)
#define GPIO_PORT_NOT4_NOTP4_Pos                              4
#define GPIO_PORT_NOT4_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos)
#define GPIO_PORT_NOT4_NOTP5_Pos                              5
#define GPIO_PORT_NOT4_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos)
#define GPIO_PORT_NOT4_NOTP6_Pos                              6
#define GPIO_PORT_NOT4_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos)
#define GPIO_PORT_NOT4_NOTP7_Pos                              7
#define GPIO_PORT_NOT4_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos)
#define GPIO_PORT_NOT4_NOTP8_Pos                              8
#define GPIO_PORT_NOT4_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos)
#define GPIO_PORT_NOT4_NOTP9_Pos                              9
#define GPIO_PORT_NOT4_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos)
#define GPIO_PORT_NOT4_NOTP10_Pos                             10
#define GPIO_PORT_NOT4_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos)
#define GPIO_PORT_NOT4_NOTP11_Pos                             11
#define GPIO_PORT_NOT4_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos)
#define GPIO_PORT_NOT4_NOTP12_Pos                             12
#define GPIO_PORT_NOT4_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos)
#define GPIO_PORT_NOT4_NOTP13_Pos                             13
#define GPIO_PORT_NOT4_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos)
#define GPIO_PORT_NOT4_NOTP14_Pos                             14
#define GPIO_PORT_NOT4_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos)
#define GPIO_PORT_NOT4_NOTP15_Pos                             15
#define GPIO_PORT_NOT4_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos)
#define GPIO_PORT_NOT4_NOTP16_Pos                             16
#define GPIO_PORT_NOT4_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos)
#define GPIO_PORT_NOT4_NOTP17_Pos                             17
#define GPIO_PORT_NOT4_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos)
#define GPIO_PORT_NOT4_NOTP18_Pos                             18
#define GPIO_PORT_NOT4_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos)
#define GPIO_PORT_NOT4_NOTP19_Pos                             19
#define GPIO_PORT_NOT4_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos)
#define GPIO_PORT_NOT4_NOTP20_Pos                             20
#define GPIO_PORT_NOT4_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos)
#define GPIO_PORT_NOT4_NOTP21_Pos                             21
#define GPIO_PORT_NOT4_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos)
#define GPIO_PORT_NOT4_NOTP22_Pos                             22
#define GPIO_PORT_NOT4_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos)
#define GPIO_PORT_NOT4_NOTP23_Pos                             23
#define GPIO_PORT_NOT4_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos)
#define GPIO_PORT_NOT4_NOTP24_Pos                             24
#define GPIO_PORT_NOT4_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos)
#define GPIO_PORT_NOT4_NOTP25_Pos                             25
#define GPIO_PORT_NOT4_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos)
#define GPIO_PORT_NOT4_NOTP26_Pos                             26
#define GPIO_PORT_NOT4_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos)
#define GPIO_PORT_NOT4_NOTP27_Pos                             27
#define GPIO_PORT_NOT4_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos)
#define GPIO_PORT_NOT4_NOTP28_Pos                             28
#define GPIO_PORT_NOT4_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos)
#define GPIO_PORT_NOT4_NOTP29_Pos                             29
#define GPIO_PORT_NOT4_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos)
#define GPIO_PORT_NOT4_NOTP30_Pos                             30
#define GPIO_PORT_NOT4_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos)
#define GPIO_PORT_NOT4_NOTP31_Pos                             31
#define GPIO_PORT_NOT4_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT5  -----------------------------------------
#define GPIO_PORT_NOT5_NOTP0_Pos                              0
#define GPIO_PORT_NOT5_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos)
#define GPIO_PORT_NOT5_NOTP1_Pos                              1
#define GPIO_PORT_NOT5_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos)
#define GPIO_PORT_NOT5_NOTP2_Pos                              2
#define GPIO_PORT_NOT5_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos)
#define GPIO_PORT_NOT5_NOTP3_Pos                              3
#define GPIO_PORT_NOT5_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos)
#define GPIO_PORT_NOT5_NOTP4_Pos                              4
#define GPIO_PORT_NOT5_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos)
#define GPIO_PORT_NOT5_NOTP5_Pos                              5
#define GPIO_PORT_NOT5_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos)
#define GPIO_PORT_NOT5_NOTP6_Pos                              6
#define GPIO_PORT_NOT5_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos)
#define GPIO_PORT_NOT5_NOTP7_Pos                              7
#define GPIO_PORT_NOT5_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos)
#define GPIO_PORT_NOT5_NOTP8_Pos                              8
#define GPIO_PORT_NOT5_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos)
#define GPIO_PORT_NOT5_NOTP9_Pos                              9
#define GPIO_PORT_NOT5_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos)
#define GPIO_PORT_NOT5_NOTP10_Pos                             10
#define GPIO_PORT_NOT5_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos)
#define GPIO_PORT_NOT5_NOTP11_Pos                             11
#define GPIO_PORT_NOT5_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos)
#define GPIO_PORT_NOT5_NOTP12_Pos                             12
#define GPIO_PORT_NOT5_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos)
#define GPIO_PORT_NOT5_NOTP13_Pos                             13
#define GPIO_PORT_NOT5_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos)
#define GPIO_PORT_NOT5_NOTP14_Pos                             14
#define GPIO_PORT_NOT5_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos)
#define GPIO_PORT_NOT5_NOTP15_Pos                             15
#define GPIO_PORT_NOT5_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos)
#define GPIO_PORT_NOT5_NOTP16_Pos                             16
#define GPIO_PORT_NOT5_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos)
#define GPIO_PORT_NOT5_NOTP17_Pos                             17
#define GPIO_PORT_NOT5_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos)
#define GPIO_PORT_NOT5_NOTP18_Pos                             18
#define GPIO_PORT_NOT5_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos)
#define GPIO_PORT_NOT5_NOTP19_Pos                             19
#define GPIO_PORT_NOT5_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos)
#define GPIO_PORT_NOT5_NOTP20_Pos                             20
#define GPIO_PORT_NOT5_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos)
#define GPIO_PORT_NOT5_NOTP21_Pos                             21
#define GPIO_PORT_NOT5_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos)
#define GPIO_PORT_NOT5_NOTP22_Pos                             22
#define GPIO_PORT_NOT5_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos)
#define GPIO_PORT_NOT5_NOTP23_Pos                             23
#define GPIO_PORT_NOT5_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos)
#define GPIO_PORT_NOT5_NOTP24_Pos                             24
#define GPIO_PORT_NOT5_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos)
#define GPIO_PORT_NOT5_NOTP25_Pos                             25
#define GPIO_PORT_NOT5_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos)
#define GPIO_PORT_NOT5_NOTP26_Pos                             26
#define GPIO_PORT_NOT5_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos)
#define GPIO_PORT_NOT5_NOTP27_Pos                             27
#define GPIO_PORT_NOT5_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos)
#define GPIO_PORT_NOT5_NOTP28_Pos                             28
#define GPIO_PORT_NOT5_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos)
#define GPIO_PORT_NOT5_NOTP29_Pos                             29
#define GPIO_PORT_NOT5_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos)
#define GPIO_PORT_NOT5_NOTP30_Pos                             30
#define GPIO_PORT_NOT5_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos)
#define GPIO_PORT_NOT5_NOTP31_Pos                             31
#define GPIO_PORT_NOT5_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT6  -----------------------------------------
#define GPIO_PORT_NOT6_NOTP0_Pos                              0
#define GPIO_PORT_NOT6_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos)
#define GPIO_PORT_NOT6_NOTP1_Pos                              1
#define GPIO_PORT_NOT6_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos)
#define GPIO_PORT_NOT6_NOTP2_Pos                              2
#define GPIO_PORT_NOT6_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos)
#define GPIO_PORT_NOT6_NOTP3_Pos                              3
#define GPIO_PORT_NOT6_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos)
#define GPIO_PORT_NOT6_NOTP4_Pos                              4
#define GPIO_PORT_NOT6_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos)
#define GPIO_PORT_NOT6_NOTP5_Pos                              5
#define GPIO_PORT_NOT6_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos)
#define GPIO_PORT_NOT6_NOTP6_Pos                              6
#define GPIO_PORT_NOT6_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos)
#define GPIO_PORT_NOT6_NOTP7_Pos                              7
#define GPIO_PORT_NOT6_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos)
#define GPIO_PORT_NOT6_NOTP8_Pos                              8
#define GPIO_PORT_NOT6_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos)
#define GPIO_PORT_NOT6_NOTP9_Pos                              9
#define GPIO_PORT_NOT6_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos)
#define GPIO_PORT_NOT6_NOTP10_Pos                             10
#define GPIO_PORT_NOT6_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos)
#define GPIO_PORT_NOT6_NOTP11_Pos                             11
#define GPIO_PORT_NOT6_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos)
#define GPIO_PORT_NOT6_NOTP12_Pos                             12
#define GPIO_PORT_NOT6_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos)
#define GPIO_PORT_NOT6_NOTP13_Pos                             13
#define GPIO_PORT_NOT6_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos)
#define GPIO_PORT_NOT6_NOTP14_Pos                             14
#define GPIO_PORT_NOT6_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos)
#define GPIO_PORT_NOT6_NOTP15_Pos                             15
#define GPIO_PORT_NOT6_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos)
#define GPIO_PORT_NOT6_NOTP16_Pos                             16
#define GPIO_PORT_NOT6_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos)
#define GPIO_PORT_NOT6_NOTP17_Pos                             17
#define GPIO_PORT_NOT6_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos)
#define GPIO_PORT_NOT6_NOTP18_Pos                             18
#define GPIO_PORT_NOT6_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos)
#define GPIO_PORT_NOT6_NOTP19_Pos                             19
#define GPIO_PORT_NOT6_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos)
#define GPIO_PORT_NOT6_NOTP20_Pos                             20
#define GPIO_PORT_NOT6_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos)
#define GPIO_PORT_NOT6_NOTP21_Pos                             21
#define GPIO_PORT_NOT6_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos)
#define GPIO_PORT_NOT6_NOTP22_Pos                             22
#define GPIO_PORT_NOT6_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos)
#define GPIO_PORT_NOT6_NOTP23_Pos                             23
#define GPIO_PORT_NOT6_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos)
#define GPIO_PORT_NOT6_NOTP24_Pos                             24
#define GPIO_PORT_NOT6_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos)
#define GPIO_PORT_NOT6_NOTP25_Pos                             25
#define GPIO_PORT_NOT6_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos)
#define GPIO_PORT_NOT6_NOTP26_Pos                             26
#define GPIO_PORT_NOT6_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos)
#define GPIO_PORT_NOT6_NOTP27_Pos                             27
#define GPIO_PORT_NOT6_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos)
#define GPIO_PORT_NOT6_NOTP28_Pos                             28
#define GPIO_PORT_NOT6_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos)
#define GPIO_PORT_NOT6_NOTP29_Pos                             29
#define GPIO_PORT_NOT6_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos)
#define GPIO_PORT_NOT6_NOTP30_Pos                             30
#define GPIO_PORT_NOT6_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos)
#define GPIO_PORT_NOT6_NOTP31_Pos                             31
#define GPIO_PORT_NOT6_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos)

// -------------------------------------  GPIO_PORT_NOT7  -----------------------------------------
#define GPIO_PORT_NOT7_NOTP0_Pos                              0
#define GPIO_PORT_NOT7_NOTP0_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos)
#define GPIO_PORT_NOT7_NOTP1_Pos                              1
#define GPIO_PORT_NOT7_NOTP1_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos)
#define GPIO_PORT_NOT7_NOTP2_Pos                              2
#define GPIO_PORT_NOT7_NOTP2_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos)
#define GPIO_PORT_NOT7_NOTP3_Pos                              3
#define GPIO_PORT_NOT7_NOTP3_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos)
#define GPIO_PORT_NOT7_NOTP4_Pos                              4
#define GPIO_PORT_NOT7_NOTP4_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos)
#define GPIO_PORT_NOT7_NOTP5_Pos                              5
#define GPIO_PORT_NOT7_NOTP5_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos)
#define GPIO_PORT_NOT7_NOTP6_Pos                              6
#define GPIO_PORT_NOT7_NOTP6_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos)
#define GPIO_PORT_NOT7_NOTP7_Pos                              7
#define GPIO_PORT_NOT7_NOTP7_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos)
#define GPIO_PORT_NOT7_NOTP8_Pos                              8
#define GPIO_PORT_NOT7_NOTP8_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos)
#define GPIO_PORT_NOT7_NOTP9_Pos                              9
#define GPIO_PORT_NOT7_NOTP9_Msk                              (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos)
#define GPIO_PORT_NOT7_NOTP10_Pos                             10
#define GPIO_PORT_NOT7_NOTP10_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos)
#define GPIO_PORT_NOT7_NOTP11_Pos                             11
#define GPIO_PORT_NOT7_NOTP11_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos)
#define GPIO_PORT_NOT7_NOTP12_Pos                             12
#define GPIO_PORT_NOT7_NOTP12_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos)
#define GPIO_PORT_NOT7_NOTP13_Pos                             13
#define GPIO_PORT_NOT7_NOTP13_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos)
#define GPIO_PORT_NOT7_NOTP14_Pos                             14
#define GPIO_PORT_NOT7_NOTP14_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos)
#define GPIO_PORT_NOT7_NOTP15_Pos                             15
#define GPIO_PORT_NOT7_NOTP15_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos)
#define GPIO_PORT_NOT7_NOTP16_Pos                             16
#define GPIO_PORT_NOT7_NOTP16_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos)
#define GPIO_PORT_NOT7_NOTP17_Pos                             17
#define GPIO_PORT_NOT7_NOTP17_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos)
#define GPIO_PORT_NOT7_NOTP18_Pos                             18
#define GPIO_PORT_NOT7_NOTP18_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos)
#define GPIO_PORT_NOT7_NOTP19_Pos                             19
#define GPIO_PORT_NOT7_NOTP19_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos)
#define GPIO_PORT_NOT7_NOTP20_Pos                             20
#define GPIO_PORT_NOT7_NOTP20_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos)
#define GPIO_PORT_NOT7_NOTP21_Pos                             21
#define GPIO_PORT_NOT7_NOTP21_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos)
#define GPIO_PORT_NOT7_NOTP22_Pos                             22
#define GPIO_PORT_NOT7_NOTP22_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos)
#define GPIO_PORT_NOT7_NOTP23_Pos                             23
#define GPIO_PORT_NOT7_NOTP23_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos)
#define GPIO_PORT_NOT7_NOTP24_Pos                             24
#define GPIO_PORT_NOT7_NOTP24_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos)
#define GPIO_PORT_NOT7_NOTP25_Pos                             25
#define GPIO_PORT_NOT7_NOTP25_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos)
#define GPIO_PORT_NOT7_NOTP26_Pos                             26
#define GPIO_PORT_NOT7_NOTP26_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos)
#define GPIO_PORT_NOT7_NOTP27_Pos                             27
#define GPIO_PORT_NOT7_NOTP27_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos)
#define GPIO_PORT_NOT7_NOTP28_Pos                             28
#define GPIO_PORT_NOT7_NOTP28_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos)
#define GPIO_PORT_NOT7_NOTP29_Pos                             29
#define GPIO_PORT_NOT7_NOTP29_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos)
#define GPIO_PORT_NOT7_NOTP30_Pos                             30
#define GPIO_PORT_NOT7_NOTP30_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos)
#define GPIO_PORT_NOT7_NOTP31_Pos                             31
#define GPIO_PORT_NOT7_NOTP31_Msk                             (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                  SPI Position & Mask                                 -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------------  SPI_CR  ---------------------------------------------
#define SPI_CR_BITENABLE_Pos                                  2
#define SPI_CR_BITENABLE_Msk                                  (0x01UL << SPI_CR_BITENABLE_Pos)
#define SPI_CR_CPHA_Pos                                       3
#define SPI_CR_CPHA_Msk                                       (0x01UL << SPI_CR_CPHA_Pos)
#define SPI_CR_CPOL_Pos                                       4
#define SPI_CR_CPOL_Msk                                       (0x01UL << SPI_CR_CPOL_Pos)
#define SPI_CR_MSTR_Pos                                       5
#define SPI_CR_MSTR_Msk                                       (0x01UL << SPI_CR_MSTR_Pos)
#define SPI_CR_LSBF_Pos                                       6
#define SPI_CR_LSBF_Msk                                       (0x01UL << SPI_CR_LSBF_Pos)
#define SPI_CR_SPIE_Pos                                       7
#define SPI_CR_SPIE_Msk                                       (0x01UL << SPI_CR_SPIE_Pos)
#define SPI_CR_BITS_Pos                                       8
#define SPI_CR_BITS_Msk                                       (0x0fUL << SPI_CR_BITS_Pos)

// -----------------------------------------  SPI_SR  ---------------------------------------------
#define SPI_SR_ABRT_Pos                                       3
#define SPI_SR_ABRT_Msk                                       (0x01UL << SPI_SR_ABRT_Pos)
#define SPI_SR_MODF_Pos                                       4
#define SPI_SR_MODF_Msk                                       (0x01UL << SPI_SR_MODF_Pos)
#define SPI_SR_ROVR_Pos                                       5
#define SPI_SR_ROVR_Msk                                       (0x01UL << SPI_SR_ROVR_Pos)
#define SPI_SR_WCOL_Pos                                       6
#define SPI_SR_WCOL_Msk                                       (0x01UL << SPI_SR_WCOL_Pos)
#define SPI_SR_SPIF_Pos                                       7
#define SPI_SR_SPIF_Msk                                       (0x01UL << SPI_SR_SPIF_Pos)

// -----------------------------------------  SPI_DR  ---------------------------------------------
#define SPI_DR_DATALOW_Pos                                    0
#define SPI_DR_DATALOW_Msk                                    (0x000000ffUL << SPI_DR_DATALOW_Pos)
#define SPI_DR_DATAHIGH_Pos                                   8
#define SPI_DR_DATAHIGH_Msk                                   (0x000000ffUL << SPI_DR_DATAHIGH_Pos)

// -----------------------------------------  SPI_CCR  --------------------------------------------
#define SPI_CCR_COUNTER_Pos                                   0
#define SPI_CCR_COUNTER_Msk                                   (0x000000ffUL << SPI_CCR_COUNTER_Pos)

// -----------------------------------------  SPI_TCR  --------------------------------------------
#define SPI_TCR_TEST_Pos                                      1
#define SPI_TCR_TEST_Msk                                      (0x7fUL << SPI_TCR_TEST_Pos)

// -----------------------------------------  SPI_TSR  --------------------------------------------
#define SPI_TSR_ABRT_Pos                                      3
#define SPI_TSR_ABRT_Msk                                      (0x01UL << SPI_TSR_ABRT_Pos)
#define SPI_TSR_MODF_Pos                                      4
#define SPI_TSR_MODF_Msk                                      (0x01UL << SPI_TSR_MODF_Pos)
#define SPI_TSR_ROVR_Pos                                      5
#define SPI_TSR_ROVR_Msk                                      (0x01UL << SPI_TSR_ROVR_Pos)
#define SPI_TSR_WCOL_Pos                                      6
#define SPI_TSR_WCOL_Msk                                      (0x01UL << SPI_TSR_WCOL_Pos)
#define SPI_TSR_SPIF_Pos                                      7
#define SPI_TSR_SPIF_Msk                                      (0x01UL << SPI_TSR_SPIF_Pos)

// -----------------------------------------  SPI_INT  --------------------------------------------
#define SPI_INT_SPIF_Pos                                      0
#define SPI_INT_SPIF_Msk                                      (0x01UL << SPI_INT_SPIF_Pos)


// ------------------------------------------------------------------------------------------------
// -----                                 SGPIO Position & Mask                                -----
// ------------------------------------------------------------------------------------------------


// -----------------------------------  SGPIO_OUT_MUX_CFG0  ---------------------------------------
#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG1  ---------------------------------------
#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG2  ---------------------------------------
#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG3  ---------------------------------------
#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG4  ---------------------------------------
#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG5  ---------------------------------------
#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG6  ---------------------------------------
#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG7  ---------------------------------------
#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG8  ---------------------------------------
#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG9  ---------------------------------------
#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos                      0
#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk                      (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos                       4
#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk                       (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG10  --------------------------------------
#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG11  --------------------------------------
#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG12  --------------------------------------
#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG13  --------------------------------------
#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG14  --------------------------------------
#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos)

// -----------------------------------  SGPIO_OUT_MUX_CFG15  --------------------------------------
#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos                     0
#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk                     (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos)
#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos                      4
#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk                      (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG0  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG1  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG2  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG3  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG4  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG5  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG6  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG7  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG8  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG9  --------------------------------------
#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos               0
#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos          1
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos        3
#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos               5
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk               (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos           7
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk           (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos         9
#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos                11
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk                (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos                 12
#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk                 (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG10  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG11  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG12  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG13  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG14  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SGPIO_MUX_CFG15  -------------------------------------
#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos              0
#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk              (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos         1
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk         (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos       3
#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk       (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos              5
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk              (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos          7
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk          (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos)
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos        9
#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk        (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos               11
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk               (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos)
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos                12
#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk                (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG0  --------------------------------------
#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG1  --------------------------------------
#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG2  --------------------------------------
#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG3  --------------------------------------
#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG4  --------------------------------------
#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG5  --------------------------------------
#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG6  --------------------------------------
#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG7  --------------------------------------
#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG8  --------------------------------------
#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG9  --------------------------------------
#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos                   0
#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk                   (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos             1
#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk             (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos                  2
#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos                  3
#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos            4
#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk            (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos                6
#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk                (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos                8
#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk                (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG10  -------------------------------------
#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG11  -------------------------------------
#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG12  -------------------------------------
#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG13  -------------------------------------
#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG14  -------------------------------------
#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos)

// ----------------------------------  SGPIO_SLICE_MUX_CFG15  -------------------------------------
#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos                  0
#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk                  (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos            1
#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk            (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos                 2
#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos                 3
#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk                 (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos)
#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos           4
#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk           (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos               6
#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk               (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos)
#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos               8
#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk               (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos)

// ---------------------------------------  SGPIO_REG0  -------------------------------------------
#define SGPIO_REG0_REG_Pos                                    0
#define SGPIO_REG0_REG_Msk                                    (0xffffffffUL << SGPIO_REG0_REG_Pos)

// ---------------------------------------  SGPIO_REG1  -------------------------------------------
#define SGPIO_REG1_REG_Pos                                    0
#define SGPIO_REG1_REG_Msk                                    (0xffffffffUL << SGPIO_REG1_REG_Pos)

// ---------------------------------------  SGPIO_REG2  -------------------------------------------
#define SGPIO_REG2_REG_Pos                                    0
#define SGPIO_REG2_REG_Msk                                    (0xffffffffUL << SGPIO_REG2_REG_Pos)

// ---------------------------------------  SGPIO_REG3  -------------------------------------------
#define SGPIO_REG3_REG_Pos                                    0
#define SGPIO_REG3_REG_Msk                                    (0xffffffffUL << SGPIO_REG3_REG_Pos)

// ---------------------------------------  SGPIO_REG4  -------------------------------------------
#define SGPIO_REG4_REG_Pos                                    0
#define SGPIO_REG4_REG_Msk                                    (0xffffffffUL << SGPIO_REG4_REG_Pos)

// ---------------------------------------  SGPIO_REG5  -------------------------------------------
#define SGPIO_REG5_REG_Pos                                    0
#define SGPIO_REG5_REG_Msk                                    (0xffffffffUL << SGPIO_REG5_REG_Pos)

// ---------------------------------------  SGPIO_REG6  -------------------------------------------
#define SGPIO_REG6_REG_Pos                                    0
#define SGPIO_REG6_REG_Msk                                    (0xffffffffUL << SGPIO_REG6_REG_Pos)

// ---------------------------------------  SGPIO_REG7  -------------------------------------------
#define SGPIO_REG7_REG_Pos                                    0
#define SGPIO_REG7_REG_Msk                                    (0xffffffffUL << SGPIO_REG7_REG_Pos)

// ---------------------------------------  SGPIO_REG8  -------------------------------------------
#define SGPIO_REG8_REG_Pos                                    0
#define SGPIO_REG8_REG_Msk                                    (0xffffffffUL << SGPIO_REG8_REG_Pos)

// ---------------------------------------  SGPIO_REG9  -------------------------------------------
#define SGPIO_REG9_REG_Pos                                    0
#define SGPIO_REG9_REG_Msk                                    (0xffffffffUL << SGPIO_REG9_REG_Pos)

// ---------------------------------------  SGPIO_REG10  ------------------------------------------
#define SGPIO_REG10_REG_Pos                                   0
#define SGPIO_REG10_REG_Msk                                   (0xffffffffUL << SGPIO_REG10_REG_Pos)

// ---------------------------------------  SGPIO_REG11  ------------------------------------------
#define SGPIO_REG11_REG_Pos                                   0
#define SGPIO_REG11_REG_Msk                                   (0xffffffffUL << SGPIO_REG11_REG_Pos)

// ---------------------------------------  SGPIO_REG12  ------------------------------------------
#define SGPIO_REG12_REG_Pos                                   0
#define SGPIO_REG12_REG_Msk                                   (0xffffffffUL << SGPIO_REG12_REG_Pos)

// ---------------------------------------  SGPIO_REG13  ------------------------------------------
#define SGPIO_REG13_REG_Pos                                   0
#define SGPIO_REG13_REG_Msk                                   (0xffffffffUL << SGPIO_REG13_REG_Pos)

// ---------------------------------------  SGPIO_REG14  ------------------------------------------
#define SGPIO_REG14_REG_Pos                                   0
#define SGPIO_REG14_REG_Msk                                   (0xffffffffUL << SGPIO_REG14_REG_Pos)

// ---------------------------------------  SGPIO_REG15  ------------------------------------------
#define SGPIO_REG15_REG_Pos                                   0
#define SGPIO_REG15_REG_Msk                                   (0xffffffffUL << SGPIO_REG15_REG_Pos)

// --------------------------------------  SGPIO_REG_SS0  -----------------------------------------
#define SGPIO_REG_SS0_REG_SS_Pos                              0
#define SGPIO_REG_SS0_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS1  -----------------------------------------
#define SGPIO_REG_SS1_REG_SS_Pos                              0
#define SGPIO_REG_SS1_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS2  -----------------------------------------
#define SGPIO_REG_SS2_REG_SS_Pos                              0
#define SGPIO_REG_SS2_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS3  -----------------------------------------
#define SGPIO_REG_SS3_REG_SS_Pos                              0
#define SGPIO_REG_SS3_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS4  -----------------------------------------
#define SGPIO_REG_SS4_REG_SS_Pos                              0
#define SGPIO_REG_SS4_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS5  -----------------------------------------
#define SGPIO_REG_SS5_REG_SS_Pos                              0
#define SGPIO_REG_SS5_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS6  -----------------------------------------
#define SGPIO_REG_SS6_REG_SS_Pos                              0
#define SGPIO_REG_SS6_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS7  -----------------------------------------
#define SGPIO_REG_SS7_REG_SS_Pos                              0
#define SGPIO_REG_SS7_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS8  -----------------------------------------
#define SGPIO_REG_SS8_REG_SS_Pos                              0
#define SGPIO_REG_SS8_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos)

// --------------------------------------  SGPIO_REG_SS9  -----------------------------------------
#define SGPIO_REG_SS9_REG_SS_Pos                              0
#define SGPIO_REG_SS9_REG_SS_Msk                              (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS10  -----------------------------------------
#define SGPIO_REG_SS10_REG_SS_Pos                             0
#define SGPIO_REG_SS10_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS11  -----------------------------------------
#define SGPIO_REG_SS11_REG_SS_Pos                             0
#define SGPIO_REG_SS11_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS12  -----------------------------------------
#define SGPIO_REG_SS12_REG_SS_Pos                             0
#define SGPIO_REG_SS12_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS13  -----------------------------------------
#define SGPIO_REG_SS13_REG_SS_Pos                             0
#define SGPIO_REG_SS13_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS14  -----------------------------------------
#define SGPIO_REG_SS14_REG_SS_Pos                             0
#define SGPIO_REG_SS14_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos)

// -------------------------------------  SGPIO_REG_SS15  -----------------------------------------
#define SGPIO_REG_SS15_REG_SS_Pos                             0
#define SGPIO_REG_SS15_REG_SS_Msk                             (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos)

// --------------------------------------  SGPIO_PRESET0  -----------------------------------------
#define SGPIO_PRESET0_PRESET_Pos                              0
#define SGPIO_PRESET0_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET1  -----------------------------------------
#define SGPIO_PRESET1_PRESET_Pos                              0
#define SGPIO_PRESET1_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET2  -----------------------------------------
#define SGPIO_PRESET2_PRESET_Pos                              0
#define SGPIO_PRESET2_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET3  -----------------------------------------
#define SGPIO_PRESET3_PRESET_Pos                              0
#define SGPIO_PRESET3_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET4  -----------------------------------------
#define SGPIO_PRESET4_PRESET_Pos                              0
#define SGPIO_PRESET4_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET5  -----------------------------------------
#define SGPIO_PRESET5_PRESET_Pos                              0
#define SGPIO_PRESET5_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET6  -----------------------------------------
#define SGPIO_PRESET6_PRESET_Pos                              0
#define SGPIO_PRESET6_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET7  -----------------------------------------
#define SGPIO_PRESET7_PRESET_Pos                              0
#define SGPIO_PRESET7_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET8  -----------------------------------------
#define SGPIO_PRESET8_PRESET_Pos                              0
#define SGPIO_PRESET8_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos)

// --------------------------------------  SGPIO_PRESET9  -----------------------------------------
#define SGPIO_PRESET9_PRESET_Pos                              0
#define SGPIO_PRESET9_PRESET_Msk                              (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET10  -----------------------------------------
#define SGPIO_PRESET10_PRESET_Pos                             0
#define SGPIO_PRESET10_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET11  -----------------------------------------
#define SGPIO_PRESET11_PRESET_Pos                             0
#define SGPIO_PRESET11_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET12  -----------------------------------------
#define SGPIO_PRESET12_PRESET_Pos                             0
#define SGPIO_PRESET12_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET13  -----------------------------------------
#define SGPIO_PRESET13_PRESET_Pos                             0
#define SGPIO_PRESET13_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET14  -----------------------------------------
#define SGPIO_PRESET14_PRESET_Pos                             0
#define SGPIO_PRESET14_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos)

// -------------------------------------  SGPIO_PRESET15  -----------------------------------------
#define SGPIO_PRESET15_PRESET_Pos                             0
#define SGPIO_PRESET15_PRESET_Msk                             (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos)

// --------------------------------------  SGPIO_COUNT0  ------------------------------------------
#define SGPIO_COUNT0_COUNT_Pos                                0
#define SGPIO_COUNT0_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT1  ------------------------------------------
#define SGPIO_COUNT1_COUNT_Pos                                0
#define SGPIO_COUNT1_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT2  ------------------------------------------
#define SGPIO_COUNT2_COUNT_Pos                                0
#define SGPIO_COUNT2_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT3  ------------------------------------------
#define SGPIO_COUNT3_COUNT_Pos                                0
#define SGPIO_COUNT3_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT4  ------------------------------------------
#define SGPIO_COUNT4_COUNT_Pos                                0
#define SGPIO_COUNT4_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT5  ------------------------------------------
#define SGPIO_COUNT5_COUNT_Pos                                0
#define SGPIO_COUNT5_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT6  ------------------------------------------
#define SGPIO_COUNT6_COUNT_Pos                                0
#define SGPIO_COUNT6_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT7  ------------------------------------------
#define SGPIO_COUNT7_COUNT_Pos                                0
#define SGPIO_COUNT7_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT8  ------------------------------------------
#define SGPIO_COUNT8_COUNT_Pos                                0
#define SGPIO_COUNT8_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT9  ------------------------------------------
#define SGPIO_COUNT9_COUNT_Pos                                0
#define SGPIO_COUNT9_COUNT_Msk                                (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT10  -----------------------------------------
#define SGPIO_COUNT10_COUNT_Pos                               0
#define SGPIO_COUNT10_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT11  -----------------------------------------
#define SGPIO_COUNT11_COUNT_Pos                               0
#define SGPIO_COUNT11_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT12  -----------------------------------------
#define SGPIO_COUNT12_COUNT_Pos                               0
#define SGPIO_COUNT12_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT13  -----------------------------------------
#define SGPIO_COUNT13_COUNT_Pos                               0
#define SGPIO_COUNT13_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT14  -----------------------------------------
#define SGPIO_COUNT14_COUNT_Pos                               0
#define SGPIO_COUNT14_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos)

// --------------------------------------  SGPIO_COUNT15  -----------------------------------------
#define SGPIO_COUNT15_COUNT_Pos                               0
#define SGPIO_COUNT15_COUNT_Msk                               (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos)

// ---------------------------------------  SGPIO_POS0  -------------------------------------------
#define SGPIO_POS0_POS_Pos                                    0
#define SGPIO_POS0_POS_Msk                                    (0x000000ffUL << SGPIO_POS0_POS_Pos)
#define SGPIO_POS0_POS_RESET_Pos                              8
#define SGPIO_POS0_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS1  -------------------------------------------
#define SGPIO_POS1_POS_Pos                                    0
#define SGPIO_POS1_POS_Msk                                    (0x000000ffUL << SGPIO_POS1_POS_Pos)
#define SGPIO_POS1_POS_RESET_Pos                              8
#define SGPIO_POS1_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS2  -------------------------------------------
#define SGPIO_POS2_POS_Pos                                    0
#define SGPIO_POS2_POS_Msk                                    (0x000000ffUL << SGPIO_POS2_POS_Pos)
#define SGPIO_POS2_POS_RESET_Pos                              8
#define SGPIO_POS2_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS3  -------------------------------------------
#define SGPIO_POS3_POS_Pos                                    0
#define SGPIO_POS3_POS_Msk                                    (0x000000ffUL << SGPIO_POS3_POS_Pos)
#define SGPIO_POS3_POS_RESET_Pos                              8
#define SGPIO_POS3_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS4  -------------------------------------------
#define SGPIO_POS4_POS_Pos                                    0
#define SGPIO_POS4_POS_Msk                                    (0x000000ffUL << SGPIO_POS4_POS_Pos)
#define SGPIO_POS4_POS_RESET_Pos                              8
#define SGPIO_POS4_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS5  -------------------------------------------
#define SGPIO_POS5_POS_Pos                                    0
#define SGPIO_POS5_POS_Msk                                    (0x000000ffUL << SGPIO_POS5_POS_Pos)
#define SGPIO_POS5_POS_RESET_Pos                              8
#define SGPIO_POS5_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS6  -------------------------------------------
#define SGPIO_POS6_POS_Pos                                    0
#define SGPIO_POS6_POS_Msk                                    (0x000000ffUL << SGPIO_POS6_POS_Pos)
#define SGPIO_POS6_POS_RESET_Pos                              8
#define SGPIO_POS6_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS7  -------------------------------------------
#define SGPIO_POS7_POS_Pos                                    0
#define SGPIO_POS7_POS_Msk                                    (0x000000ffUL << SGPIO_POS7_POS_Pos)
#define SGPIO_POS7_POS_RESET_Pos                              8
#define SGPIO_POS7_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS8  -------------------------------------------
#define SGPIO_POS8_POS_Pos                                    0
#define SGPIO_POS8_POS_Msk                                    (0x000000ffUL << SGPIO_POS8_POS_Pos)
#define SGPIO_POS8_POS_RESET_Pos                              8
#define SGPIO_POS8_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS9  -------------------------------------------
#define SGPIO_POS9_POS_Pos                                    0
#define SGPIO_POS9_POS_Msk                                    (0x000000ffUL << SGPIO_POS9_POS_Pos)
#define SGPIO_POS9_POS_RESET_Pos                              8
#define SGPIO_POS9_POS_RESET_Msk                              (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS10  ------------------------------------------
#define SGPIO_POS10_POS_Pos                                   0
#define SGPIO_POS10_POS_Msk                                   (0x000000ffUL << SGPIO_POS10_POS_Pos)
#define SGPIO_POS10_POS_RESET_Pos                             8
#define SGPIO_POS10_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS11  ------------------------------------------
#define SGPIO_POS11_POS_Pos                                   0
#define SGPIO_POS11_POS_Msk                                   (0x000000ffUL << SGPIO_POS11_POS_Pos)
#define SGPIO_POS11_POS_RESET_Pos                             8
#define SGPIO_POS11_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS12  ------------------------------------------
#define SGPIO_POS12_POS_Pos                                   0
#define SGPIO_POS12_POS_Msk                                   (0x000000ffUL << SGPIO_POS12_POS_Pos)
#define SGPIO_POS12_POS_RESET_Pos                             8
#define SGPIO_POS12_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS13  ------------------------------------------
#define SGPIO_POS13_POS_Pos                                   0
#define SGPIO_POS13_POS_Msk                                   (0x000000ffUL << SGPIO_POS13_POS_Pos)
#define SGPIO_POS13_POS_RESET_Pos                             8
#define SGPIO_POS13_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS14  ------------------------------------------
#define SGPIO_POS14_POS_Pos                                   0
#define SGPIO_POS14_POS_Msk                                   (0x000000ffUL << SGPIO_POS14_POS_Pos)
#define SGPIO_POS14_POS_RESET_Pos                             8
#define SGPIO_POS14_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos)

// ---------------------------------------  SGPIO_POS15  ------------------------------------------
#define SGPIO_POS15_POS_Pos                                   0
#define SGPIO_POS15_POS_Msk                                   (0x000000ffUL << SGPIO_POS15_POS_Pos)
#define SGPIO_POS15_POS_RESET_Pos                             8
#define SGPIO_POS15_POS_RESET_Msk                             (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos)

// --------------------------------------  SGPIO_MASK_A  ------------------------------------------
#define SGPIO_MASK_A_MASK_A0_Pos                              0
#define SGPIO_MASK_A_MASK_A0_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A0_Pos)
#define SGPIO_MASK_A_MASK_A1_Pos                              1
#define SGPIO_MASK_A_MASK_A1_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A1_Pos)
#define SGPIO_MASK_A_MASK_A2_Pos                              2
#define SGPIO_MASK_A_MASK_A2_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A2_Pos)
#define SGPIO_MASK_A_MASK_A3_Pos                              3
#define SGPIO_MASK_A_MASK_A3_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A3_Pos)
#define SGPIO_MASK_A_MASK_A4_Pos                              4
#define SGPIO_MASK_A_MASK_A4_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A4_Pos)
#define SGPIO_MASK_A_MASK_A5_Pos                              5
#define SGPIO_MASK_A_MASK_A5_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A5_Pos)
#define SGPIO_MASK_A_MASK_A6_Pos                              6
#define SGPIO_MASK_A_MASK_A6_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A6_Pos)
#define SGPIO_MASK_A_MASK_A7_Pos                              7
#define SGPIO_MASK_A_MASK_A7_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A7_Pos)
#define SGPIO_MASK_A_MASK_A8_Pos                              8
#define SGPIO_MASK_A_MASK_A8_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A8_Pos)
#define SGPIO_MASK_A_MASK_A9_Pos                              9
#define SGPIO_MASK_A_MASK_A9_Msk                              (0x01UL << SGPIO_MASK_A_MASK_A9_Pos)
#define SGPIO_MASK_A_MASK_A10_Pos                             10
#define SGPIO_MASK_A_MASK_A10_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A10_Pos)
#define SGPIO_MASK_A_MASK_A11_Pos                             11
#define SGPIO_MASK_A_MASK_A11_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A11_Pos)
#define SGPIO_MASK_A_MASK_A12_Pos                             12
#define SGPIO_MASK_A_MASK_A12_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A12_Pos)
#define SGPIO_MASK_A_MASK_A13_Pos                             13
#define SGPIO_MASK_A_MASK_A13_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A13_Pos)
#define SGPIO_MASK_A_MASK_A14_Pos                             14
#define SGPIO_MASK_A_MASK_A14_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A14_Pos)
#define SGPIO_MASK_A_MASK_A15_Pos                             15
#define SGPIO_MASK_A_MASK_A15_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A15_Pos)
#define SGPIO_MASK_A_MASK_A16_Pos                             16
#define SGPIO_MASK_A_MASK_A16_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A16_Pos)
#define SGPIO_MASK_A_MASK_A17_Pos                             17
#define SGPIO_MASK_A_MASK_A17_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A17_Pos)
#define SGPIO_MASK_A_MASK_A18_Pos                             18
#define SGPIO_MASK_A_MASK_A18_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A18_Pos)
#define SGPIO_MASK_A_MASK_A19_Pos                             19
#define SGPIO_MASK_A_MASK_A19_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A19_Pos)
#define SGPIO_MASK_A_MASK_A20_Pos                             20
#define SGPIO_MASK_A_MASK_A20_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A20_Pos)
#define SGPIO_MASK_A_MASK_A21_Pos                             21
#define SGPIO_MASK_A_MASK_A21_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A21_Pos)
#define SGPIO_MASK_A_MASK_A22_Pos                             22
#define SGPIO_MASK_A_MASK_A22_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A22_Pos)
#define SGPIO_MASK_A_MASK_A23_Pos                             23
#define SGPIO_MASK_A_MASK_A23_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A23_Pos)
#define SGPIO_MASK_A_MASK_A24_Pos                             24
#define SGPIO_MASK_A_MASK_A24_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A24_Pos)
#define SGPIO_MASK_A_MASK_A25_Pos                             25
#define SGPIO_MASK_A_MASK_A25_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A25_Pos)
#define SGPIO_MASK_A_MASK_A26_Pos                             26
#define SGPIO_MASK_A_MASK_A26_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A26_Pos)
#define SGPIO_MASK_A_MASK_A27_Pos                             27
#define SGPIO_MASK_A_MASK_A27_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A27_Pos)
#define SGPIO_MASK_A_MASK_A28_Pos                             28
#define SGPIO_MASK_A_MASK_A28_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A28_Pos)
#define SGPIO_MASK_A_MASK_A29_Pos                             29
#define SGPIO_MASK_A_MASK_A29_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A29_Pos)
#define SGPIO_MASK_A_MASK_A30_Pos                             30
#define SGPIO_MASK_A_MASK_A30_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A30_Pos)
#define SGPIO_MASK_A_MASK_A31_Pos                             31
#define SGPIO_MASK_A_MASK_A31_Msk                             (0x01UL << SGPIO_MASK_A_MASK_A31_Pos)

// --------------------------------------  SGPIO_MASK_H  ------------------------------------------
#define SGPIO_MASK_H_MASK_H0_Pos                              0
#define SGPIO_MASK_H_MASK_H0_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H0_Pos)
#define SGPIO_MASK_H_MASK_H1_Pos                              1
#define SGPIO_MASK_H_MASK_H1_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H1_Pos)
#define SGPIO_MASK_H_MASK_H2_Pos                              2
#define SGPIO_MASK_H_MASK_H2_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H2_Pos)
#define SGPIO_MASK_H_MASK_H3_Pos                              3
#define SGPIO_MASK_H_MASK_H3_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H3_Pos)
#define SGPIO_MASK_H_MASK_H4_Pos                              4
#define SGPIO_MASK_H_MASK_H4_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H4_Pos)
#define SGPIO_MASK_H_MASK_H5_Pos                              5
#define SGPIO_MASK_H_MASK_H5_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H5_Pos)
#define SGPIO_MASK_H_MASK_H6_Pos                              6
#define SGPIO_MASK_H_MASK_H6_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H6_Pos)
#define SGPIO_MASK_H_MASK_H7_Pos                              7
#define SGPIO_MASK_H_MASK_H7_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H7_Pos)
#define SGPIO_MASK_H_MASK_H8_Pos                              8
#define SGPIO_MASK_H_MASK_H8_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H8_Pos)
#define SGPIO_MASK_H_MASK_H9_Pos                              9
#define SGPIO_MASK_H_MASK_H9_Msk                              (0x01UL << SGPIO_MASK_H_MASK_H9_Pos)
#define SGPIO_MASK_H_MASK_H10_Pos                             10
#define SGPIO_MASK_H_MASK_H10_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H10_Pos)
#define SGPIO_MASK_H_MASK_H11_Pos                             11
#define SGPIO_MASK_H_MASK_H11_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H11_Pos)
#define SGPIO_MASK_H_MASK_H12_Pos                             12
#define SGPIO_MASK_H_MASK_H12_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H12_Pos)
#define SGPIO_MASK_H_MASK_H13_Pos                             13
#define SGPIO_MASK_H_MASK_H13_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H13_Pos)
#define SGPIO_MASK_H_MASK_H14_Pos                             14
#define SGPIO_MASK_H_MASK_H14_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H14_Pos)
#define SGPIO_MASK_H_MASK_H15_Pos                             15
#define SGPIO_MASK_H_MASK_H15_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H15_Pos)
#define SGPIO_MASK_H_MASK_H16_Pos                             16
#define SGPIO_MASK_H_MASK_H16_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H16_Pos)
#define SGPIO_MASK_H_MASK_H17_Pos                             17
#define SGPIO_MASK_H_MASK_H17_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H17_Pos)
#define SGPIO_MASK_H_MASK_H18_Pos                             18
#define SGPIO_MASK_H_MASK_H18_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H18_Pos)
#define SGPIO_MASK_H_MASK_H19_Pos                             19
#define SGPIO_MASK_H_MASK_H19_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H19_Pos)
#define SGPIO_MASK_H_MASK_H20_Pos                             20
#define SGPIO_MASK_H_MASK_H20_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H20_Pos)
#define SGPIO_MASK_H_MASK_H21_Pos                             21
#define SGPIO_MASK_H_MASK_H21_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H21_Pos)
#define SGPIO_MASK_H_MASK_H22_Pos                             22
#define SGPIO_MASK_H_MASK_H22_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H22_Pos)
#define SGPIO_MASK_H_MASK_H23_Pos                             23
#define SGPIO_MASK_H_MASK_H23_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H23_Pos)
#define SGPIO_MASK_H_MASK_H24_Pos                             24
#define SGPIO_MASK_H_MASK_H24_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H24_Pos)
#define SGPIO_MASK_H_MASK_H25_Pos                             25
#define SGPIO_MASK_H_MASK_H25_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H25_Pos)
#define SGPIO_MASK_H_MASK_H26_Pos                             26
#define SGPIO_MASK_H_MASK_H26_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H26_Pos)
#define SGPIO_MASK_H_MASK_H27_Pos                             27
#define SGPIO_MASK_H_MASK_H27_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H27_Pos)
#define SGPIO_MASK_H_MASK_H28_Pos                             28
#define SGPIO_MASK_H_MASK_H28_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H28_Pos)
#define SGPIO_MASK_H_MASK_H29_Pos                             29
#define SGPIO_MASK_H_MASK_H29_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H29_Pos)
#define SGPIO_MASK_H_MASK_H30_Pos                             30
#define SGPIO_MASK_H_MASK_H30_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H30_Pos)
#define SGPIO_MASK_H_MASK_H31_Pos                             31
#define SGPIO_MASK_H_MASK_H31_Msk                             (0x01UL << SGPIO_MASK_H_MASK_H31_Pos)

// --------------------------------------  SGPIO_MASK_I  ------------------------------------------
#define SGPIO_MASK_I_MASK_I0_Pos                              0
#define SGPIO_MASK_I_MASK_I0_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I0_Pos)
#define SGPIO_MASK_I_MASK_I1_Pos                              1
#define SGPIO_MASK_I_MASK_I1_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I1_Pos)
#define SGPIO_MASK_I_MASK_I2_Pos                              2
#define SGPIO_MASK_I_MASK_I2_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I2_Pos)
#define SGPIO_MASK_I_MASK_I3_Pos                              3
#define SGPIO_MASK_I_MASK_I3_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I3_Pos)
#define SGPIO_MASK_I_MASK_I4_Pos                              4
#define SGPIO_MASK_I_MASK_I4_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I4_Pos)
#define SGPIO_MASK_I_MASK_I5_Pos                              5
#define SGPIO_MASK_I_MASK_I5_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I5_Pos)
#define SGPIO_MASK_I_MASK_I6_Pos                              6
#define SGPIO_MASK_I_MASK_I6_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I6_Pos)
#define SGPIO_MASK_I_MASK_I7_Pos                              7
#define SGPIO_MASK_I_MASK_I7_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I7_Pos)
#define SGPIO_MASK_I_MASK_I8_Pos                              8
#define SGPIO_MASK_I_MASK_I8_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I8_Pos)
#define SGPIO_MASK_I_MASK_I9_Pos                              9
#define SGPIO_MASK_I_MASK_I9_Msk                              (0x01UL << SGPIO_MASK_I_MASK_I9_Pos)
#define SGPIO_MASK_I_MASK_I10_Pos                             10
#define SGPIO_MASK_I_MASK_I10_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I10_Pos)
#define SGPIO_MASK_I_MASK_I11_Pos                             11
#define SGPIO_MASK_I_MASK_I11_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I11_Pos)
#define SGPIO_MASK_I_MASK_I12_Pos                             12
#define SGPIO_MASK_I_MASK_I12_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I12_Pos)
#define SGPIO_MASK_I_MASK_I13_Pos                             13
#define SGPIO_MASK_I_MASK_I13_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I13_Pos)
#define SGPIO_MASK_I_MASK_I14_Pos                             14
#define SGPIO_MASK_I_MASK_I14_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I14_Pos)
#define SGPIO_MASK_I_MASK_I15_Pos                             15
#define SGPIO_MASK_I_MASK_I15_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I15_Pos)
#define SGPIO_MASK_I_MASK_I16_Pos                             16
#define SGPIO_MASK_I_MASK_I16_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I16_Pos)
#define SGPIO_MASK_I_MASK_I17_Pos                             17
#define SGPIO_MASK_I_MASK_I17_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I17_Pos)
#define SGPIO_MASK_I_MASK_I18_Pos                             18
#define SGPIO_MASK_I_MASK_I18_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I18_Pos)
#define SGPIO_MASK_I_MASK_I19_Pos                             19
#define SGPIO_MASK_I_MASK_I19_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I19_Pos)
#define SGPIO_MASK_I_MASK_I20_Pos                             20
#define SGPIO_MASK_I_MASK_I20_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I20_Pos)
#define SGPIO_MASK_I_MASK_I21_Pos                             21
#define SGPIO_MASK_I_MASK_I21_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I21_Pos)
#define SGPIO_MASK_I_MASK_I22_Pos                             22
#define SGPIO_MASK_I_MASK_I22_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I22_Pos)
#define SGPIO_MASK_I_MASK_I23_Pos                             23
#define SGPIO_MASK_I_MASK_I23_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I23_Pos)
#define SGPIO_MASK_I_MASK_I24_Pos                             24
#define SGPIO_MASK_I_MASK_I24_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I24_Pos)
#define SGPIO_MASK_I_MASK_I25_Pos                             25
#define SGPIO_MASK_I_MASK_I25_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I25_Pos)
#define SGPIO_MASK_I_MASK_I26_Pos                             26
#define SGPIO_MASK_I_MASK_I26_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I26_Pos)
#define SGPIO_MASK_I_MASK_I27_Pos                             27
#define SGPIO_MASK_I_MASK_I27_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I27_Pos)
#define SGPIO_MASK_I_MASK_I28_Pos                             28
#define SGPIO_MASK_I_MASK_I28_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I28_Pos)
#define SGPIO_MASK_I_MASK_I29_Pos                             29
#define SGPIO_MASK_I_MASK_I29_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I29_Pos)
#define SGPIO_MASK_I_MASK_I30_Pos                             30
#define SGPIO_MASK_I_MASK_I30_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I30_Pos)
#define SGPIO_MASK_I_MASK_I31_Pos                             31
#define SGPIO_MASK_I_MASK_I31_Msk                             (0x01UL << SGPIO_MASK_I_MASK_I31_Pos)

// --------------------------------------  SGPIO_MASK_P  ------------------------------------------
#define SGPIO_MASK_P_MASK_P0_Pos                              0
#define SGPIO_MASK_P_MASK_P0_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P0_Pos)
#define SGPIO_MASK_P_MASK_P1_Pos                              1
#define SGPIO_MASK_P_MASK_P1_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P1_Pos)
#define SGPIO_MASK_P_MASK_P2_Pos                              2
#define SGPIO_MASK_P_MASK_P2_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P2_Pos)
#define SGPIO_MASK_P_MASK_P3_Pos                              3
#define SGPIO_MASK_P_MASK_P3_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P3_Pos)
#define SGPIO_MASK_P_MASK_P4_Pos                              4
#define SGPIO_MASK_P_MASK_P4_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P4_Pos)
#define SGPIO_MASK_P_MASK_P5_Pos                              5
#define SGPIO_MASK_P_MASK_P5_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P5_Pos)
#define SGPIO_MASK_P_MASK_P6_Pos                              6
#define SGPIO_MASK_P_MASK_P6_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P6_Pos)
#define SGPIO_MASK_P_MASK_P7_Pos                              7
#define SGPIO_MASK_P_MASK_P7_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P7_Pos)
#define SGPIO_MASK_P_MASK_P8_Pos                              8
#define SGPIO_MASK_P_MASK_P8_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P8_Pos)
#define SGPIO_MASK_P_MASK_P9_Pos                              9
#define SGPIO_MASK_P_MASK_P9_Msk                              (0x01UL << SGPIO_MASK_P_MASK_P9_Pos)
#define SGPIO_MASK_P_MASK_P10_Pos                             10
#define SGPIO_MASK_P_MASK_P10_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P10_Pos)
#define SGPIO_MASK_P_MASK_P11_Pos                             11
#define SGPIO_MASK_P_MASK_P11_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P11_Pos)
#define SGPIO_MASK_P_MASK_P12_Pos                             12
#define SGPIO_MASK_P_MASK_P12_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P12_Pos)
#define SGPIO_MASK_P_MASK_P13_Pos                             13
#define SGPIO_MASK_P_MASK_P13_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P13_Pos)
#define SGPIO_MASK_P_MASK_P14_Pos                             14
#define SGPIO_MASK_P_MASK_P14_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P14_Pos)
#define SGPIO_MASK_P_MASK_P15_Pos                             15
#define SGPIO_MASK_P_MASK_P15_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P15_Pos)
#define SGPIO_MASK_P_MASK_P16_Pos                             16
#define SGPIO_MASK_P_MASK_P16_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P16_Pos)
#define SGPIO_MASK_P_MASK_P17_Pos                             17
#define SGPIO_MASK_P_MASK_P17_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P17_Pos)
#define SGPIO_MASK_P_MASK_P18_Pos                             18
#define SGPIO_MASK_P_MASK_P18_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P18_Pos)
#define SGPIO_MASK_P_MASK_P19_Pos                             19
#define SGPIO_MASK_P_MASK_P19_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P19_Pos)
#define SGPIO_MASK_P_MASK_P20_Pos                             20
#define SGPIO_MASK_P_MASK_P20_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P20_Pos)
#define SGPIO_MASK_P_MASK_P21_Pos                             21
#define SGPIO_MASK_P_MASK_P21_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P21_Pos)
#define SGPIO_MASK_P_MASK_P22_Pos                             22
#define SGPIO_MASK_P_MASK_P22_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P22_Pos)
#define SGPIO_MASK_P_MASK_P23_Pos                             23
#define SGPIO_MASK_P_MASK_P23_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P23_Pos)
#define SGPIO_MASK_P_MASK_P24_Pos                             24
#define SGPIO_MASK_P_MASK_P24_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P24_Pos)
#define SGPIO_MASK_P_MASK_P25_Pos                             25
#define SGPIO_MASK_P_MASK_P25_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P25_Pos)
#define SGPIO_MASK_P_MASK_P26_Pos                             26
#define SGPIO_MASK_P_MASK_P26_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P26_Pos)
#define SGPIO_MASK_P_MASK_P27_Pos                             27
#define SGPIO_MASK_P_MASK_P27_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P27_Pos)
#define SGPIO_MASK_P_MASK_P28_Pos                             28
#define SGPIO_MASK_P_MASK_P28_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P28_Pos)
#define SGPIO_MASK_P_MASK_P29_Pos                             29
#define SGPIO_MASK_P_MASK_P29_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P29_Pos)
#define SGPIO_MASK_P_MASK_P30_Pos                             30
#define SGPIO_MASK_P_MASK_P30_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P30_Pos)
#define SGPIO_MASK_P_MASK_P31_Pos                             31
#define SGPIO_MASK_P_MASK_P31_Msk                             (0x01UL << SGPIO_MASK_P_MASK_P31_Pos)

// ------------------------------------  SGPIO_GPIO_INREG  ----------------------------------------
#define SGPIO_GPIO_INREG_GPIO_IN0_Pos                         0
#define SGPIO_GPIO_INREG_GPIO_IN0_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN1_Pos                         1
#define SGPIO_GPIO_INREG_GPIO_IN1_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN2_Pos                         2
#define SGPIO_GPIO_INREG_GPIO_IN2_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN3_Pos                         3
#define SGPIO_GPIO_INREG_GPIO_IN3_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN4_Pos                         4
#define SGPIO_GPIO_INREG_GPIO_IN4_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN5_Pos                         5
#define SGPIO_GPIO_INREG_GPIO_IN5_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN6_Pos                         6
#define SGPIO_GPIO_INREG_GPIO_IN6_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN7_Pos                         7
#define SGPIO_GPIO_INREG_GPIO_IN7_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN8_Pos                         8
#define SGPIO_GPIO_INREG_GPIO_IN8_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN9_Pos                         9
#define SGPIO_GPIO_INREG_GPIO_IN9_Msk                         (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN10_Pos                        10
#define SGPIO_GPIO_INREG_GPIO_IN10_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN11_Pos                        11
#define SGPIO_GPIO_INREG_GPIO_IN11_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN12_Pos                        12
#define SGPIO_GPIO_INREG_GPIO_IN12_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN13_Pos                        13
#define SGPIO_GPIO_INREG_GPIO_IN13_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN14_Pos                        14
#define SGPIO_GPIO_INREG_GPIO_IN14_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos)
#define SGPIO_GPIO_INREG_GPIO_IN15_Pos                        15
#define SGPIO_GPIO_INREG_GPIO_IN15_Msk                        (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos)

// ------------------------------------  SGPIO_GPIO_OUTREG  ---------------------------------------
#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos                       0
#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos                       1
#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos                       2
#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos                       3
#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos                       4
#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos                       5
#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos                       6
#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos                       7
#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos                       8
#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos                       9
#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk                       (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos                      10
#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos                      11
#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos                      12
#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos                      13
#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos                      14
#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos)
#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos                      15
#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk                      (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos)

// ------------------------------------  SGPIO_GPIO_OENREG  ---------------------------------------
#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos                        0
#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos                        1
#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos                        2
#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos                        3
#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos                        4
#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos                        5
#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos                        6
#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos                        7
#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos                        8
#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos                        9
#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk                        (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos                       10
#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos                       11
#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos                       12
#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos                       13
#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos                       14
#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos)
#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos                       15
#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk                       (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos)

// -----------------------------------  SGPIO_CTRL_ENABLED  ---------------------------------------
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos                  0
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos                  1
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos                  2
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos                  3
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos                  4
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos                  5
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos                  6
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos                  7
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos                  8
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos                  9
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk                  (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos                 10
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos                 11
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos                 12
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos                 13
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos                 14
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos)
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos                 15
#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk                 (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos)

// -----------------------------------  SGPIO_CTRL_DISABLED  --------------------------------------
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos               0
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos               1
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos               2
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos               3
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos               4
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos               5
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos               6
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos               7
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos               8
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos               9
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk               (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos              10
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos              11
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos              12
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos              13
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos              14
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos)
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos              15
#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk              (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos)

// -------------------------------------  SGPIO_CLR_EN_0  -----------------------------------------
#define SGPIO_CLR_EN_0_CLR_SCI0_Pos                           0
#define SGPIO_CLR_EN_0_CLR_SCI0_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI1_Pos                           1
#define SGPIO_CLR_EN_0_CLR_SCI1_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI2_Pos                           2
#define SGPIO_CLR_EN_0_CLR_SCI2_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI3_Pos                           3
#define SGPIO_CLR_EN_0_CLR_SCI3_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI4_Pos                           4
#define SGPIO_CLR_EN_0_CLR_SCI4_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI5_Pos                           5
#define SGPIO_CLR_EN_0_CLR_SCI5_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI6_Pos                           6
#define SGPIO_CLR_EN_0_CLR_SCI6_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI7_Pos                           7
#define SGPIO_CLR_EN_0_CLR_SCI7_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI8_Pos                           8
#define SGPIO_CLR_EN_0_CLR_SCI8_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI9_Pos                           9
#define SGPIO_CLR_EN_0_CLR_SCI9_Msk                           (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI10_Pos                          10
#define SGPIO_CLR_EN_0_CLR_SCI10_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI11_Pos                          11
#define SGPIO_CLR_EN_0_CLR_SCI11_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI12_Pos                          12
#define SGPIO_CLR_EN_0_CLR_SCI12_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI13_Pos                          13
#define SGPIO_CLR_EN_0_CLR_SCI13_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI14_Pos                          14
#define SGPIO_CLR_EN_0_CLR_SCI14_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos)
#define SGPIO_CLR_EN_0_CLR_SCI15_Pos                          15
#define SGPIO_CLR_EN_0_CLR_SCI15_Msk                          (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos)

// -------------------------------------  SGPIO_SET_EN_0  -----------------------------------------
#define SGPIO_SET_EN_0_SET_SCI0_Pos                           0
#define SGPIO_SET_EN_0_SET_SCI0_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos)
#define SGPIO_SET_EN_0_SET_SCI1_Pos                           1
#define SGPIO_SET_EN_0_SET_SCI1_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos)
#define SGPIO_SET_EN_0_SET_SCI2_Pos                           2
#define SGPIO_SET_EN_0_SET_SCI2_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos)
#define SGPIO_SET_EN_0_SET_SCI3_Pos                           3
#define SGPIO_SET_EN_0_SET_SCI3_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos)
#define SGPIO_SET_EN_0_SET_SCI4_Pos                           4
#define SGPIO_SET_EN_0_SET_SCI4_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos)
#define SGPIO_SET_EN_0_SET_SCI5_Pos                           5
#define SGPIO_SET_EN_0_SET_SCI5_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos)
#define SGPIO_SET_EN_0_SET_SCI6_Pos                           6
#define SGPIO_SET_EN_0_SET_SCI6_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos)
#define SGPIO_SET_EN_0_SET_SCI7_Pos                           7
#define SGPIO_SET_EN_0_SET_SCI7_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos)
#define SGPIO_SET_EN_0_SET_SCI8_Pos                           8
#define SGPIO_SET_EN_0_SET_SCI8_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos)
#define SGPIO_SET_EN_0_SET_SCI9_Pos                           9
#define SGPIO_SET_EN_0_SET_SCI9_Msk                           (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos)
#define SGPIO_SET_EN_0_SET_SCI10_Pos                          10
#define SGPIO_SET_EN_0_SET_SCI10_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos)
#define SGPIO_SET_EN_0_SET_SCI11_Pos                          11
#define SGPIO_SET_EN_0_SET_SCI11_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos)
#define SGPIO_SET_EN_0_SET_SCI12_Pos                          12
#define SGPIO_SET_EN_0_SET_SCI12_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos)
#define SGPIO_SET_EN_0_SET_SCI13_Pos                          13
#define SGPIO_SET_EN_0_SET_SCI13_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos)
#define SGPIO_SET_EN_0_SET_SCI14_Pos                          14
#define SGPIO_SET_EN_0_SET_SCI14_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos)
#define SGPIO_SET_EN_0_SET_SCI15_Pos                          15
#define SGPIO_SET_EN_0_SET_SCI15_Msk                          (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos)

// -------------------------------------  SGPIO_ENABLE_0  -----------------------------------------
#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos                        0
#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos                        1
#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos                        2
#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos                        3
#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos                        4
#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos                        5
#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos                        6
#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos                        7
#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos                        8
#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos                        9
#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk                        (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos                       10
#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos                       11
#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos                       12
#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos                       13
#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos                       14
#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos)
#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos                       15
#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk                       (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos)

// -------------------------------------  SGPIO_STATUS_0  -----------------------------------------
#define SGPIO_STATUS_0_STATUS_SCI0_Pos                        0
#define SGPIO_STATUS_0_STATUS_SCI0_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos)
#define SGPIO_STATUS_0_STATUS_SCI1_Pos                        1
#define SGPIO_STATUS_0_STATUS_SCI1_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos)
#define SGPIO_STATUS_0_STATUS_SCI2_Pos                        2
#define SGPIO_STATUS_0_STATUS_SCI2_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos)
#define SGPIO_STATUS_0_STATUS_SCI3_Pos                        3
#define SGPIO_STATUS_0_STATUS_SCI3_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos)
#define SGPIO_STATUS_0_STATUS_SCI4_Pos                        4
#define SGPIO_STATUS_0_STATUS_SCI4_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos)
#define SGPIO_STATUS_0_STATUS_SCI5_Pos                        5
#define SGPIO_STATUS_0_STATUS_SCI5_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos)
#define SGPIO_STATUS_0_STATUS_SCI6_Pos                        6
#define SGPIO_STATUS_0_STATUS_SCI6_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos)
#define SGPIO_STATUS_0_STATUS_SCI7_Pos                        7
#define SGPIO_STATUS_0_STATUS_SCI7_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos)
#define SGPIO_STATUS_0_STATUS_SCI8_Pos                        8
#define SGPIO_STATUS_0_STATUS_SCI8_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos)
#define SGPIO_STATUS_0_STATUS_SCI9_Pos                        9
#define SGPIO_STATUS_0_STATUS_SCI9_Msk                        (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos)
#define SGPIO_STATUS_0_STATUS_SCI10_Pos                       10
#define SGPIO_STATUS_0_STATUS_SCI10_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos)
#define SGPIO_STATUS_0_STATUS_SCI11_Pos                       11
#define SGPIO_STATUS_0_STATUS_SCI11_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos)
#define SGPIO_STATUS_0_STATUS_SCI12_Pos                       12
#define SGPIO_STATUS_0_STATUS_SCI12_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos)
#define SGPIO_STATUS_0_STATUS_SCI13_Pos                       13
#define SGPIO_STATUS_0_STATUS_SCI13_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos)
#define SGPIO_STATUS_0_STATUS_SCI14_Pos                       14
#define SGPIO_STATUS_0_STATUS_SCI14_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos)
#define SGPIO_STATUS_0_STATUS_SCI15_Pos                       15
#define SGPIO_STATUS_0_STATUS_SCI15_Msk                       (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos)

// -----------------------------------  SGPIO_CTR_STATUS_0  ---------------------------------------
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos                0
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos                1
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos                2
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos                3
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos                4
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos                5
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos                6
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos                7
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos                8
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos                9
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos               10
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos               11
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos               12
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos               13
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos               14
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos)
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos               15
#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos)

// -----------------------------------  SGPIO_SET_STATUS_0  ---------------------------------------
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos                0
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos                1
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos                2
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos                3
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos                4
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos                5
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos                6
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos                7
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos                8
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos                9
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk                (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos               10
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos               11
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos               12
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos               13
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos               14
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos)
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos               15
#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk               (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos)

// -------------------------------------  SGPIO_CLR_EN_1  -----------------------------------------
#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos                        0
#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos                        1
#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos                        2
#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos                        3
#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos                        4
#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos                        5
#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos                        6
#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos                        7
#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos                        8
#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos                        9
#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk                        (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos                       10
#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos                       11
#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos                       12
#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos                       13
#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos                       14
#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos)
#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos                       15
#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk                       (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos)

// -------------------------------------  SGPIO_SET_EN_1  -----------------------------------------
#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos                        0
#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos                        1
#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos                        2
#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos                        3
#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos                        4
#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos                        5
#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos                        6
#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos                        7
#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos                        8
#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos                        9
#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk                        (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos                       10
#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos                       11
#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos                       12
#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos                       13
#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos                       14
#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos)
#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos                       15
#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk                       (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos)

// -------------------------------------  SGPIO_ENABLE_1  -----------------------------------------
#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos                        0
#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos                        1
#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos                        2
#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos                        3
#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos                        4
#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos                        5
#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos                        6
#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos                        7
#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos                        8
#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos                        9
#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk                        (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos                       10
#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos                       11
#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos                       12
#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos                       13
#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos                       14
#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos)
#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos                       15
#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk                       (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos)

// -------------------------------------  SGPIO_STATUS_1  -----------------------------------------
#define SGPIO_STATUS_1_STATUS_CCI0_Pos                        0
#define SGPIO_STATUS_1_STATUS_CCI0_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos)
#define SGPIO_STATUS_1_STATUS_CCI1_Pos                        1
#define SGPIO_STATUS_1_STATUS_CCI1_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos)
#define SGPIO_STATUS_1_STATUS_CCI2_Pos                        2
#define SGPIO_STATUS_1_STATUS_CCI2_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos)
#define SGPIO_STATUS_1_STATUS_CCI3_Pos                        3
#define SGPIO_STATUS_1_STATUS_CCI3_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos)
#define SGPIO_STATUS_1_STATUS_CCI4_Pos                        4
#define SGPIO_STATUS_1_STATUS_CCI4_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos)
#define SGPIO_STATUS_1_STATUS_CCI5_Pos                        5
#define SGPIO_STATUS_1_STATUS_CCI5_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos)
#define SGPIO_STATUS_1_STATUS_CCI6_Pos                        6
#define SGPIO_STATUS_1_STATUS_CCI6_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos)
#define SGPIO_STATUS_1_STATUS_CCI7_Pos                        7
#define SGPIO_STATUS_1_STATUS_CCI7_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos)
#define SGPIO_STATUS_1_STATUS_CCI8_Pos                        8
#define SGPIO_STATUS_1_STATUS_CCI8_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos)
#define SGPIO_STATUS_1_STATUS_CCI9_Pos                        9
#define SGPIO_STATUS_1_STATUS_CCI9_Msk                        (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos)
#define SGPIO_STATUS_1_STATUS_CCI10_Pos                       10
#define SGPIO_STATUS_1_STATUS_CCI10_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos)
#define SGPIO_STATUS_1_STATUS_CCI11_Pos                       11
#define SGPIO_STATUS_1_STATUS_CCI11_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos)
#define SGPIO_STATUS_1_STATUS_CCI12_Pos                       12
#define SGPIO_STATUS_1_STATUS_CCI12_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos)
#define SGPIO_STATUS_1_STATUS_CCI13_Pos                       13
#define SGPIO_STATUS_1_STATUS_CCI13_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos)
#define SGPIO_STATUS_1_STATUS_CCI14_Pos                       14
#define SGPIO_STATUS_1_STATUS_CCI14_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos)
#define SGPIO_STATUS_1_STATUS_CCI15_Pos                       15
#define SGPIO_STATUS_1_STATUS_CCI15_Msk                       (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos)

// -----------------------------------  SGPIO_CTR_STATUS_1  ---------------------------------------
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos                0
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos                1
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos                2
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos                3
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos                4
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos                5
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos                6
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos                7
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos                8
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos                9
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos               10
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos               11
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos               12
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos               13
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos               14
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos)
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos               15
#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos)

// -----------------------------------  SGPIO_SET_STATUS_1  ---------------------------------------
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos                0
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos                1
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos                2
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos                3
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos                4
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos                5
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos                6
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos                7
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos                8
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos                9
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk                (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos               10
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos               11
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos               12
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos               13
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos               14
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos)
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos               15
#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk               (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos)

// -------------------------------------  SGPIO_CLR_EN_2  -----------------------------------------
#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos                       0
#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos                       1
#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos                       2
#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos                       3
#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos                       4
#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos                       5
#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos                       6
#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos                       7
#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos                       8
#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos                       9
#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk                       (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos                      10
#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos                      11
#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos                      12
#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos                      13
#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos                      14
#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos)
#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos                      15
#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk                      (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos)

// -------------------------------------  SGPIO_SET_EN_2  -----------------------------------------
#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos                        0
#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos                        1
#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos                        2
#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos                        3
#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos                        4
#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos                        5
#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos                        6
#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos                        7
#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos                        8
#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos                        9
#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk                        (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos                       10
#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos                       11
#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos                       12
#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos                       13
#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos                       14
#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos)
#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos                       15
#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk                       (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos)

// -------------------------------------  SGPIO_ENABLE_2  -----------------------------------------
#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos                        0
#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos                        1
#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos                        2
#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos                        3
#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos                        4
#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos                        5
#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos                        6
#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos                        7
#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos                        8
#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos                        9
#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk                        (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos                       10
#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos                       11
#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos                       12
#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos                       13
#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos                       14
#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos)
#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos                       15
#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk                       (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos)

// -------------------------------------  SGPIO_STATUS_2  -----------------------------------------
#define SGPIO_STATUS_2_STATUS_PMI0_Pos                        0
#define SGPIO_STATUS_2_STATUS_PMI0_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos)
#define SGPIO_STATUS_2_STATUS_PMI1_Pos                        1
#define SGPIO_STATUS_2_STATUS_PMI1_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos)
#define SGPIO_STATUS_2_STATUS_PMI2_Pos                        2
#define SGPIO_STATUS_2_STATUS_PMI2_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos)
#define SGPIO_STATUS_2_STATUS_PMI3_Pos                        3
#define SGPIO_STATUS_2_STATUS_PMI3_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos)
#define SGPIO_STATUS_2_STATUS_PMI4_Pos                        4
#define SGPIO_STATUS_2_STATUS_PMI4_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos)
#define SGPIO_STATUS_2_STATUS_PMI5_Pos                        5
#define SGPIO_STATUS_2_STATUS_PMI5_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos)
#define SGPIO_STATUS_2_STATUS_PMI6_Pos                        6
#define SGPIO_STATUS_2_STATUS_PMI6_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos)
#define SGPIO_STATUS_2_STATUS_PMI7_Pos                        7
#define SGPIO_STATUS_2_STATUS_PMI7_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos)
#define SGPIO_STATUS_2_STATUS_PMI8_Pos                        8
#define SGPIO_STATUS_2_STATUS_PMI8_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos)
#define SGPIO_STATUS_2_STATUS_PMI9_Pos                        9
#define SGPIO_STATUS_2_STATUS_PMI9_Msk                        (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos)
#define SGPIO_STATUS_2_STATUS_PMI10_Pos                       10
#define SGPIO_STATUS_2_STATUS_PMI10_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos)
#define SGPIO_STATUS_2_STATUS_PMI11_Pos                       11
#define SGPIO_STATUS_2_STATUS_PMI11_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos)
#define SGPIO_STATUS_2_STATUS_PMI12_Pos                       12
#define SGPIO_STATUS_2_STATUS_PMI12_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos)
#define SGPIO_STATUS_2_STATUS_PMI13_Pos                       13
#define SGPIO_STATUS_2_STATUS_PMI13_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos)
#define SGPIO_STATUS_2_STATUS_PMI14_Pos                       14
#define SGPIO_STATUS_2_STATUS_PMI14_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos)
#define SGPIO_STATUS_2_STATUS_PMI15_Pos                       15
#define SGPIO_STATUS_2_STATUS_PMI15_Msk                       (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos)

// -----------------------------------  SGPIO_CTR_STATUS_2  ---------------------------------------
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos                0
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos                1
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos                2
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos                3
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos                4
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos                5
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos                6
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos                7
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos                8
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos                9
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos               10
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos               11
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos               12
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos               13
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos               14
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos)
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos               15
#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos)

// -----------------------------------  SGPIO_SET_STATUS_2  ---------------------------------------
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos                0
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos                1
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos                2
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos                3
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos                4
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos                5
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos                6
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos                7
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos                8
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos                9
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk                (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos               10
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos               11
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos               12
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos               13
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos               14
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos)
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos               15
#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk               (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos)

// -------------------------------------  SGPIO_CLR_EN_3  -----------------------------------------
#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos                       0
#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos                       1
#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos                       2
#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos                       3
#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos                       4
#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos                       5
#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos                       6
#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos                       7
#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos                       8
#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos                       9
#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk                       (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos                      10
#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos                      11
#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos                      12
#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos                      13
#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos                      14
#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos)
#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos                      15
#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk                      (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos)

// -------------------------------------  SGPIO_SET_EN_3  -----------------------------------------
#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos                       0
#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos                       1
#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos                       2
#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos                       3
#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos                       4
#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos                       5
#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos                       6
#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos                       7
#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos                       8
#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos                       9
#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk                       (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos                      10
#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos                      11
#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos                      12
#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos                      13
#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos                      14
#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos)
#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos                      15
#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk                      (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos)

// -------------------------------------  SGPIO_ENABLE_3  -----------------------------------------
#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos                      0
#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos                      1
#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos                      2
#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos                      3
#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos                      4
#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos                      5
#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos                      6
#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos                      7
#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos                      8
#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos                      9
#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk                      (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos                     10
#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos                     11
#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos                     12
#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos                     13
#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos                     14
#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos)
#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos                     15
#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk                     (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos)

// -------------------------------------  SGPIO_STATUS_3  -----------------------------------------
#define SGPIO_STATUS_3_STATUS_INPI0_Pos                       0
#define SGPIO_STATUS_3_STATUS_INPI0_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos)
#define SGPIO_STATUS_3_STATUS_INPI1_Pos                       1
#define SGPIO_STATUS_3_STATUS_INPI1_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos)
#define SGPIO_STATUS_3_STATUS_INPI2_Pos                       2
#define SGPIO_STATUS_3_STATUS_INPI2_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos)
#define SGPIO_STATUS_3_STATUS_INPI3_Pos                       3
#define SGPIO_STATUS_3_STATUS_INPI3_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos)
#define SGPIO_STATUS_3_STATUS_INPI4_Pos                       4
#define SGPIO_STATUS_3_STATUS_INPI4_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos)
#define SGPIO_STATUS_3_STATUS_INPI5_Pos                       5
#define SGPIO_STATUS_3_STATUS_INPI5_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos)
#define SGPIO_STATUS_3_STATUS_INPI6_Pos                       6
#define SGPIO_STATUS_3_STATUS_INPI6_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos)
#define SGPIO_STATUS_3_STATUS_INPI7_Pos                       7
#define SGPIO_STATUS_3_STATUS_INPI7_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos)
#define SGPIO_STATUS_3_STATUS_INPI8_Pos                       8
#define SGPIO_STATUS_3_STATUS_INPI8_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos)
#define SGPIO_STATUS_3_STATUS_INPI9_Pos                       9
#define SGPIO_STATUS_3_STATUS_INPI9_Msk                       (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos)
#define SGPIO_STATUS_3_STATUS_INPI10_Pos                      10
#define SGPIO_STATUS_3_STATUS_INPI10_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos)
#define SGPIO_STATUS_3_STATUS_INPI11_Pos                      11
#define SGPIO_STATUS_3_STATUS_INPI11_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos)
#define SGPIO_STATUS_3_STATUS_INPI12_Pos                      12
#define SGPIO_STATUS_3_STATUS_INPI12_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos)
#define SGPIO_STATUS_3_STATUS_INPI13_Pos                      13
#define SGPIO_STATUS_3_STATUS_INPI13_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos)
#define SGPIO_STATUS_3_STATUS_INPI14_Pos                      14
#define SGPIO_STATUS_3_STATUS_INPI14_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos)
#define SGPIO_STATUS_3_STATUS_INPI15_Pos                      15
#define SGPIO_STATUS_3_STATUS_INPI15_Msk                      (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos)

// -----------------------------------  SGPIO_CTR_STATUS_3  ---------------------------------------
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos               0
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos               1
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos               2
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos               3
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos               4
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos               5
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos               6
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos               7
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos               8
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos               9
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos              10
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos              11
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos              12
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos              13
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos              14
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos)
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos              15
#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos)

// -----------------------------------  SGPIO_SET_STATUS_3  ---------------------------------------
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos               0
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos               1
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos               2
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos               3
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos               4
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos               5
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos               6
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos               7
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos               8
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos               9
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk               (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos              10
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos              11
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos              12
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos              13
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos              14
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos)
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos              15
#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk              (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos)

#endif

// ------------------------------------------------------------------------------------------------
// -----                                 Peripheral memory map                                -----
// ------------------------------------------------------------------------------------------------

#define LPC_SCT_BASE              0x40000000
#define LPC_GPDMA_BASE            0x40002000
#define LPC_SDMMC_BASE            0x40004000
#define LPC_EMC_BASE              0x40005000
#define LPC_USB0_BASE             0x40006000
#define LPC_USB1_BASE             0x40007000
#define LPC_LCD_BASE              0x40008000
#define LPC_ETHERNET_BASE         0x40010000
#define LPC_ATIMER_BASE           0x40040000
#define LPC_REGFILE_BASE          0x40041000
#define LPC_PMC_BASE              0x40042000
#define LPC_CREG_BASE             0x40043000
#define LPC_EVENTROUTER_BASE      0x40044000
#define LPC_RTC_BASE              0x40046000
#define LPC_CGU_BASE              0x40050000
#define LPC_CCU1_BASE             0x40051000
#define LPC_CCU2_BASE             0x40052000
#define LPC_RGU_BASE              0x40053000
#define LPC_WWDT_BASE             0x40080000
#define LPC_USART0_BASE           0x40081000
#define LPC_USART2_BASE           0x400C1000
#define LPC_USART3_BASE           0x400C2000
#define LPC_UART1_BASE            0x40082000
#define LPC_SSP0_BASE             0x40083000
#define LPC_SSP1_BASE             0x400C5000
#define LPC_TIMER0_BASE           0x40084000
#define LPC_TIMER1_BASE           0x40085000
#define LPC_TIMER2_BASE           0x400C3000
#define LPC_TIMER3_BASE           0x400C4000
#define LPC_SCU_BASE              0x40086000
#define LPC_GPIO_PIN_INT_BASE     0x40087000
#define LPC_GPIO_GROUP_INT0_BASE  0x40088000
#define LPC_GPIO_GROUP_INT1_BASE  0x40089000
#define LPC_MCPWM_BASE            0x400A0000
#define LPC_I2C0_BASE             0x400A1000
#define LPC_I2C1_BASE             0x400E0000
#define LPC_I2S0_BASE             0x400A2000
#define LPC_I2S1_BASE             0x400A3000
#define LPC_C_CAN1_BASE           0x400A4000
#define LPC_RITIMER_BASE          0x400C0000
#define LPC_QEI_BASE              0x400C6000
#define LPC_GIMA_BASE             0x400C7000
#define LPC_DAC_BASE              0x400E1000
#define LPC_C_CAN0_BASE           0x400E2000
#define LPC_ADC0_BASE             0x400E3000
#define LPC_ADC1_BASE             0x400E4000
#define LPC_GPIO_PORT_BASE        0x400F4000
#define LPC_SPI_BASE              0x40100000
#define LPC_SGPIO_BASE            0x40101000


// ------------------------------------------------------------------------------------------------
// -----                                Peripheral declaration                                -----
// ------------------------------------------------------------------------------------------------

#define LPC_SCT                   ((LPC_SCT_Type            *) LPC_SCT_BASE)
#define LPC_GPDMA                 ((LPC_GPDMA_Type          *) LPC_GPDMA_BASE)
#define LPC_SDMMC                 ((LPC_SDMMC_Type          *) LPC_SDMMC_BASE)
#define LPC_EMC                   ((LPC_EMC_Type            *) LPC_EMC_BASE)
#define LPC_USB0                  ((LPC_USB0_Type           *) LPC_USB0_BASE)
#define LPC_USB1                  ((LPC_USB1_Type           *) LPC_USB1_BASE)
#define LPC_LCD                   ((LPC_LCD_Type            *) LPC_LCD_BASE)
#define LPC_ETHERNET              ((LPC_ETHERNET_Type       *) LPC_ETHERNET_BASE)
#define LPC_ATIMER                ((LPC_ATIMER_Type         *) LPC_ATIMER_BASE)
#define LPC_REGFILE               ((LPC_REGFILE_Type        *) LPC_REGFILE_BASE)
#define LPC_PMC                   ((LPC_PMC_Type            *) LPC_PMC_BASE)
#define LPC_CREG                  ((LPC_CREG_Type           *) LPC_CREG_BASE)
#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type    *) LPC_EVENTROUTER_BASE)
#define LPC_RTC                   ((LPC_RTC_Type            *) LPC_RTC_BASE)
#define LPC_CGU                   ((LPC_CGU_Type            *) LPC_CGU_BASE)
#define LPC_CCU1                  ((LPC_CCU1_Type           *) LPC_CCU1_BASE)
#define LPC_CCU2                  ((LPC_CCU2_Type           *) LPC_CCU2_BASE)
#define LPC_RGU                   ((LPC_RGU_Type            *) LPC_RGU_BASE)
#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
#define LPC_USART0                ((LPC_USARTn_Type         *) LPC_USART0_BASE)
#define LPC_USART2                ((LPC_USARTn_Type         *) LPC_USART2_BASE)
#define LPC_USART3                ((LPC_USARTn_Type         *) LPC_USART3_BASE)
#define LPC_UART1                 ((LPC_UART1_Type          *) LPC_UART1_BASE)
#define LPC_SSP0                  ((LPC_SSPn_Type           *) LPC_SSP0_BASE)
#define LPC_SSP1                  ((LPC_SSPn_Type           *) LPC_SSP1_BASE)
#define LPC_TIMER0                ((LPC_TIMERn_Type         *) LPC_TIMER0_BASE)
#define LPC_TIMER1                ((LPC_TIMERn_Type         *) LPC_TIMER1_BASE)
#define LPC_TIMER2                ((LPC_TIMERn_Type         *) LPC_TIMER2_BASE)
#define LPC_TIMER3                ((LPC_TIMERn_Type         *) LPC_TIMER3_BASE)
#define LPC_SCU                   ((LPC_SCU_Type            *) LPC_SCU_BASE)
#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_MCPWM                 ((LPC_MCPWM_Type          *) LPC_MCPWM_BASE)
#define LPC_I2C0                  ((LPC_I2Cn_Type           *) LPC_I2C0_BASE)
#define LPC_I2C1                  ((LPC_I2Cn_Type           *) LPC_I2C1_BASE)
#define LPC_I2S0                  ((LPC_I2Sn_Type           *) LPC_I2S0_BASE)
#define LPC_I2S1                  ((LPC_I2Sn_Type           *) LPC_I2S1_BASE)
#define LPC_C_CAN1                ((LPC_C_CANn_Type         *) LPC_C_CAN1_BASE)
#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
#define LPC_QEI                   ((LPC_QEI_Type            *) LPC_QEI_BASE)
#define LPC_GIMA                  ((LPC_GIMA_Type           *) LPC_GIMA_BASE)
#define LPC_DAC                   ((LPC_DAC_Type            *) LPC_DAC_BASE)
#define LPC_C_CAN0                ((LPC_C_CANn_Type         *) LPC_C_CAN0_BASE)
#define LPC_ADC0                  ((LPC_ADCn_Type           *) LPC_ADC0_BASE)
#define LPC_ADC1                  ((LPC_ADCn_Type           *) LPC_ADC1_BASE)
#define LPC_GPIO_PORT             ((LPC_GPIO_PORT_Type      *) LPC_GPIO_PORT_BASE)
#define LPC_SPI                   ((LPC_SPI_Type            *) LPC_SPI_BASE)
#define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)


/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group LPC43xx */
/** @} */ /* End of group (null) */

#ifdef __cplusplus
}
#endif


#endif  // __LPC43xx_H__

