/*******************************************************************************
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*******************************************************************************/
/*******************************************************************************
* File Name   : l1_cache_init.s
* $Rev: $
* $Date::                           $
* Description : L1 cache initialize
*******************************************************************************/

/******************************************************************************/
/* This code provides basic global enable for Cortex-A9 cache.                */
/* It also enables branch prediction                                          */
/* This code must be run from a privileged mode                               */
/******************************************************************************/
/*	AREA   INITCA9CACHE, CODE, READONLY */
	.text
	.code 32

	.global L1CacheInit

	.func L1CacheInit
L1CacheInit:

/******************************************************************************/
/* Enable caches                                                              */
/* Caches are controlled by the System Control Register:                      */
/******************************************************************************/
	MRC  p15, 0, r0, c1, c0, 0			              /* Read CP15 register 1 */
	ORR  r0, r0, #(0x1 << 12)			                    /* Enable I Cache */
	ORR  r0, r0, #(0x1 << 2)			                    /* Enable D Cache */
	MCR  p15, 0, r0, c1, c0, 0			             /* Write CP15 register 1 */

/******************************************************************************/
/* Enable Program Flow Prediction                                             */
/*                                                                            */
/* Branch prediction is controlled by the System Control Register:            */
/* Set Bit 11 to enable branch prediction and return                          */
/******************************************************************************/
	MRC  p15, 0, r0, c1, c0, 0		  	      /* Read System Control Register */
	ORR  r0, r0, #(0x1 << 11)
	MCR  p15, 0, r0, c1, c0, 0			     /* Write System Control Register */

/******************************************************************************/
/* Enable D-side prefetch                                                     */
/******************************************************************************/
	MRC  p15, 0, r0, c1, c0, 1			   /* Read Auxiliary Control Register */
	ORR  r0, r0, #(0x1 << 2)			     /* Enable Dside prefetch */
	MCR  p15, 0, r0, c1, c0, 1			/* Write Auxiliary Control Register */

	BX   lr

	.endfunc
	.align 4
	.end
