am335x_eth_driver.h
Go to the documentation of this file.
1 /**
2  * @file am335x_eth_driver.h
3  * @brief Sitara AM335x Gigabit Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _AM335X_ETH_DRIVER_H
32 #define _AM335X_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef AM335X_ETH_TX_BUFFER_COUNT
39  #define AM335X_ETH_TX_BUFFER_COUNT 16
40 #elif (AM335X_ETH_TX_BUFFER_COUNT < 1)
41  #error AM335X_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef AM335X_ETH_TX_BUFFER_SIZE
46  #define AM335X_ETH_TX_BUFFER_SIZE 1536
47 #elif (AM335X_ETH_TX_BUFFER_SIZE != 1536)
48  #error AM335X_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef AM335X_ETH_RX_BUFFER_COUNT
53  #define AM335X_ETH_RX_BUFFER_COUNT 16
54 #elif (AM335X_ETH_RX_BUFFER_COUNT < 1)
55  #error AM335X_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef AM335X_ETH_RX_BUFFER_SIZE
60  #define AM335X_ETH_RX_BUFFER_SIZE 1536
61 #elif (AM335X_ETH_RX_BUFFER_SIZE != 1536)
62  #error AM335X_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt priority
66 #ifndef AM335X_ETH_IRQ_PRIORITY
67  #define AM335X_ETH_IRQ_PRIORITY 1
68 #elif (AM335X_ETH_IRQ_PRIORITY < 0)
69  #error AM335X_ETH_IRQ_PRIORITY parameter is not valid
70 #endif
71 
72 //Name of the section where to place DMA buffers
73 #ifndef AM335X_ETH_RAM_SECTION
74  #define AM335X_ETH_RAM_SECTION ".ram_no_cache"
75 #endif
76 
77 //Name of the section where to place DMA descriptors
78 #ifndef AM335X_ETH_RAM_CPPI_SECTION
79  #define AM335X_ETH_RAM_CPPI_SECTION ".ram_cppi"
80 #endif
81 
82 //CPSW interrupts
83 #ifndef SYS_INT_3PGSWRXINT0
84  #define SYS_INT_3PGSWRXINT0 41
85 #endif
86 
87 #ifndef SYS_INT_3PGSWTXINT0
88  #define SYS_INT_3PGSWTXINT0 42
89 #endif
90 
91 //CPSW cores
92 #define CPSW_CORE0 0
93 #define CPSW_CORE1 1
94 #define CPSW_CORE2 2
95 
96 //CPSW ports
97 #define CPSW_PORT0 0
98 #define CPSW_PORT1 1
99 #define CPSW_PORT2 2
100 
101 //CPSW channels
102 #define CPSW_CH0 0
103 #define CPSW_CH1 1
104 #define CPSW_CH2 2
105 #define CPSW_CH3 3
106 #define CPSW_CH4 4
107 #define CPSW_CH5 5
108 #define CPSW_CH6 6
109 #define CPSW_CH7 7
110 
111 //PRCM registers
112 #define CM_PER_CPGMAC0_CLKCTRL_R HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
113 #define CM_PER_CPSW_CLKSTCTRL_R HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)
114 
115 //CONTROL registers
116 #define CONTROL_MAC_ID_LO_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(n))
117 #define CONTROL_MAC_ID_HI_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(n))
118 #define CONTROL_GMII_SEL_R HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL)
119 #define CONTROL_CONF_GPMC_A_R(n) HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(n))
120 #define CONTROL_CONF_MII1_COL_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL)
121 #define CONTROL_CONF_MII1_CRS_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS)
122 #define CONTROL_CONF_MII1_RXERR_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR)
123 #define CONTROL_CONF_MII1_TXEN_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN)
124 #define CONTROL_CONF_MII1_RXDV_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV)
125 #define CONTROL_CONF_MII1_TXD3_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3)
126 #define CONTROL_CONF_MII1_TXD2_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2)
127 #define CONTROL_CONF_MII1_TXD1_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1)
128 #define CONTROL_CONF_MII1_TXD0_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0)
129 #define CONTROL_CONF_MII1_TXCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK)
130 #define CONTROL_CONF_MII1_RXCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK)
131 #define CONTROL_CONF_MII1_RXD3_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3)
132 #define CONTROL_CONF_MII1_RXD2_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2)
133 #define CONTROL_CONF_MII1_RXD1_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1)
134 #define CONTROL_CONF_MII1_RXD0_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0)
135 #define CONTROL_CONF_RMII1_REFCLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK)
136 #define CONTROL_CONF_MDIO_DATA_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA)
137 #define CONTROL_CONF_MDIO_CLK_R HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK)
138 
139 //CPSW_ALE registers
140 #define CPSW_ALE_IDVER_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_IDVER)
141 #define CPSW_ALE_CTRL_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_CTRL)
142 #define CPSW_ALE_PRESCALE_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PRESCALE)
143 #define CPSW_ALE_UNKNOWN_VLAN_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_UNKNOWN_VLAN)
144 #define CPSW_ALE_TBLCTL_R HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLCTL)
145 #define CPSW_ALE_TBLW_R(n) HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLW(n))
146 #define CPSW_ALE_PORTCTL_R(n) HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PORTCTL(n))
147 
148 //CPSW_CPDMA registers
149 #define CPSW_CPDMA_TX_IDVER_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_IDVER)
150 #define CPSW_CPDMA_TX_CTRL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CTRL)
151 #define CPSW_CPDMA_TX_TEARDOWN_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_TEARDOWN)
152 #define CPSW_CPDMA_RX_IDVER_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_IDVER)
153 #define CPSW_CPDMA_RX_CTRL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CTRL)
154 #define CPSW_CPDMA_RX_TEARDOWN_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_TEARDOWN)
155 #define CPSW_CPDMA_SOFT_RESET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_SOFT_RESET)
156 #define CPSW_CPDMA_DMACONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMACONTROL)
157 #define CPSW_CPDMA_DMASTATUS_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMASTATUS)
158 #define CPSW_CPDMA_RX_BUFFER_OFFSET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_BUFFER_OFFSET)
159 #define CPSW_CPDMA_EMCONTROL_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EMCONTROL)
160 #define CPSW_CPDMA_TX_PRI_RATE_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_PRI_RATE(n))
161 #define CPSW_CPDMA_TX_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_RAW)
162 #define CPSW_CPDMA_TX_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_MASKED)
163 #define CPSW_CPDMA_TX_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_SET)
164 #define CPSW_CPDMA_TX_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_CLEAR)
165 #define CPSW_CPDMA_IN_VECTOR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_IN_VECTOR)
166 #define CPSW_CPDMA_EOI_VECTOR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EOI_VECTOR)
167 #define CPSW_CPDMA_RX_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_RAW)
168 #define CPSW_CPDMA_RX_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_MASKED)
169 #define CPSW_CPDMA_RX_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_SET)
170 #define CPSW_CPDMA_RX_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_CLEAR)
171 #define CPSW_CPDMA_DMA_INTSTAT_RAW_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_RAW)
172 #define CPSW_CPDMA_DMA_INTSTAT_MASKED_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_MASKED)
173 #define CPSW_CPDMA_DMA_INTMASK_SET_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_SET)
174 #define CPSW_CPDMA_DMA_INTMASK_CLEAR_R HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_CLEAR)
175 #define CPSW_CPDMA_RX_PENDTHRESH_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_PENDTHRESH(n))
176 #define CPSW_CPDMA_RX_FREEBUFFER_R(n) HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_FREEBUFFER(n))
177 #define CPSW_CPDMA_STATERAM_TX_HDP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + 0x200 + CPSW_CPDMA_STATERAM_TX_HDP(n))
178 #define CPSW_CPDMA_STATERAM_RX_HDP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + 0x200 + CPSW_CPDMA_STATERAM_RX_HDP(n))
179 #define CPSW_CPDMA_STATERAM_TX_CP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + 0x200 + CPSW_CPDMA_STATERAM_TX_CP(n))
180 #define CPSW_CPDMA_STATERAM_RX_CP_R(n) HWREG(SOC_CPSW_CPDMA_REGS + 0x200 + CPSW_CPDMA_STATERAM_RX_CP(n))
181 
182 //CPSW_PORT registers
183 #define CPSW_PORT0_CTRL_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_CTRL(0))
184 #define CPSW_PORT0_MAX_BLKS_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_MAX_BLKS(0))
185 #define CPSW_PORT0_BLK_CNT_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_BLK_CNT(0))
186 #define CPSW_PORT0_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_TX_IN_CTL(0))
187 #define CPSW_PORT0_VLAN_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_VLAN(0))
188 #define CPSW_PORT0_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_TX_PRI_MAP(0))
189 #define CPSW_PORT0_CPDMA_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P0_CPDMA_TX_PRI_MAP)
190 #define CPSW_PORT0_CPDMA_RX_CH_MAP_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P0_CPDMA_RX_CH_MAP)
191 #define CPSW_PORT0_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_RX_DSCP_PRI_MAP(0, n))
192 #define CPSW_PORT0_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_TS_SEQ_MTYPE(0))
193 #define CPSW_PORT0_SA_LO_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_SA_LO(0))
194 #define CPSW_PORT0_SA_HI_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_SA_HI(0))
195 #define CPSW_PORT0_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_P_SEND_PERCENT(0))
196 
197 #define CPSW_PORT1_CTRL_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_CTRL(0))
198 #define CPSW_PORT1_MAX_BLKS_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_MAX_BLKS(0))
199 #define CPSW_PORT1_BLK_CNT_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_BLK_CNT(0))
200 #define CPSW_PORT1_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_TX_IN_CTL(0))
201 #define CPSW_PORT1_VLAN_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_VLAN(0))
202 #define CPSW_PORT1_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_TX_PRI_MAP(0))
203 #define CPSW_PORT1_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_RX_DSCP_PRI_MAP(0, n))
204 #define CPSW_PORT1_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_TS_SEQ_MTYPE(0))
205 #define CPSW_PORT1_SA_LO_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_SA_LO(0))
206 #define CPSW_PORT1_SA_HI_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_SA_HI(0))
207 #define CPSW_PORT1_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_P_SEND_PERCENT(0))
208 
209 #define CPSW_PORT2_CTRL_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_CTRL(0))
210 #define CPSW_PORT2_MAX_BLKS_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_MAX_BLKS(0))
211 #define CPSW_PORT2_BLK_CNT_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_BLK_CNT(0))
212 #define CPSW_PORT2_TX_IN_CTL_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_TX_IN_CTL(0))
213 #define CPSW_PORT2_VLAN_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_VLAN(0))
214 #define CPSW_PORT2_TX_PRI_MAP_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_TX_PRI_MAP(0))
215 #define CPSW_PORT2_RX_DSCP_PRI_MAP_R(n) HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_RX_DSCP_PRI_MAP(0, n))
216 #define CPSW_PORT2_TS_SEQ_MTYPE_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_TS_SEQ_MTYPE(0))
217 #define CPSW_PORT2_SA_LO_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_SA_LO(0))
218 #define CPSW_PORT2_SA_HI_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_SA_HI(0))
219 #define CPSW_PORT2_SEND_PERCENT_R HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_P_SEND_PERCENT(0))
220 
221 //CPSW_SL registers
222 #define CPSW_SL1_IDVER_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_IDVER)
223 #define CPSW_SL1_MACCTRL_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACCTRL)
224 #define CPSW_SL1_MACSTS_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACSTS)
225 #define CPSW_SL1_SOFT_RESET_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_SOFT_RESET)
226 #define CPSW_SL1_RX_MAXLEN_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_MAXLEN)
227 #define CPSW_SL1_BOFFTEST_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_BOFFTEST)
228 #define CPSW_SL1_RX_PAUSE_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PAUSE)
229 #define CPSW_SL1_TX_PAUSE_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_PAUSE)
230 #define CPSW_SL1_EMCTRL_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_EMCTRL)
231 #define CPSW_SL1_RX_PRI_MAP_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PRI_MAP)
232 #define CPSW_SL1_TX_GAP_R HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_GAP)
233 
234 #define CPSW_SL2_IDVER_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_IDVER)
235 #define CPSW_SL2_MACCTRL_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACCTRL)
236 #define CPSW_SL2_MACSTS_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACSTS)
237 #define CPSW_SL2_SOFT_RESET_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_SOFT_RESET)
238 #define CPSW_SL2_RX_MAXLEN_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_MAXLEN)
239 #define CPSW_SL2_BOFFTEST_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_BOFFTEST)
240 #define CPSW_SL2_RX_PAUSE_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PAUSE)
241 #define CPSW_SL2_TX_PAUSE_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_PAUSE)
242 #define CPSW_SL2_EMCTRL_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_EMCTRL)
243 #define CPSW_SL2_RX_PRI_MAP_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PRI_MAP)
244 #define CPSW_SL2_TX_GAP_R HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_GAP)
245 
246 //CPSW_SS registers
247 #define CPSW_SS_ID_VER_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_ID_VER)
248 #define CPSW_SS_CTRL_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_CTRL)
249 #define CPSW_SS_SOFT_RESET_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_RESET)
250 #define CPSW_SS_STAT_PORT_EN_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_STAT_PORT_EN)
251 #define CPSW_SS_PTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_PTYPE)
252 #define CPSW_SS_SOFT_IDLE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_IDLE)
253 #define CPSW_SS_THRU_RATE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_THRU_RATE)
254 #define CPSW_SS_GAP_THRESH_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_GAP_THRESH)
255 #define CPSW_SS_TX_START_WDS_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TX_START_WDS)
256 #define CPSW_SS_FLOW_CTRL_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_FLOW_CTRL)
257 #define CPSW_SS_VLAN_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_VLAN_LTYPE)
258 #define CPSW_SS_TS_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TS_LTYPE)
259 #define CPSW_SS_DLR_LTYPE_R HWREG(SOC_CPSW_SS_REGS + CPSW_SS_DLR_LTYPE)
260 
261 //CPSW_WR registers
262 #define CPSW_WR_IDVER_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_IDVER)
263 #define CPSW_WR_SOFT_RESET_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_SOFT_RESET)
264 #define CPSW_WR_CTRL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_CTRL)
265 #define CPSW_WR_INT_CTRL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_INT_CTRL)
266 #define CPSW_WR_C_RX_THRESH_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_EN(n))
267 #define CPSW_WR_C_RX_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_EN(n))
268 #define CPSW_WR_C_TX_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_EN(n))
269 #define CPSW_WR_C_MISC_EN_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_EN(n))
270 #define CPSW_WR_C_RX_THRESH_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_STAT(n))
271 #define CPSW_WR_C_RX_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_STAT(n))
272 #define CPSW_WR_C_TX_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_STAT(n))
273 #define CPSW_WR_C_MISC_STAT_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_STAT(n))
274 #define CPSW_WR_C_RX_IMAX_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_IMAX(n))
275 #define CPSW_WR_C_TX_IMAX_R(n) HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_IMAX(n))
276 #define CPSW_WR_RGMII_CTL_R HWREG(SOC_CPSW_WR_REGS + CPSW_WR_RGMII_CTL)
277 
278 //MDIO registers
279 #define MDIO_REVID_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_REVID)
280 #define MDIO_CTRL_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_CTRL)
281 #define MDIO_ALIVE_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_ALIVE)
282 #define MDIO_LINK_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINK)
283 #define MDIO_LINKINTRAW_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTRAW)
284 #define MDIO_LINKINTMASKED_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTMASKED)
285 #define MDIO_USERINTRAW_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTRAW)
286 #define MDIO_USERINTMASKED_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKED)
287 #define MDIO_USERINTMASKSET_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKSET)
288 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKCLEAR)
289 #define MDIO_USERACCESS_R(n) HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS(n))
290 #define MDIO_USERPHYSEL_R(n) HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL(n))
291 
292 //GMII_SEL register
293 #define CONTROL_GMII_SEL_GMII2_SEL_MII 0x00000000
294 #define CONTROL_GMII_SEL_GMII2_SEL_RMII 0x00000004
295 #define CONTROL_GMII_SEL_GMII2_SEL_RGMII 0x00000008
296 #define CONTROL_GMII_SEL_GMII1_SEL_MII 0x00000000
297 #define CONTROL_GMII_SEL_GMII1_SEL_RMII 0x00000001
298 #define CONTROL_GMII_SEL_GMII1_SEL_RGMII 0x00000002
299 
300 //CPDMA_EOI_VECTOR register
301 #define CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE 0x00000000
302 #define CPSW_CPDMA_EOI_VECTOR_RX_PULSE 0x00000001
303 #define CPSW_CPDMA_EOI_VECTOR_TX_PULSE 0x00000002
304 #define CPSW_CPDMA_EOI_VECTOR_MISC_PULSE 0x00000003
305 
306 //CPSW_PORT_P_TX_IN_CTL register
307 #define CPSW_PORT_P_TX_IN_CTL_SEL_DUAL_MAC 0x00010000
308 
309 //TX buffer descriptor flags
310 #define CPSW_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
311 #define CPSW_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
312 #define CPSW_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
313 #define CPSW_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
314 #define CPSW_TX_WORD3_SOP 0x80000000
315 #define CPSW_TX_WORD3_EOP 0x40000000
316 #define CPSW_TX_WORD3_OWNER 0x20000000
317 #define CPSW_TX_WORD3_EOQ 0x10000000
318 #define CPSW_TX_WORD3_TDOWN_CMPLT 0x08000000
319 #define CPSW_TX_WORD3_PASS_CRC 0x04000000
320 #define CPSW_TX_WORD3_TO_PORT_EN 0x00100000
321 #define CPSW_TX_WORD3_TO_PORT 0x00030000
322 #define CPSW_TX_WORD3_TO_PORT_1 0x00010000
323 #define CPSW_TX_WORD3_TO_PORT_2 0x00020000
324 #define CPSW_TX_WORD3_PACKET_LENGTH 0x000007FF
325 
326 //RX buffer descriptor flags
327 #define CPSW_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
328 #define CPSW_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
329 #define CPSW_RX_WORD2_BUFFER_OFFSET 0x07FF0000
330 #define CPSW_RX_WORD2_BUFFER_LENGTH 0x000007FF
331 #define CPSW_RX_WORD3_SOP 0x80000000
332 #define CPSW_RX_WORD3_EOP 0x40000000
333 #define CPSW_RX_WORD3_OWNER 0x20000000
334 #define CPSW_RX_WORD3_EOQ 0x10000000
335 #define CPSW_RX_WORD3_TDOWN_CMPLT 0x08000000
336 #define CPSW_RX_WORD3_PASS_CRC 0x04000000
337 #define CPSW_RX_WORD3_LONG 0x02000000
338 #define CPSW_RX_WORD3_SHORT 0x01000000
339 #define CPSW_RX_WORD3_CONTROL 0x00800000
340 #define CPSW_RX_WORD3_OVERRUN 0x00400000
341 #define CPSW_RX_WORD3_PKT_ERROR 0x00300000
342 #define CPSW_RX_WORD3_RX_VLAN_ENCAP 0x000C0000
343 #define CPSW_RX_WORD3_FROM_PORT 0x00030000
344 #define CPSW_RX_WORD3_FROM_PORT_1 0x00010000
345 #define CPSW_RX_WORD3_FROM_PORT_2 0x00020000
346 #define CPSW_RX_WORD3_PACKET_LENGTH 0x000007FF
347 
348 //Number of entries in the ALE table
349 #define CPSW_ALE_MAX_ENTRIES 1024
350 
351 //ALE table entry
352 #define CPSW_ALE_WORD1_ENTRY_TYPE_MASK (3 << 28)
353 #define CPSW_ALE_WORD1_ENTRY_TYPE_FREE (0 << 28)
354 #define CPSW_ALE_WORD1_ENTRY_TYPE_ADDR (1 << 28)
355 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN (2 << 28)
356 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR (3 << 28)
357 #define CPSW_ALE_WORD1_MULTICAST (1 << 8)
358 
359 //Unicast address table entry
360 #define CPSW_ALE_WORD2_DLR_UNICAST (1 << 5)
361 #define CPSW_ALE_WORD2_PORT_NUMBER_MASK (3 << 2)
362 #define CPSW_ALE_WORD2_PORT_NUMBER(n) ((n) << 2)
363 #define CPSW_ALE_WORD2_BLOCK (1 << 1)
364 #define CPSW_ALE_WORD2_SECURE (1 << 0)
365 #define CPSW_ALE_WORD1_UNICAST_TYPE_MASK (3 << 30)
366 #define CPSW_ALE_WORD1_UNICAST_TYPE(n) ((n) << 30)
367 
368 //Multicast address table entry
369 #define CPSW_ALE_WORD2_PORT_MASK_MASK (3 << 2)
370 #define CPSW_ALE_WORD2_PORT_MASK(n) ((n) << 2)
371 #define CPSW_ALE_WORD2_SUPER (1 << 1)
372 #define CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK (3 << 30)
373 #define CPSW_ALE_WORD1_MCAST_FWD_STATE(n) ((n) << 30)
374 
375 //VLAN table entry
376 #define CPSW_ALE_WORD1_VLAN_ID_MASK (4095 << 16)
377 #define CPSW_ALE_WORD1_VLAN_ID(n) ((n) << 16)
378 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK (7 << 24)
379 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS(n) ((n) << 24)
380 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK (7 << 16)
381 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD(n) ((n) << 16)
382 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK (7 << 8)
383 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD(n) ((n) << 8)
384 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK (7 << 0)
385 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST(n) ((n) << 0)
386 
387 //C++ guard
388 #ifdef __cplusplus
389 extern "C" {
390 #endif
391 
392 
393 /**
394  * @brief ALE table entry
395  **/
396 
397 typedef struct
398 {
399  uint32_t word2;
400  uint32_t word1;
401  uint32_t word0;
403 
404 
405 /**
406  * @brief TX buffer descriptor
407  **/
408 
409 typedef struct _Am335xTxBufferDesc
410 {
411  uint32_t word0;
412  uint32_t word1;
413  uint32_t word2;
414  uint32_t word3;
418 
419 
420 /**
421  * @brief RX buffer descriptor
422  **/
423 
424 typedef struct _Am335xRxBufferDesc
425 {
426  uint32_t word0;
427  uint32_t word1;
428  uint32_t word2;
429  uint32_t word3;
433 
434 
435 //AM335x Ethernet MAC driver
436 extern const NicDriver am335xEthPort1Driver;
437 extern const NicDriver am335xEthPort2Driver;
438 
439 //AM335x Ethernet MAC related functions
442 void am335xEthInitInstance(NetInterface *interface);
443 void am335xEthInitGpio(NetInterface *interface);
444 void am335xEthInitBufferDesc(NetInterface *interface);
445 
446 void am335xEthTick(NetInterface *interface);
447 
448 void am335xEthEnableIrq(NetInterface *interface);
449 void am335xEthDisableIrq(NetInterface *interface);
450 void am335xEthTxIrqHandler(void);
451 void am335xEthRxIrqHandler(void);
452 void am335xEthEventHandler(NetInterface *interface);
453 
455  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
456 
458  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
459 
462 
463 void am335xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
464  uint8_t regAddr, uint16_t data);
465 
466 uint16_t am335xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
467  uint8_t regAddr);
468 
469 void am335xEthWriteEntry(uint_t index, const Am335xAleEntry *entry);
470 void am335xEthReadEntry(uint_t index, Am335xAleEntry *entry);
471 
475 
479 
480 //C++ guard
481 #ifdef __cplusplus
482 }
483 #endif
484 
485 #endif
uint16_t am335xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint_t am335xEthFindVlanAddrEntry(uint_t vlanId, MacAddr *macAddr)
Search the ALE table for the specified VLAN/address entry.
void am335xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t am335xEthDeleteVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr)
Remove a VLAN/address entry from the ALE table.
const NicDriver am335xEthPort2Driver
AM335x Ethernet MAC driver (port2)
void am335xEthInitInstance(NetInterface *interface)
Initialize CPSW instance.
const NicDriver am335xEthPort1Driver
AM335x Ethernet MAC driver (port1)
uint_t am335xEthFindFreeEntry(void)
Find a free entry in the ALE table.
error_t am335xEthAddVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr)
Add a VLAN/address entry in the ALE table.
error_t am335xEthInitPort2(NetInterface *interface)
AM335x Ethernet MAC initialization (port 2)
void am335xEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t am335xEthAddVlanEntry(uint_t port, uint_t vlanId)
Add a VLAN entry in the ALE table.
void am335xEthReadEntry(uint_t index, Am335xAleEntry *entry)
Read an ALE table entry.
void am335xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
error_t am335xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t am335xEthSendPacketPort2(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet (port 2)
void am335xEthInitGpio(NetInterface *interface)
GPIO configuration.
void am335xEthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
void am335xEthDisableIrq(NetInterface *interface)
Disable interrupts.
struct _Am335xTxBufferDesc Am335xTxBufferDesc
TX buffer descriptor.
error_t am335xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t am335xEthInitPort1(NetInterface *interface)
AM335x Ethernet MAC initialization (port 1)
error_t am335xEthSendPacketPort1(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet (port 1)
uint_t am335xEthFindVlanEntry(uint_t vlanId)
Search the ALE table for the specified VLAN entry.
void am335xEthEventHandler(NetInterface *interface)
AM335x Ethernet MAC event handler.
struct _Am335xRxBufferDesc Am335xRxBufferDesc
RX buffer descriptor.
void am335xEthTick(NetInterface *interface)
AM335x Ethernet MAC timer handler.
void am335xEthRxIrqHandler(void)
Ethernet MAC receive interrupt.
void am335xEthWriteEntry(uint_t index, const Am335xAleEntry *entry)
Write an ALE table entry.
unsigned int uint_t
Definition: compiler_port.h:50
uint8_t opcode
Definition: dns_common.h:188
uint16_t port
Definition: dns_common.h:267
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
RX buffer descriptor.
struct _Am335xRxBufferDesc * next
struct _Am335xRxBufferDesc * prev
TX buffer descriptor.
struct _Am335xTxBufferDesc * next
struct _Am335xTxBufferDesc * prev
ALE table entry.
uint32_t word1
uint32_t word2
uint32_t word0
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283