dm9000_driver.h
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1 /**
2  * @file dm9000_driver.h
3  * @brief DM9000A/B Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _DM9000_DRIVER_H
32 #define _DM9000_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Loopback mode
38 #ifndef DM9000_LOOPBACK_MODE
39  #define DM9000_LOOPBACK_MODE DISABLED
40 #elif (DM9000_LOOPBACK_MODE != ENABLED && DM9000_LOOPBACK_MODE != DISABLED)
41  #error DM9000_LOOPBACK_MODE parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef DM9000_ETH_TX_BUFFER_SIZE
46  #define DM9000_ETH_TX_BUFFER_SIZE 1536
47 #elif (DM9000_ETH_TX_BUFFER_SIZE != 1536)
48  #error DM9000_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //RX buffer size
52 #ifndef DM9000_ETH_RX_BUFFER_SIZE
53  #define DM9000_ETH_RX_BUFFER_SIZE 1536
54 #elif (DM9000_ETH_RX_BUFFER_SIZE != 1536)
55  #error DM9000_ETH_RX_BUFFER_SIZE parameter is not valid
56 #endif
57 
58 //DM9000 index register
59 #ifndef DM9000_INDEX_REG
60  #define DM9000_INDEX_REG *((volatile uint16_t *) 0x30000000)
61 #endif
62 
63 //DM9000 data register
64 #ifndef DM9000_DATA_REG
65  #define DM9000_DATA_REG *((volatile uint16_t *) 0x30001000)
66 #endif
67 
68 //DM9000 identifiers
69 #define DM9000_VID ((DM9000_VIDH_DEFAULT << 8) | DM9000_VIDL_DEFAULT)
70 #define DM9000_PID ((DM9000_PIDH_DEFAULT << 8) | DM9000_PIDL_DEFAULT)
71 
72 //DM9000 registers
73 #define DM9000_NCR 0x00
74 #define DM9000_NSR 0x01
75 #define DM9000_TCR 0x02
76 #define DM9000_TSR1 0x03
77 #define DM9000_TSR2 0x04
78 #define DM9000_RCR 0x05
79 #define DM9000_RSR 0x06
80 #define DM9000_ROCR 0x07
81 #define DM9000_BPTR 0x08
82 #define DM9000_FCTR 0x09
83 #define DM9000_FCR 0x0A
84 #define DM9000_EPCR 0x0B
85 #define DM9000_EPAR 0x0C
86 #define DM9000_EPDRL 0x0D
87 #define DM9000_EPDRH 0x0E
88 #define DM9000_WCR 0x0F
89 #define DM9000_PAR0 0x10
90 #define DM9000_PAR1 0x11
91 #define DM9000_PAR2 0x12
92 #define DM9000_PAR3 0x13
93 #define DM9000_PAR4 0x14
94 #define DM9000_PAR5 0x15
95 #define DM9000_MAR0 0x16
96 #define DM9000_MAR1 0x17
97 #define DM9000_MAR2 0x18
98 #define DM9000_MAR3 0x19
99 #define DM9000_MAR4 0x1A
100 #define DM9000_MAR5 0x1B
101 #define DM9000_MAR6 0x1C
102 #define DM9000_MAR7 0x1D
103 #define DM9000_GPCR 0x1E
104 #define DM9000_GPR 0x1F
105 #define DM9000_TRPAL 0x22
106 #define DM9000_TRPAH 0x23
107 #define DM9000_RWPAL 0x24
108 #define DM9000_RWPAH 0x25
109 #define DM9000_VIDL 0x28
110 #define DM9000_VIDH 0x29
111 #define DM9000_PIDL 0x2A
112 #define DM9000_PIDH 0x2B
113 #define DM9000_CHIPR 0x2C
114 #define DM9000_TCR2 0x2D
115 #define DM9000_OCR 0x2E
116 #define DM9000_SMCR 0x2F
117 #define DM9000_ETXCSR 0x30
118 #define DM9000_TCSCR 0x31
119 #define DM9000_RCSCSR 0x32
120 #define DM9000_MPAR 0x33
121 #define DM9000_LEDCR 0x34
122 #define DM9000_BUSCR 0x38
123 #define DM9000_INTCR 0x39
124 #define DM9000_SCCR 0x50
125 #define DM9000_RSCCR 0x51
126 #define DM9000_MRCMDX 0xF0
127 #define DM9000_MRCMDX1 0xF1
128 #define DM9000_MRCMD 0xF2
129 #define DM9000_MRRL 0xF4
130 #define DM9000_MRRH 0xF5
131 #define DM9000_MWCMDX 0xF6
132 #define DM9000_MWCMD 0xF8
133 #define DM9000_MWRL 0xFA
134 #define DM9000_MWRH 0xFB
135 #define DM9000_TXPLL 0xFC
136 #define DM9000_TXPLH 0xFD
137 #define DM9000_ISR 0xFE
138 #define DM9000_IMR 0xFF
139 
140 //DM9000 PHY registers
141 #define DM9000_BMCR 0x00
142 #define DM9000_BMSR 0x01
143 #define DM9000_PHYIDR1 0x02
144 #define DM9000_PHYIDR2 0x03
145 #define DM9000_ANAR 0x04
146 #define DM9000_ANLPAR 0x05
147 #define DM9000_ANER 0x06
148 #define DM9000_DSCR 0x10
149 #define DM9000_DSCSR 0x11
150 #define DM9000_10BTCSR 0x12
151 #define DM9000_PWDOR 0x13
152 #define DM9000_SCR 0x14
153 #define DM9000_DSPCR 0x1B
154 #define DM9000_PSCR 0x1D
155 
156 //Network Control register
157 #define DM9000_NCR_WAKEEN 0x40
158 #define DM9000_NCR_FCOL 0x10
159 #define DM9000_NCR_FDX 0x08
160 #define DM9000_NCR_LBK 0x06
161 #define DM9000_NCR_LBK_NORMAL 0x00
162 #define DM9000_NCR_LBK_MAC 0x02
163 #define DM9000_NCR_LBK_PHY 0x04
164 #define DM9000_NCR_RST 0x01
165 
166 //Network Status register
167 #define DM9000_NSR_SPEED 0x80
168 #define DM9000_NSR_LINKST 0x40
169 #define DM9000_NSR_WAKEST 0x20
170 #define DM9000_NSR_TX2END 0x08
171 #define DM9000_NSR_TX1END 0x04
172 #define DM9000_NSR_RXOV 0x02
173 
174 //TX Control register
175 #define DM9000_TCR_TJDIS 0x40
176 #define DM9000_TCR_EXCECM 0x20
177 #define DM9000_TCR_PAD_DIS2 0x10
178 #define DM9000_TCR_CRC_DIS2 0x08
179 #define DM9000_TCR_PAD_DIS1 0x04
180 #define DM9000_TCR_CRC_DIS1 0x02
181 #define DM9000_TCR_TXREQ 0x01
182 
183 //TX Status 1 register
184 #define DM9000_TSR1_TJTO 0x80
185 #define DM9000_TSR1_LC 0x40
186 #define DM9000_TSR1_NC 0x20
187 #define DM9000_TSR1_LCOL 0x10
188 #define DM9000_TSR1_COL 0x08
189 #define DM9000_TSR1_EC 0x04
190 
191 //TX Status 2 register
192 #define DM9000_TSR2_TJTO 0x80
193 #define DM9000_TSR2_LC 0x40
194 #define DM9000_TSR2_NC 0x20
195 #define DM9000_TSR2_LCOL 0x10
196 #define DM9000_TSR2_COL 0x08
197 #define DM9000_TSR2_EC 0x04
198 
199 //RX Control register
200 #define DM9000_RCR_WTDIS 0x40
201 #define DM9000_RCR_DIS_LONG 0x20
202 #define DM9000_RCR_DIS_CRC 0x10
203 #define DM9000_RCR_ALL 0x08
204 #define DM9000_RCR_RUNT 0x04
205 #define DM9000_RCR_PRMSC 0x02
206 #define DM9000_RCR_RXEN 0x01
207 
208 //RX Status register
209 #define DM9000_RSR_RF 0x80
210 #define DM9000_RSR_MF 0x40
211 #define DM9000_RSR_LCS 0x20
212 #define DM9000_RSR_RWTO 0x10
213 #define DM9000_RSR_PLE 0x08
214 #define DM9000_RSR_AE 0x04
215 #define DM9000_RSR_CE 0x02
216 #define DM9000_RSR_FOE 0x01
217 
218 //Receive Overflow Counter register
219 #define DM9000_ROCR_RXFU 0x80
220 #define DM9000_ROCR_ROC 0x7F
221 
222 //Back Pressure Threshold register
223 #define DM9000_BPTR_BPHW 0xF0
224 #define DM9000_BPTR_JPT 0x0F
225 
226 //Flow Control Threshold register
227 #define DM9000_FCTR_HWOT 0xF0
228 #define DM9000_FCTR_LWOT 0x0F
229 
230 //RX Flow Control register
231 #define DM9000_FCR_TXP0 0x80
232 #define DM9000_FCR_TXPF 0x40
233 #define DM9000_FCR_TXPEN 0x20
234 #define DM9000_FCR_BKPA 0x10
235 #define DM9000_FCR_BKPM 0x08
236 #define DM9000_FCR_RXPS 0x04
237 #define DM9000_FCR_RXPCS 0x02
238 #define DM9000_FCR_FLCE 0x01
239 
240 //EEPROM & PHY Control register
241 #define DM9000_EPCR_REEP 0x20
242 #define DM9000_EPCR_WEP 0x10
243 #define DM9000_EPCR_EPOS 0x08
244 #define DM9000_EPCR_ERPRR 0x04
245 #define DM9000_EPCR_ERPRW 0x02
246 #define DM9000_EPCR_ERRE 0x01
247 
248 //EEPROM & PHY Address register
249 #define DM9000_EPAR_PHY_ADR 0xC0
250 #define DM9000_EPAR_EROA 0x3F
251 
252 //Wake Up Control register
253 #define DM9000_WCR_LINKEN 0x20
254 #define DM9000_WCR_SAMPLEEN 0x10
255 #define DM9000_WCR_MAGICEN 0x08
256 #define DM9000_WCR_LINKST 0x04
257 #define DM9000_WCR_SAMPLEST 0x02
258 #define DM9000_WCR_MAGICST 0x01
259 
260 //General Purpose Control register
261 #define DM9000_GPCR_GPC6 0x40
262 #define DM9000_GPCR_GPC5 0x20
263 #define DM9000_GPCR_GPC4 0x10
264 #define DM9000_GPCR_GPC3 0x08
265 #define DM9000_GPCR_GPC2 0x04
266 #define DM9000_GPCR_GPC1 0x02
267 
268 //General Purpose register
269 #define DM9000_GPR_GPO6 0x40
270 #define DM9000_GPR_GPO5 0x20
271 #define DM9000_GPR_GPO4 0x10
272 #define DM9000_GPR_GPIO3 0x08
273 #define DM9000_GPR_GPIO2 0x04
274 #define DM9000_GPR_GPIO1 0x02
275 #define DM9000_GPR_PHYPD 0x01
276 
277 //Vendor ID Low Byte register
278 #define DM9000_VIDL_DEFAULT 0x46
279 
280 //Vendor ID High Byte register
281 #define DM9000_VIDH_DEFAULT 0x0A
282 
283 //Product ID Low Byte register
284 #define DM9000_PIDL_DEFAULT 0x00
285 
286 //Product ID High Byte register
287 #define DM9000_PIDH_DEFAULT 0x90
288 
289 //Chip Revision register
290 #define DM9000_CHIPR_REV_A 0x19
291 #define DM9000_CHIPR_REV_B 0x1A
292 
293 //TX Control 2 register
294 #define DM9000_TCR2_LED 0x80
295 #define DM9000_TCR2_RLCP 0x40
296 #define DM9000_TCR2_DTU 0x20
297 #define DM9000_TCR2_ONEPM 0x10
298 #define DM9000_TCR2_IFGS 0x0F
299 #define DM9000_TCR2_IFGS_64_BIT 0x08
300 #define DM9000_TCR2_IFGS_72_BIT 0x09
301 #define DM9000_TCR2_IFGS_80_BIT 0x0A
302 #define DM9000_TCR2_IFGS_88_BIT 0x0B
303 #define DM9000_TCR2_IFGS_96_BIT 0x0C
304 #define DM9000_TCR2_IFGS_104_BIT 0x0D
305 #define DM9000_TCR2_IFGS_112_BIT 0x0E
306 #define DM9000_TCR2_IFGS_120_BIT 0x0F
307 
308 //Operation Control register
309 #define DM9000_OCR_SCC 0xC0
310 #define DM9000_OCR_SCC_50MHZ 0x00
311 #define DM9000_OCR_SCC_20MHZ 0x40
312 #define DM9000_OCR_SCC_100MHZ 0x80
313 #define DM9000_OCR_SOE 0x10
314 #define DM9000_OCR_SCS 0x08
315 #define DM9000_OCR_PHYOP 0x07
316 
317 //Special Mode Control register
318 #define DM9000_SMCR_SM_EN 0x80
319 #define DM9000_SMCR_FLC 0x04
320 #define DM9000_SMCR_FB1 0x02
321 #define DM9000_SMCR_FB0 0x01
322 
323 //Early Transmit Control/Status register
324 #define DM9000_ETXCSR_ETE 0x80
325 #define DM9000_ETXCSR_ETS2 0x40
326 #define DM9000_ETXCSR_ETS1 0x20
327 #define DM9000_ETXCSR_ETT 0x03
328 #define DM9000_ETXCSR_ETT_12_5_PERCENT 0x00
329 #define DM9000_ETXCSR_ETT_25_PERCENT 0x01
330 #define DM9000_ETXCSR_ETT_50_PERCENT 0x02
331 #define DM9000_ETXCSR_ETT_75_PERCENT 0x03
332 
333 //Transmit Check Sum Control register
334 #define DM9000_TCSCR_UDPCSE 0x04
335 #define DM9000_TCSCR_TCPCSE 0x02
336 #define DM9000_TCSCR_IPCSE 0x01
337 
338 //Receive Check Sum Control Status register
339 #define DM9000_RCSCSR_UDPS 0x80
340 #define DM9000_RCSCSR_TCPS 0x40
341 #define DM9000_RCSCSR_IPS 0x20
342 #define DM9000_RCSCSR_UDPP 0x10
343 #define DM9000_RCSCSR_TCPP 0x08
344 #define DM9000_RCSCSR_IPP 0x04
345 #define DM9000_RCSCSR_RCSEN 0x02
346 #define DM9000_RCSCSR_DCSE 0x01
347 
348 //MII PHY Address register
349 #define DM9000_MPAR_ADR_EN 0x80
350 #define DM9000_MPAR_EPHYADR 0x1F
351 
352 //LED Pin Control register
353 #define DM9000_LEDCR_GPIO 0x02
354 #define DM9000_LEDCR_MII 0x01
355 
356 //Processor Bus Control register
357 #define DM9000_BUSCR_CURR 0x60
358 #define DM9000_BUSCR_CURR_2MA 0x00
359 #define DM9000_BUSCR_CURR_4MA 0x20
360 #define DM9000_BUSCR_CURR_6MA 0x40
361 #define DM9000_BUSCR_CURR_8MA 0x60
362 #define DM9000_BUSCR_EST 0x08
363 #define DM9000_BUSCR_IOW_SPIKE 0x02
364 #define DM9000_BUSCR_IOR_SPIKE 0x01
365 
366 //INT Pin Control register
367 #define DM9000_INTCR_INT_TYPE 0x02
368 #define DM9000_INTCR_INT_TYPE_DIRECT 0x00
369 #define DM9000_INTCR_INT_TYPE_OC 0x02
370 #define DM9000_INTCR_INT_POL 0x01
371 #define DM9000_INTCR_INT_POL_HIGH 0x00
372 #define DM9000_INTCR_INT_POL_LOW 0x01
373 
374 //System Clock Turn On Control register
375 #define DM9000_SCCR_DIS_CLK 0x01
376 
377 //Interrupt Status register
378 #define DM9000_ISR_IOMODE 0x80
379 #define DM9000_ISR_IOMODE_16_BIT 0x00
380 #define DM9000_ISR_IOMODE_8_BIT 0x80
381 #define DM9000_ISR_LNKCHG 0x20
382 #define DM9000_ISR_UDRUN 0x10
383 #define DM9000_ISR_ROO 0x08
384 #define DM9000_ISR_ROS 0x04
385 #define DM9000_ISR_PT 0x02
386 #define DM9000_ISR_PR 0x01
387 
388 //Interrupt Mask register
389 #define DM9000_IMR_PAR 0x80
390 #define DM9000_IMR_LNKCHGI 0x20
391 #define DM9000_IMR_UDRUNI 0x10
392 #define DM9000_IMR_ROOI 0x08
393 #define DM9000_IMR_ROI 0x04
394 #define DM9000_IMR_PTI 0x02
395 #define DM9000_IMR_PRI 0x01
396 
397 //Basic Mode Control register
398 #define DM9000_BMCR_RST 0x8000
399 #define DM9000_BMCR_LOOPBACK 0x4000
400 #define DM9000_BMCR_SPEED_SEL 0x2000
401 #define DM9000_BMCR_AN_EN 0x1000
402 #define DM9000_BMCR_POWER_DOWN 0x0800
403 #define DM9000_BMCR_ISOLATE 0x0400
404 #define DM9000_BMCR_RESTART_AN 0x0200
405 #define DM9000_BMCR_DUPLEX_MODE 0x0100
406 #define DM9000_BMCR_COL_TEST 0x0080
407 
408 //Basic Mode Status register
409 #define DM9000_BMSR_100BT4 0x8000
410 #define DM9000_BMSR_100BTX_FD 0x4000
411 #define DM9000_BMSR_100BTX_HD 0x2000
412 #define DM9000_BMSR_10BT_FD 0x1000
413 #define DM9000_BMSR_10BT_HD 0x0800
414 #define DM9000_BMSR_MF_PREAMBLE_SUPPR 0x0040
415 #define DM9000_BMSR_AN_COMPLETE 0x0020
416 #define DM9000_BMSR_REMOTE_FAULT 0x0010
417 #define DM9000_BMSR_AN_CAPABLE 0x0008
418 #define DM9000_BMSR_LINK_STATUS 0x0004
419 #define DM9000_BMSR_JABBER_DETECT 0x0002
420 #define DM9000_BMSR_EXTENDED_CAPABLE 0x0001
421 
422 //PHY ID Identifier 1 register
423 #define DM9000_PHYIDR1_OUI_MSB 0xFFFF
424 #define DM9000_PHYIDR1_OUI_MSB_DEFAULT 0x0181
425 
426 //PHY ID Identifier 2 register
427 #define DM9000_PHYIDR2_OUI_LSB 0xFC00
428 #define DM9000_PHYIDR2_OUI_LSB_DEFAULT 0xB800
429 #define DM9000_PHYIDR2_VNDR_MDL 0x03F0
430 #define DM9000_PHYIDR2_VNDR_MDL_DEFAULT 0x0070
431 #define DM9000_PHYIDR2_MDL_REV 0x000F
432 #define DM9000_PHYIDR2_MDL_REV_DEFAULT 0x0000
433 
434 //Auto-Negotiation Advertisement register
435 #define DM9000_ANAR_NP 0x8000
436 #define DM9000_ANAR_ACK 0x4000
437 #define DM9000_ANAR_RF 0x2000
438 #define DM9000_ANAR_FCS 0x0400
439 #define DM9000_ANAR_100BT4 0x0200
440 #define DM9000_ANAR_100BTX_FD 0x0100
441 #define DM9000_ANAR_100BTX_HD 0x0080
442 #define DM9000_ANAR_10BT_FD 0x0040
443 #define DM9000_ANAR_10BT_HD 0x0020
444 #define DM9000_ANAR_SELECTOR 0x001F
445 #define DM9000_ANAR_SELECTOR_DEFAULT 0x0001
446 
447 //Auto-Negotiation Link Partner Ability register
448 #define DM9000_ANLPAR_NP 0x8000
449 #define DM9000_ANLPAR_ACK 0x4000
450 #define DM9000_ANLPAR_RF 0x2000
451 #define DM9000_ANLPAR_FCS 0x0400
452 #define DM9000_ANLPAR_100BT4 0x0200
453 #define DM9000_ANLPAR_100BTX_FD 0x0100
454 #define DM9000_ANLPAR_100BTX_HD 0x0080
455 #define DM9000_ANLPAR_10BT_FD 0x0040
456 #define DM9000_ANLPAR_10BT_HD 0x0020
457 #define DM9000_ANLPAR_SELECTOR 0x001F
458 #define DM9000_ANLPAR_SELECTOR_DEFAULT 0x0001
459 
460 //Auto-Negotiation Expansion register
461 #define DM9000_ANER_PDF 0x0010
462 #define DM9000_ANER_LP_NP_ABLE 0x0008
463 #define DM9000_ANER_NP_ABLE 0x0004
464 #define DM9000_ANER_PAGE_RX 0x0002
465 #define DM9000_ANER_LP_AN_ABLE 0x0001
466 
467 //Davicom Specified Configuration register
468 #define DM9000_DSCR_BP_4B5B 0x8000
469 #define DM9000_DSCR_BP_SCR 0x4000
470 #define DM9000_DSCR_BP_ALIGN 0x2000
471 #define DM9000_DSCR_BP_ADPOK 0x1000
472 #define DM9000_DSCR_TX_FX 0x0400
473 #define DM9000_DSCR_F_LINK_100 0x0080
474 #define DM9000_DSCR_SPLED_CTL 0x0040
475 #define DM9000_DSCR_COLLED_CTL 0x0020
476 #define DM9000_DSCR_RPDCTR_EN 0x0010
477 #define DM9000_DSCR_SMRST 0x0008
478 #define DM9000_DSCR_MFPSC 0x0004
479 #define DM9000_DSCR_SLEEP 0x0002
480 #define DM9000_DSCR_RLOUT 0x0001
481 
482 //Davicom Specified Configuration/Status register
483 #define DM9000_DSCSR_100FDX 0x8000
484 #define DM9000_DSCSR_100HDX 0x4000
485 #define DM9000_DSCSR_10FDX 0x2000
486 #define DM9000_DSCSR_10HDX 0x1000
487 #define DM9000_DSCSR_PHYADR 0x01F0
488 #define DM9000_DSCSR_ANMB 0x000F
489 
490 //10BASE-T Configuration/Status register
491 #define DM9000_10BTCSR_LP_EN 0x4000
492 #define DM9000_10BTCSR_HBE 0x2000
493 #define DM9000_10BTCSR_SQUELCH 0x1000
494 #define DM9000_10BTCSR_JABEN 0x0800
495 #define DM9000_10BTCSR_POLR 0x0001
496 
497 //Power Down Control register
498 #define DM9000_PWDOR_PD10DRV 0x0100
499 #define DM9000_PWDOR_PD100DL 0x0080
500 #define DM9000_PWDOR_PDCHIP 0x0040
501 #define DM9000_PWDOR_PDCOM 0x0020
502 #define DM9000_PWDOR_PDAEQ 0x0010
503 #define DM9000_PWDOR_PDDRV 0x0008
504 #define DM9000_PWDOR_PDEDI 0x0004
505 #define DM9000_PWDOR_PDEDO 0x0002
506 #define DM9000_PWDOR_PD10 0x0001
507 
508 //Specified Configuration register
509 #define DM9000_SCR_TSTSE1 0x8000
510 #define DM9000_SCR_TSTSE2 0x4000
511 #define DM9000_SCR_FORCE_TXSD 0x2000
512 #define DM9000_SCR_FORCE_FEF 0x1000
513 #define DM9000_SCR_PREAMBLEX 0x0800
514 #define DM9000_SCR_TX10M_PWR 0x0400
515 #define DM9000_SCR_NWAY_PWR 0x0200
516 #define DM9000_SCR_MDIX_CNTL 0x0080
517 #define DM9000_SCR_AUTONEG_LPBK 0x0040
518 #define DM9000_SCR_MDIX_FIX 0x0020
519 #define DM9000_SCR_MDIX_DOWN 0x0010
520 #define DM9000_SCR_MONSEL1 0x0008
521 #define DM9000_SCR_MONSEL0 0x0004
522 #define DM9000_SCR_PD_VALUE 0x0001
523 
524 //DSP Control register
525 #define DM9000_DSPCR_DSP 0xFFFF
526 
527 //Power Saving Control register
528 #define DM9000_PSCR_PREAMBLEX 0x0800
529 #define DM9000_PSCR_AMPLITUDE 0x0400
530 #define DM9000_PSCR_TX_PWR 0x0200
531 
532 //C++ guard
533 #ifdef __cplusplus
534 extern "C" {
535 #endif
536 
537 
538 /**
539  * @brief DM9000 driver context
540  **/
541 
542 typedef struct
543 {
544  uint_t queuedPackets; ///<Number of packets in transmission buffer
545 } Dm9000Context;
546 
547 
548 //DM9000 driver
549 extern const NicDriver dm9000Driver;
550 
551 //DM9000 related functions
552 error_t dm9000Init(NetInterface *interface);
553 void dm9000InitHook(NetInterface *interface);
554 
555 void dm9000Tick(NetInterface *interface);
556 
557 void dm9000EnableIrq(NetInterface *interface);
558 void dm9000DisableIrq(NetInterface *interface);
560 void dm9000EventHandler(NetInterface *interface);
561 
563  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
564 
566 
568 
569 void dm9000WriteReg(uint8_t address, uint8_t data);
570 uint8_t dm9000ReadReg(uint8_t address);
571 
572 void dm9000WritePhyReg(uint8_t address, uint16_t data);
573 uint16_t dm9000ReadPhyReg(uint8_t address);
574 
575 uint32_t dm9000CalcCrc(const void *data, size_t length);
576 
577 //C++ guard
578 #ifdef __cplusplus
579 }
580 #endif
581 
582 #endif
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
void dm9000InitHook(NetInterface *interface)
DM9000 custom configuration.
error_t dm9000ReceivePacket(NetInterface *interface)
Receive a packet.
void dm9000WriteReg(uint8_t address, uint8_t data)
Write DM9000 register.
error_t dm9000SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t dm9000ReadPhyReg(uint8_t address)
Read DM9000 PHY register.
void dm9000DisableIrq(NetInterface *interface)
Disable interrupts.
void dm9000EventHandler(NetInterface *interface)
DM9000 event handler.
const NicDriver dm9000Driver
DM9000 driver.
Definition: dm9000_driver.c:45
void dm9000WritePhyReg(uint8_t address, uint16_t data)
Write DM9000 PHY register.
error_t dm9000UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void dm9000Tick(NetInterface *interface)
DM9000 timer handler.
uint32_t dm9000CalcCrc(const void *data, size_t length)
CRC calculation.
void dm9000EnableIrq(NetInterface *interface)
Enable interrupts.
bool_t dm9000IrqHandler(NetInterface *interface)
DM9000 interrupt service routine.
uint8_t dm9000ReadReg(uint8_t address)
Read DM9000 register.
error_t dm9000Init(NetInterface *interface)
DM9000 controller initialization.
Definition: dm9000_driver.c:72
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
DM9000 driver context.
uint_t queuedPackets
Number of packets in transmission buffer.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368