dp83825_driver.h
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1 /**
2  * @file dp83825_driver.h
3  * @brief DP83825 Ethernet PHY driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _DP83825_DRIVER_H
32 #define _DP83825_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DP83825_PHY_ADDR
39  #define DP83825_PHY_ADDR 0
40 #elif (DP83825_PHY_ADDR < 0 || DP83825_PHY_ADDR > 31)
41  #error DP83825_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DP83825 PHY registers
45 #define DP83825_BMCR 0x00
46 #define DP83825_BMSR 0x01
47 #define DP83825_PHYIDR1 0x02
48 #define DP83825_PHYIDR2 0x03
49 #define DP83825_ANAR 0x04
50 #define DP83825_ANLPAR 0x05
51 #define DP83825_ANER 0x06
52 #define DP83825_ANNPTR 0x07
53 #define DP83825_ANLNPTR 0x08
54 #define DP83825_CR1 0x09
55 #define DP83825_CR2 0x0A
56 #define DP83825_CR3 0x0B
57 #define DP83825_REG_12 0x0C
58 #define DP83825_REGCR 0x0D
59 #define DP83825_ADDAR 0x0E
60 #define DP83825_FLDS 0x0F
61 #define DP83825_PHYSTS 0x10
62 #define DP83825_PHYSCR 0x11
63 #define DP83825_MISR1 0x12
64 #define DP83825_MISR2 0x13
65 #define DP83825_FCSCR 0x14
66 #define DP83825_RECR 0x15
67 #define DP83825_BISCR 0x16
68 #define DP83825_RCSR 0x17
69 #define DP83825_LEDCR 0x18
70 #define DP83825_PHYCR 0x19
71 #define DP83825_10BTSCR 0x1A
72 #define DP83825_BICSR1 0x1B
73 #define DP83825_BICSR2 0x1C
74 #define DP83825_CDCR 0x1E
75 #define DP83825_PHYRCR 0x1F
76 
77 //DP83825 MMD registers
78 #define DP83825_MMD3_PCS_CTRL_1 0x03, 0x1000
79 #define DP83825_MMD3_PCS_STATUS_1 0x03, 0x1001
80 #define DP83825_MMD3_EEE_CAPABILITY 0x03, 0x1014
81 #define DP83825_MMD3_WAKE_ERR_CNT 0x03, 0x1016
82 #define DP83825_MMD7_EEE_ADVERTISEMENT 0x07, 0x203C
83 #define DP83825_MMD7_EEE_LP_ABILITY_Register 0x07, 0x203D
84 #define DP83825_MLEDCR 0x1F, 0x0025
85 #define DP83825_COMPT 0x1F, 0x0027
86 #define DP83825_REG_101 0x1F, 0x0101
87 #define DP83825_REG_10A 0x1F, 0x010A
88 #define DP83825_REG_123 0x1F, 0x0123
89 #define DP83825_REG_130 0x1F, 0x0130
90 #define DP83825_CDSCR 0x1F, 0x0170
91 #define DP83825_CDSCR2 0x1F, 0x0171
92 #define DP83825_TDR_172 0x1F, 0x0172
93 #define DP83825_CDSCR3 0x1F, 0x0173
94 #define DP83825_TDR_174 0x1F, 0x0174
95 #define DP83825_TDR_175 0x1F, 0x0175
96 #define DP83825_TDR_176 0x1F, 0x0176
97 #define DP83825_CDSCR4 0x1F, 0x0177
98 #define DP83825_TDR_178 0x1F, 0x0178
99 #define DP83825_CDLRR1 0x1F, 0x0180
100 #define DP83825_CDLRR2 0x1F, 0x0181
101 #define DP83825_CDLRR3 0x1F, 0x0182
102 #define DP83825_CDLRR4 0x1F, 0x0183
103 #define DP83825_CDLRR5 0x1F, 0x0184
104 #define DP83825_CDLAR1 0x1F, 0x0185
105 #define DP83825_CDLAR2 0x1F, 0x0186
106 #define DP83825_CDLAR3 0x1F, 0x0187
107 #define DP83825_CDLAR4 0x1F, 0x0188
108 #define DP83825_CDLAR5 0x1F, 0x0189
109 #define DP83825_CDLAR6 0x1F, 0x018A
110 #define DP83825_IO_CFG 0x1F, 0x0302
111 #define DP83825_SPARE_OUT 0x1F, 0x0308
112 #define DP83825_DAC_CFG_0 0x1F, 0x030B
113 #define DP83825_DAC_CFG_1 0x1F, 0x030C
114 #define DP83825_DSP_CFG_0 0x1F, 0x030F
115 #define DP83825_DSP_CFG_2 0x1F, 0x0311
116 #define DP83825_DSP_CFG_4 0x1F, 0x0313
117 #define DP83825_DSP_CFG_13 0x1F, 0x031C
118 #define DP83825_DSP_CFG_16 0x1F, 0x031F
119 #define DP83825_DSP_CFG_25 0x1F, 0x033C
120 #define DP83825_DSP_CFG_27 0x1F, 0x033E
121 #define DP83825_ANA_LD_PROG_SL 0x1F, 0x0404
122 #define DP83825_ANA_RX10BT_CTRL 0x1F, 0x040D
123 #define DP83825_REG_416 0x1F, 0x0416
124 #define DP83825_REG_429 0x1F, 0x0429
125 #define DP83825_GENCFG 0x1F, 0x0456
126 #define DP83825_LEDCFG 0x1F, 0x0460
127 #define DP83825_IOCTRL 0x1F, 0x0461
128 #define DP83825_SOR1 0x1F, 0x0467
129 #define DP83825_SOR2 0x1F, 0x0468
130 #define DP83825_REG_469 0x1F, 0x0469
131 #define DP83825_RXFCFG 0x1F, 0x04A0
132 #define DP83825_RXFS 0x1F, 0x04A1
133 #define DP83825_RXFPMD1 0x1F, 0x04A2
134 #define DP83825_RXFPMD2 0x1F, 0x04A3
135 #define DP83825_RXFPMD3 0x1F, 0x04A4
136 #define DP83825_REG_4CD 0x1F, 0x04CD
137 #define DP83825_REG_4CE 0x1F, 0x04CE
138 #define DP83825_REG_4CF 0x1F, 0x04CF
139 #define DP83825_EEECFG2 0x1F, 0x04D0
140 #define DP83825_EEECFG3 0x1F, 0x04D1
141 #define DP83825_REG_4D2 0x1F, 0x04D2
142 #define DP83825_REG_4D4 0x1F, 0x04D4
143 #define DP83825_DSP_100M_STEP_2 0x1F, 0x04D5
144 #define DP83825_DSP_100M_STEP_3 0x1F, 0x04D6
145 #define DP83825_DSP_100M_STEP_4 0x1F, 0x04D7
146 
147 //BMCR register
148 #define DP83825_BMCR_RESET 0x8000
149 #define DP83825_BMCR_LOOPBACK 0x4000
150 #define DP83825_BMCR_SPEED_SEL 0x2000
151 #define DP83825_BMCR_AN_EN 0x1000
152 #define DP83825_BMCR_POWER_DOWN 0x0800
153 #define DP83825_BMCR_ISOLATE 0x0400
154 #define DP83825_BMCR_RESTART_AN 0x0200
155 #define DP83825_BMCR_DUPLEX_MODE 0x0100
156 #define DP83825_BMCR_COL_TEST 0x0080
157 
158 //BMSR register
159 #define DP83825_BMSR_100BT4 0x8000
160 #define DP83825_BMSR_100BTX_FD 0x4000
161 #define DP83825_BMSR_100BTX_HD 0x2000
162 #define DP83825_BMSR_10BT_FD 0x1000
163 #define DP83825_BMSR_10BT_HD 0x0800
164 #define DP83825_BMSR_SMI_PREAMBLE_SUPPR 0x0040
165 #define DP83825_BMSR_AN_COMPLETE 0x0020
166 #define DP83825_BMSR_REMOTE_FAULT 0x0010
167 #define DP83825_BMSR_AN_CAPABLE 0x0008
168 #define DP83825_BMSR_LINK_STATUS 0x0004
169 #define DP83825_BMSR_JABBER_DETECT 0x0002
170 #define DP83825_BMSR_EXTENDED_CAPABLE 0x0001
171 
172 //PHYIDR1 register
173 #define DP83825_PHYIDR1_OUI_MSB 0xFFFF
174 #define DP83825_PHYIDR1_OUI_MSB_DEFAULT 0x2000
175 
176 //PHYIDR2 register
177 #define DP83825_PHYIDR2_OUI_LSB 0xFC00
178 #define DP83825_PHYIDR2_OUI_LSB_DEFAULT 0xA000
179 #define DP83825_PHYIDR2_MODEL_NUMBER 0x03F0
180 #define DP83825_PHYIDR2_MODEL_NUMBER_DEFAULT 0x0140
181 #define DP83825_PHYIDR2_REV_NUMBER 0x000F
182 
183 //ANAR register
184 #define DP83825_ANAR_NEXT_PAGE 0x8000
185 #define DP83825_ANAR_REMOTE_FAULT 0x2000
186 #define DP83825_ANAR_ASYM_DIR 0x0800
187 #define DP83825_ANAR_PAUSE 0x0400
188 #define DP83825_ANAR_100BT4 0x0200
189 #define DP83825_ANAR_100BTX_FD 0x0100
190 #define DP83825_ANAR_100BTX_HD 0x0080
191 #define DP83825_ANAR_10BT_FD 0x0040
192 #define DP83825_ANAR_10BT_HD 0x0020
193 #define DP83825_ANAR_SELECTOR 0x001F
194 #define DP83825_ANAR_SELECTOR_DEFAULT 0x0001
195 
196 //ANLPAR register
197 #define DP83825_ANLPAR_NEXT_PAGE 0x8000
198 #define DP83825_ANLPAR_ACK 0x4000
199 #define DP83825_ANLPAR_REMOTE_FAULT 0x2000
200 #define DP83825_ANLPAR_ASYM_DIR 0x0800
201 #define DP83825_ANLPAR_PAUSE 0x0400
202 #define DP83825_ANLPAR_100BT4 0x0200
203 #define DP83825_ANLPAR_100BTX_FD 0x0100
204 #define DP83825_ANLPAR_100BTX_HD 0x0080
205 #define DP83825_ANLPAR_10BT_FD 0x0040
206 #define DP83825_ANLPAR_10BT_HD 0x0020
207 #define DP83825_ANLPAR_SELECTOR 0x001F
208 #define DP83825_ANLPAR_SELECTOR_DEFAULT 0x0001
209 
210 //ANER register
211 #define DP83825_ANER_PAR_DETECT_FAULT 0x0010
212 #define DP83825_ANER_LP_NEXT_PAGE_ABLE 0x0008
213 #define DP83825_ANER_NEXT_PAGE_ABLE 0x0004
214 #define DP83825_ANER_PAGE_RECEIVED 0x0002
215 #define DP83825_ANER_LP_AN_ABLE 0x0001
216 
217 //ANNPTR register
218 #define DP83825_ANNPTR_NEXT_PAGE 0x8000
219 #define DP83825_ANNPTR_MSG_PAGE 0x2000
220 #define DP83825_ANNPTR_ACK2 0x1000
221 #define DP83825_ANNPTR_TOGGLE 0x0800
222 #define DP83825_ANNPTR_CODE 0x07FF
223 
224 //ANLNPTR register
225 #define DP83825_ANLNPTR_NEXT_PAGE 0x8000
226 #define DP83825_ANLNPTR_ACK 0x4000
227 #define DP83825_ANLNPTR_MSG_PAGE 0x2000
228 #define DP83825_ANLNPTR_ACK2 0x1000
229 #define DP83825_ANLNPTR_TOGGLE 0x0800
230 #define DP83825_ANLNPTR_MESSAGE 0x07FF
231 
232 //CR1 register
233 #define DP83825_CR1_RMII_ENHANCED_MODE 0x0200
234 #define DP83825_CR1_TDR_AUTO_RUN 0x0100
235 #define DP83825_CR1_ROBUST_AUTO_MDIX 0x0020
236 #define DP83825_CR1_FAST_RX_DV_DETECT 0x0002
237 
238 //CR2 register
239 #define DP83825_CR2_EXTENDED_FD_ABLE 0x0020
240 #define DP83825_CR2_RX_ER_DURING_IDLE 0x0004
241 #define DP83825_CR2_ODD_NIBBLE_DETECT_DIS 0x0002
242 
243 //CR3 register
244 #define DP83825_CR3_DESCRAMBLER_FAST_LINK_DOWN 0x0400
245 #define DP83825_CR3_POLARITY_SWAP 0x0040
246 #define DP83825_CR3_MDIX_SWAP 0x0020
247 #define DP83825_CR3_FAST_LINK_DOWN_MODE 0x000F
248 
249 //REGCR register
250 #define DP83825_REGCR_CMD 0xC000
251 #define DP83825_REGCR_CMD_ADDR 0x0000
252 #define DP83825_REGCR_CMD_DATA_NO_POST_INC 0x4000
253 #define DP83825_REGCR_CMD_DATA_POST_INC_RW 0x8000
254 #define DP83825_REGCR_CMD_DATA_POST_INC_W 0xC000
255 #define DP83825_REGCR_DEVAD 0x001F
256 
257 //FLDS register
258 #define DP83825_FLDS_FAST_LINK_DOWN_STATUS 0x01F0
259 
260 //PHYSTS register
261 #define DP83825_PHYSTS_MDIX_MODE 0x4000
262 #define DP83825_PHYSTS_RECEIVE_ERROR_LATCH 0x2000
263 #define DP83825_PHYSTS_POLARITY_STATUS 0x1000
264 #define DP83825_PHYSTS_FALSE_CARRIER_SENSE_LATCH 0x0800
265 #define DP83825_PHYSTS_SIGNAL_DETECT 0x0400
266 #define DP83825_PHYSTS_DESCRAMBLER_LOCK 0x0200
267 #define DP83825_PHYSTS_PAGE_RECEIVED 0x0100
268 #define DP83825_PHYSTS_MII_INTERRUPT 0x0080
269 #define DP83825_PHYSTS_REMOTE_FAULT 0x0040
270 #define DP83825_PHYSTS_JABBER_DETECT 0x0020
271 #define DP83825_PHYSTS_AN_STATUS 0x0010
272 #define DP83825_PHYSTS_LOOPBACK_STATUS 0x0008
273 #define DP83825_PHYSTS_DUPLEX_STATUS 0x0004
274 #define DP83825_PHYSTS_SPEED_STATUS 0x0002
275 #define DP83825_PHYSTS_LINK_STATUS 0x0001
276 
277 //PHYSCR register
278 #define DP83825_PHYSCR_PLL_DIS 0x8000
279 #define DP83825_PHYSCR_POWER_SAVE_MODE_EN 0x4000
280 #define DP83825_PHYSCR_POWER_SAVE_MODE 0x3000
281 #define DP83825_PHYSCR_SCRAMBLER_BYPASS 0x0800
282 #define DP83825_PHYSCR_LOOPBACK_FIFO_DEPTH 0x0300
283 #define DP83825_PHYSCR_INT_POLARITY 0x0008
284 #define DP83825_PHYSCR_TEST_INT 0x0004
285 #define DP83825_PHYSCR_INT_EN 0x0002
286 #define DP83825_PHYSCR_INT_OE 0x0001
287 
288 //MISR1 register
289 #define DP83825_MISR1_LQ_INT 0x8000
290 #define DP83825_MISR1_ED_INT 0x4000
291 #define DP83825_MISR1_LINK_INT 0x2000
292 #define DP83825_MISR1_SPD_INT 0x1000
293 #define DP83825_MISR1_DUP_INT 0x0800
294 #define DP83825_MISR1_ANC_INT 0x0400
295 #define DP83825_MISR1_FHF_INT 0x0200
296 #define DP83825_MISR1_RHF_INT 0x0100
297 #define DP83825_MISR1_LQ_INT_EN 0x0080
298 #define DP83825_MISR1_ED_INT_EN 0x0040
299 #define DP83825_MISR1_LINK_INT_EN 0x0020
300 #define DP83825_MISR1_SPD_INT_EN 0x0010
301 #define DP83825_MISR1_DUP_INT_EN 0x0008
302 #define DP83825_MISR1_ANC_INT_EN 0x0004
303 #define DP83825_MISR1_FHF_INT_EN 0x0002
304 #define DP83825_MISR1_RHF_INT_EN 0x0001
305 
306 //MISR2 register
307 #define DP83825_MISR2_EEE_ERROR_INT 0x8000
308 #define DP83825_MISR2_AN_ERROR_INT 0x4000
309 #define DP83825_MISR2_PR_INT 0x2000
310 #define DP83825_MISR2_FIFO_OF_UF_INT 0x1000
311 #define DP83825_MISR2_MDI_CHANGE_INT 0x0800
312 #define DP83825_MISR2_SLEEP_MODE_INT 0x0400
313 #define DP83825_MISR2_POL_CHANGE_INT 0x0200
314 #define DP83825_MISR2_JABBER_DETECT_INT 0x0100
315 #define DP83825_MISR2_EEE_ERROR_INT_EN 0x0080
316 #define DP83825_MISR2_AN_ERROR_INT_EN 0x0040
317 #define DP83825_MISR2_PR_INT_EN 0x0020
318 #define DP83825_MISR2_FIFO_OF_UF_INT_EN 0x0010
319 #define DP83825_MISR2_MDI_CHANGE_INT_EN 0x0008
320 #define DP83825_MISR2_SLEEP_MODE_INT_EN 0x0004
321 #define DP83825_MISR2_POL_CHANGE_INT_EN 0x0002
322 #define DP83825_MISR2_JABBER_DETECT_INT_EN 0x0001
323 
324 //FCSCR register
325 #define DP83825_FCSCR_FCSCNT 0x00FF
326 
327 //RECR register
328 #define DP83825_RECR_RXERCNT 0xFFFF
329 
330 //BISCR register
331 #define DP83825_BISCR_ERROR_COUNTER_MODE 0x4000
332 #define DP83825_BISCR_PRBS_CHECKER 0x2000
333 #define DP83825_BISCR_PACKET_GEN_EN 0x1000
334 #define DP83825_BISCR_PRBS_CHECKER_LOCK_SYNC 0x0800
335 #define DP83825_BISCR_PRBS_CHECKER_SYNC_LOSS 0x0400
336 #define DP83825_BISCR_PACKET_GEN_STATUS 0x0200
337 #define DP83825_BISCR_POWER_MODE 0x0100
338 #define DP83825_BISCR_TX_MII_LOOPBACK 0x0040
339 #define DP83825_BISCR_LOOPBACK_MODE 0x001F
340 #define DP83825_BISCR_LOOPBACK_MODE_PCS_INPUT 0x0001
341 #define DP83825_BISCR_LOOPBACK_MODE_PCS_OUTPUT 0x0002
342 #define DP83825_BISCR_LOOPBACK_MODE_DIGITAL 0x0004
343 #define DP83825_BISCR_LOOPBACK_MODE_ANALOG 0x0008
344 #define DP83825_BISCR_LOOPBACK_MODE_REVERSE 0x0010
345 
346 //RCSR register
347 #define DP83825_RCSR_RMII_TX_CLOCK_SHIFT 0x0100
348 #define DP83825_RCSR_RMII_CLK_SEL 0x0080
349 #define DP83825_RCSR_RMII_REV_SEL 0x0010
350 #define DP83825_RCSR_RMII_OVF_STATUS 0x0008
351 #define DP83825_RCSR_RMII_UNF_STATUS 0x0004
352 #define DP83825_RCSR_RX_ELAST_BUFFER_SIZE 0x0003
353 #define DP83825_RCSR_RX_ELAST_BUFFER_SIZE_14_BITS 0x0000
354 #define DP83825_RCSR_RX_ELAST_BUFFER_SIZE_2_BITS 0x0001
355 #define DP83825_RCSR_RX_ELAST_BUFFER_SIZE_6_BITS 0x0002
356 #define DP83825_RCSR_RX_ELAST_BUFFER_SIZE_10_BITS 0x0003
357 
358 //LEDCR register
359 #define DP83825_LEDCR_BLINK_RATE 0x0600
360 #define DP83825_LEDCR_BLINK_RATE_20MHZ 0x0000
361 #define DP83825_LEDCR_BLINK_RATE_10MHZ 0x0200
362 #define DP83825_LEDCR_BLINK_RATE_5MHZ 0x0400
363 #define DP83825_LEDCR_BLINK_RATE_2MHZ 0x0600
364 #define DP83825_LEDCR_LED_LINK_POLARITY 0x0080
365 #define DP83825_LEDCR_DRIVE_LINK_LED 0x0010
366 #define DP83825_LEDCR_LINK_LED_ON_OFF 0x0002
367 
368 //PHYCR register
369 #define DP83825_PHYCR_MDIX_EN 0x8000
370 #define DP83825_PHYCR_FORCE_MDIX 0x4000
371 #define DP83825_PHYCR_PAUSE_RX_STATUS 0x2000
372 #define DP83825_PHYCR_PAUSE_TX_STATUS 0x1000
373 #define DP83825_PHYCR_MII_LINK_STATUS 0x0800
374 #define DP83825_PHYCR_BYPASS_LED_STRETCH 0x0080
375 #define DP83825_PHYCR_LED_CONFIG 0x0020
376 #define DP83825_PHYCR_PHY_ADDR 0x001F
377 
378 //10BTSCR register
379 #define DP83825_10BTSCR_RX_THRESHOLD_EN 0x2000
380 #define DP83825_10BTSCR_SQUELCH 0x1E00
381 #define DP83825_10BTSCR_SQUELCH_200MV 0x0000
382 #define DP83825_10BTSCR_SQUELCH_250MV 0x0200
383 #define DP83825_10BTSCR_SQUELCH_300MV 0x0400
384 #define DP83825_10BTSCR_SQUELCH_350MV 0x0600
385 #define DP83825_10BTSCR_SQUELCH_400MV 0x0800
386 #define DP83825_10BTSCR_SQUELCH_450MV 0x0A00
387 #define DP83825_10BTSCR_SQUELCH_500MV 0x0C00
388 #define DP83825_10BTSCR_SQUELCH_550MV 0x0E00
389 #define DP83825_10BTSCR_SQUELCH_600MV 0x1000
390 #define DP83825_10BTSCR_NLP_DIS 0x0080
391 #define DP83825_10BTSCR_POLARITY_STATUS 0x0010
392 #define DP83825_10BTSCR_JABBER_DIS 0x0001
393 
394 //BICSR1 register
395 #define DP83825_BICSR1_BIST_ERROR_COUNT 0xFF00
396 #define DP83825_BICSR1_BIST_IPG_LENGTH 0x00FF
397 
398 //BICSR2 register
399 #define DP83825_BICSR2_BIST_PACKET_LENGTH 0x07FF
400 
401 //CDCR register
402 #define DP83825_CDCR_CABLE_DIAG_START 0x8000
403 #define DP83825_CDCR_CFG_RESCAL_EN 0x4000
404 #define DP83825_CDCR_CDCR_CABLE_DIAG_STATUS 0x0002
405 #define DP83825_CDCR_CDCR_CABLE_DIAG_TEST_FAIL 0x0001
406 
407 //PHYRCR register
408 #define DP83825_PHYRCR_SOFT_HARD_RESET 0x8000
409 #define DP83825_PHYRCR_DIGITAL_RESET 0x4000
410 
411 //MLEDCR register
412 #define DP83825_MLEDCR_MLED_POLARITY_SWAP 0x0200
413 #define DP83825_MLEDCR_LED0_CONFIG 0x0078
414 #define DP83825_MLEDCR_LED0_CONFIG_LINK 0x0000
415 #define DP83825_MLEDCR_LED0_CONFIG_ACT 0x0008
416 #define DP83825_MLEDCR_LED0_CONFIG_TX_ACT 0x0010
417 #define DP83825_MLEDCR_LED0_CONFIG_RX_ACT 0x0018
418 #define DP83825_MLEDCR_LED0_CONFIG_COL 0x0020
419 #define DP83825_MLEDCR_LED0_CONFIG_SPEED_100 0x0028
420 #define DP83825_MLEDCR_LED0_CONFIG_SPEED_10 0x0030
421 #define DP83825_MLEDCR_LED0_CONFIG_FD 0x0038
422 #define DP83825_MLEDCR_LED0_CONFIG_LINK_ACT 0x0040
423 #define DP83825_MLEDCR_LED0_CONFIG_ACT_STRETCH_SIG 0x0048
424 #define DP83825_MLEDCR_LED0_CONFIG_MII_LINK 0x0050
425 #define DP83825_MLEDCR_LED0_CONFIG_LPI_MODE 0x0058
426 #define DP83825_MLEDCR_LED0_CONFIG_MII_ERR 0x0060
427 #define DP83825_MLEDCR_LED0_CONFIG_LINK_LOST 0x0068
428 #define DP83825_MLEDCR_LED0_CONFIG_PRBS_ERR 0x0070
429 #define DP83825_MLEDCR_CFG_MLED_EN 0x0001
430 
431 //C++ guard
432 #ifdef __cplusplus
433 extern "C" {
434 #endif
435 
436 //DP83825 Ethernet PHY driver
437 extern const PhyDriver dp83825PhyDriver;
438 
439 //DP83825 related functions
440 error_t dp83825Init(NetInterface *interface);
441 void dp83825InitHook(NetInterface *interface);
442 
443 void dp83825Tick(NetInterface *interface);
444 
445 void dp83825EnableIrq(NetInterface *interface);
446 void dp83825DisableIrq(NetInterface *interface);
447 
448 void dp83825EventHandler(NetInterface *interface);
449 
450 void dp83825WritePhyReg(NetInterface *interface, uint8_t address,
451  uint16_t data);
452 
453 uint16_t dp83825ReadPhyReg(NetInterface *interface, uint8_t address);
454 
455 void dp83825DumpPhyReg(NetInterface *interface);
456 
457 void dp83825WriteMmdReg(NetInterface *interface, uint8_t devAddr,
458  uint16_t regAddr, uint16_t data);
459 
460 uint16_t dp83825ReadMmdReg(NetInterface *interface, uint8_t devAddr,
461  uint16_t regAddr);
462 
463 //C++ guard
464 #ifdef __cplusplus
465 }
466 #endif
467 
468 #endif
void dp83825WriteMmdReg(NetInterface *interface, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
void dp83825EventHandler(NetInterface *interface)
DP83825 event handler.
void dp83825Tick(NetInterface *interface)
DP83825 timer handler.
uint16_t dp83825ReadMmdReg(NetInterface *interface, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
void dp83825WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void dp83825DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
uint16_t dp83825ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void dp83825InitHook(NetInterface *interface)
DP83825 custom configuration.
void dp83825EnableIrq(NetInterface *interface)
Enable interrupts.
void dp83825DisableIrq(NetInterface *interface)
Disable interrupts.
error_t dp83825Init(NetInterface *interface)
DP83825 PHY transceiver initialization.
const PhyDriver dp83825PhyDriver
DP83825 Ethernet PHY driver.
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
Ipv6Addr address[]
Definition: ipv6.h:316
uint16_t regAddr
#define NetInterface
Definition: net.h:36
Network interface controller abstraction layer.
Ethernet PHY driver.
Definition: nic.h:308