32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "esp_crypto_lock.h"
36 #include "hal/sha_types.h"
37 #include "soc/hwcrypto_reg.h"
38 #include "soc/dport_access.h"
39 #include "esp_private/periph_ctrl.h"
47 #if (ESP32_CRYPTO_HASH_SUPPORT == ENABLED)
72 DPORT_REG_WRITE(SHA_TEXT_BASE, temp);
74 DPORT_REG_WRITE(SHA_TEXT_BASE + 4, temp);
76 DPORT_REG_WRITE(SHA_TEXT_BASE + 8, temp);
78 DPORT_REG_WRITE(SHA_TEXT_BASE + 12, temp);
80 DPORT_REG_WRITE(SHA_TEXT_BASE + 16, temp);
82 DPORT_REG_WRITE(SHA_TEXT_BASE + 20, temp);
84 DPORT_REG_WRITE(SHA_TEXT_BASE + 24, temp);
86 DPORT_REG_WRITE(SHA_TEXT_BASE + 28, temp);
88 DPORT_REG_WRITE(SHA_TEXT_BASE + 32, temp);
90 DPORT_REG_WRITE(SHA_TEXT_BASE + 36, temp);
92 DPORT_REG_WRITE(SHA_TEXT_BASE + 40, temp);
94 DPORT_REG_WRITE(SHA_TEXT_BASE + 44, temp);
96 DPORT_REG_WRITE(SHA_TEXT_BASE + 48, temp);
98 DPORT_REG_WRITE(SHA_TEXT_BASE + 52, temp);
100 DPORT_REG_WRITE(SHA_TEXT_BASE + 56, temp);
102 DPORT_REG_WRITE(SHA_TEXT_BASE + 60, temp);
105 if(algo == SHA2_384 || algo == SHA2_512)
108 DPORT_REG_WRITE(SHA_TEXT_BASE + 64, temp);
110 DPORT_REG_WRITE(SHA_TEXT_BASE + 68, temp);
112 DPORT_REG_WRITE(SHA_TEXT_BASE + 72, temp);
114 DPORT_REG_WRITE(SHA_TEXT_BASE + 76, temp);
116 DPORT_REG_WRITE(SHA_TEXT_BASE + 80, temp);
118 DPORT_REG_WRITE(SHA_TEXT_BASE + 84, temp);
120 DPORT_REG_WRITE(SHA_TEXT_BASE + 88, temp);
122 DPORT_REG_WRITE(SHA_TEXT_BASE + 92, temp);
124 DPORT_REG_WRITE(SHA_TEXT_BASE + 96, temp);
126 DPORT_REG_WRITE(SHA_TEXT_BASE + 100, temp);
128 DPORT_REG_WRITE(SHA_TEXT_BASE + 104, temp);
130 DPORT_REG_WRITE(SHA_TEXT_BASE + 108, temp);
132 DPORT_REG_WRITE(SHA_TEXT_BASE + 112, temp);
134 DPORT_REG_WRITE(SHA_TEXT_BASE + 116, temp);
136 DPORT_REG_WRITE(SHA_TEXT_BASE + 120, temp);
138 DPORT_REG_WRITE(SHA_TEXT_BASE + 124, temp);
148 DPORT_REG_WRITE(SHA_1_START_REG, 1);
152 DPORT_REG_WRITE(SHA_1_CONTINUE_REG, 1);
156 while(DPORT_REG_READ(SHA_1_BUSY_REG) != 0)
160 else if(algo == SHA2_256)
165 DPORT_REG_WRITE(SHA_256_START_REG, 1);
169 DPORT_REG_WRITE(SHA_256_CONTINUE_REG, 1);
173 while(DPORT_REG_READ(SHA_256_BUSY_REG) != 0)
177 else if(algo == SHA2_384)
182 DPORT_REG_WRITE(SHA_384_START_REG, 1);
186 DPORT_REG_WRITE(SHA_384_CONTINUE_REG, 1);
190 while(DPORT_REG_READ(SHA_384_BUSY_REG) != 0)
199 DPORT_REG_WRITE(SHA_512_START_REG, 1);
203 DPORT_REG_WRITE(SHA_512_CONTINUE_REG, 1);
207 while(DPORT_REG_READ(SHA_512_BUSY_REG) != 0)
217 #if (SHA1_SUPPORT == ENABLED)
235 esp_crypto_sha_aes_lock_acquire();
237 periph_module_enable(PERIPH_SHA_MODULE);
272 DPORT_REG_WRITE(SHA_1_LOAD_REG, 1);
275 while(DPORT_REG_READ(SHA_1_BUSY_REG) != 0)
280 DPORT_INTERRUPT_DISABLE();
281 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
283 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
285 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
287 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
289 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
291 DPORT_INTERRUPT_RESTORE();
294 periph_module_disable(PERIPH_SHA_MODULE);
296 esp_crypto_sha_aes_lock_release();
303 #if (SHA256_SUPPORT == ENABLED)
321 esp_crypto_sha_aes_lock_acquire();
323 periph_module_enable(PERIPH_SHA_MODULE);
358 DPORT_REG_WRITE(SHA_256_LOAD_REG, 1);
361 while(DPORT_REG_READ(SHA_256_BUSY_REG) != 0)
366 DPORT_INTERRUPT_DISABLE();
367 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
369 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
371 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
373 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
375 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
377 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
379 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
381 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
383 DPORT_INTERRUPT_RESTORE();
386 periph_module_disable(PERIPH_SHA_MODULE);
388 esp_crypto_sha_aes_lock_release();
395 #if (SHA384_SUPPORT == ENABLED)
413 esp_crypto_sha_aes_lock_acquire();
415 periph_module_enable(PERIPH_SHA_MODULE);
450 DPORT_REG_WRITE(SHA_384_LOAD_REG, 1);
453 while(DPORT_REG_READ(SHA_384_BUSY_REG) != 0)
458 DPORT_INTERRUPT_DISABLE();
459 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
461 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
463 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
465 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
467 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
469 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
471 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
473 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
475 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 32);
477 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 36);
479 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 40);
481 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 44);
483 DPORT_INTERRUPT_RESTORE();
486 periph_module_disable(PERIPH_SHA_MODULE);
488 esp_crypto_sha_aes_lock_release();
495 #if (SHA512_SUPPORT == ENABLED)
513 esp_crypto_sha_aes_lock_acquire();
515 periph_module_enable(PERIPH_SHA_MODULE);
550 DPORT_REG_WRITE(SHA_512_LOAD_REG, 1);
553 while(DPORT_REG_READ(SHA_512_BUSY_REG) != 0)
558 DPORT_INTERRUPT_DISABLE();
559 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
561 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
563 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
565 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
567 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
569 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
571 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
573 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
575 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 32);
577 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 36);
579 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 40);
581 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 44);
583 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 48);
585 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 52);
587 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 56);
589 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 60);
591 DPORT_INTERRUPT_RESTORE();
594 periph_module_disable(PERIPH_SHA_MODULE);
596 esp_crypto_sha_aes_lock_release();