esp32_eth_driver.h
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1 /**
2  * @file esp32_eth_driver.h
3  * @brief ESP32 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _ESP32_ETH_DRIVER_H
32 #define _ESP32_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef ESP32_ETH_TX_BUFFER_COUNT
39  #define ESP32_ETH_TX_BUFFER_COUNT 3
40 #elif (ESP32_ETH_TX_BUFFER_COUNT < 1)
41  #error ESP32_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef ESP32_ETH_TX_BUFFER_SIZE
46  #define ESP32_ETH_TX_BUFFER_SIZE 1536
47 #elif (ESP32_ETH_TX_BUFFER_SIZE != 1536)
48  #error ESP32_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef ESP32_ETH_RX_BUFFER_COUNT
53  #define ESP32_ETH_RX_BUFFER_COUNT 6
54 #elif (ESP32_ETH_RX_BUFFER_COUNT < 1)
55  #error ESP32_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef ESP32_ETH_RX_BUFFER_SIZE
60  #define ESP32_ETH_RX_BUFFER_SIZE 1536
61 #elif (ESP32_ETH_RX_BUFFER_SIZE != 1536)
62  #error ESP32_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Ethernet interrupt flags
66 #ifndef ESP32_ETH_IRQ_FLAGS
67  #define ESP32_ETH_IRQ_FLAGS ESP_INTR_FLAG_LEVEL2
68 #endif
69 
70 //DMA configuration and control registers
71 #define EMAC_DMABUSMODE_REG *((volatile uint32_t *) 0x3FF69000)
72 #define EMAC_DMATXPOLLDEMAND_REG *((volatile uint32_t *) 0x3FF69004)
73 #define EMAC_DMARXPOLLDEMAND_REG *((volatile uint32_t *) 0x3FF69008)
74 #define EMAC_DMARXBASEADDR_REG *((volatile uint32_t *) 0x3FF6900C)
75 #define EMAC_DMATXBASEADDR_REG *((volatile uint32_t *) 0x3FF69010)
76 #define EMAC_DMASTATUS_REG *((volatile uint32_t *) 0x3FF69014)
77 #define EMAC_DMAOPERATION_MODE_REG *((volatile uint32_t *) 0x3FF69018)
78 #define EMAC_DMAIN_EN_REG *((volatile uint32_t *) 0x3FF6901C)
79 #define EMAC_DMAMISSEDFR_REG *((volatile uint32_t *) 0x3FF69020)
80 #define EMAC_DMARINTWDTIMER_REG *((volatile uint32_t *) 0x3FF69024)
81 #define EMAC_DMATXCURRDESC_REG *((volatile uint32_t *) 0x3FF69048)
82 #define EMAC_DMARXCURRDESC_REG *((volatile uint32_t *) 0x3FF6904C)
83 #define EMAC_DMATXCURRADDR_BUF_REG *((volatile uint32_t *) 0x3FF69050)
84 #define EMAC_DMARXCURRADDR_BUF_REG *((volatile uint32_t *) 0x3FF69054)
85 
86 //MAC configuration and control registers
87 #define EMAC_CONFIG_REG *((volatile uint32_t *) 0x3FF6A000)
88 #define EMAC_FF_REG *((volatile uint32_t *) 0x3FF6A004)
89 #define EMAC_MIIADDR_REG *((volatile uint32_t *) 0x3FF6A010)
90 #define EMAC_MIIDATA_REG *((volatile uint32_t *) 0x3FF6A014)
91 #define EMAC_FC_REG *((volatile uint32_t *) 0x3FF6A018)
92 #define EMAC_DEBUG_REG *((volatile uint32_t *) 0x3FF6A024)
93 #define EMAC_PMT_RWUFFR_REG *((volatile uint32_t *) 0x3FF6A028)
94 #define EMAC_PMT_CSR_REG *((volatile uint32_t *) 0x3FF6A02C)
95 #define EMAC_LPI_CSR_REG *((volatile uint32_t *) 0x3FF6A030)
96 #define EMAC_LPITIMERSCONTROL_REG *((volatile uint32_t *) 0x3FF6A034)
97 #define EMAC_INTS_REG *((volatile uint32_t *) 0x3FF6A038)
98 #define EMAC_INTMASK_REG *((volatile uint32_t *) 0x3FF6A03C)
99 #define EMAC_ADDR0HIGH_REG *((volatile uint32_t *) 0x3FF6A040)
100 #define EMAC_ADDR0LOW_REG *((volatile uint32_t *) 0x3FF6A044)
101 #define EMAC_ADDR1HIGH_REG *((volatile uint32_t *) 0x3FF6A048)
102 #define EMAC_ADDR1LOW_REG *((volatile uint32_t *) 0x3FF6A04C)
103 #define EMAC_ADDR2HIGH_REG *((volatile uint32_t *) 0x3FF6A050)
104 #define EMAC_ADDR2LOW_REG *((volatile uint32_t *) 0x3FF6A054)
105 #define EMAC_ADDR3HIGH_REG *((volatile uint32_t *) 0x3FF6A058)
106 #define EMAC_ADDR3LOW_REG *((volatile uint32_t *) 0x3FF6A05C)
107 #define EMAC_ADDR4HIGH_REG *((volatile uint32_t *) 0x3FF6A060)
108 #define EMAC_ADDR4LOW_REG *((volatile uint32_t *) 0x3FF6A064)
109 #define EMAC_ADDR5HIGH_REG *((volatile uint32_t *) 0x3FF6A068)
110 #define EMAC_ADDR5LOW_REG *((volatile uint32_t *) 0x3FF6A06C)
111 #define EMAC_ADDR6HIGH_REG *((volatile uint32_t *) 0x3FF6A070)
112 #define EMAC_ADDR6LOW_REG *((volatile uint32_t *) 0x3FF6A074)
113 #define EMAC_ADDR7HIGH_REG *((volatile uint32_t *) 0x3FF6A078)
114 #define EMAC_ADDR7LOW_REG *((volatile uint32_t *) 0x3FF6A07C)
115 #define EMAC_STATUS_REG *((volatile uint32_t *) 0x3FF6A0D8)
116 #define EMAC_WDOGTO_REG *((volatile uint32_t *) 0x3FF6A0DC)
117 
118 //Clock configuration registers
119 #define EMAC_EX_CLKOUT_CONF_REG *((volatile uint32_t *) 0x3FF69800)
120 #define EMAC_EX_OSCCLK_CONF_REG *((volatile uint32_t *) 0x3FF69804)
121 #define EMAC_EX_CLK_CTRL_REG *((volatile uint32_t *) 0x3FF69808)
122 
123 //PHY type and SRAM configuration registers
124 #define EMAC_EX_PHYINF_CONF_REG *((volatile uint32_t *) 0x3FF6980C)
125 #define EMAC_PD_SEL_REG *((volatile uint32_t *) 0x3FF69810)
126 
127 //DMA Bus Mode register
128 #define EMAC_DMABUSMODE_DMAMIXEDBURST 0x04000000
129 #define EMAC_DMABUSMODE_DMAADDRALIBEA 0x02000000
130 #define EMAC_DMABUSMODE_PBLX8_MODE 0x01000000
131 #define EMAC_DMABUSMODE_USE_SEP_PBL 0x00800000
132 #define EMAC_DMABUSMODE_RX_DMA_PBL 0x007E0000
133 #define EMAC_DMABUSMODE_RX_DMA_PBL_1 0x00020000
134 #define EMAC_DMABUSMODE_RX_DMA_PBL_2 0x00040000
135 #define EMAC_DMABUSMODE_RX_DMA_PBL_4 0x00080000
136 #define EMAC_DMABUSMODE_RX_DMA_PBL_8 0x00100000
137 #define EMAC_DMABUSMODE_RX_DMA_PBL_16 0x00200000
138 #define EMAC_DMABUSMODE_RX_DMA_PBL_32 0x00400000
139 #define EMAC_DMABUSMODE_FIXED_BURST 0x00010000
140 #define EMAC_DMABUSMODE_PRI_RATIO 0x0000C000
141 #define EMAC_DMABUSMODE_PRI_RATIO_1_1 0x00000000
142 #define EMAC_DMABUSMODE_PRI_RATIO_2_1 0x00004000
143 #define EMAC_DMABUSMODE_PRI_RATIO_3_1 0x00008000
144 #define EMAC_DMABUSMODE_PRI_RATIO_4_1 0x0000C000
145 #define EMAC_DMABUSMODE_PROG_BURST_LEN 0x00003F00
146 #define EMAC_DMABUSMODE_PROG_BURST_LEN_1 0x00000100
147 #define EMAC_DMABUSMODE_PROG_BURST_LEN_2 0x00000200
148 #define EMAC_DMABUSMODE_PROG_BURST_LEN_4 0x00000400
149 #define EMAC_DMABUSMODE_PROG_BURST_LEN_8 0x00000800
150 #define EMAC_DMABUSMODE_PROG_BURST_LEN_16 0x00001000
151 #define EMAC_DMABUSMODE_PROG_BURST_LEN_32 0x00002000
152 #define EMAC_DMABUSMODE_ALT_DESC_SIZE 0x00000080
153 #define EMAC_DMABUSMODE_DESC_SKIP_LEN 0x0000007C
154 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_0 0x00000000
155 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_1 0x00000004
156 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_2 0x00000008
157 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_4 0x00000010
158 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_8 0x00000020
159 #define EMAC_DMABUSMODE_DESC_SKIP_LEN_16 0x00000040
160 #define EMAC_DMABUSMODE_DMA_ARB_SCH 0x00000002
161 #define EMAC_DMABUSMODE_SW_RST 0x00000001
162 
163 //DMA Status register
164 #define EMAC_DMASTATUS_TS_TRI_INT 0x20000000
165 #define EMAC_DMASTATUS_EMAC_PMT_INT 0x10000000
166 #define EMAC_DMASTATUS_ERROR_BITS 0x03800000
167 #define EMAC_DMASTATUS_TRANS_PROC_STATE 0x00700000
168 #define EMAC_DMASTATUS_RECV_PROC_STATE 0x000E0000
169 #define EMAC_DMASTATUS_NORM_INT_SUMM 0x00010000
170 #define EMAC_DMASTATUS_ABN_INT_SUMM 0x00008000
171 #define EMAC_DMASTATUS_EARLY_RECV_INT 0x00004000
172 #define EMAC_DMASTATUS_FATAL_BUS_ERR_INT 0x00002000
173 #define EMAC_DMASTATUS_EARLY_TRANS_INT 0x00000400
174 #define EMAC_DMASTATUS_RECV_WDT_TO 0x00000200
175 #define EMAC_DMASTATUS_RECV_PROC_STOP 0x00000100
176 #define EMAC_DMASTATUS_RECV_BUF_UNAVAIL 0x00000080
177 #define EMAC_DMASTATUS_RECV_INT 0x00000040
178 #define EMAC_DMASTATUS_TRANS_UNDFLOW 0x00000020
179 #define EMAC_DMASTATUS_RECV_OVFLOW 0x00000010
180 #define EMAC_DMASTATUS_TRANS_JABBER_TO 0x00000008
181 #define EMAC_DMASTATUS_TRANS_BUF_UNAVAIL 0x00000004
182 #define EMAC_DMASTATUS_TRANS_PROC_STOP 0x00000002
183 #define EMAC_DMASTATUS_TRANS_INT 0x00000001
184 
185 //DMA Operation Mode register
186 #define EMAC_DMAOPERATION_MODE_DIS_DROP_TCPIP_ERR_FRAM 0x04000000
187 #define EMAC_DMAOPERATION_MODE_RX_STORE_FORWARD 0x02000000
188 #define EMAC_DMAOPERATION_MODE_DIS_FLUSH_RECV_FRAMES 0x01000000
189 #define EMAC_DMAOPERATION_MODE_TX_STORE_FORWARD 0x00200000
190 #define EMAC_DMAOPERATION_MODE_FLUSH_TX_FIFO 0x00100000
191 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL 0x0001C000
192 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_64 0x00000000
193 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_128 0x00004000
194 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_192 0x00008000
195 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_256 0x0000C000
196 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_40 0x00010000
197 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_32 0x00014000
198 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_24 0x00018000
199 #define EMAC_DMAOPERATION_MODE_TX_THRESH_CTRL_16 0x0001C000
200 #define EMAC_DMAOPERATION_MODE_START_STOP_TX 0x00002000
201 #define EMAC_DMAOPERATION_MODE_FWD_ERR_FRAME 0x00000080
202 #define EMAC_DMAOPERATION_MODE_FWD_UNDER_GF 0x00000040
203 #define EMAC_DMAOPERATION_MODE_DROP_GFRM 0x00000020
204 #define EMAC_DMAOPERATION_MODE_RX_THRESH_CTRL 0x00000018
205 #define EMAC_DMAOPERATION_MODE_RX_THRESH_CTRL_64 0x00000000
206 #define EMAC_DMAOPERATION_MODE_RX_THRESH_CTRL_32 0x00000008
207 #define EMAC_DMAOPERATION_MODE_RX_THRESH_CTRL_96 0x00000010
208 #define EMAC_DMAOPERATION_MODE_RX_THRESH_CTRL_128 0x00000018
209 #define EMAC_DMAOPERATION_MODE_OPT_SECOND_FRAME 0x00000004
210 #define EMAC_DMAOPERATION_MODE_START_STOP_RX 0x00000002
211 
212 //DMA Interrupt Enable register
213 #define EMAC_DMAIN_EN_DMAIN_NISE 0x00010000
214 #define EMAC_DMAIN_EN_DMAIN_AISE 0x00008000
215 #define EMAC_DMAIN_EN_DMAIN_ERIE 0x00004000
216 #define EMAC_DMAIN_EN_DMAIN_FBEE 0x00002000
217 #define EMAC_DMAIN_EN_DMAIN_ETIE 0x00000400
218 #define EMAC_DMAIN_EN_DMAIN_RWTE 0x00000200
219 #define EMAC_DMAIN_EN_DMAIN_RSE 0x00000100
220 #define EMAC_DMAIN_EN_DMAIN_RBUE 0x00000080
221 #define EMAC_DMAIN_EN_DMAIN_RIE 0x00000040
222 #define EMAC_DMAIN_EN_DMAIN_UIE 0x00000020
223 #define EMAC_DMAIN_EN_DMAIN_OIE 0x00000010
224 #define EMAC_DMAIN_EN_DMAIN_TJTE 0x00000008
225 #define EMAC_DMAIN_EN_DMAIN_TBUE 0x00000004
226 #define EMAC_DMAIN_EN_DMAIN_TSE 0x00000002
227 #define EMAC_DMAIN_EN_DMAIN_TIE 0x00000001
228 
229 //Missed Frame and Buffer Overflow Counter register
230 #define EMAC_DMAMISSEDFR_OVERFLOW_BFOC 0x10000000
231 #define EMAC_DMAMISSEDFR_OVERFLOW_FC 0x0FFE0000
232 #define EMAC_DMAMISSEDFR_OVERFLOW_BMFC 0x00010000
233 #define EMAC_DMAMISSEDFR_MISSED_FC 0x0000FFFF
234 
235 //DMA Receive Status Watchdog Timer register
236 #define EMAC_DMARINTWDTIMER_RIWTC 0x000000FF
237 
238 //DMA Current Host Transmit Descriptor register
239 #define EMAC_DMATXCURRDESC_TRANS_DSCR_ADDR_PTR 0xFFFFFFFF
240 
241 //DMA Current Host Receive Descriptor register
242 #define EMAC_DMARXCURRDESC_RECV_DSCR_ADDR_PTR 0xFFFFFFFF
243 
244 //DMA Current Host Transmit Buffer Address register
245 #define EMAC_DMATXCURRADDR_BUF_TRANS_BUFF_ADDR_PTR 0xFFFFFFFF
246 
247 //DMA Current Host Receive Buffer Address register
248 #define EMAC_DMARXCURRADDR_BUF_RECV_BUFF_ADDR_PTR 0xFFFFFFFF
249 
250 //MAC Configuration register
251 #define EMAC_CONFIG_SAIRC 0x70000000
252 #define EMAC_CONFIG_ASS2KP 0x08000000
253 #define EMAC_CONFIG_EMACWATCHDOG 0x00800000
254 #define EMAC_CONFIG_EMACJABBER 0x00400000
255 #define EMAC_CONFIG_EMACJUMBOFRAME 0x00100000
256 #define EMAC_CONFIG_EMACINTERFRAMEGAP 0x000E0000
257 #define EMAC_CONFIG_EMACINTERFRAMEGAP_96 0x00000000
258 #define EMAC_CONFIG_EMACINTERFRAMEGAP_88 0x00020000
259 #define EMAC_CONFIG_EMACINTERFRAMEGAP_80 0x00040000
260 #define EMAC_CONFIG_EMACINTERFRAMEGAP_72 0x00060000
261 #define EMAC_CONFIG_EMACINTERFRAMEGAP_64 0x00080000
262 #define EMAC_CONFIG_EMACINTERFRAMEGAP_56 0x000A0000
263 #define EMAC_CONFIG_EMACINTERFRAMEGAP_48 0x000C0000
264 #define EMAC_CONFIG_EMACINTERFRAMEGAP_40 0x000E0000
265 #define EMAC_CONFIG_EMACDISABLECRS 0x00010000
266 #define EMAC_CONFIG_EMACMII 0x00008000
267 #define EMAC_CONFIG_EMACFESPEED 0x00004000
268 #define EMAC_CONFIG_EMACRXOWN 0x00002000
269 #define EMAC_CONFIG_EMACLOOPBACK 0x00001000
270 #define EMAC_CONFIG_EMACDUPLEX 0x00000800
271 #define EMAC_CONFIG_EMACRXIPCOFFLOAD 0x00000400
272 #define EMAC_CONFIG_EMACRETRY 0x00000200
273 #define EMAC_CONFIG_EMACPADCRCSTRIP 0x00000080
274 #define EMAC_CONFIG_EMACBACKOFFLIMIT 0x00000060
275 #define EMAC_CONFIG_EMACBACKOFFLIMIT_10 0x00000040
276 #define EMAC_CONFIG_EMACBACKOFFLIMIT_8 0x00000020
277 #define EMAC_CONFIG_EMACBACKOFFLIMIT_4 0x00000040
278 #define EMAC_CONFIG_EMACBACKOFFLIMIT_1 0x00000060
279 #define EMAC_CONFIG_EMACDEFERRALCHECK 0x00000010
280 #define EMAC_CONFIG_EMACTX 0x00000008
281 #define EMAC_CONFIG_EMACRX 0x00000004
282 #define EMAC_CONFIG_PLTF 0x00000003
283 #define EMAC_CONFIG_PLTF_7 0x00000000
284 #define EMAC_CONFIG_PLTF_5 0x00000001
285 #define EMAC_CONFIG_PLTF_3 0x00000002
286 
287 //Frame Filter register
288 #define EMAC_FF_RECEIVE_ALL 0x80000000
289 #define EMAC_FF_SAFE 0x00000200
290 #define EMAC_FF_SAIF 0x00000100
291 #define EMAC_FF_PCF 0x000000C0
292 #define EMAC_FF_DBF 0x00000020
293 #define EMAC_FF_PAM 0x00000010
294 #define EMAC_FF_DAIF 0x00000008
295 #define EMAC_FF_PMODE 0x00000001
296 
297 //MAC MII Address register
298 #define EMAC_MIIADDR_MIIDEV 0x0000F800
299 #define EMAC_MIIADDR_MIIREG 0x000007C0
300 #define EMAC_MIIADDR_MIICSRCLK 0x0000003C
301 #define EMAC_MIIADDR_MIICSRCLK_DIV_42 0x00000000
302 #define EMAC_MIIADDR_MIICSRCLK_DIV_62 0x00000004
303 #define EMAC_MIIADDR_MIICSRCLK_DIV_16 0x00000008
304 #define EMAC_MIIADDR_MIICSRCLK_DIV_26 0x0000000C
305 #define EMAC_MIIADDR_MIICSRCLK_DIV_102 0x00000010
306 #define EMAC_MIIADDR_MIICSRCLK_DIV_124 0x00000014
307 #define EMAC_MIIADDR_MIIWRITE 0x00000002
308 #define EMAC_MIIADDR_MIIBUSY 0x00000001
309 
310 //MAC MII Data register
311 #define EMAC_MIIDATA_MII_DATA 0x0000FFFF
312 
313 //MAC Flow Control register
314 #define EMAC_FC_PAUSE_TIME 0xFFFF0000
315 #define EMAC_FC_PLT 0x00000030
316 #define EMAC_FC_UPFD 0x00000008
317 #define EMAC_FC_RFCE 0x00000004
318 #define EMAC_FC_TFCE 0x00000002
319 #define EMAC_FC_FCBBA 0x00000001
320 
321 //MAC Debug register
322 #define EMAC_DEBUG_MTLTSFFS 0x02000000
323 #define EMAC_DEBUG_MTLTFNES 0x01000000
324 #define EMAC_DEBUG_MTLTFWCS 0x00400000
325 #define EMAC_DEBUG_MTLTFRCS 0x00300000
326 #define EMAC_DEBUG_MTLTFRCS_IDLE 0x00000000
327 #define EMAC_DEBUG_MTLTFRCS_READ 0x00100000
328 #define EMAC_DEBUG_MTLTFRCS_WAITING 0x00200000
329 #define EMAC_DEBUG_MTLTFRCS_WRITING 0x00300000
330 #define EMAC_DEBUG_MACTP 0x00080000
331 #define EMAC_DEBUG_MACTFCS 0x00060000
332 #define EMAC_DEBUG_MACTFCS_IDLE 0x00000000
333 #define EMAC_DEBUG_MACTFCS_WAITING_STATUS 0x00020000
334 #define EMAC_DEBUG_MACTFCS_GENERATING_PAUSE 0x00040000
335 #define EMAC_DEBUG_MACTFCS_TRANSFERRING_FRAME 0x00060000
336 #define EMAC_DEBUG_MACTPES 0x00010000
337 #define EMAC_DEBUG_MTLRFFLS 0x00000300
338 #define EMAC_DEBUG_MTLRFFLS_EMPTY 0x00000000
339 #define EMAC_DEBUG_MTLRFFLS_BELOW_THRESHOLD 0x00000100
340 #define EMAC_DEBUG_MTLRFFLS_ABOVE_THRESHOLD 0x00000200
341 #define EMAC_DEBUG_MTLRFFLS_FULL 0x00000300
342 #define EMAC_DEBUG_MTLRFRCS 0x00000060
343 #define EMAC_DEBUG_MTLRFRCS_IDLE 0x00000000
344 #define EMAC_DEBUG_MTLRFRCS_READING_DATA 0x00000020
345 #define EMAC_DEBUG_MTLRFRCS_READING_STATUS 0x00000040
346 #define EMAC_DEBUG_MTLRFRCS_FLUSHING 0x00000060
347 #define EMAC_DEBUG_MTLRFWCAS 0x00000010
348 #define EMAC_DEBUG_MACRFFCS 0x00000006
349 #define EMAC_DEBUG_MACRPES 0x00000001
350 
351 //PMT Control and Status register
352 #define EMAC_PMT_CSR_RWKFILTRST 0x80000000
353 #define EMAC_PMT_CSR_RWKPTR 0x1F000000
354 #define EMAC_PMT_CSR_GLBLUCAST 0x00000200
355 #define EMAC_PMT_CSR_RWKPRCVD 0x00000040
356 #define EMAC_PMT_CSR_MGKPRCVD 0x00000020
357 #define EMAC_PMT_CSR_RWKPKTEN 0x00000004
358 #define EMAC_PMT_CSR_MGKPKTEN 0x00000002
359 #define EMAC_PMT_CSR_PWRDWN 0x00000001
360 
361 //LPI Control and Status register
362 #define EMAC_LPI_CSR_LPITXA 0x00080000
363 #define EMAC_LPI_CSR_PLS 0x00020000
364 #define EMAC_LPI_CSR_LPIEN 0x00010000
365 #define EMAC_LPI_CSR_RLPIST 0x00000200
366 #define EMAC_LPI_CSR_TLPIST 0x00000100
367 #define EMAC_LPI_CSR_RLPIEX 0x00000008
368 #define EMAC_LPI_CSR_RLPIEN 0x00000004
369 #define EMAC_LPI_CSR_TLPIEX 0x00000002
370 #define EMAC_LPI_CSR_TLPIEN 0x00000001
371 
372 //LPI Timers Control register
373 #define EMAC_LPITIMERSCONTROL_LPI_LS_TIMER 0x03FF0000
374 #define EMAC_LPITIMERSCONTROL_LPI_TW_TIMER 0x0000FFFF
375 
376 //MAC Interrupt Status register
377 #define EMAC_INTS_LPIINTS 0x00000400
378 #define EMAC_INTS_PMTINTS 0x00000008
379 
380 //MAC Interrupt Mask register
381 #define EMAC_INTMASK_LPIINTMASK 0x00000400
382 #define EMAC_INTMASK_PMTINTMASK 0x00000008
383 
384 //MAC Address 0 High register
385 #define EMAC_ADDR0HIGH_ADDRESS_ENABLE0 0x80000000
386 #define EMAC_ADDR0HIGH_MAC_ADDRESS0_HI 0x0000FFFF
387 
388 //MAC Address 0 Low register
389 #define EMAC_ADDR0LOW_MAC_ADDRESS0_LO 0xFFFFFFFF
390 
391 //MAC Address 1 High register
392 #define EMAC_ADDR1HIGH_ADDRESS_ENABLE1 0x80000000
393 #define EMAC_ADDR1HIGH_SOURCE_ADDRESS1 0x40000000
394 #define EMAC_ADDR1HIGH_MASK_BYTE_CONTROL1 0x3F000000
395 #define EMAC_ADDR1HIGH_MAC_ADDRESS1_HI 0x0000FFFF
396 
397 //MAC Address 1 Low register
398 #define EMAC_ADDR1LOW_MAC_ADDRESS1_LO 0xFFFFFFFF
399 
400 //MAC Address 2 High register
401 #define EMAC_ADDR2HIGH_ADDRESS_ENABLE2 0x80000000
402 #define EMAC_ADDR2HIGH_SOURCE_ADDRESS2 0x40000000
403 #define EMAC_ADDR2HIGH_MASK_BYTE_CONTROL2 0x3F000000
404 #define EMAC_ADDR2HIGH_MAC_ADDRESS2_HI 0x0000FFFF
405 
406 //MAC Address 2 Low register
407 #define EMAC_ADDR2LOW_MAC_ADDRESS2_LO 0xFFFFFFFF
408 
409 //MAC Address 3 High register
410 #define EMAC_ADDR3HIGH_ADDRESS_ENABLE3 0x80000000
411 #define EMAC_ADDR3HIGH_SOURCE_ADDRESS3 0x40000000
412 #define EMAC_ADDR3HIGH_MASK_BYTE_CONTROL3 0x3F000000
413 #define EMAC_ADDR3HIGH_MAC_ADDRESS3_HI 0x0000FFFF
414 
415 //MAC Address 3 Low register
416 #define EMAC_ADDR3LOW_MAC_ADDRESS3_LO 0xFFFFFFFF
417 
418 //MAC Address 4 High register
419 #define EMAC_ADDR4HIGH_ADDRESS_ENABLE4 0x80000000
420 #define EMAC_ADDR4HIGH_SOURCE_ADDRESS4 0x40000000
421 #define EMAC_ADDR4HIGH_MASK_BYTE_CONTROL4 0x3F000000
422 #define EMAC_ADDR4HIGH_MAC_ADDRESS4_HI 0x0000FFFF
423 
424 //MAC Address 4 Low register
425 #define EMAC_ADDR4LOW_MAC_ADDRESS4_LO 0xFFFFFFFF
426 
427 //MAC Address 5 High register
428 #define EMAC_ADDR5HIGH_ADDRESS_ENABLE5 0x80000000
429 #define EMAC_ADDR5HIGH_SOURCE_ADDRESS5 0x40000000
430 #define EMAC_ADDR5HIGH_MASK_BYTE_CONTROL5 0x3F000000
431 #define EMAC_ADDR5HIGH_MAC_ADDRESS5_HI 0x0000FFFF
432 
433 //MAC Address 5 Low register
434 #define EMAC_ADDR5LOW_MAC_ADDRESS5_LO 0xFFFFFFFF
435 
436 //MAC Address 6 High register
437 #define EMAC_ADDR6HIGH_ADDRESS_ENABLE6 0x80000000
438 #define EMAC_ADDR6HIGH_SOURCE_ADDRESS6 0x40000000
439 #define EMAC_ADDR6HIGH_MASK_BYTE_CONTROL6 0x3F000000
440 #define EMAC_ADDR6HIGH_MAC_ADDRESS6_HI 0x0000FFFF
441 
442 //MAC Address 6 Low register
443 #define EMAC_ADDR6LOW_MAC_ADDRESS6_LO 0xFFFFFFFF
444 
445 //MAC Address 7 High register
446 #define EMAC_ADDR7HIGH_ADDRESS_ENABLE7 0x80000000
447 #define EMAC_ADDR7HIGH_SOURCE_ADDRESS7 0x40000000
448 #define EMAC_ADDR7HIGH_MASK_BYTE_CONTROL7 0x3F000000
449 #define EMAC_ADDR7HIGH_MAC_ADDRESS7_HI 0x0000FFFF
450 
451 //MAC Address 7 Low register
452 #define EMAC_ADDR7LOW_MAC_ADDRESS7_LO 0xFFFFFFFF
453 
454 //MAC Status register
455 #define EMAC_STATUS_SMIDRXS 0x00010000
456 #define EMAC_STATUS_JABBER_TIMEOUT 0x00000010
457 #define EMAC_STATUS_LINK_SPEED 0x00000006
458 #define EMAC_STATUS_LINK_SPEED_2_5_MHZ 0x00000000
459 #define EMAC_STATUS_LINK_SPEED_25_MHZ 0x00000002
460 #define EMAC_STATUS_LINK_SPEED_125_MHZ 0x00000004
461 #define EMAC_STATUS_LINK_MODE 0x00000001
462 #define EMAC_STATUS_LINK_MODE_HALF_DUPLEX 0x00000000
463 #define EMAC_STATUS_LINK_MODE_FULL_DUPLEX 0x00000001
464 
465 //Watchdog Timeout Control register
466 #define EMAC_WDOGTO_PWDOGEN 0x00010000
467 #define EMAC_WDOGTO_WDOGTO 0x00003FFF
468 
469 //Ethernet Clock Output Configuration register
470 #define EMAC_EX_CLKOUT_CONF_EMAC_CLK_OUT_H_DIV_NUM 0x000000F0
471 #define EMAC_EX_CLKOUT_CONF_EMAC_CLK_OUT_DIV_NUM 0x0000000F
472 
473 //Ethernet Clock Configuration register
474 #define EMAC_EX_OSCCLK_CONF_EMAC_OSC_CLK_SEL 0x01000000
475 #define EMAC_EX_OSCCLK_CONF_EMAC_OSC_H_DIV_NUM_100M 0x00FC0000
476 #define EMAC_EX_OSCCLK_CONF_EMAC_OSC_DIV_NUM_100M 0x0003F000
477 #define EMAC_EX_OSCCLK_CONF_EMAC_OSC_H_DIV_NUM_10M 0x00000FC0
478 #define EMAC_EX_OSCCLK_CONF_EMAC_OSC_DIV_NUM_10M 0x0000003F
479 
480 //Ethernet Clock Control register
481 #define EMAC_EX_CLK_CTRL_EMAC_MII_CLK_RX_EN 0x00000010
482 #define EMAC_EX_CLK_CTRL_EMAC_MII_CLK_TX_EN 0x00000008
483 #define EMAC_EX_CLK_CTRL_EMAC_INT_OSC_EN 0x00000002
484 #define EMAC_EX_CLK_CTRL_EMAC_EXT_OSC_EN 0x00000001
485 
486 //PHY Interface Selection register
487 #define EMAC_EX_PHYINF_CONF_EMAC_PHY_INTF_SEL 0x0000E000
488 #define EMAC_EX_PHYINF_CONF_EMAC_PHY_INTF_SEL_MII 0x00000000
489 #define EMAC_EX_PHYINF_CONF_EMAC_PHY_INTF_SEL_RMII 0x00008000
490 
491 //Ethernet RAM Power-Down register
492 #define EMAC_PD_SEL_EMAC_RAM_PD_EN 0x00000003
493 
494 //Transmit DMA descriptor flags
495 #define EMAC_TDES0_OWN 0x80000000
496 #define EMAC_TDES0_IC 0x40000000
497 #define EMAC_TDES0_LS 0x20000000
498 #define EMAC_TDES0_FS 0x10000000
499 #define EMAC_TDES0_DC 0x08000000
500 #define EMAC_TDES0_DP 0x04000000
501 #define EMAC_TDES0_TTSE 0x02000000
502 #define EMAC_TDES0_CIC 0x00C00000
503 #define EMAC_TDES0_TER 0x00200000
504 #define EMAC_TDES0_TCH 0x00100000
505 #define EMAC_TDES0_TTSS 0x00020000
506 #define EMAC_TDES0_IHE 0x00010000
507 #define EMAC_TDES0_ES 0x00008000
508 #define EMAC_TDES0_JT 0x00004000
509 #define EMAC_TDES0_FF 0x00002000
510 #define EMAC_TDES0_IPE 0x00001000
511 #define EMAC_TDES0_LCA 0x00000800
512 #define EMAC_TDES0_NC 0x00000400
513 #define EMAC_TDES0_LCO 0x00000200
514 #define EMAC_TDES0_EC 0x00000100
515 #define EMAC_TDES0_VF 0x00000080
516 #define EMAC_TDES0_CC 0x00000078
517 #define EMAC_TDES0_ED 0x00000004
518 #define EMAC_TDES0_UF 0x00000002
519 #define EMAC_TDES0_DB 0x00000001
520 #define EMAC_TDES1_TBS2 0x1FFF0000
521 #define EMAC_TDES1_TBS1 0x00001FFF
522 #define EMAC_TDES2_TBAP1 0xFFFFFFFF
523 #define EMAC_TDES3_TBAP2 0xFFFFFFFF
524 #define EMAC_TDES6_TTSL 0xFFFFFFFF
525 #define EMAC_TDES7_TTSH 0xFFFFFFFF
526 
527 //Receive DMA descriptor flags
528 #define EMAC_RDES0_OWN 0x80000000
529 #define EMAC_RDES0_AFM 0x40000000
530 #define EMAC_RDES0_FL 0x3FFF0000
531 #define EMAC_RDES0_ES 0x00008000
532 #define EMAC_RDES0_DE 0x00004000
533 #define EMAC_RDES0_SAF 0x00002000
534 #define EMAC_RDES0_LE 0x00001000
535 #define EMAC_RDES0_OE 0x00000800
536 #define EMAC_RDES0_VLAN 0x00000400
537 #define EMAC_RDES0_FS 0x00000200
538 #define EMAC_RDES0_LS 0x00000100
539 #define EMAC_RDES0_IPHCE 0x00000080
540 #define EMAC_RDES0_LCO 0x00000040
541 #define EMAC_RDES0_FT 0x00000020
542 #define EMAC_RDES0_RWT 0x00000010
543 #define EMAC_RDES0_RE 0x00000008
544 #define EMAC_RDES0_DBE 0x00000004
545 #define EMAC_RDES0_CE 0x00000002
546 #define EMAC_RDES0_PCE 0x00000001
547 #define EMAC_RDES1_DIC 0x80000000
548 #define EMAC_RDES1_RBS2 0x1FFF0000
549 #define EMAC_RDES1_RER 0x00008000
550 #define EMAC_RDES1_RCH 0x00004000
551 #define EMAC_RDES1_RBS1 0x00001FFF
552 #define EMAC_RDES2_RBAP1 0xFFFFFFFF
553 #define EMAC_RDES3_RBAP2 0xFFFFFFFF
554 #define EMAC_RDES4_PV 0x00002000
555 #define EMAC_RDES4_PFT 0x00001000
556 #define EMAC_RDES4_PMT 0x00000F00
557 #define EMAC_RDES4_IPV6PR 0x00000080
558 #define EMAC_RDES4_IPV4PR 0x00000040
559 #define EMAC_RDES4_IPCB 0x00000020
560 #define EMAC_RDES4_IPPE 0x00000010
561 #define EMAC_RDES4_IPHE 0x00000008
562 #define EMAC_RDES4_IPPT 0x00000007
563 #define EMAC_RDES6_RTSL 0xFFFFFFFF
564 #define EMAC_RDES7_RTSH 0xFFFFFFFF
565 
566 //C++ guard
567 #ifdef __cplusplus
568 extern "C" {
569 #endif
570 
571 
572 /**
573  * @brief Enhanced TX DMA descriptor
574  **/
575 
576 typedef struct
577 {
578  uint32_t tdes0;
579  uint32_t tdes1;
580  uint32_t tdes2;
581  uint32_t tdes3;
582  uint32_t tdes4;
583  uint32_t tdes5;
584  uint32_t tdes6;
585  uint32_t tdes7;
587 
588 
589 /**
590  * @brief Enhanced RX DMA descriptor
591  **/
592 
593 typedef struct
594 {
595  uint32_t rdes0;
596  uint32_t rdes1;
597  uint32_t rdes2;
598  uint32_t rdes3;
599  uint32_t rdes4;
600  uint32_t rdes5;
601  uint32_t rdes6;
602  uint32_t rdes7;
604 
605 
606 //ESP32 Ethernet MAC driver
607 extern const NicDriver esp32EthDriver;
608 
609 //ESP32 Ethernet MAC related functions
610 error_t esp32EthInit(NetInterface *interface);
611 void esp32EthInitGpio(NetInterface *interface);
612 void esp32EthInitDmaDesc(NetInterface *interface);
613 
614 void esp32EthTick(NetInterface *interface);
615 
616 void esp32EthEnableIrq(NetInterface *interface);
617 void esp32EthDisableIrq(NetInterface *interface);
618 void esp32EthIrqHandler(void *arg);
619 void esp32EthEventHandler(NetInterface *interface);
620 
622  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
623 
625 
628 
629 void esp32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
630  uint8_t regAddr, uint16_t data);
631 
632 uint16_t esp32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
633  uint8_t regAddr);
634 
635 //C++ guard
636 #ifdef __cplusplus
637 }
638 #endif
639 
640 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
error_t esp32EthInit(NetInterface *interface)
ESP32 Ethernet MAC initialization.
error_t esp32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void esp32EthEventHandler(NetInterface *interface)
ESP32 Ethernet MAC event handler.
const NicDriver esp32EthDriver
ESP32 Ethernet MAC driver.
error_t esp32EthReceivePacket(NetInterface *interface)
Receive a packet.
void esp32EthInitGpio(NetInterface *interface)
GPIO configuration.
void esp32EthTick(NetInterface *interface)
ESP32 Ethernet MAC timer handler.
void esp32EthDisableIrq(NetInterface *interface)
Disable interrupts.
void esp32EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t esp32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void esp32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t esp32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t esp32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void esp32EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void esp32EthIrqHandler(void *arg)
ESP32 Ethernet MAC interrupt service routine.
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Enhanced RX DMA descriptor.
Enhanced TX DMA descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283