ksz8795_driver.h
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1 /**
2  * @file ksz8795_driver.h
3  * @brief KSZ8795 5-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2025 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.5.4
29  **/
30 
31 #ifndef _KSZ8795_DRIVER_H
32 #define _KSZ8795_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ8795_PORT1 1
39 #define KSZ8795_PORT2 2
40 #define KSZ8795_PORT3 3
41 #define KSZ8795_PORT4 4
42 #define KSZ8795_PORT5 5
43 
44 //Port masks
45 #define KSZ8795_PORT_MASK 0x1F
46 #define KSZ8795_PORT1_MASK 0x01
47 #define KSZ8795_PORT2_MASK 0x02
48 #define KSZ8795_PORT3_MASK 0x04
49 #define KSZ8795_PORT4_MASK 0x08
50 #define KSZ8795_PORT5_MASK 0x10
51 
52 //SPI command byte
53 #define KSZ8795_SPI_CMD_WRITE 0x4000
54 #define KSZ8795_SPI_CMD_READ 0x6000
55 #define KSZ8795_SPI_CMD_ADDR 0x1FFE
56 
57 //Size of static and dynamic MAC tables
58 #define KSZ8795_STATIC_MAC_TABLE_SIZE 32
59 #define KSZ8795_DYNAMIC_MAC_TABLE_SIZE 1024
60 #define KSZ8795_VLAN_TABLE_SIZE 4096
61 
62 //Tail tag rules (host to KSZ8795)
63 #define KSZ8795_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x80
64 #define KSZ8795_TAIL_TAG_PORT_SEL 0x40
65 #define KSZ8795_TAIL_TAG_DEST_QUEUE 0x30
66 #define KSZ8795_TAIL_TAG_DEST_PORT4 0x08
67 #define KSZ8795_TAIL_TAG_DEST_PORT3 0x04
68 #define KSZ8795_TAIL_TAG_DEST_PORT2 0x02
69 #define KSZ8795_TAIL_TAG_DEST_PORT1 0x01
70 
71 //Tail tag rules (KSZ8795 to host)
72 #define KSZ8795_TAIL_TAG_SRC_PORT 0x03
73 
74 //KSZ8795 PHY registers
75 #define KSZ8795_BMCR 0x00
76 #define KSZ8795_BMSR 0x01
77 #define KSZ8795_PHYID1 0x02
78 #define KSZ8795_PHYID2 0x03
79 #define KSZ8795_ANAR 0x04
80 #define KSZ8795_ANLPAR 0x05
81 #define KSZ8795_LINKMD 0x1D
82 #define KSZ8795_PHYSCS 0x1F
83 
84 //KSZ8795 Switch registers
85 #define KSZ8795_CHIP_ID0 0x00
86 #define KSZ8795_CHIP_ID1 0x01
87 #define KSZ8795_GLOBAL_CTRL0 0x02
88 #define KSZ8795_GLOBAL_CTRL1 0x03
89 #define KSZ8795_GLOBAL_CTRL2 0x04
90 #define KSZ8795_GLOBAL_CTRL3 0x05
91 #define KSZ8795_GLOBAL_CTRL4 0x06
92 #define KSZ8795_GLOBAL_CTRL5 0x07
93 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL 0x08
94 #define KSZ8795_GLOBAL_CTRL7 0x09
95 #define KSZ8795_GLOBAL_CTRL8 0x0A
96 #define KSZ8795_GLOBAL_CTRL9 0x0B
97 #define KSZ8795_GLOBAL_CTRL10 0x0C
98 #define KSZ8795_GLOBAL_CTRL11 0x0D
99 #define KSZ8795_PD_MGMT_CTRL1 0x0E
100 #define KSZ8795_PD_MGMT_CTRL2 0x0F
101 #define KSZ8795_PORT1_CTRL0 0x10
102 #define KSZ8795_PORT1_CTRL1 0x11
103 #define KSZ8795_PORT1_CTRL2 0x12
104 #define KSZ8795_PORT1_CTRL3 0x13
105 #define KSZ8795_PORT1_CTRL4 0x14
106 #define KSZ8795_PORT1_CTRL5 0x15
107 #define KSZ8795_PORT1_CTRL7 0x17
108 #define KSZ8795_PORT1_STAT0 0x18
109 #define KSZ8795_PORT1_STAT1 0x19
110 #define KSZ8795_PORT1_PHY_CTRL8 0x1A
111 #define KSZ8795_PORT1_LINKMD 0x1B
112 #define KSZ8795_PORT1_CTRL9 0x1C
113 #define KSZ8795_PORT1_CTRL10 0x1D
114 #define KSZ8795_PORT1_STAT2 0x1E
115 #define KSZ8795_PORT1_CTRL11_STAT3 0x1F
116 #define KSZ8795_PORT2_CTRL0 0x20
117 #define KSZ8795_PORT2_CTRL1 0x21
118 #define KSZ8795_PORT2_CTRL2 0x22
119 #define KSZ8795_PORT2_CTRL3 0x23
120 #define KSZ8795_PORT2_CTRL4 0x24
121 #define KSZ8795_PORT2_CTRL5 0x25
122 #define KSZ8795_PORT2_CTRL7 0x27
123 #define KSZ8795_PORT2_STAT0 0x28
124 #define KSZ8795_PORT2_STAT1 0x29
125 #define KSZ8795_PORT2_PHY_CTRL8 0x2A
126 #define KSZ8795_PORT2_LINKMD 0x2B
127 #define KSZ8795_PORT2_CTRL9 0x2C
128 #define KSZ8795_PORT2_CTRL10 0x2D
129 #define KSZ8795_PORT2_STAT2 0x2E
130 #define KSZ8795_PORT2_CTRL11_STAT3 0x2F
131 #define KSZ8795_PORT3_CTRL0 0x30
132 #define KSZ8795_PORT3_CTRL1 0x31
133 #define KSZ8795_PORT3_CTRL2 0x32
134 #define KSZ8795_PORT3_CTRL3 0x33
135 #define KSZ8795_PORT3_CTRL4 0x34
136 #define KSZ8795_PORT3_CTRL5 0x35
137 #define KSZ8795_PORT3_CTRL7 0x37
138 #define KSZ8795_PORT3_STAT0 0x38
139 #define KSZ8795_PORT3_STAT1 0x39
140 #define KSZ8795_PORT3_PHY_CTRL8 0x3A
141 #define KSZ8795_PORT3_LINKMD 0x3B
142 #define KSZ8795_PORT3_CTRL9 0x3C
143 #define KSZ8795_PORT3_CTRL10 0x3D
144 #define KSZ8795_PORT3_STAT2 0x3E
145 #define KSZ8795_PORT3_CTRL11_STAT3 0x3F
146 #define KSZ8795_PORT4_CTRL0 0x40
147 #define KSZ8795_PORT4_CTRL1 0x41
148 #define KSZ8795_PORT4_CTRL2 0x42
149 #define KSZ8795_PORT4_CTRL3 0x43
150 #define KSZ8795_PORT4_CTRL4 0x44
151 #define KSZ8795_PORT4_CTRL5 0x45
152 #define KSZ8795_PORT4_CTRL7 0x47
153 #define KSZ8795_PORT4_STAT0 0x48
154 #define KSZ8795_PORT4_STAT1 0x49
155 #define KSZ8795_PORT4_PHY_CTRL8 0x4A
156 #define KSZ8795_PORT4_LINKMD 0x4B
157 #define KSZ8795_PORT4_CTRL9 0x4C
158 #define KSZ8795_PORT4_CTRL10 0x4D
159 #define KSZ8795_PORT4_STAT2 0x4E
160 #define KSZ8795_PORT4_CTRL11_STAT3 0x4F
161 #define KSZ8795_PORT5_CTRL0 0x50
162 #define KSZ8795_PORT5_CTRL1 0x51
163 #define KSZ8795_PORT5_CTRL2 0x52
164 #define KSZ8795_PORT5_CTRL3 0x53
165 #define KSZ8795_PORT5_CTRL4 0x54
166 #define KSZ8795_PORT5_CTRL5 0x55
167 #define KSZ8795_PORT5_IF_CTRL6 0x56
168 #define KSZ8795_MAC_ADDR0 0x68
169 #define KSZ8795_MAC_ADDR1 0x69
170 #define KSZ8795_MAC_ADDR2 0x6A
171 #define KSZ8795_MAC_ADDR3 0x6B
172 #define KSZ8795_MAC_ADDR4 0x6C
173 #define KSZ8795_MAC_ADDR5 0x6D
174 #define KSZ8795_INDIRECT_CTRL0 0x6E
175 #define KSZ8795_INDIRECT_CTRL1 0x6F
176 #define KSZ8795_INDIRECT_DATA8 0x70
177 #define KSZ8795_INDIRECT_DATA7 0x71
178 #define KSZ8795_INDIRECT_DATA6 0x72
179 #define KSZ8795_INDIRECT_DATA5 0x73
180 #define KSZ8795_INDIRECT_DATA4 0x74
181 #define KSZ8795_INDIRECT_DATA3 0x75
182 #define KSZ8795_INDIRECT_DATA2 0x76
183 #define KSZ8795_INDIRECT_DATA1 0x77
184 #define KSZ8795_INDIRECT_DATA0 0x78
185 #define KSZ8795_INT_STAT 0x7C
186 #define KSZ8795_INT_MASK 0x7D
187 #define KSZ8795_ACL_INT_STAT 0x7E
188 #define KSZ8795_ACL_INT_CTRL 0x7F
189 #define KSZ8795_GLOBAL_CTRL12 0x80
190 #define KSZ8795_GLOBAL_CTRL13 0x81
191 #define KSZ8795_GLOBAL_CTRL14 0x82
192 #define KSZ8795_GLOBAL_CTRL15 0x83
193 #define KSZ8795_GLOBAL_CTRL16 0x84
194 #define KSZ8795_GLOBAL_CTRL17 0x85
195 #define KSZ8795_GLOBAL_CTRL18 0x86
196 #define KSZ8795_GLOBAL_CTRL19 0x87
197 #define KSZ8795_TOS_PRIO_CTRL0 0x90
198 #define KSZ8795_TOS_PRIO_CTRL1 0x91
199 #define KSZ8795_TOS_PRIO_CTRL2 0x92
200 #define KSZ8795_TOS_PRIO_CTRL3 0x93
201 #define KSZ8795_TOS_PRIO_CTRL4 0x94
202 #define KSZ8795_TOS_PRIO_CTRL5 0x95
203 #define KSZ8795_TOS_PRIO_CTRL6 0x96
204 #define KSZ8795_TOS_PRIO_CTRL7 0x97
205 #define KSZ8795_TOS_PRIO_CTRL8 0x98
206 #define KSZ8795_TOS_PRIO_CTRL9 0x99
207 #define KSZ8795_TOS_PRIO_CTRL10 0x9A
208 #define KSZ8795_TOS_PRIO_CTRL11 0x9B
209 #define KSZ8795_TOS_PRIO_CTRL12 0x9C
210 #define KSZ8795_TOS_PRIO_CTRL13 0x9D
211 #define KSZ8795_TOS_PRIO_CTRL14 0x9E
212 #define KSZ8795_TOS_PRIO_CTRL15 0x9F
213 #define KSZ8795_INDIRECT_BYTE 0xA0
214 #define KSZ8795_GLOBAL_CTRL20 0xA3
215 #define KSZ8795_GLOBAL_CTRL21 0xA4
216 #define KSZ8795_PORT1_CTRL12 0xB0
217 #define KSZ8795_PORT1_CTRL13 0xB1
218 #define KSZ8795_PORT1_CTRL14 0xB2
219 #define KSZ8795_PORT1_CTRL15 0xB3
220 #define KSZ8795_PORT1_CTRL16 0xB4
221 #define KSZ8795_PORT1_CTRL17 0xB5
222 #define KSZ8795_PORT1_RATE_LIMIT_CTRL 0xB6
223 #define KSZ8795_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7
224 #define KSZ8795_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8
225 #define KSZ8795_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9
226 #define KSZ8795_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA
227 #define KSZ8795_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB
228 #define KSZ8795_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC
229 #define KSZ8795_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD
230 #define KSZ8795_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE
231 #define KSZ8795_TEST 0xBF
232 #define KSZ8795_PORT2_CTRL12 0xC0
233 #define KSZ8795_PORT2_CTRL13 0xC1
234 #define KSZ8795_PORT2_CTRL14 0xC2
235 #define KSZ8795_PORT2_CTRL15 0xC3
236 #define KSZ8795_PORT2_CTRL16 0xC4
237 #define KSZ8795_PORT2_CTRL17 0xC5
238 #define KSZ8795_PORT2_RATE_LIMIT_CTRL 0xC6
239 #define KSZ8795_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7
240 #define KSZ8795_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8
241 #define KSZ8795_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9
242 #define KSZ8795_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA
243 #define KSZ8795_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB
244 #define KSZ8795_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC
245 #define KSZ8795_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD
246 #define KSZ8795_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE
247 #define KSZ8795_PORT3_CTRL12 0xD0
248 #define KSZ8795_PORT3_CTRL13 0xD1
249 #define KSZ8795_PORT3_CTRL14 0xD2
250 #define KSZ8795_PORT3_CTRL15 0xD3
251 #define KSZ8795_PORT3_CTRL16 0xD4
252 #define KSZ8795_PORT3_CTRL17 0xD5
253 #define KSZ8795_PORT3_RATE_LIMIT_CTRL 0xD6
254 #define KSZ8795_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7
255 #define KSZ8795_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8
256 #define KSZ8795_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9
257 #define KSZ8795_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA
258 #define KSZ8795_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB
259 #define KSZ8795_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC
260 #define KSZ8795_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD
261 #define KSZ8795_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE
262 #define KSZ8795_TEST2 0xDF
263 #define KSZ8795_PORT4_CTRL12 0xE0
264 #define KSZ8795_PORT4_CTRL13 0xE1
265 #define KSZ8795_PORT4_CTRL14 0xE2
266 #define KSZ8795_PORT4_CTRL15 0xE3
267 #define KSZ8795_PORT4_CTRL16 0xE4
268 #define KSZ8795_PORT4_CTRL17 0xE5
269 #define KSZ8795_PORT4_RATE_LIMIT_CTRL 0xE6
270 #define KSZ8795_PORT4_PRIO0_IG_LIMIT_CTRL1 0xE7
271 #define KSZ8795_PORT4_PRIO1_IG_LIMIT_CTRL2 0xE8
272 #define KSZ8795_PORT4_PRIO2_IG_LIMIT_CTRL3 0xE9
273 #define KSZ8795_PORT4_PRIO3_IG_LIMIT_CTRL4 0xEA
274 #define KSZ8795_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xEB
275 #define KSZ8795_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xEC
276 #define KSZ8795_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xED
277 #define KSZ8795_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xEE
278 #define KSZ8795_TEST3 0xEF
279 #define KSZ8795_PORT5_CTRL12 0xF0
280 #define KSZ8795_PORT5_CTRL13 0xF1
281 #define KSZ8795_PORT5_CTRL14 0xF2
282 #define KSZ8795_PORT5_CTRL15 0xF3
283 #define KSZ8795_PORT5_CTRL16 0xF4
284 #define KSZ8795_PORT5_CTRL17 0xF5
285 #define KSZ8795_PORT5_RATE_LIMIT_CTRL 0xF6
286 #define KSZ8795_PORT5_PRIO0_IG_LIMIT_CTRL1 0xF7
287 #define KSZ8795_PORT5_PRIO1_IG_LIMIT_CTRL2 0xF8
288 #define KSZ8795_PORT5_PRIO2_IG_LIMIT_CTRL3 0xF9
289 #define KSZ8795_PORT5_PRIO3_IG_LIMIT_CTRL4 0xFA
290 #define KSZ8795_PORT5_QUEUE0_EG_LIMIT_CTRL1 0xFB
291 #define KSZ8795_PORT5_QUEUE1_EG_LIMIT_CTRL2 0xFC
292 #define KSZ8795_PORT5_QUEUE2_EG_LIMIT_CTRL3 0xFD
293 #define KSZ8795_PORT5_QUEUE3_EG_LIMIT_CTRL4 0xFE
294 #define KSZ8795_TEST4 0xFF
295 
296 //KSZ8795 Switch register access macros
297 #define KSZ8795_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
298 #define KSZ8795_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
299 #define KSZ8795_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
300 #define KSZ8795_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
301 #define KSZ8795_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
302 #define KSZ8795_PORTn_CTRL5(port) (0x05 + ((port) * 0x10))
303 #define KSZ8795_PORTn_CTRL7(port) (0x07 + ((port) * 0x10))
304 #define KSZ8795_PORTn_STAT0(port) (0x08 + ((port) * 0x10))
305 #define KSZ8795_PORTn_STAT1(port) (0x09 + ((port) * 0x10))
306 #define KSZ8795_PORTn_PHY_CTRL8(port) (0x0A + ((port) * 0x10))
307 #define KSZ8795_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
308 #define KSZ8795_PORTn_CTRL9(port) (0x0C + ((port) * 0x10))
309 #define KSZ8795_PORTn_CTRL10(port) (0x0D + ((port) * 0x10))
310 #define KSZ8795_PORTn_STAT2(port) (0x0E + ((port) * 0x10))
311 #define KSZ8795_PORTn_CTRL11_STAT3(port) (0x0F + ((port) * 0x10))
312 #define KSZ8795_PORTn_CTRL12(port) (0xA0 + ((port) * 0x10))
313 #define KSZ8795_PORTn_CTRL13(port) (0xA1 + ((port) * 0x10))
314 #define KSZ8795_PORTn_CTRL14(port) (0xA2 + ((port) * 0x10))
315 #define KSZ8795_PORTn_CTRL15(port) (0xA3 + ((port) * 0x10))
316 #define KSZ8795_PORTn_CTRL16(port) (0xA4 + ((port) * 0x10))
317 #define KSZ8795_PORTn_CTRL17(port) (0xA5 + ((port) * 0x10))
318 #define KSZ8795_PORTn_RATE_LIMIT_CTRL(port) (0xA6 + ((port) * 0x10))
319 #define KSZ8795_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xA7 + ((port) * 0x10))
320 #define KSZ8795_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xA8 + ((port) * 0x10))
321 #define KSZ8795_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xA9 + ((port) * 0x10))
322 #define KSZ8795_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xAA + ((port) * 0x10))
323 #define KSZ8795_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xAB + ((port) * 0x10))
324 #define KSZ8795_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xAC + ((port) * 0x10))
325 #define KSZ8795_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xAD + ((port) * 0x10))
326 #define KSZ8795_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xAE + ((port) * 0x10))
327 
328 //Basic Control register
329 #define KSZ8795_BMCR_RESET 0x8000
330 #define KSZ8795_BMCR_LOOPBACK 0x4000
331 #define KSZ8795_BMCR_FORCE_100 0x2000
332 #define KSZ8795_BMCR_AN_EN 0x1000
333 #define KSZ8795_BMCR_POWER_DOWN 0x0800
334 #define KSZ8795_BMCR_ISOLATE 0x0400
335 #define KSZ8795_BMCR_RESTART_AN 0x0200
336 #define KSZ8795_BMCR_FORCE_FULL_DUPLEX 0x0100
337 #define KSZ8795_BMCR_HP_MDIX 0x0020
338 #define KSZ8795_BMCR_FORCE_MDI 0x0010
339 #define KSZ8795_BMCR_AUTO_MDIX_DIS 0x0008
340 #define KSZ8795_BMCR_FAR_END_FAULT_DIS 0x0004
341 #define KSZ8795_BMCR_TRANSMIT_DIS 0x0002
342 #define KSZ8795_BMCR_LED_DIS 0x0001
343 
344 //Basic Status register
345 #define KSZ8795_BMSR_100BT4 0x8000
346 #define KSZ8795_BMSR_100BTX_FD 0x4000
347 #define KSZ8795_BMSR_100BTX_HD 0x2000
348 #define KSZ8795_BMSR_10BT_FD 0x1000
349 #define KSZ8795_BMSR_10BT_HD 0x0800
350 #define KSZ8795_BMSR_AN_COMPLETE 0x0020
351 #define KSZ8795_BMSR_FAR_END_FAULT 0x0010
352 #define KSZ8795_BMSR_AN_CAPABLE 0x0008
353 #define KSZ8795_BMSR_LINK_STATUS 0x0004
354 #define KSZ8795_BMSR_EXTENDED_CAPABLE 0x0001
355 
356 //PHYID High register
357 #define KSZ8795_PHYID1_DEFAULT 0x0022
358 
359 //PHYID Low register
360 #define KSZ8795_PHYID2_DEFAULT 0x1550
361 
362 //Advertisement Ability register
363 #define KSZ8795_ANAR_PAUSE 0x0400
364 #define KSZ8795_ANAR_100BTX_FD 0x0100
365 #define KSZ8795_ANAR_100BTX_HD 0x0080
366 #define KSZ8795_ANAR_10BT_FD 0x0040
367 #define KSZ8795_ANAR_10BT_HD 0x0020
368 #define KSZ8795_ANAR_SELECTOR 0x001F
369 #define KSZ8795_ANAR_SELECTOR_DEFAULT 0x0001
370 
371 //Link Partner Ability register
372 #define KSZ8795_ANLPAR_PAUSE 0x0400
373 #define KSZ8795_ANLPAR_100BTX_FD 0x0100
374 #define KSZ8795_ANLPAR_100BTX_HD 0x0080
375 #define KSZ8795_ANLPAR_10BT_FD 0x0040
376 #define KSZ8795_ANLPAR_10BT_HD 0x0020
377 
378 //LinkMD Control/Status register
379 #define KSZ8795_LINKMD_TEST_EN 0x8000
380 #define KSZ8795_LINKMD_RESULT 0x6000
381 #define KSZ8795_LINKMD_RESULT_NORMAL 0x0000
382 #define KSZ8795_LINKMD_RESULT_OPEN 0x2000
383 #define KSZ8795_LINKMD_RESULT_SHORT 0x4000
384 #define KSZ8795_LINKMD_RESULT_FAIL 0x6000
385 #define KSZ8795_LINKMD_SHORT 0x1000
386 #define KSZ8795_LINKMD_FAULT_COUNT 0x01FF
387 
388 //PHY Special Control/Status register
389 #define KSZ8795_PHYSCS_OP_MODE 0x0700
390 #define KSZ8795_PHYSCS_OP_MODE_AN 0x0100
391 #define KSZ8795_PHYSCS_OP_MODE_10BT_HD 0x0200
392 #define KSZ8795_PHYSCS_OP_MODE_100BTX_HD 0x0300
393 #define KSZ8795_PHYSCS_OP_MODE_10BT_FD 0x0500
394 #define KSZ8795_PHYSCS_OP_MODE_100BTX_FD 0x0600
395 #define KSZ8795_PHYSCS_OP_MODE_ISOLATE 0x0700
396 #define KSZ8795_PHYSCS_POLRVS 0x0020
397 #define KSZ8795_PHYSCS_MDIX_STATUS 0x0010
398 #define KSZ8795_PHYSCS_FORCE_LINK 0x0008
399 #define KSZ8795_PHYSCS_PWRSAVE 0x0004
400 #define KSZ8795_PHYSCS_REMOTE_LOOPBACK 0x0002
401 
402 //Chip ID0 register
403 #define KSZ8795_CHIP_ID0_FAMILY_ID 0xFF
404 #define KSZ8795_CHIP_ID0_FAMILY_ID_DEFAULT 0x87
405 
406 //Chip ID1 / Start Switch register
407 #define KSZ8795_CHIP_ID1_CHIP_ID 0xF0
408 #define KSZ8795_CHIP_ID1_CHIP_ID_DEFAULT 0x90
409 #define KSZ8795_CHIP_ID1_REVISION_ID 0x0E
410 #define KSZ8795_CHIP_ID1_START_SWITCH 0x01
411 
412 //Global Control 0 register
413 #define KSZ8795_GLOBAL_CTRL0_NEW_BACK_OFF_EN 0x80
414 #define KSZ8795_GLOBAL_CTRL0_GLOBAL_SOFT_RESET_EN 0x40
415 #define KSZ8795_GLOBAL_CTRL0_FLUSH_DYNAMIC_MAC_TABLE 0x20
416 #define KSZ8795_GLOBAL_CTRL0_FLUSH_STATIC_MAC_TABLE 0x10
417 #define KSZ8795_GLOBAL_CTRL0_UNH_MODE 0x02
418 #define KSZ8795_GLOBAL_CTRL0_LINK_CHANGE_AGE 0x01
419 
420 //Global Control 1 register
421 #define KSZ8795_GLOBAL_CTRL1_2KB_PKT_SUPPORT 0x40
422 #define KSZ8795_GLOBAL_CTRL1_TX_FLOW_CTRL_DIS 0x20
423 #define KSZ8795_GLOBAL_CTRL1_RX_FLOW_CTRL_DIS 0x10
424 #define KSZ8795_GLOBAL_CTRL1_FRAME_LEN_CHECK_EN 0x08
425 #define KSZ8795_GLOBAL_CTRL1_AGING_EN 0x04
426 #define KSZ8795_GLOBAL_CTRL1_FAST_AGE_EN 0x02
427 #define KSZ8795_GLOBAL_CTRL1_AGGRESSIVE_BACK_OFF_EN 0x01
428 
429 //Global Control 2 register
430 #define KSZ8795_GLOBAL_CTRL2_UNI_VLAN_MISMATCH_DISCARD 0x80
431 #define KSZ8795_GLOBAL_CTRL2_MCAST_STORM_PROTECT_DIS 0x40
432 #define KSZ8795_GLOBAL_CTRL2_BACK_PRESSURE_MODE 0x20
433 #define KSZ8795_GLOBAL_CTRL2_FLOW_CTRL_FAIR_MODE 0x10
434 #define KSZ8795_GLOBAL_CTRL2_NO_EXCESSIVE_COL_DROP 0x08
435 #define KSZ8795_GLOBAL_CTRL2_MAX_PKT_SIZE_CHECK_DIS 0x02
436 
437 //Global Control 3 register
438 #define KSZ8795_GLOBAL_CTRL3_VLAN_EN 0x80
439 #define KSZ8795_GLOBAL_CTRL3_SW5_IGMP_SNOOP_EN 0x40
440 #define KSZ8795_GLOBAL_CTRL3_SNIFF_MODE_SEL 0x01
441 
442 //Global Control 4 register
443 #define KSZ8795_GLOBAL_CTRL4_SW5_BACK_PRESSURE_EN 0x80
444 #define KSZ8795_GLOBAL_CTRL4_SW5_HALF_DUPLEX_MODE 0x40
445 #define KSZ8795_GLOBAL_CTRL4_SW5_FLOW_CTRL_EN 0x20
446 #define KSZ8795_GLOBAL_CTRL4_SW5_SPEED 0x10
447 #define KSZ8795_GLOBAL_CTRL4_NULL_VID_REPLACEMENT 0x08
448 #define KSZ8795_GLOBAL_CTRL4_BCAST_STORM_PROTECT_RATE_MSB 0x07
449 
450 //Global Control 5 register
451 #define KSZ8795_GLOBAL_CTRL5_BCAST_STORM_PROTECT_RATE_LSB 0xFF
452 
453 //Global Control 6 MIB Control register
454 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_FLUSH_COUNTER 0x80
455 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_FREEZE_COUNTER 0x40
456 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN 0x1F
457 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT1 0x01
458 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT2 0x02
459 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT3 0x04
460 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT4 0x08
461 #define KSZ8795_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT5 0x10
462 
463 //Global Control 7 register
464 #define KSZ8795_GLOBAL_CTRL7_FACTORY_TESTING 0xFF
465 
466 //Global Control 8 register
467 #define KSZ8795_GLOBAL_CTRL8_FACTORY_TESTING 0xFF
468 
469 //Global Control 9 register
470 #define KSZ8795_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL 0x40
471 #define KSZ8795_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL_RISING 0x00
472 #define KSZ8795_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL_FALLING 0x40
473 #define KSZ8795_GLOBAL_CTRL9_LED_MODE 0x30
474 #define KSZ8795_GLOBAL_CTRL9_LED_MODE_LED0_LNK_ACT_LED1_SPD 0x00
475 #define KSZ8795_GLOBAL_CTRL9_LED_MODE_LED0_LNK_LED1_ACT 0x10
476 #define KSZ8795_GLOBAL_CTRL9_LED_MODE_LED0_LNK_ACT_LED1_DPLX 0x20
477 #define KSZ8795_GLOBAL_CTRL9_LED_MODE_LED0_LNK_LED1_ACT_DPLX 0x30
478 #define KSZ8795_GLOBAL_CTRL9_REFCLKO_ENABLE 0x02
479 #define KSZ8795_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL 0x01
480 #define KSZ8795_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL_FALLING 0x00
481 #define KSZ8795_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL_RISING 0x01
482 
483 //Global Control 10 register
484 #define KSZ8795_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
485 #define KSZ8795_GLOBAL_CTRL10_PASS_FLOW_CTRL_PKT 0x01
486 
487 //Global Control 11 register
488 #define KSZ8795_GLOBAL_CTRL11_FACTORY_TESTING 0xFF
489 
490 //Power-Down Management Control 1 register
491 #define KSZ8795_PD_MGMT_CTRL1_PLL_PWR_DOWN 0x20
492 #define KSZ8795_PD_MGMT_CTRL1_PWR_MGMT_MODE 0x18
493 #define KSZ8795_PD_MGMT_CTRL1_PWR_MGMT_MODE_NORMAL 0x00
494 #define KSZ8795_PD_MGMT_CTRL1_PWR_MGMT_MODE_ENERGY_DETECT 0x08
495 #define KSZ8795_PD_MGMT_CTRL1_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
496 
497 //Power-Down Management Control 2 register
498 #define KSZ8795_PD_MGMT_CTRL2_GO_SLEEP_TIME 0xFF
499 
500 //Port N Control 0 register
501 #define KSZ8795_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
502 #define KSZ8795_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
503 #define KSZ8795_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
504 #define KSZ8795_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
505 #define KSZ8795_PORTn_CTRL0_TAG_INSERTION 0x04
506 #define KSZ8795_PORTn_CTRL0_TAG_REMOVAL 0x02
507 #define KSZ8795_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
508 
509 //Port N Control 1 register
510 #define KSZ8795_PORTn_CTRL1_SNIFFER_PORT 0x80
511 #define KSZ8795_PORTn_CTRL1_RECEIVE_SNIFF 0x40
512 #define KSZ8795_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
513 #define KSZ8795_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
514 
515 //Port N Control 2 register
516 #define KSZ8795_PORTn_CTRL2_USER_PRIO_CEILING 0x80
517 #define KSZ8795_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
518 #define KSZ8795_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
519 #define KSZ8795_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
520 #define KSZ8795_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
521 #define KSZ8795_PORTn_CTRL2_TRANSMIT_EN 0x04
522 #define KSZ8795_PORTn_CTRL2_RECEIVE_EN 0x02
523 #define KSZ8795_PORTn_CTRL2_LEARNING_DIS 0x01
524 
525 //Port N Control 3 register
526 #define KSZ8795_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
527 #define KSZ8795_PORTn_CTRL3_DEFAULT_CFI 0x10
528 #define KSZ8795_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
529 
530 //Port N Control 4 register
531 #define KSZ8795_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
532 
533 //Port N Control 5 register
534 #define KSZ8795_PORTn_CTRL5_ACL_EN 0x04
535 #define KSZ8795_PORTn_CTRL5_AUTH_MODE 0x03
536 
537 //Port 5 Interface Control 6 register
538 #define KSZ8795_PORT5_IF_CTRL6_RMII_CLK_SEL 0x80
539 #define KSZ8795_PORT5_IF_CTRL6_IS_1GBPS 0x40
540 #define KSZ8795_PORT5_IF_CTRL6_RGMII_ID_IG_EN 0x10
541 #define KSZ8795_PORT5_IF_CTRL6_RGMII_ID_EG_EN 0x08
542 #define KSZ8795_PORT5_IF_CTRL6_GMII_MII_MODE_SEL 0x04
543 #define KSZ8795_PORT5_IF_CTRL6_GMII_MII_MODE_SEL_PHY 0x00
544 #define KSZ8795_PORT5_IF_CTRL6_GMII_MII_MODE_SEL_MAC 0x04
545 #define KSZ8795_PORT5_IF_CTRL6_IF_MODE_SEL 0x03
546 #define KSZ8795_PORT5_IF_CTRL6_IF_MODE_SEL_MII 0x00
547 #define KSZ8795_PORT5_IF_CTRL6_IF_MODE_SEL_RMII 0x01
548 #define KSZ8795_PORT5_IF_CTRL6_IF_MODE_SEL_GMII 0x02
549 #define KSZ8795_PORT5_IF_CTRL6_IF_MODE_SEL_RGMII 0x03
550 
551 //Port N Control 7 register
552 #define KSZ8795_PORTn_CTRL7_ADV_FLOW_CTRL_CAP 0x30
553 #define KSZ8795_PORTn_CTRL7_ADV_FLOW_CTRL_CAP_NO 0x00
554 #define KSZ8795_PORTn_CTRL7_ADV_FLOW_CTRL_CAP_SYMMETRIC 0x10
555 #define KSZ8795_PORTn_CTRL7_ADV_FLOW_CTRL_CAP_ASYMMETRIC 0x20
556 #define KSZ8795_PORTn_CTRL7_ADV_FLOW_CTRL_CAP_BOTH 0x30
557 #define KSZ8795_PORTn_CTRL7_ADV_100BT_FD 0x08
558 #define KSZ8795_PORTn_CTRL7_ADV_100BT_HD 0x04
559 #define KSZ8795_PORTn_CTRL7_ADV_10BT_FD 0x02
560 #define KSZ8795_PORTn_CTRL7_ADV_10BT_HD 0x01
561 
562 //Port N Status 0 register
563 #define KSZ8795_PORTn_STAT0_LP_FLOW_CTRL_CAPABLE 0x30
564 #define KSZ8795_PORTn_STAT0_LP_100BTX_FD_CAPABLE 0x08
565 #define KSZ8795_PORTn_STAT0_LP_100BTX_HF_CAPABLE 0x04
566 #define KSZ8795_PORTn_STAT0_LP_10BT_FD_CAPABLE 0x02
567 #define KSZ8795_PORTn_STAT0_LP_10BT_HD_CAPABLE 0x01
568 
569 //Port N Status 1 register
570 #define KSZ8795_PORTn_STAT1_HP_MDIX 0x80
571 #define KSZ8795_PORTn_STAT1_FACTORY_TESTING 0x40
572 #define KSZ8795_PORTn_STAT1_POLRVS 0x20
573 #define KSZ8795_PORTn_STAT1_TX_FLOW_CTRL_EN 0x10
574 #define KSZ8795_PORTn_STAT1_RX_FLOW_CTRL_EN 0x08
575 #define KSZ8795_PORTn_STAT1_OP_SPEED 0x04
576 #define KSZ8795_PORTn_STAT1_OP_DUPLEX 0x02
577 
578 //Port N PHY Control 8 register
579 #define KSZ8795_PORTn_PHY_CTRL8_CDT_10M_SHORT 0x80
580 #define KSZ8795_PORTn_PHY_CTRL8_CDT_RESULT 0x60
581 #define KSZ8795_PORTn_PHY_CTRL8_CDT_EN 0x10
582 #define KSZ8795_PORTn_PHY_CTRL8_FORCE_LINK 0x08
583 #define KSZ8795_PORTn_PHY_CTRL8_PWRSAVE 0x04
584 #define KSZ8795_PORTn_PHY_CTRL8_REMOTE_LOOPBACK 0x02
585 #define KSZ8795_PORTn_PHY_CTRL8_VCT_FAULT_COUNT_MSB 0x01
586 
587 //Port N LinkMD Result register
588 #define KSZ8795_PORTn_LINKMD_VCT_FAULT_COUNT_LSB 0xFF
589 
590 //Port N Control 9 register
591 #define KSZ8795_PORTn_CTRL9_AN_DIS 0x80
592 #define KSZ8795_PORTn_CTRL9_FORCED_SPEED 0x40
593 #define KSZ8795_PORTn_CTRL9_FORCED_DUPLEX 0x20
594 
595 //Port N Control 10 register
596 #define KSZ8795_PORTn_CTRL10_LED_OFF 0x80
597 #define KSZ8795_PORTn_CTRL10_TX_DIS 0x40
598 #define KSZ8795_PORTn_CTRL10_RESTART_AN 0x20
599 #define KSZ8795_PORTn_CTRL10_POWER_DOWN 0x08
600 #define KSZ8795_PORTn_CTRL10_AUTO_MDIX_DIS 0x04
601 #define KSZ8795_PORTn_CTRL10_FORCED_MDI 0x02
602 #define KSZ8795_PORTn_CTRL10_MAC_LOOPBACK 0x01
603 
604 //Port N Status 2 register
605 #define KSZ8795_PORTn_STAT2_MDIX_STATUS 0x80
606 #define KSZ8795_PORTn_STAT2_AN_DONE 0x40
607 #define KSZ8795_PORTn_STAT2_LINK_GOOD 0x20
608 
609 //Port N Control 11 / Status 3 register
610 #define KSZ8795_PORTn_CTRL11_STAT3_PHY_LOOPBACK 0x80
611 #define KSZ8795_PORTn_CTRL11_STAT3_PHY_ISOLATE 0x20
612 #define KSZ8795_PORTn_CTRL11_STAT3_SOFT_RESET 0x10
613 #define KSZ8795_PORTn_CTRL11_STAT3_FORCE_LINK 0x08
614 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE 0x07
615 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE_AN 0x01
616 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE_10BT_HD 0x02
617 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE_100BTX_HD 0x03
618 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE_10BT_FD 0x05
619 #define KSZ8795_PORTn_CTRL11_STAT3_OP_MODE_100BTX_FD 0x06
620 
621 //Indirect Access Control 0 register
622 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL 0xE0
623 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL_INDIRECT_MODE 0x00
624 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL_EEE 0x20
625 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL_ACL 0x40
626 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL_PME 0x80
627 #define KSZ8795_INDIRECT_CTRL0_FUNC_SEL_LINKMD 0xA0
628 #define KSZ8795_INDIRECT_CTRL0_WRITE 0x00
629 #define KSZ8795_INDIRECT_CTRL0_READ 0x10
630 #define KSZ8795_INDIRECT_CTRL0_TABLE_SEL 0x0C
631 #define KSZ8795_INDIRECT_CTRL0_TABLE_SEL_STATIC_MAC 0x00
632 #define KSZ8795_INDIRECT_CTRL0_TABLE_SEL_VLAN 0x04
633 #define KSZ8795_INDIRECT_CTRL0_TABLE_SEL_DYNAMIC_MAC 0x08
634 #define KSZ8795_INDIRECT_CTRL0_TABLE_SEL_MIB_COUNTER 0x0C
635 #define KSZ8795_INDIRECT_CTRL0_ADDR_11_8 0x0F
636 #define KSZ8795_INDIRECT_CTRL0_ADDR_9_8 0x03
637 
638 //Indirect Access Control 1 register
639 #define KSZ8795_INDIRECT_CTRL1_ADDR_7_0 0xFF
640 
641 //Interrupt Status register
642 #define KSZ8795_INT_STAT_PME 0x10
643 #define KSZ8795_INT_STAT_PORT4 0x08
644 #define KSZ8795_INT_STAT_PORT3 0x04
645 #define KSZ8795_INT_STAT_PORT2 0x02
646 #define KSZ8795_INT_STAT_PORT1 0x01
647 
648 //Interrupt Mask register
649 #define KSZ8795_INT_MASK_PME 0x10
650 #define KSZ8795_INT_MASK_PORT4 0x08
651 #define KSZ8795_INT_MASK_PORT3 0x04
652 #define KSZ8795_INT_MASK_PORT2 0x02
653 #define KSZ8795_INT_MASK_PORT1 0x01
654 
655 //ACL Interrupt Status register
656 #define KSZ8795_ACL_INT_STAT_PORT5 0x10
657 #define KSZ8795_ACL_INT_STAT_PORT4 0x08
658 #define KSZ8795_ACL_INT_STAT_PORT3 0x04
659 #define KSZ8795_ACL_INT_STAT_PORT2 0x02
660 #define KSZ8795_ACL_INT_STAT_PORT1 0x01
661 
662 //ACL Interrupt Control register
663 #define KSZ8795_ACL_INT_CTRL_PORT5 0x10
664 #define KSZ8795_ACL_INT_CTRL_PORT4 0x08
665 #define KSZ8795_ACL_INT_CTRL_PORT3 0x04
666 #define KSZ8795_ACL_INT_CTRL_PORT2 0x02
667 #define KSZ8795_ACL_INT_CTRL_PORT1 0x01
668 
669 //Global Control 12 register
670 #define KSZ8795_GLOBAL_CTRL12_TAG3 0xC0
671 #define KSZ8795_GLOBAL_CTRL12_TAG2 0x30
672 #define KSZ8795_GLOBAL_CTRL12_TAG1 0x0C
673 #define KSZ8795_GLOBAL_CTRL12_TAG0 0x03
674 
675 //Global Control 13 register
676 #define KSZ8795_GLOBAL_CTRL13_TAG7 0xC0
677 #define KSZ8795_GLOBAL_CTRL13_TAG6 0x30
678 #define KSZ8795_GLOBAL_CTRL13_TAG5 0x0C
679 #define KSZ8795_GLOBAL_CTRL13_TAG4 0x03
680 
681 //Global Control 14 register
682 #define KSZ8795_GLOBAL_CTRL14_PRI_2Q 0xC0
683 
684 //Global Control 15 register
685 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD 0x20
686 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP 0x1F
687 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_FILT 0x00
688 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT1 0x01
689 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT2 0x02
690 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT3 0x04
691 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT4 0x08
692 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT5 0x10
693 #define KSZ8795_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_ALL 0x1F
694 
695 //Global Control 16 register
696 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD 0x20
697 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP 0x1F
698 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_FILT 0x00
699 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT1 0x01
700 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT2 0x02
701 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT3 0x04
702 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT4 0x08
703 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT5 0x10
704 #define KSZ8795_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_ALL 0x1F
705 
706 //Global Control 17 register
707 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD 0x20
708 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP 0x1F
709 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_FILT 0x00
710 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT1 0x01
711 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT2 0x02
712 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT3 0x04
713 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT4 0x08
714 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT5 0x10
715 #define KSZ8795_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_ALL 0x1F
716 
717 //Global Control 18 register
718 #define KSZ8795_GLOBAL_CTRL18_SELF_ADDR_FILTER_EN 0x40
719 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD 0x20
720 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP 0x1F
721 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_FILT 0x00
722 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT1 0x01
723 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT2 0x02
724 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT3 0x04
725 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT4 0x08
726 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT5 0x10
727 #define KSZ8795_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_ALL 0x1F
728 
729 //Global Control 19 register
730 #define KSZ8795_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD 0x30
731 #define KSZ8795_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_16MS 0x00
732 #define KSZ8795_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_64MS 0x10
733 #define KSZ8795_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_256MS 0x20
734 #define KSZ8795_GLOBAL_CTRL19_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
735 #define KSZ8795_GLOBAL_CTRL19_INSERT_SRC_PORT_PVID_TAG_EN 0x04
736 
737 //Global Control 20 register
738 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH 0x70
739 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_2MA 0x00
740 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_4MA 0x10
741 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_8MA 0x20
742 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_12MA 0x30
743 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_16MA 0x40
744 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_20MA 0x50
745 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_24MA 0x60
746 #define KSZ8795_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_28MA 0x70
747 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH 0x07
748 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_2MA 0x00
749 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_4MA 0x01
750 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_8MA 0x02
751 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_12MA 0x03
752 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_16MA 0x04
753 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_20MA 0x05
754 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_24MA 0x06
755 #define KSZ8795_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_28MA 0x07
756 
757 //Global Control 21 register
758 #define KSZ8795_GLOBAL_CTRL21_MLD_SNOOP_OPT 0x08
759 #define KSZ8795_GLOBAL_CTRL21_MLD_SNOOP_EN 0x04
760 
761 //Port N Control 12 register
762 #define KSZ8795_PORTn_CTRL12_PASS_ALL_FRAMES 0x40
763 #define KSZ8795_PORTn_CTRL12_INSERT_SRC_PORT_PVID_H 0x08
764 #define KSZ8795_PORTn_CTRL12_INSERT_SRC_PORT_PVID_H2 0x04
765 #define KSZ8795_PORTn_CTRL12_INSERT_SRC_PORT_PVID_L2 0x02
766 #define KSZ8795_PORTn_CTRL12_INSERT_SRC_PORT_PVID_L 0x01
767 
768 //Port N Control 13 register
769 #define KSZ8795_PORTn_CTRL13_4_QUEUE_SPLIT_EN 0x02
770 #define KSZ8795_PORTn_CTRL13_DROPPING_TAG_EN 0x01
771 
772 //Port N Control 14 register
773 #define KSZ8795_PORTn_CTRL14_PORT_TX_QUEUE3_RATIO_EN 0x80
774 #define KSZ8795_PORTn_CTRL14_PORT_TX_QUEUE3_RATIO 0x7F
775 
776 //Port N Control 15 register
777 #define KSZ8795_PORTn_CTRL15_PORT_TX_QUEUE2_RATIO_EN 0x80
778 #define KSZ8795_PORTn_CTRL15_PORT_TX_QUEUE2_RATIO 0x7F
779 
780 //Port N Control 16 register
781 #define KSZ8795_PORTn_CTRL16_PORT_TX_QUEUE1_RATIO_EN 0x80
782 #define KSZ8795_PORTn_CTRL16_PORT_TX_QUEUE1_RATIO 0x7F
783 
784 //Port N Control 17 register
785 #define KSZ8795_PORTn_CTRL17_PORT_TX_QUEUE0_RATIO_EN 0x80
786 #define KSZ8795_PORTn_CTRL17_PORT_TX_QUEUE0_RATIO 0x7F
787 
788 //Port N Rate Limit Control register
789 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_IG_LIMIT_PORT_PRIO_SEL 0x40
790 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_IG_LIMIT_BIT_PKT_MODE_SEL 0x20
791 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_IG_RATE_LIMIT_FLOW_CTRL_EN 0x10
792 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_LIMIT_MODE 0x0C
793 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_COUNT_IFG 0x02
794 #define KSZ8795_PORTn_RATE_LIMIT_CTRL_COUNT_PRE 0x01
795 
796 //C++ guard
797 #ifdef __cplusplus
798 extern "C" {
799 #endif
800 
801 //CC-RX, CodeWarrior or Win32 compiler?
802 #if defined(__CCRX__)
803  #pragma pack
804 #elif defined(__CWCC__) || defined(_WIN32)
805  #pragma pack(push, 1)
806 #endif
807 
808 
809 /**
810  * @brief Static MAC table entry (read operation)
811  **/
812 
813 typedef struct
814 {
815 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
816  uint8_t fid : 7; //0
817  uint8_t useFid : 1;
818  uint8_t reserved : 1; //1
819  uint8_t override : 1;
820  uint8_t valid : 1;
821  uint8_t forwardPorts : 5;
822 #else
823  uint8_t useFid : 1; //0
824  uint8_t fid : 7;
825  uint8_t forwardPorts : 5; //1
826  uint8_t valid : 1;
827  uint8_t override : 1;
828  uint8_t reserved : 1;
829 #endif
832 
833 
834 /**
835  * @brief Static MAC table entry (write operation)
836  **/
837 
838 typedef struct
839 {
840  uint8_t fid; //0
841 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
842  uint8_t useFid : 1; //1
843  uint8_t override : 1;
844  uint8_t valid : 1;
845  uint8_t forwardPorts : 5;
846 #else
847  uint8_t forwardPorts : 5; //1
848  uint8_t valid : 1;
849  uint8_t override : 1;
850  uint8_t useFid : 1;
851 #endif
854 
855 
856 /**
857  * @brief Dynamic MAC table entry
858  **/
859 
860 typedef struct
861 {
862 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
863  uint8_t macEmpty : 1; //0
864  uint8_t numValidEntriesH : 7;
865  uint8_t numValidEntriesL : 3; //1
866  uint8_t timestamp : 2;
867  uint8_t sourcePort : 3;
868  uint8_t dataNotReady : 1; //2
869  uint8_t fid : 7;
870 #else
871  uint8_t numValidEntriesH : 7; //0
872  uint8_t macEmpty : 1;
873  uint8_t sourcePort : 3; //1
874  uint8_t timestamp : 2;
875  uint8_t numValidEntriesL : 3;
876  uint8_t fid : 7; //2
877  uint8_t dataNotReady : 1;
878 #endif
881 
882 
883 /**
884  * @brief Set of VLAN entries
885  **/
886 
887 typedef struct
888 {
889 #if defined(_CPU_BIG_ENDIAN) && !defined(__IAR_SYSTEMS_ICC__)
890  uint8_t reserved3 : 3; //0
891  uint8_t entry3Valid : 1;
892  uint8_t entry3MembershipH : 4;
893  uint8_t entry3MembershipL : 1; //1
894  uint8_t entry3Fid : 7;
895  uint8_t reserved2 : 3; //2
896  uint8_t entry2Valid : 1;
897  uint8_t entry2MembershipH : 4;
898  uint8_t entry2MembershipL : 1; //3
899  uint8_t entry2Fid : 7;
900  uint8_t reserved1 : 3; //4
901  uint8_t entry1Valid : 1;
902  uint8_t entry1MembershipH : 4;
903  uint8_t entry1MembershipL : 1; //5
904  uint8_t entry1Fid : 7;
905  uint8_t reserved0 : 3; //6
906  uint8_t entry0Valid : 1;
907  uint8_t entry0MembershipH : 4;
908  uint8_t entry0MembershipL : 1; //7
909  uint8_t entry0Fid : 7;
910 #else
911  uint8_t entry3MembershipH : 4; //0
912  uint8_t entry3Valid : 1;
913  uint8_t reserved3 : 3;
914  uint8_t entry3Fid : 7; //1
915  uint8_t entry3MembershipL : 1;
916  uint8_t entry2MembershipH : 4; //2
917  uint8_t entry2Valid : 1;
918  uint8_t reserved2 : 3;
919  uint8_t entry2Fid : 7; //3
920  uint8_t entry2MembershipL : 1;
921  uint8_t entry1MembershipH : 4; //4
922  uint8_t entry1Valid : 1;
923  uint8_t reserved1 : 3;
924  uint8_t entry1Fid : 7; //5
925  uint8_t entry1MembershipL : 1;
926  uint8_t entry0MembershipH : 4; //6
927  uint8_t entry0Valid : 1;
928  uint8_t reserved0 : 3;
929  uint8_t entry0Fid : 7; //7
930  uint8_t entry0MembershipL : 1;
931 #endif
933 
934 
935 //CC-RX, CodeWarrior or Win32 compiler?
936 #if defined(__CCRX__)
937  #pragma unpack
938 #elif defined(__CWCC__) || defined(_WIN32)
939  #pragma pack(pop)
940 #endif
941 
942 //KSZ8795 Ethernet switch driver
943 extern const SwitchDriver ksz8795SwitchDriver;
944 
945 //KSZ8795 related functions
946 error_t ksz8795Init(NetInterface *interface);
947 void ksz8795InitHook(NetInterface *interface);
948 
949 void ksz8795Tick(NetInterface *interface);
950 
951 void ksz8795EnableIrq(NetInterface *interface);
952 void ksz8795DisableIrq(NetInterface *interface);
953 
954 void ksz8795EventHandler(NetInterface *interface);
955 
956 error_t ksz8795TagFrame(NetInterface *interface, NetBuffer *buffer,
957  size_t *offset, NetTxAncillary *ancillary);
958 
959 error_t ksz8795UntagFrame(NetInterface *interface, uint8_t **frame,
960  size_t *length, NetRxAncillary *ancillary);
961 
962 bool_t ksz8795GetLinkState(NetInterface *interface, uint8_t port);
963 uint32_t ksz8795GetLinkSpeed(NetInterface *interface, uint8_t port);
965 
966 void ksz8795SetPortState(NetInterface *interface, uint8_t port,
967  SwitchPortState state);
968 
970 
971 void ksz8795SetAgingTime(NetInterface *interface, uint32_t agingTime);
972 
973 void ksz8795EnableIgmpSnooping(NetInterface *interface, bool_t enable);
974 void ksz8795EnableMldSnooping(NetInterface *interface, bool_t enable);
975 void ksz8795EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
976 
978  const SwitchFdbEntry *entry);
979 
981  const SwitchFdbEntry *entry);
982 
984  SwitchFdbEntry *entry);
985 
987 
989  SwitchFdbEntry *entry);
990 
991 void ksz8795FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
992 
994  bool_t enable, uint32_t forwardPorts);
995 
997  const SwitchVlanEntry *entry);
998 
999 void ksz8795WritePhyReg(NetInterface *interface, uint8_t port,
1000  uint8_t address, uint16_t data);
1001 
1002 uint16_t ksz8795ReadPhyReg(NetInterface *interface, uint8_t port,
1003  uint8_t address);
1004 
1005 void ksz8795DumpPhyReg(NetInterface *interface, uint8_t port);
1006 
1007 void ksz8795WriteSwitchReg(NetInterface *interface, uint16_t address,
1008  uint8_t data);
1009 
1010 uint8_t ksz8795ReadSwitchReg(NetInterface *interface, uint16_t address);
1011 
1012 void ksz8795DumpSwitchReg(NetInterface *interface);
1013 
1014 //C++ guard
1015 #ifdef __cplusplus
1016 }
1017 #endif
1018 
1019 #endif
MacAddr macAddr
void ksz8795SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
uint16_t ksz8795ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint8_t valid
int bool_t
Definition: compiler_port.h:61
void ksz8795DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
uint8_t fid
uint8_t forwardPorts
void ksz8795FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
void ksz8795EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t data[]
Definition: ethernet.h:224
void ksz8795SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
uint8_t sourcePort
uint8_t reserved0
uint8_t macEmpty
uint8_t ksz8795ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void ksz8795DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8795GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
uint8_t entry1MembershipH
uint8_t reserved
uint8_t fid
uint8_t reserved
Definition: igmp_common.h:250
uint8_t entry3Valid
void ksz8795EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
uint8_t valid
VLAN entry.
Definition: nic.h:162
error_t
Error codes.
Definition: error.h:43
NicDuplexMode ksz8795GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
uint8_t entry2Fid
uint8_t entry0MembershipL
uint8_t numValidEntriesL
uint8_t reserved1
Definition: tcp.h:356
uint8_t entry0Fid
void ksz8795EventHandler(NetInterface *interface)
KSZ8795 event handler.
uint8_t entry1MembershipL
uint8_t dataNotReady
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
uint8_t useFid
uint8_t reserved2
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t entry0MembershipH
SwitchPortState
Switch port state.
Definition: nic.h:134
error_t ksz8795DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
uint8_t length
Definition: tcp.h:375
void ksz8795DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz8795SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
uint8_t entry0Valid
error_t ksz8795UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
uint8_t entry1Valid
uint8_t numValidEntriesH
MacAddr
Definition: ethernet.h:197
void ksz8795Tick(NetInterface *interface)
KSZ8795 timer handler.
error_t ksz8795TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
uint8_t entry1Fid
uint8_t useFid
uint16_t port
Definition: dns_common.h:270
uint8_t reserved2
Definition: tcp.h:359
uint8_t override
void ksz8795InitHook(NetInterface *interface)
KSZ8795 custom configuration.
uint8_t entry3MembershipL
uint8_t entry2Valid
uint32_t ksz8795GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
Ethernet switch driver.
Definition: nic.h:325
Static MAC table entry (read operation)
bool_t ksz8795GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
error_t ksz8795AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
void ksz8795EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
Ipv6Addr address[]
Definition: ipv6.h:325
uint8_t reserved3
error_t ksz8795GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
NicDuplexMode
Duplex mode.
Definition: nic.h:122
Network interface controller abstraction layer.
Static MAC table entry (write operation)
uint8_t fid
uint8_t entry3Fid
uint8_t forwardPorts
SwitchPortState ksz8795GetPortState(NetInterface *interface, uint8_t port)
Get port state.
uint8_t timestamp
uint8_t reserved1
error_t ksz8795Init(NetInterface *interface)
KSZ8795 Ethernet switch initialization.
uint8_t entry3MembershipH
void ksz8795FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
uint8_t entry2MembershipH
MacAddr macAddr
unsigned int uint_t
Definition: compiler_port.h:57
void ksz8795WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
void ksz8795EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
void ksz8795WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint8_t entry2MembershipL
Dynamic MAC table entry.
MacAddr macAddr
uint8_t override
const SwitchDriver ksz8795SwitchDriver
KSZ8795 Ethernet switch driver.
error_t ksz8795WriteVlanEntry(NetInterface *interface, const SwitchVlanEntry *entry)
Write VLAN entry.
Set of VLAN entries.
Forwarding database entry.
Definition: nic.h:149