ksz8851_driver.h
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1 /**
2  * @file ksz8851_driver.h
3  * @brief KSZ8851 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2023 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.2.2
29  **/
30 
31 #ifndef _KSZ8851_DRIVER_H
32 #define _KSZ8851_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //SPI interface support
38 #ifndef KSZ8851_SPI_SUPPORT
39  #define KSZ8851_SPI_SUPPORT ENABLED
40 #elif (KSZ8851_SPI_SUPPORT != ENABLED && KSZ8851_SPI_SUPPORT != DISABLED)
41  #error KSZ8851_SPI_SUPPORT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef KSZ8851_ETH_TX_BUFFER_SIZE
46  #define KSZ8851_ETH_TX_BUFFER_SIZE 1536
47 #elif (KSZ8851_ETH_TX_BUFFER_SIZE != 1536)
48  #error KSZ8851_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //RX buffer size
52 #ifndef KSZ8851_ETH_RX_BUFFER_SIZE
53  #define KSZ8851_ETH_RX_BUFFER_SIZE 1536
54 #elif (KSZ8851_ETH_RX_BUFFER_SIZE != 1536)
55  #error KSZ8851_ETH_RX_BUFFER_SIZE parameter is not valid
56 #endif
57 
58 //KSZ8851 data register
59 #ifndef KSZ8851_DATA_REG
60  #define KSZ8851_DATA_REG *((volatile uint16_t *) 0x60000000)
61 #endif
62 
63 //KSZ8851 command register
64 #ifndef KSZ8851_CMD_REG
65  #define KSZ8851_CMD_REG *((volatile uint16_t *) 0x60000004)
66 #endif
67 
68 //SPI command set
69 #define KSZ8851_CMD_RD_REG 0x00
70 #define KSZ8851_CMD_WR_REG 0x40
71 #define KSZ8851_CMD_RD_FIFO 0x80
72 #define KSZ8851_CMD_WR_FIFO 0xC0
73 
74 //Byte enable bits
75 #if (KSZ8851_SPI_SUPPORT == ENABLED)
76  #define KSZ8851_CMD_B0 0x04
77  #define KSZ8851_CMD_B1 0x08
78  #define KSZ8851_CMD_B2 0x10
79  #define KSZ8851_CMD_B3 0x20
80 #else
81  #define KSZ8851_CMD_B0 0x1000
82  #define KSZ8851_CMD_B1 0x2000
83  #define KSZ8851_CMD_B2 0x4000
84  #define KSZ8851_CMD_B3 0x8000
85 #endif
86 
87 //KSZ8851 registers
88 #define KSZ8851_CCR 0x08
89 #define KSZ8851_MARL 0x10
90 #define KSZ8851_MARM 0x12
91 #define KSZ8851_MARH 0x14
92 #define KSZ8851_OBCR 0x20
93 #define KSZ8851_EEPCR 0x22
94 #define KSZ8851_MBIR 0x24
95 #define KSZ8851_GRR 0x26
96 #define KSZ8851_WFCR 0x2A
97 #define KSZ8851_WF0CRC0 0x30
98 #define KSZ8851_WF0CRC1 0x32
99 #define KSZ8851_WF0BM0 0x34
100 #define KSZ8851_WF0BM1 0x36
101 #define KSZ8851_WF0BM2 0x38
102 #define KSZ8851_WF0BM3 0x3A
103 #define KSZ8851_WF1CRC0 0x40
104 #define KSZ8851_WF1CRC1 0x42
105 #define KSZ8851_WF1BM0 0x44
106 #define KSZ8851_WF1BM1 0x46
107 #define KSZ8851_WF1BM2 0x48
108 #define KSZ8851_WF1BM3 0x4A
109 #define KSZ8851_WF2CRC0 0x50
110 #define KSZ8851_WF2CRC1 0x52
111 #define KSZ8851_WF2BM0 0x54
112 #define KSZ8851_WF2BM1 0x56
113 #define KSZ8851_WF2BM2 0x58
114 #define KSZ8851_WF2BM3 0x5A
115 #define KSZ8851_WF3CRC0 0x60
116 #define KSZ8851_WF3CRC1 0x62
117 #define KSZ8851_WF3BM0 0x64
118 #define KSZ8851_WF3BM1 0x66
119 #define KSZ8851_WF3BM2 0x68
120 #define KSZ8851_WF3BM3 0x6A
121 #define KSZ8851_TXCR 0x70
122 #define KSZ8851_TXSR 0x72
123 #define KSZ8851_RXCR1 0x74
124 #define KSZ8851_RXCR2 0x76
125 #define KSZ8851_TXMIR 0x78
126 #define KSZ8851_RXFHSR 0x7C
127 #define KSZ8851_RXFHBCR 0x7E
128 #define KSZ8851_TXQCR 0x80
129 #define KSZ8851_RXQCR 0x82
130 #define KSZ8851_TXFDPR 0x84
131 #define KSZ8851_RXFDPR 0x86
132 #define KSZ8851_RXDTTR 0x8C
133 #define KSZ8851_RXDBCTR 0x8E
134 #define KSZ8851_IER 0x90
135 #define KSZ8851_ISR 0x92
136 #define KSZ8851_RXFCTR 0x9C
137 #define KSZ8851_TXNTFSR 0x9E
138 #define KSZ8851_MAHTR0 0xA0
139 #define KSZ8851_MAHTR1 0xA2
140 #define KSZ8851_MAHTR2 0xA4
141 #define KSZ8851_MAHTR3 0xA6
142 #define KSZ8851_FCLWR 0xB0
143 #define KSZ8851_FCHWR 0xB2
144 #define KSZ8851_FCOWR 0xB4
145 #define KSZ8851_CIDER 0xC0
146 #define KSZ8851_CGCR 0xC6
147 #define KSZ8851_IACR 0xC8
148 #define KSZ8851_IADLR 0xD0
149 #define KSZ8851_IADHR 0xD2
150 #define KSZ8851_PMECR 0xD4
151 #define KSZ8851_GSWUTR 0xD6
152 #define KSZ8851_PHYRR 0xD8
153 #define KSZ8851_P1MBCR 0xE4
154 #define KSZ8851_P1MBSR 0xE6
155 #define KSZ8851_PHY1ILR 0xE8
156 #define KSZ8851_PHY1IHR 0xEA
157 #define KSZ8851_P1ANAR 0xEC
158 #define KSZ8851_P1ANLPR 0xEE
159 #define KSZ8851_P1SCLMD 0xF4
160 #define KSZ8851_P1CR 0xF6
161 #define KSZ8851_P1SR 0xF8
162 
163 //Chip Configuration register
164 #define KSZ8851_CCR_BUS_ENDIAN_MODE 0x0400
165 #define KSZ8851_CCR_EEPROM_PRESENCE 0x0200
166 #define KSZ8851_CCR_SPI_BUS_MODE 0x0100
167 #define KSZ8851_CCR_8_BIT_DATA_BUS 0x0080
168 #define KSZ8851_CCR_16_BIT_DATA_BUS 0x0040
169 #define KSZ8851_CCR_32_BIT_DATA_BUS 0x0020
170 #define KSZ8851_CCR_SHARED_BUS_MODE 0x0010
171 #define KSZ8851_CCR_128_PIN_PACKAGE 0x0008
172 #define KSZ8851_CCR_48_PIN_PACKAGE 0x0002
173 #define KSZ8851_CCR_32_PIN_PACKAGE 0x0001
174 
175 //On-Chip Bus Control register
176 #define KSZ8851_OBCR_OUT_PIN_DRIVE_STRENGTH 0x0040
177 #define KSZ8851_OBCR_BUS_CLK_SEL 0x0004
178 #define KSZ8851_OBCR_BUS_CLK_DIV 0x0003
179 #define KSZ8851_OBCR_BUS_CLK_DIV_1 0x0000
180 #define KSZ8851_OBCR_BUS_CLK_DIV_2 0x0001
181 #define KSZ8851_OBCR_BUS_CLK_DIV_3 0x0002
182 
183 //EEPROM Control register
184 #define KSZ8851_EEPCR_EESRWA 0x0020
185 #define KSZ8851_EEPCR_EESA 0x0010
186 #define KSZ8851_EEPCR_EESB 0x0008
187 #define KSZ8851_EEPCR_EECB 0x0007
188 #define KSZ8851_EEPCR_EECB_EED_IO 0x0004
189 #define KSZ8851_EEPCR_EECB_EESK 0x0002
190 #define KSZ8851_EEPCR_EECB_EECS 0x0001
191 
192 //Memory BIST Info register
193 #define KSZ8851_MBIR_TXMBF 0x1000
194 #define KSZ8851_MBIR_TXMBFA 0x0800
195 #define KSZ8851_MBIR_TXMBFC 0x0700
196 #define KSZ8851_MBIR_RXMBF 0x0010
197 #define KSZ8851_MBIR_RXMBFA 0x0008
198 #define KSZ8851_MBIR_RXMBFC 0x0007
199 
200 //Global Reset register
201 #define KSZ8851_GRR_QMU_MODULE_SOFT_RESET 0x0002
202 #define KSZ8851_GRR_GLOBAL_SOFT_RESET 0x0001
203 
204 //Wakeup Frame Control register
205 #define KSZ8851_WFCR_MPRXE 0x0080
206 #define KSZ8851_WFCR_WF3E 0x0008
207 #define KSZ8851_WFCR_WF2E 0x0004
208 #define KSZ8851_WFCR_WF1E 0x0002
209 #define KSZ8851_WFCR_WF0E 0x0001
210 
211 //Transmit Control register
212 #define KSZ8851_TXCR_TCGICMP 0x0100
213 #define KSZ8851_TXCR_TCGTCP 0x0040
214 #define KSZ8851_TXCR_TCGIP 0x0020
215 #define KSZ8851_TXCR_FTXQ 0x0010
216 #define KSZ8851_TXCR_TXFCE 0x0008
217 #define KSZ8851_TXCR_TXPE 0x0004
218 #define KSZ8851_TXCR_TXCE 0x0002
219 #define KSZ8851_TXCR_TXE 0x0001
220 
221 //Transmit Status register
222 #define KSZ8851_TXSR_TXLC 0x2000
223 #define KSZ8851_TXSR_TXMC 0x1000
224 #define KSZ8851_TXSR_TXFID 0x003F
225 
226 //Receive Control 1 register
227 #define KSZ8851_RXCR1_FRXQ 0x8000
228 #define KSZ8851_RXCR1_RXUDPFCC 0x4000
229 #define KSZ8851_RXCR1_RXTCPFCC 0x2000
230 #define KSZ8851_RXCR1_RXIPFCC 0x1000
231 #define KSZ8851_RXCR1_RXPAFMA 0x0800
232 #define KSZ8851_RXCR1_RXFCE 0x0400
233 #define KSZ8851_RXCR1_RXEFE 0x0200
234 #define KSZ8851_RXCR1_RXMAFMA 0x0100
235 #define KSZ8851_RXCR1_RXBE 0x0080
236 #define KSZ8851_RXCR1_RXME 0x0040
237 #define KSZ8851_RXCR1_RXUE 0x0020
238 #define KSZ8851_RXCR1_RXAE 0x0010
239 #define KSZ8851_RXCR1_RXINVF 0x0002
240 #define KSZ8851_RXCR1_RXE 0x0001
241 
242 //Receive Control 2 register
243 #define KSZ8851_RXCR2_SRDBL 0x00E0
244 #define KSZ8851_RXCR2_SRDBL_4_BYTES 0x0000
245 #define KSZ8851_RXCR2_SRDBL_8_BYTES 0x0020
246 #define KSZ8851_RXCR2_SRDBL_16_BYTES 0x0040
247 #define KSZ8851_RXCR2_SRDBL_32_BYTES 0x0060
248 #define KSZ8851_RXCR2_SRDBL_SINGLE_FRAME 0x0080
249 #define KSZ8851_RXCR2_IUFFP 0x0010
250 #define KSZ8851_RXCR2_RXIUFCEZ 0x0008
251 #define KSZ8851_RXCR2_UDPLFE 0x0004
252 #define KSZ8851_RXCR2_RXICMPFCC 0x0002
253 #define KSZ8851_RXCR2_RXSAF 0x0001
254 
255 //TXQ Memory Information register
256 #define KSZ8851_TXMIR_TXMA 0x1FFF
257 
258 //Receive Frame Header Status register
259 #define KSZ8851_RXFHSR_RXFV 0x8000
260 #define KSZ8851_RXFHSR_RXICMPFCS 0x2000
261 #define KSZ8851_RXFHSR_RXIPFCS 0x1000
262 #define KSZ8851_RXFHSR_RXTCPFCS 0x0800
263 #define KSZ8851_RXFHSR_RXUDPFCS 0x0400
264 #define KSZ8851_RXFHSR_RXBF 0x0080
265 #define KSZ8851_RXFHSR_RXMF 0x0040
266 #define KSZ8851_RXFHSR_RXUF 0x0020
267 #define KSZ8851_RXFHSR_RXMR 0x0010
268 #define KSZ8851_RXFHSR_RXFT 0x0008
269 #define KSZ8851_RXFHSR_RXFTL 0x0004
270 #define KSZ8851_RXFHSR_RXRF 0x0002
271 #define KSZ8851_RXFHSR_RXCE 0x0001
272 
273 //Receive Frame Header Byte Count register
274 #define KSZ8851_RXFHBCR_RXBC 0x0FFF
275 
276 //TXQ Command register
277 #define KSZ8851_TXQCR_AETFE 0x0004
278 #define KSZ8851_TXQCR_TXQMAM 0x0002
279 #define KSZ8851_TXQCR_METFE 0x0001
280 
281 //RXQ Command register
282 #define KSZ8851_RXQCR_RXDTTS 0x1000
283 #define KSZ8851_RXQCR_RXDBCTS 0x0800
284 #define KSZ8851_RXQCR_RXFCTS 0x0400
285 #define KSZ8851_RXQCR_RXIPHTOE 0x0200
286 #define KSZ8851_RXQCR_RXDTTE 0x0080
287 #define KSZ8851_RXQCR_RXDBCTE 0x0040
288 #define KSZ8851_RXQCR_RXFCTE 0x0020
289 #define KSZ8851_RXQCR_ADRFE 0x0010
290 #define KSZ8851_RXQCR_SDA 0x0008
291 #define KSZ8851_RXQCR_RRXEF 0x0001
292 
293 //TX Frame Data Pointer register
294 #define KSZ8851_TXFDPR_TXFPAI 0x4000
295 #define KSZ8851_TXFDPR_TXFP 0x07FF
296 
297 //RX Frame Data Pointer register
298 #define KSZ8851_RXFDPR_RXFPAI 0x4000
299 #define KSZ8851_RXFDPR_WST 0x1000
300 #define KSZ8851_RXFDPR_EMS 0x0800
301 #define KSZ8851_RXFDPR_RXFP 0x07FF
302 
303 //Interrupt Enable register
304 #define KSZ8851_IER_LCIE 0x8000
305 #define KSZ8851_IER_TXIE 0x4000
306 #define KSZ8851_IER_RXIE 0x2000
307 #define KSZ8851_IER_RXOIE 0x0800
308 #define KSZ8851_IER_TXPSIE 0x0200
309 #define KSZ8851_IER_RXPSIE 0x0100
310 #define KSZ8851_IER_TXSAIE 0x0040
311 #define KSZ8851_IER_RXWFDIE 0x0020
312 #define KSZ8851_IER_RXMPDIE 0x0010
313 #define KSZ8851_IER_LDIE 0x0008
314 #define KSZ8851_IER_EDIE 0x0004
315 #define KSZ8851_IER_SPIBEIE 0x0002
316 #define KSZ8851_IER_DEDIE 0x0001
317 
318 //Interrupt Status register
319 #define KSZ8851_ISR_LCIS 0x8000
320 #define KSZ8851_ISR_TXIS 0x4000
321 #define KSZ8851_ISR_RXIS 0x2000
322 #define KSZ8851_ISR_RXOIS 0x0800
323 #define KSZ8851_ISR_TXPSIS 0x0200
324 #define KSZ8851_ISR_RXPSIS 0x0100
325 #define KSZ8851_ISR_TXSAIS 0x0040
326 #define KSZ8851_ISR_RXWFDIS 0x0020
327 #define KSZ8851_ISR_RXMPDIS 0x0010
328 #define KSZ8851_ISR_LDIS 0x0008
329 #define KSZ8851_ISR_EDIS 0x0004
330 #define KSZ8851_ISR_SPIBEIS 0x0002
331 
332 //RX Frame Count & Threshold register
333 #define KSZ8851_RXFCTR_RXFC 0xFF00
334 #define KSZ8851_RXFCTR_RXFCT 0x00FF
335 
336 //Flow Control Low Watermark register
337 #define KSZ8851_FCLWR_FCLWC 0x0FFF
338 
339 //Flow Control High Watermark register
340 #define KSZ8851_FCHWR_FCHWC 0x0FFF
341 
342 //Flow Control Overrun Watermark register
343 #define KSZ8851_FCOWR_FCLWC 0x0FFF
344 
345 //Chip ID and Enable register
346 #define KSZ8851_CIDER_FAMILY_ID 0xFF00
347 #define KSZ8851_CIDER_FAMILY_ID_DEFAULT 0x8800
348 #define KSZ8851_CIDER_CHIP_ID 0x00F0
349 #define KSZ8851_CIDER_CHIP_ID_DEFAULT 0x0070
350 #define KSZ8851_CIDER_REV_ID 0x000E
351 #define KSZ8851_CIDER_REV_ID_A2 0x0000
352 #define KSZ8851_CIDER_REV_ID_A3 0x0002
353 
354 //Chip Global Control register
355 #define KSZ8851_CGCR_LEDSEL0 0x0200
356 
357 //Indirect Access Control register
358 #define KSZ8851_IACR_READ_EN 0x1000
359 #define KSZ8851_IACR_TABLE_SEL 0x0C00
360 #define KSZ8851_IACR_TABLE_SEL_MIB_COUNTER 0x0C00
361 #define KSZ8851_IACR_INDIRECT_ADDR 0x001F
362 
363 //Power Management Event Control register
364 #define KSZ8851_PMECR_PME_DELAY_EN 0x4000
365 #define KSZ8851_PMECR_PME_OUT_POLARITY 0x1000
366 #define KSZ8851_PMECR_WOL_TO_PME_OUT_EN 0x0F00
367 #define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_WUP_FRAME 0x0800
368 #define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_MAGIC_PKT 0x0400
369 #define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_LINK_UP 0x0200
370 #define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_ENERGY_DETECT 0x0100
371 #define KSZ8851_PMECR_AUTO_WUP_EN 0x0080
372 #define KSZ8851_PMECR_WUP_TO_NORMAL_OP_MODE 0x0040
373 #define KSZ8851_PMECR_WUP_EVENT 0x003C
374 #define KSZ8851_PMECR_WUP_EVENT_NONE 0x0000
375 #define KSZ8851_PMECR_WUP_EVENT_ENERGY_DETECT 0x0004
376 #define KSZ8851_PMECR_WUP_EVENT_LINK_UP 0x0008
377 #define KSZ8851_PMECR_WUP_EVENT_MAGIC_PKT 0x0010
378 #define KSZ8851_PMECR_WUP_EVENT_WUP_FRAME 0x0020
379 #define KSZ8851_PMECR_PWR_MGMT_MODE 0x0003
380 #define KSZ8851_PMECR_PWR_MGMT_MODE_NORMAL 0x0000
381 #define KSZ8851_PMECR_PWR_MGMT_MODE_ENERGY_DETECT 0x0001
382 #define KSZ8851_PMECR_PWR_MGMT_MODE_PWR_SAVING 0x0003
383 
384 //Go-Sleep & Wake-Up Time register
385 #define KSZ8851_GSWUTR_WUP_TIME 0xFF00
386 #define KSZ8851_GSWUTR_GO_SLEEP_TIME 0x00FF
387 
388 //PHY Reset register
389 #define KSZ8851_PHYRR_PHY_RESET 0x0001
390 
391 //PHY 1 MII Basic Control register
392 #define KSZ8851_P1MBCR_LOCAL_LOOPBACK 0x4000
393 #define KSZ8851_P1MBCR_FORCE_100 0x2000
394 #define KSZ8851_P1MBCR_AN_ENABLE 0x1000
395 #define KSZ8851_P1MBCR_RESTART_AN 0x0200
396 #define KSZ8851_P1MBCR_FORCE_FULL_DUPLEX 0x0100
397 #define KSZ8851_P1MBCR_HP_MDIX 0x0020
398 #define KSZ8851_P1MBCR_FORCE_MDIX 0x0010
399 #define KSZ8851_P1MBCR_DISABLE_MDIX 0x0008
400 #define KSZ8851_P1MBCR_DISABLE_TRANSMIT 0x0002
401 #define KSZ8851_P1MBCR_DISABLE_LED 0x0001
402 
403 //PHY 1 MII Basic Status register
404 #define KSZ8851_P1MBSR_T4_CAPABLE 0x8000
405 #define KSZ8851_P1MBSR_100_FULL_CAPABLE 0x4000
406 #define KSZ8851_P1MBSR_100_HALF_CAPABLE 0x2000
407 #define KSZ8851_P1MBSR_10_FULL_CAPABLE 0x1000
408 #define KSZ8851_P1MBSR_10_HALF_CAPABLE 0x0800
409 #define KSZ8851_P1MBSR_PREAMBLE_SUPPR 0x0040
410 #define KSZ8851_P1MBSR_AN_COMPLETE 0x0020
411 #define KSZ8851_P1MBSR_AN_CAPABLE 0x0008
412 #define KSZ8851_P1MBSR_LINK_STATUS 0x0004
413 #define KSZ8851_P1MBSR_JABBER_TEST 0x0002
414 #define KSZ8851_P1MBSR_EXTENDED_CAPABLE 0x0001
415 
416 //PHY 1 ID Low register
417 #define KSZ8851_PHY1ILR_DEFAULT 0x1430
418 
419 //PHY 1 ID High register
420 #define KSZ8851_PHY1IHR_DEFAULT 0x0022
421 
422 //PHY 1 Auto-Negotiation Advertisement register
423 #define KSZ8851_P1ANAR_NEXT_PAGE 0x8000
424 #define KSZ8851_P1ANAR_REMOTE_FAULT 0x2000
425 #define KSZ8851_P1ANAR_PAUSE 0x0400
426 #define KSZ8851_P1ANAR_ADV_100_FULL 0x0100
427 #define KSZ8851_P1ANAR_ADV_100_HALF 0x0080
428 #define KSZ8851_P1ANAR_ADV_10_FULL 0x0040
429 #define KSZ8851_P1ANAR_ADV_10_HALF 0x0020
430 #define KSZ8851_P1ANAR_SELECTOR 0x001F
431 
432 //PHY 1 Auto-Negotiation Link Partner Ability register
433 #define KSZ8851_P1ANLPR_NEXT_PAGE 0x8000
434 #define KSZ8851_P1ANLPR_LP_ACK 0x4000
435 #define KSZ8851_P1ANLPR_REMOTE_FAULT 0x2000
436 #define KSZ8851_P1ANLPR_PAUSE 0x0400
437 #define KSZ8851_P1ANLPR_ADV_100_FULL 0x0100
438 #define KSZ8851_P1ANLPR_ADV_100_HALF 0x0080
439 #define KSZ8851_P1ANLPR_ADV_10_FULL 0x0040
440 #define KSZ8851_P1ANLPR_ADV_10_HALF 0x0020
441 
442 //Port 1 PHY Special Control/Status & LinkMD register
443 #define KSZ8851_P1SCLMD_VCT_RESULT 0x6000
444 #define KSZ8851_P1SCLMD_VCT_EN 0x1000
445 #define KSZ8851_P1SCLMD_FORCE_LNK 0x0800
446 #define KSZ8851_P1SCLMD_REMOTE_LOOPBACK 0x0200
447 #define KSZ8851_P1SCLMD_VCT_FAULT_COUNT 0x01FF
448 
449 //Port 1 Control register
450 #define KSZ8851_P1CR_LED_OFF 0x8000
451 #define KSZ8851_P1CR_TX_DISABLE 0x4000
452 #define KSZ8851_P1CR_RESTART_AN 0x2000
453 #define KSZ8851_P1CR_DISABLE_AUTO_MDIX 0x0400
454 #define KSZ8851_P1CR_FORCE_MDIX 0x0200
455 #define KSZ8851_P1CR_AN_ENABLE 0x0080
456 #define KSZ8851_P1CR_FORCE_SPEED 0x0040
457 #define KSZ8851_P1CR_FORCE_DUPLEX 0x0020
458 #define KSZ8851_P1CR_ADV_PAUSE 0x0010
459 #define KSZ8851_P1CR_ADV_100_FULL 0x0008
460 #define KSZ8851_P1CR_ADV_100_HALF 0x0004
461 #define KSZ8851_P1CR_ADV_10_FULL 0x0002
462 #define KSZ8851_P1CR_ADV_10_HALF 0x0001
463 
464 //Port 1 Status register
465 #define KSZ8851_P1SR_HP_MDIX 0x8000
466 #define KSZ8851_P1SR_POLARITY_REVERSE 0x2000
467 #define KSZ8851_P1SR_OPERATION_SPEED 0x0400
468 #define KSZ8851_P1SR_OPERATION_DUPLEX 0x0200
469 #define KSZ8851_P1SR_MDIX_STATUS 0x0080
470 #define KSZ8851_P1SR_AN_DONE 0x0040
471 #define KSZ8851_P1SR_LINK_GOOD 0x0020
472 #define KSZ8851_P1SR_LP_PAUSE 0x0010
473 #define KSZ8851_P1SR_LP_100_FULL 0x0008
474 #define KSZ8851_P1SR_LP_100_HALF 0x0004
475 #define KSZ8851_P1SR_LP_10_FULL 0x0002
476 #define KSZ8851_P1SR_LP_10_HALF 0x0001
477 
478 //Transmit control word
479 #define KSZ8851_TX_CTRL_TXIC 0x8000
480 #define KSZ8851_TX_CTRL_TXFID 0x003F
481 
482 //C++ guard
483 #ifdef __cplusplus
484 extern "C" {
485 #endif
486 
487 
488 /**
489  * @brief TX packet header
490  **/
491 
492 typedef __start_packed struct
493 {
494  uint16_t controlWord;
495  uint16_t byteCount;
497 
498 
499 /**
500  * @brief RX packet header
501  **/
502 
503 typedef __start_packed struct
504 {
505  uint16_t statusWord;
506  uint16_t byteCount;
508 
509 
510 /**
511  * @brief KSZ8851 driver context
512  **/
513 
514 typedef struct
515 {
516  uint16_t frameId; ///<Identify a frame and its associated status
518 
519 
520 //KSZ8851 driver
521 extern const NicDriver ksz8851Driver;
522 
523 //KSZ8851 related functions
524 error_t ksz8851Init(NetInterface *interface);
525 
526 void ksz8851Tick(NetInterface *interface);
527 
528 void ksz8851EnableIrq(NetInterface *interface);
529 void ksz8851DisableIrq(NetInterface *interface);
531 void ksz8851EventHandler(NetInterface *interface);
532 
534  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
535 
537 
539 
540 void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data);
541 uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address);
542 
543 void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data,
544  size_t length);
545 
546 void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length);
547 
548 void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask);
549 void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask);
550 
551 uint32_t ksz8851CalcCrc(const void *data, size_t length);
552 
553 void ksz8851DumpReg(NetInterface *interface);
554 
555 //C++ guard
556 #ifdef __cplusplus
557 }
558 #endif
559 
560 #endif
uint8_t length
Definition: coap_common.h:193
void ksz8851EnableIrq(NetInterface *interface)
Enable interrupts.
int bool_t
Definition: compiler_port.h:53
uint8_t data[]
Definition: ethernet.h:220
uint16_t byteCount
uint16_t frameId
Identify a frame and its associated status.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint16_t controlWord
error_t ksz8851UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void ksz8851ReadFifo(NetInterface *interface, uint8_t *data, size_t length)
Read RX FIFO.
void ksz8851DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
error_t
Error codes.
Definition: error.h:43
error_t ksz8851Init(NetInterface *interface)
KSZ8851 controller initialization.
bool_t ksz8851IrqHandler(NetInterface *interface)
KSZ8851 interrupt service routine.
void ksz8851EventHandler(NetInterface *interface)
KSZ8851 event handler.
#define NetInterface
Definition: net.h:36
__start_packed struct _Ipv4Header __end_packed
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t mask
Definition: web_socket.h:317
uint32_t ksz8851CalcCrc(const void *data, size_t length)
CRC calculation.
uint16_t statusWord
KSZ8851 driver context.
error_t ksz8851ReceivePacket(NetInterface *interface)
Receive a packet.
Network interface controller abstraction layer.
uint16_t ksz8851ReadReg(NetInterface *interface, uint8_t address)
Read KSZ8851 register.
Ipv6Addr address
__start_packed struct @1 Ksz8851RxHeader
RX packet header.
void ksz8851DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8851SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void ksz8851ClearBit(NetInterface *interface, uint8_t address, uint16_t mask)
Clear bit field.
void ksz8851WriteReg(NetInterface *interface, uint8_t address, uint16_t data)
Write KSZ8851 register.
void ksz8851SetBit(NetInterface *interface, uint8_t address, uint16_t mask)
Set bit field.
NIC driver.
Definition: nic.h:281
void ksz8851WriteFifo(NetInterface *interface, const uint8_t *data, size_t length)
Write TX FIFO.
__start_packed struct @0 Ksz8851TxHeader
TX packet header.
void ksz8851Tick(NetInterface *interface)
KSZ8851 timer handler.
const NicDriver ksz8851Driver
KSZ8851 driver.