lpc54xxx_eth_driver.h
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1 /**
2  * @file lpc54xxx_eth_driver.h
3  * @brief LPC540xx/LPC546xx Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _LPC54XXX_ETH_DRIVER_H
32 #define _LPC54XXX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef LPC54XXX_ETH_TX_BUFFER_COUNT
39  #define LPC54XXX_ETH_TX_BUFFER_COUNT 3
40 #elif (LPC54XXX_ETH_TX_BUFFER_COUNT < 1)
41  #error LPC54XXX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef LPC54XXX_ETH_TX_BUFFER_SIZE
46  #define LPC54XXX_ETH_TX_BUFFER_SIZE 1536
47 #elif (LPC54XXX_ETH_TX_BUFFER_SIZE != 1536)
48  #error LPC54XXX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef LPC54XXX_ETH_RX_BUFFER_COUNT
53  #define LPC54XXX_ETH_RX_BUFFER_COUNT 6
54 #elif (LPC54XXX_ETH_RX_BUFFER_COUNT < 1)
55  #error LPC54XXX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef LPC54XXX_ETH_RX_BUFFER_SIZE
60  #define LPC54XXX_ETH_RX_BUFFER_SIZE 1536
61 #elif (LPC54XXX_ETH_RX_BUFFER_SIZE != 1536)
62  #error LPC54XXX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef LPC54XXX_ETH_IRQ_PRIORITY_GROUPING
67  #define LPC54XXX_ETH_IRQ_PRIORITY_GROUPING 4
68 #elif (LPC54XXX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error LPC54XXX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef LPC54XXX_ETH_IRQ_GROUP_PRIORITY
74  #define LPC54XXX_ETH_IRQ_GROUP_PRIORITY 6
75 #elif (LPC54XXX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error LPC54XXX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef LPC54XXX_ETH_IRQ_SUB_PRIORITY
81  #define LPC54XXX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (LPC54XXX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error LPC54XXX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Transmit normal descriptor (read format)
87 #define ENET_TDES0_BUF1AP 0xFFFFFFFF
88 #define ENET_TDES1_BUF2AP 0xFFFFFFFF
89 #define ENET_TDES2_IOC 0x80000000
90 #define ENET_TDES2_TTSE 0x40000000
91 #define ENET_TDES2_B2L 0x3FFF0000
92 #define ENET_TDES2_B1L 0x00003FFF
93 #define ENET_TDES3_OWN 0x80000000
94 #define ENET_TDES3_CTXT 0x40000000
95 #define ENET_TDES3_FD 0x20000000
96 #define ENET_TDES3_LD 0x10000000
97 #define ENET_TDES3_CPC 0x0C000000
98 #define ENET_TDES3_SLOTNUM 0x00780000
99 #define ENET_TDES3_CIC 0x00030000
100 #define ENET_TDES3_FL 0x00007FFF
101 
102 //Transmit normal descriptor (write-back format)
103 #define ENET_TDES0_TTSL 0xFFFFFFFF
104 #define ENET_TDES1_TTSH 0xFFFFFFFF
105 #define ENET_TDES3_OWN 0x80000000
106 #define ENET_TDES3_CTXT 0x40000000
107 #define ENET_TDES3_FD 0x20000000
108 #define ENET_TDES3_LD 0x10000000
109 #define ENET_TDES3_TTSS 0x00020000
110 #define ENET_TDES3_ES 0x00008000
111 #define ENET_TDES3_JT 0x00004000
112 #define ENET_TDES3_FF 0x00002000
113 #define ENET_TDES3_PCE 0x00001000
114 #define ENET_TDES3_LOC 0x00000800
115 #define ENET_TDES3_NC 0x00000400
116 #define ENET_TDES3_LC 0x00000200
117 #define ENET_TDES3_EC 0x00000100
118 #define ENET_TDES3_CC 0x000000F0
119 #define ENET_TDES3_ED 0x00000008
120 #define ENET_TDES3_UF 0x00000004
121 #define ENET_TDES3_DB 0x00000002
122 #define ENET_TDES3_IHE 0x00000001
123 
124 //Receive normal descriptor (read format)
125 #define ENET_RDES0_BUF1AP 0xFFFFFFFF
126 #define ENET_RDES2_BUF2AP 0xFFFFFFFF
127 #define ENET_RDES3_OWN 0x80000000
128 #define ENET_RDES3_IOC 0x40000000
129 #define ENET_RDES3_BUF2V 0x02000000
130 #define ENET_RDES3_BUF1V 0x01000000
131 
132 //Receive normal descriptor (write-back format)
133 #define ENET_RDES0_IVT 0xFFFF0000
134 #define ENET_RDES0_OVT 0x0000FFFF
135 #define ENET_RDES1_OPC 0xFFFF0000
136 #define ENET_RDES1_TD 0x00008000
137 #define ENET_RDES1_TSA 0x00004000
138 #define ENET_RDES1_PV 0x00002000
139 #define ENET_RDES1_PFT 0x00001000
140 #define ENET_RDES1_PMT 0x00000F00
141 #define ENET_RDES1_IPCE 0x00000080
142 #define ENET_RDES1_IPCB 0x00000040
143 #define ENET_RDES1_IPV6 0x00000020
144 #define ENET_RDES1_IPV4 0x00000010
145 #define ENET_RDES1_IPHE 0x00000008
146 #define ENET_RDES1_PT 0x00000007
147 #define ENET_RDES2_MADRM 0x07F80000
148 #define ENET_RDES2_DAF 0x00020000
149 #define ENET_RDES2_SAF 0x00010000
150 #define ENET_RDES3_OWN 0x80000000
151 #define ENET_RDES3_CTXT 0x40000000
152 #define ENET_RDES3_FD 0x20000000
153 #define ENET_RDES3_LD 0x10000000
154 #define ENET_RDES3_RS2V 0x08000000
155 #define ENET_RDES3_RS1V 0x04000000
156 #define ENET_RDES3_RS0V 0x02000000
157 #define ENET_RDES3_CE 0x01000000
158 #define ENET_RDES3_GP 0x00800000
159 #define ENET_RDES3_RWT 0x00400000
160 #define ENET_RDES3_OE 0x00200000
161 #define ENET_RDES3_RE 0x00100000
162 #define ENET_RDES3_DE 0x00080000
163 #define ENET_RDES3_LT 0x00070000
164 #define ENET_RDES3_ES 0x00008000
165 #define ENET_RDES3_PL 0x00007FFF
166 
167 //C++ guard
168 #ifdef __cplusplus
169 extern "C" {
170 #endif
171 
172 
173 /**
174  * @brief Transmit descriptor
175  **/
176 
177 typedef struct
178 {
179  uint32_t tdes0;
180  uint32_t tdes1;
181  uint32_t tdes2;
182  uint32_t tdes3;
184 
185 
186 /**
187  * @brief Receive descriptor
188  **/
189 
190 typedef struct
191 {
192  uint32_t rdes0;
193  uint32_t rdes1;
194  uint32_t rdes2;
195  uint32_t rdes3;
197 
198 
199 //LPC54xxx Ethernet MAC driver
200 extern const NicDriver lpc54xxxEthDriver;
201 
202 //LPC54xxx Ethernet MAC related functions
204 void lpc54xxxEthInitGpio(NetInterface *interface);
205 void lpc54xxxEthInitDmaDesc(NetInterface *interface);
206 
207 void lpc54xxxEthTick(NetInterface *interface);
208 
209 void lpc54xxxEthEnableIrq(NetInterface *interface);
210 void lpc54xxxEthDisableIrq(NetInterface *interface);
211 void lpc54xxxEthEventHandler(NetInterface *interface);
212 
214  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
215 
217 
220 
221 void lpc54xxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
222  uint8_t regAddr, uint16_t data);
223 
224 uint16_t lpc54xxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
225  uint8_t regAddr);
226 
227 //C++ guard
228 #ifdef __cplusplus
229 }
230 #endif
231 
232 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
const NicDriver lpc54xxxEthDriver
LPC54xxx Ethernet MAC driver.
error_t lpc54xxxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t lpc54xxxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t lpc54xxxEthReceivePacket(NetInterface *interface)
Receive a packet.
void lpc54xxxEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t lpc54xxxEthInit(NetInterface *interface)
LPC54xxx Ethernet MAC initialization.
uint16_t lpc54xxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void lpc54xxxEthEventHandler(NetInterface *interface)
LPC54xxx Ethernet MAC event handler.
void lpc54xxxEthTick(NetInterface *interface)
LPC54xxx Ethernet MAC timer handler.
void lpc54xxxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void lpc54xxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void lpc54xxxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t lpc54xxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void lpc54xxxEthInitGpio(NetInterface *interface)
GPIO configuration.
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Receive descriptor.
Transmit descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283