pic32mx_eth.c
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1 /**
2  * @file pic32mx_eth.c
3  * @brief PIC32MX Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.7.8
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <p32xxxx.h>
34 #include <sys/kmem.h>
35 #include "core/net.h"
36 #include "drivers/pic32mx_eth.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //Transmit buffer
44  __attribute__((aligned(4)));
45 //Receive buffer
47  __attribute__((aligned(4)));
48 //Transmit buffer descriptors
50  __attribute__((aligned(4)));
51 //Receive buffer descriptors
53  __attribute__((aligned(4)));
54 
55 //Pointer to the current TX buffer descriptor
56 static Pic32mxTxBufferDesc *txCurBufferDesc;
57 //Pointer to the current RX buffer descriptor
58 static Pic32mxRxBufferDesc *rxCurBufferDesc;
59 
60 
61 /**
62  * @brief PIC32MX Ethernet MAC driver
63  **/
64 
66 {
68  ETH_MTU,
79  TRUE,
80  TRUE,
81  TRUE,
82  FALSE
83 };
84 
85 
86 /**
87  * @brief PIC32MX Ethernet MAC initialization
88  * @param[in] interface Underlying network interface
89  * @return Error code
90  **/
91 
93 {
94  error_t error;
95 
96  //Debug message
97  TRACE_INFO("Initializing PIC32MX Ethernet MAC...\r\n");
98 
99  //Save underlying network interface
100  nicDriverInterface = interface;
101 
102  //GPIO configuration
103  pic32mxEthInitGpio(interface);
104 
105  //Disable Ethernet interrupts
106  IEC1CLR = _IEC1_ETHIE_MASK;
107  //Turn the Ethernet controller off
108  ETHCON1CLR = _ETHCON1_ON_MASK | _ETHCON1_TXRTS_POSITION | _ETHCON1_RXEN_MASK;
109 
110  //Wait activity abort by polling the ETHBUSY bit
111  while(ETHSTAT & _ETHSTAT_ETHBUSY_MASK);
112 
113  //Enable the Ethernet controller by setting the ON bit
114  ETHCON1SET = _ETHCON1_ON_MASK;
115 
116  //Clear Ethernet interrupt flag
117  IFS1CLR = _IFS1_ETHIF_MASK;
118  //Disable any Ethernet controller interrupt generation
119  ETHIEN = 0;
120  ETHIRQ = 0;
121  //Clear the TX and RX start addresses
122  ETHTXST = 0;
123  ETHRXST = 0;
124 
125  //Reset the MAC using SOFTRESET
126  EMAC1CFG1SET = _EMAC1CFG1_SOFTRESET_MASK;
127  EMAC1CFG1CLR = _EMAC1CFG1_SOFTRESET_MASK;
128 
129  //Reset the RMII module
130  EMAC1SUPPSET = _EMAC1SUPP_RESETRMII_MASK;
131  EMAC1SUPPCLR = _EMAC1SUPP_RESETRMII_MASK;
132 
133  //Issue an MIIM block reset by setting the RESETMGMT bit
134  EMAC1MCFGSET = _EMAC1MCFG_RESETMGMT_MASK;
135  EMAC1MCFGCLR = _EMAC1MCFG_RESETMGMT_MASK;
136 
137  //Select the proper divider for the MDC clock
138  EMAC1MCFG = _EMAC1MCFG_CLKSEL_DIV40;
139 
140  //PHY transceiver initialization
141  error = interface->phyDriver->init(interface);
142  //Failed to initialize PHY transceiver?
143  if(error)
144  return error;
145 
146  //Optionally set the station MAC address
147  if(macCompAddr(&interface->macAddr, &MAC_UNSPECIFIED_ADDR))
148  {
149  //Use the factory preprogrammed station address
150  interface->macAddr.w[0] = EMAC1SA2;
151  interface->macAddr.w[1] = EMAC1SA1;
152  interface->macAddr.w[2] = EMAC1SA0;
153 
154  //Generate the 64-bit interface identifier
155  macAddrToEui64(&interface->macAddr, &interface->eui64);
156  }
157  else
158  {
159  //Override the factory preprogrammed address
160  EMAC1SA0 = interface->macAddr.w[2];
161  EMAC1SA1 = interface->macAddr.w[1];
162  EMAC1SA2 = interface->macAddr.w[0];
163  }
164 
165  //Initialize hash table
166  ETHHT0 = 0;
167  ETHHT1 = 0;
168 
169  //Configure the receive filter
170  ETHRXFC = _ETHRXFC_HTEN_MASK | _ETHRXFC_CRCOKEN_MASK |
171  _ETHRXFC_RUNTEN_MASK | _ETHRXFC_UCEN_MASK | _ETHRXFC_BCEN_MASK;
172 
173  //Disable flow control
174  EMAC1CFG1 = _EMAC1CFG1_RXENABLE_MASK;
175  //Automatic padding and CRC generation
176  EMAC1CFG2 = _EMAC1CFG2_PADENABLE_MASK | _EMAC1CFG2_CRCENABLE_MASK;
177  //Set the maximum frame length
178  EMAC1MAXF = 1518;
179 
180  //Initialize DMA descriptor lists
181  pic32mxEthInitBufferDesc(interface);
182 
183  //Enable desired interrupts
184  ETHIENSET = _ETHIEN_PKTPENDIE_MASK | _ETHIEN_TXDONEIE_MASK;
185 
186  //Set interrupt priority
187  IPC12CLR = _IPC12_ETHIP_MASK;
188  IPC12SET = (PIC32MX_ETH_IRQ_PRIORITY << _IPC12_ETHIP_POSITION);
189  //Set interrupt subpriority
190  IPC12CLR = _IPC12_ETHIS_MASK;
191  IPC12SET = (PIC32MX_ETH_IRQ_SUB_PRIORITY << _IPC12_ETHIS_POSITION);
192 
193  //Enable the reception by setting the RXEN bit
194  ETHCON1SET = _ETHCON1_RXEN_MASK;
195 
196  //Accept any packets from the upper layer
197  osSetEvent(&interface->nicTxEvent);
198 
199  //Successful initialization
200  return NO_ERROR;
201 }
202 
203 
204 //PIC32 Ethernet Starter Kit?
205 #if defined(USE_PIC32_ETH_STARTER_KIT) || defined(USE_PIC32_ETH_STARTER_KIT_2)
206 
207 /**
208  * @brief GPIO configuration
209  * @param[in] interface Underlying network interface
210  **/
211 
212 void pic32mxEthInitGpio(NetInterface *interface)
213 {
214  //No analog pins are shared with the alternate RMII interface
215 }
216 
217 #endif
218 
219 
220 /**
221  * @brief Initialize DMA descriptor lists
222  * @param[in] interface Underlying network interface
223  **/
224 
226 {
227  uint_t i;
228 
229  //Initialize TX descriptor list
230  for(i = 0; i < PIC32MX_ETH_TX_BUFFER_COUNT; i++)
231  {
232  //Point to the current descriptor
233  txCurBufferDesc = KVA0_TO_KVA1(&txBufferDesc[i]);
234 
235  //Use linked list rather than linear list
236  txCurBufferDesc->control = ETH_TX_CTRL_NPV;
237  //Transmit buffer address
238  txCurBufferDesc->address = (uint32_t) KVA_TO_PA(txBuffer[i]);
239  //Transmit status vector
240  txCurBufferDesc->status1 = 0;
241  txCurBufferDesc->status2 = 0;
242  //Next descriptor address
243  txCurBufferDesc->next = (uint32_t) KVA_TO_PA(&txBufferDesc[i + 1]);
244  }
245 
246  //The last descriptor is chained to the first entry
247  txCurBufferDesc->next = (uint32_t) KVA_TO_PA(&txBufferDesc[0]);
248  //Point to the very first descriptor
249  txCurBufferDesc = KVA0_TO_KVA1(&txBufferDesc[0]);
250 
251  //Initialize RX descriptor list
252  for(i = 0; i < PIC32MX_ETH_RX_BUFFER_COUNT; i++)
253  {
254  //Point to the current descriptor
255  rxCurBufferDesc = KVA0_TO_KVA1(&rxBufferDesc[i]);
256 
257  //The descriptor is initially owned by the DMA
258  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
259  //Receive buffer address
260  rxCurBufferDesc->address = (uint32_t) KVA_TO_PA(rxBuffer[i]);
261  //Receive status vector
262  rxCurBufferDesc->status1 = 0;
263  rxCurBufferDesc->status2 = 0;
264  //Next descriptor address
265  rxCurBufferDesc->next = (uint32_t) KVA_TO_PA(&rxBufferDesc[i + 1]);
266  }
267 
268  //The last descriptor is chained to the first entry
269  rxCurBufferDesc->next = (uint32_t) KVA_TO_PA(&rxBufferDesc[0]);
270  //Point to the very first descriptor
271  rxCurBufferDesc = KVA0_TO_KVA1(&rxBufferDesc[0]);
272 
273  //Starting address of TX descriptor table
274  ETHTXST = (uint32_t) KVA_TO_PA(&txBufferDesc[0]);
275  //Starting address of RX descriptor table
276  ETHRXST = (uint32_t) KVA_TO_PA(&rxBufferDesc[0]);
277  //Set receive buffer size
278  ETHCON2 = PIC32MX_ETH_RX_BUFFER_SIZE;
279 }
280 
281 
282 /**
283  * @brief PIC32MX Ethernet MAC timer handler
284  *
285  * This routine is periodically called by the TCP/IP stack to
286  * handle periodic operations such as polling the link state
287  *
288  * @param[in] interface Underlying network interface
289  **/
290 
291 void pic32mxEthTick(NetInterface *interface)
292 {
293  //Handle periodic operations
294  interface->phyDriver->tick(interface);
295 }
296 
297 
298 /**
299  * @brief Enable interrupts
300  * @param[in] interface Underlying network interface
301  **/
302 
304 {
305  //Enable Ethernet MAC interrupts
306  IEC1SET = _IEC1_ETHIE_MASK;
307  //Enable Ethernet PHY interrupts
308  interface->phyDriver->enableIrq(interface);
309 }
310 
311 
312 /**
313  * @brief Disable interrupts
314  * @param[in] interface Underlying network interface
315  **/
316 
318 {
319  //Disable Ethernet MAC interrupts
320  IEC1CLR = _IEC1_ETHIE_MASK;
321  //Disable Ethernet PHY interrupts
322  interface->phyDriver->disableIrq(interface);
323 }
324 
325 
326 /**
327  * @brief PIC32MX Ethernet MAC interrupt service routine
328  **/
329 
331 {
332  bool_t flag;
333  uint32_t status;
334 
335  //Enter interrupt service routine
336  osEnterIsr();
337 
338  //This flag will be set if a higher priority task must be woken
339  flag = FALSE;
340 
341  //Read interrupt status register
342  status = ETHIRQ;
343 
344  //A packet has been transmitted?
345  if(status & _ETHIRQ_TXDONE_MASK)
346  {
347  //Clear TXDONE interrupt flag
348  ETHIRQCLR = _ETHIRQ_TXDONE_MASK;
349 
350  //Check whether the TX buffer is available for writing
351  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
352  {
353  //Notify the TCP/IP stack that the transmitter is ready to send
354  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
355  }
356  }
357 
358  //A packet has been received?
359  if(status & _ETHIRQ_PKTPEND_MASK)
360  {
361  //Disable PKTPEND interrupt
362  ETHIENCLR = _ETHIEN_PKTPENDIE_MASK;
363 
364  //Set event flag
365  nicDriverInterface->nicEvent = TRUE;
366  //Notify the TCP/IP stack of the event
367  flag |= osSetEventFromIsr(&netEvent);
368  }
369 
370  //Clear ETHIF interrupt flag before exiting the service routine
371  IFS1CLR = _IFS1_ETHIF_MASK;
372 
373  //Leave interrupt service routine
374  osExitIsr(flag);
375 }
376 
377 
378 /**
379  * @brief PIC32MX Ethernet MAC event handler
380  * @param[in] interface Underlying network interface
381  **/
382 
384 {
385  error_t error;
386 
387  //Packet received?
388  if(ETHIRQ & _ETHIRQ_PKTPEND_MASK)
389  {
390  //Process all pending packets
391  do
392  {
393  //Read incoming packet
394  error = pic32mxEthReceivePacket(interface);
395 
396  //No more data in the receive buffer?
397  } while(error != ERROR_BUFFER_EMPTY);
398  }
399 
400  //Re-enable PKTPEND interrupt
401  ETHIENSET = _ETHIEN_PKTPENDIE_MASK;
402 }
403 
404 
405 /**
406  * @brief Send a packet
407  * @param[in] interface Underlying network interface
408  * @param[in] buffer Multi-part buffer containing the data to send
409  * @param[in] offset Offset to the first data byte
410  * @return Error code
411  **/
412 
414  const NetBuffer *buffer, size_t offset)
415 {
416  size_t length;
417  uint32_t value;
418 
419  //Retrieve the length of the packet
420  length = netBufferGetLength(buffer) - offset;
421 
422  //Check the frame length
423  if(length > PIC32MX_ETH_TX_BUFFER_SIZE)
424  {
425  //The transmitter can accept another packet
426  osSetEvent(&interface->nicTxEvent);
427  //Report an error
428  return ERROR_INVALID_LENGTH;
429  }
430 
431  //Make sure the current buffer is available for writing
432  if(txCurBufferDesc->control & ETH_TX_CTRL_EOWN)
433  return ERROR_FAILURE;
434 
435  //Copy user data to the transmit buffer
436  netBufferRead(PA_TO_KVA1(txCurBufferDesc->address), buffer, offset, length);
437 
438  //Write the number of bytes to send
439  value = (length << 16) & ETH_TX_CTRL_BYTE_COUNT;
440  //Set SOP and EOP flags since the data fits in a single buffer
442  //Give the ownership of the descriptor to the DMA
443  txCurBufferDesc->control = value | ETH_TX_CTRL_EOWN;
444 
445  //Set TXRTS bit to start the transmission
446  ETHCON1SET = _ETHCON1_TXRTS_MASK;
447 
448  //Point to the next descriptor in the list
449  txCurBufferDesc = PA_TO_KVA1(txCurBufferDesc->next);
450 
451  //Check whether the next buffer is available for writing
452  if(!(txCurBufferDesc->control & ETH_TX_CTRL_EOWN))
453  {
454  //The transmitter can accept another packet
455  osSetEvent(&interface->nicTxEvent);
456  }
457 
458  //Data successfully written
459  return NO_ERROR;
460 }
461 
462 
463 /**
464  * @brief Receive a packet
465  * @param[in] interface Underlying network interface
466  * @return Error code
467  **/
468 
470 {
471  static uint8_t temp[PIC32MX_ETH_RX_BUFFER_SIZE];
472  error_t error;
473  size_t n;
474 
475  //The current buffer is available for reading?
476  if(!(rxCurBufferDesc->control & ETH_RX_CTRL_EOWN))
477  {
478  //SOP and EOP flags should be set
479  if((rxCurBufferDesc->control & ETH_RX_CTRL_SOP) &&
480  (rxCurBufferDesc->control & ETH_RX_CTRL_EOP))
481  {
482  //Make sure no error occurred
483  if(rxCurBufferDesc->status2 & ETH_RX_STATUS2_OK)
484  {
485  //Retrieve the length of the frame
486  n = (rxCurBufferDesc->control & ETH_RX_CTRL_BYTE_COUNT) >> 16;
487  //Limit the number of data to read
489 
490  //Copy data from the receive buffer
491  memcpy(temp, PA_TO_KVA1(rxCurBufferDesc->address), n);
492 
493  //Pass the packet to the upper layer
494  nicProcessPacket(interface, temp, n);
495 
496  //Valid packet received
497  error = NO_ERROR;
498  }
499  else
500  {
501  //The received packet contains an error
502  error = ERROR_INVALID_PACKET;
503  }
504  }
505  else
506  {
507  //The packet is not valid
508  error = ERROR_INVALID_PACKET;
509  }
510 
511  //Give the ownership of the descriptor back to the DMA
512  rxCurBufferDesc->control = ETH_RX_CTRL_NPV | ETH_RX_CTRL_EOWN;
513 
514  //Point to the next descriptor in the list
515  rxCurBufferDesc = PA_TO_KVA1(rxCurBufferDesc->next);
516 
517  //Decrement BUFCNT counter
518  ETHCON1SET = _ETHCON1_BUFCDEC_MASK;
519  }
520  else
521  {
522  //No more data in the receive buffer
523  error = ERROR_BUFFER_EMPTY;
524  }
525 
526  //Return status code
527  return error;
528 }
529 
530 
531 /**
532  * @brief Configure multicast MAC address filtering
533  * @param[in] interface Underlying network interface
534  * @return Error code
535  **/
536 
538 {
539  uint_t i;
540  uint_t k;
541  uint32_t crc;
542  uint32_t hashTable[2];
543  MacFilterEntry *entry;
544 
545  //Debug message
546  TRACE_DEBUG("Updating PIC32MX hash table...\r\n");
547 
548  //Clear hash table
549  hashTable[0] = 0;
550  hashTable[1] = 0;
551 
552  //The MAC filter table contains the multicast MAC addresses
553  //to accept when receiving an Ethernet frame
554  for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
555  {
556  //Point to the current entry
557  entry = &interface->macMulticastFilter[i];
558 
559  //Valid entry?
560  if(entry->refCount > 0)
561  {
562  //Compute CRC over the current MAC address
563  crc = pic32mxEthCalcCrc(&entry->addr, sizeof(MacAddr));
564  //Calculate the corresponding index in the table
565  k = (crc >> 23) & 0x3F;
566  //Update hash table contents
567  hashTable[k / 32] |= (1 << (k % 32));
568  }
569  }
570 
571  //Write the hash table
572  ETHHT0 = hashTable[0];
573  ETHHT1 = hashTable[1];
574 
575  //Debug message
576  TRACE_DEBUG(" ETHHT0 = %08" PRIX32 "\r\n", ETHHT0);
577  TRACE_DEBUG(" ETHHT1 = %08" PRIX32 "\r\n", ETHHT1);
578 
579  //Successful processing
580  return NO_ERROR;
581 }
582 
583 
584 /**
585  * @brief Adjust MAC configuration parameters for proper operation
586  * @param[in] interface Underlying network interface
587  * @return Error code
588  **/
589 
591 {
592  //Check current operating speed
593  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
594  {
595  //100BASE-TX operation mode
596  EMAC1SUPPSET = _EMAC1SUPP_SPEEDRMII_MASK;
597  }
598  else
599  {
600  //10BASE-T operation mode
601  EMAC1SUPPCLR = _EMAC1SUPP_SPEEDRMII_MASK;
602  }
603 
604  //Half-duplex or full-duplex mode?
605  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
606  {
607  //Configure FULLDPLX bit to match the current duplex mode
608  EMAC1CFG2SET = _EMAC1CFG2_FULLDPLX_MASK;
609  //Configure the Back-to-Back Inter-Packet Gap register
610  EMAC1IPGT = 0x15;
611  }
612  else
613  {
614  //Configure FULLDPLX bit to match the current duplex mode
615  EMAC1CFG2CLR = _EMAC1CFG2_FULLDPLX_MASK;
616  //Configure the Back-to-Back Inter-Packet Gap register
617  EMAC1IPGT = 0x12;
618  }
619 
620  //Successful processing
621  return NO_ERROR;
622 }
623 
624 
625 /**
626  * @brief Write PHY register
627  * @param[in] phyAddr PHY address
628  * @param[in] regAddr Register address
629  * @param[in] data Register value
630  **/
631 
632 void pic32mxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
633 {
634  //Set PHY address and register address
635  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
636  //Start a write operation
637  EMAC1MWTD = data & _EMAC1MWTD_MWTD_MASK;
638 
639  //Wait for busy bit to be set
640  __asm__ __volatile__ ("nop;");
641  __asm__ __volatile__ ("nop;");
642  __asm__ __volatile__ ("nop;");
643 
644  //Wait for the write to complete
645  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK);
646 }
647 
648 
649 /**
650  * @brief Read PHY register
651  * @param[in] phyAddr PHY address
652  * @param[in] regAddr Register address
653  * @return Register value
654  **/
655 
656 uint16_t pic32mxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
657 {
658  //Set PHY address and register address
659  EMAC1MADR = (phyAddr << _EMAC1MADR_PHYADDR_POSITION) | regAddr;
660  //Start a read operation
661  EMAC1MCMD = _EMAC1MCMD_READ_MASK;
662 
663  //Wait for busy bit to be set
664  __asm__ __volatile__ ("nop;");
665  __asm__ __volatile__ ("nop;");
666  __asm__ __volatile__ ("nop;");
667 
668  //Wait for the read to complete
669  while(EMAC1MIND & _EMAC1MIND_MIIMBUSY_MASK);
670 
671  //Clear command register
672  EMAC1MCMD = 0;
673  //Return PHY register contents
674  return EMAC1MRDD & _EMAC1MRDD_MRDD_MASK;
675 }
676 
677 
678 /**
679  * @brief CRC calculation
680  * @param[in] data Pointer to the data over which to calculate the CRC
681  * @param[in] length Number of bytes to process
682  * @return Resulting CRC value
683  **/
684 
685 uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
686 {
687  uint_t i;
688  uint_t j;
689 
690  //Point to the data over which to calculate the CRC
691  const uint8_t *p = (uint8_t *) data;
692  //CRC preset value
693  uint32_t crc = 0xFFFFFFFF;
694 
695  //Loop through data
696  for(i = 0; i < length; i++)
697  {
698  //The message is processed bit by bit
699  for(j = 0; j < 8; j++)
700  {
701  //Update CRC value
702  if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
703  crc = (crc << 1) ^ 0x04C11DB7;
704  else
705  crc = crc << 1;
706  }
707  }
708 
709  //Return CRC value
710  return crc;
711 }
MacAddr addr
MAC address.
Definition: ethernet.h:165
#define ETH_TX_CTRL_SOP
Definition: pic32mx_eth.h:88
#define PIC32MX_ETH_IRQ_SUB_PRIORITY
Definition: pic32mx_eth.h:72
#define ETH_TX_CTRL_BYTE_COUNT
Definition: pic32mx_eth.h:90
TCP/IP stack core.
#define PIC32MX_ETH_IRQ_PRIORITY
Definition: pic32mx_eth.h:65
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Definition: avr32_eth.c:309
Debugging facilities.
void pic32mxEthDisableIrq(NetInterface *interface)
Disable interrupts.
Definition: pic32mx_eth.c:317
uint8_t p
Definition: ndp.h:290
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
Generic error code.
Definition: error.h:38
#define ETH_RX_STATUS2_OK
Definition: pic32mx_eth.h:135
PIC32MX Ethernet MAC controller.
uint8_t data[]
Definition: tls.h:1133
error_t pic32mxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Definition: pic32mx_eth.c:590
#define ETH_TX_CTRL_EOP
Definition: pic32mx_eth.h:89
__start_packed struct @80 MacAddr
MAC address.
#define TRUE
Definition: os_port.h:48
#define _EMAC1MCFG_CLKSEL_DIV40
Definition: pic32mx_eth.h:85
#define ETH_TX_CTRL_EOWN
Definition: pic32mx_eth.h:92
uint32_t pic32mxEthCalcCrc(const void *data, size_t length)
CRC calculation.
Definition: pic32mx_eth.c:685
void pic32mxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Definition: pic32mx_eth.c:632
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
RX buffer descriptor.
Definition: pic32mx_eth.h:164
error_t pic32mxEthInit(NetInterface *interface)
PIC32MX Ethernet MAC initialization.
Definition: pic32mx_eth.c:92
NIC driver.
Definition: nic.h:149
uint16_t length
Definition: tls.h:933
const NicDriver pic32mxEthDriver
PIC32MX Ethernet MAC driver.
Definition: pic32mx_eth.c:65
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:97
#define PIC32MX_ETH_RX_BUFFER_SIZE
Definition: pic32mx_eth.h:58
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
error_t pic32mxEthSetMulticastFilter(NetInterface *interface)
Configure multicast MAC address filtering.
Definition: pic32mx_eth.c:537
void pic32mxEthTick(NetInterface *interface)
PIC32MX Ethernet MAC timer handler.
Definition: pic32mx_eth.c:291
#define ETH_RX_CTRL_BYTE_COUNT
Definition: pic32mx_eth.h:116
TX buffer descriptor.
Definition: pic32mx_eth.h:150
#define rxBuffer
Definition: aps3_eth.c:45
uint16_t value[]
Definition: tls.h:934
#define ETH_RX_CTRL_SOP
Definition: pic32mx_eth.h:114
void macAddrToEui64(const MacAddr *macAddr, Eui64 *interfaceId)
Map a MAC address to the IPv6 modified EUI-64 identifier.
Definition: ethernet.c:1058
#define ETH_RX_CTRL_NPV
Definition: pic32mx_eth.h:117
#define TRACE_INFO(...)
Definition: debug.h:86
error_t pic32mxEthReceivePacket(NetInterface *interface)
Receive a packet.
Definition: pic32mx_eth.c:469
#define ETH_MTU
Definition: ethernet.h:61
Ethernet interface.
Definition: nic.h:63
Success.
Definition: error.h:37
void pic32mxEthEventHandler(NetInterface *interface)
PIC32MX Ethernet MAC event handler.
Definition: pic32mx_eth.c:383
error_t pic32mxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Definition: pic32mx_eth.c:413
OsEvent netEvent
Definition: net.c:72
void pic32mxEthEnableIrq(NetInterface *interface)
Enable interrupts.
Definition: pic32mx_eth.c:303
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:158
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:166
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:35
#define ETH_RX_CTRL_EOWN
Definition: pic32mx_eth.h:118
void pic32mxEthInitBufferDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Definition: pic32mx_eth.c:225
unsigned int uint_t
Definition: compiler_port.h:38
#define NetInterface
Definition: net.h:34
#define ETH_RX_CTRL_EOP
Definition: pic32mx_eth.h:115
#define PIC32MX_ETH_TX_BUFFER_COUNT
Definition: pic32mx_eth.h:37
#define macCompAddr(macAddr1, macAddr2)
Definition: ethernet.h:69
uint16_t pic32mxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Definition: pic32mx_eth.c:656
#define MAC_MULTICAST_FILTER_SIZE
Definition: ethernet.h:44
#define osExitIsr(flag)
#define ETH_TX_CTRL_NPV
Definition: pic32mx_eth.h:91
void pic32mxEthInitGpio(NetInterface *interface)
#define PIC32MX_ETH_TX_BUFFER_SIZE
Definition: pic32mx_eth.h:44
void pic32mxEthIrqHandler(void)
PIC32MX Ethernet MAC interrupt service routine.
Definition: pic32mx_eth.c:330
#define osEnterIsr()
uint8_t n
#define PIC32MX_ETH_RX_BUFFER_COUNT
Definition: pic32mx_eth.h:51
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:42
#define txBuffer
Definition: aps3_eth.c:43
MAC filter table entry.
Definition: ethernet.h:163
#define TRACE_DEBUG(...)
Definition: debug.h:98