avr32_eth_driver.c
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1 /**
2  * @file avr32_eth_driver.c
3  * @brief AVR32 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2023 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.3.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include <avr32/io.h>
37 #include "interrupt.h"
38 #include "intc.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 4
52 //RX buffer
53 #pragma data_alignment = 4
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 static Avr32TxBufferDesc txBufferDesc[AVR32_ETH_TX_BUFFER_COUNT];
58 //RX buffer descriptors
59 #pragma data_alignment = 8
60 static Avr32RxBufferDesc rxBufferDesc[AVR32_ETH_RX_BUFFER_COUNT];
61 
62 //GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(4)));
68 //RX buffer
70  __attribute__((aligned(4)));
71 //TX buffer descriptors
73  __attribute__((aligned(8)));
74 //RX buffer descriptors
76  __attribute__((aligned(8)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief AVR32 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief AVR32 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing AVR32 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Disable transmit and receive circuits
129  AVR32_MACB.ncr = 0;
130 
131  //GPIO configuration
132  avr32EthInitGpio(interface);
133 
134  //Configure MDC clock speed
135  AVR32_MACB.ncfgr = AVR32_MACB_NCFGR_CLK_DIV64;
136  //Enable management port (MDC and MDIO)
137  AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
138 
139  //Valid Ethernet PHY or switch driver?
140  if(interface->phyDriver != NULL)
141  {
142  //Ethernet PHY initialization
143  error = interface->phyDriver->init(interface);
144  }
145  else if(interface->switchDriver != NULL)
146  {
147  //Ethernet switch initialization
148  error = interface->switchDriver->init(interface);
149  }
150  else
151  {
152  //The interface is not properly configured
153  error = ERROR_FAILURE;
154  }
155 
156  //Any error to report?
157  if(error)
158  {
159  return error;
160  }
161 
162  //Set the MAC address of the station
163  AVR32_MACB.sa1b = interface->macAddr.b[0] |
164  (interface->macAddr.b[1] << 8) |
165  (interface->macAddr.b[2] << 16) |
166  (interface->macAddr.b[3] << 24);
167 
168  AVR32_MACB.sa1t = interface->macAddr.b[4] |
169  (interface->macAddr.b[5] << 8);
170 
171  //Initialize hash table
172  AVR32_MACB.hrb = 0;
173  AVR32_MACB.hrt = 0;
174 
175  //Configure the receive filter
176  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_BIG_MASK | AVR32_MACB_NCFGR_UNI_MASK |
177  AVR32_MACB_NCFGR_MTI_MASK;
178 
179  //Initialize buffer descriptors
180  avr32EthInitBufferDesc(interface);
181 
182  //Clear transmit status register
183  AVR32_MACB.tsr = AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK | AVR32_MACB_TSR_BEX_MASK |
184  AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK | AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK;
185  //Clear receive status register
186  AVR32_MACB.rsr = AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK;
187 
188  //First disable all EMAC interrupts
189  AVR32_MACB.idr = 0xFFFFFFFF;
190  //Only the desired ones are enabled
191  AVR32_MACB.ier = AVR32_MACB_IER_ROVR_MASK | AVR32_MACB_IER_TCOMP_MASK | AVR32_MACB_IER_TXERR_MASK |
192  AVR32_MACB_IER_RLE_MASK | AVR32_MACB_IER_TUND_MASK | AVR32_MACB_IER_RXUBR_MASK | AVR32_MACB_IER_RCOMP_MASK;
193 
194  //Read EMAC_ISR register to clear any pending interrupt
195  status = AVR32_MACB.isr;
196  (void) status;
197 
198  //Register interrupt handler
199  INTC_register_interrupt(avr32EthIrqWrapper, AVR32_MACB_IRQ, AVR32_ETH_IRQ_PRIORITY);
200 
201  //Enable the EMAC to transmit and receive data
202  AVR32_MACB.ncr |= AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 /**
213  * @brief GPIO configuration
214  * @param[in] interface Underlying network interface
215  **/
216 
217 __weak_func void avr32EthInitGpio(NetInterface *interface)
218 {
219 //EVK1105 evaluation board?
220 #if defined(USE_EVK1105)
221  //Assign RMII pins to peripheral A function
222  AVR32_GPIO.port[1].pmr0c = MACB_RMII_MASK;
223  AVR32_GPIO.port[1].pmr1c =MACB_RMII_MASK;
224 
225  //Disable the PIO from controlling the corresponding pins
226  AVR32_GPIO.port[1].gperc = MACB_RMII_MASK;
227 
228  //Select RMII operation mode
229  AVR32_MACB.usrio &= ~AVR32_MACB_USRIO_RMII_MASK;
230 #endif
231 }
232 
233 
234 /**
235  * @brief Initialize buffer descriptors
236  * @param[in] interface Underlying network interface
237  **/
238 
240 {
241  uint_t i;
242  uint32_t address;
243 
244  //Initialize TX buffer descriptors
245  for(i = 0; i < AVR32_ETH_TX_BUFFER_COUNT; i++)
246  {
247  //Calculate the address of the current TX buffer
248  address = (uint32_t) txBuffer[i];
249  //Write the address to the descriptor entry
250  txBufferDesc[i].address = address;
251  //Initialize status field
252  txBufferDesc[i].status = MACB_TX_USED;
253  }
254 
255  //Mark the last descriptor entry with the wrap flag
256  txBufferDesc[i - 1].status |= MACB_TX_WRAP;
257  //Initialize TX buffer index
258  txBufferIndex = 0;
259 
260  //Initialize RX buffer descriptors
261  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
262  {
263  //Calculate the address of the current RX buffer
264  address = (uint32_t) rxBuffer[i];
265  //Write the address to the descriptor entry
266  rxBufferDesc[i].address = address & MACB_RX_ADDRESS;
267  //Clear status field
268  rxBufferDesc[i].status = 0;
269  }
270 
271  //Mark the last descriptor entry with the wrap flag
272  rxBufferDesc[i - 1].address |= MACB_RX_WRAP;
273  //Initialize RX buffer index
274  rxBufferIndex = 0;
275 
276  //Start location of the TX descriptor list
277  AVR32_MACB.tbqp = (uint32_t) txBufferDesc;
278  //Start location of the RX descriptor list
279  AVR32_MACB.rbqp = (uint32_t) rxBufferDesc;
280 }
281 
282 
283 /**
284  * @brief AVR32 Ethernet MAC timer handler
285  *
286  * This routine is periodically called by the TCP/IP stack to handle periodic
287  * operations such as polling the link state
288  *
289  * @param[in] interface Underlying network interface
290  **/
291 
292 void avr32EthTick(NetInterface *interface)
293 {
294  //Valid Ethernet PHY or switch driver?
295  if(interface->phyDriver != NULL)
296  {
297  //Handle periodic operations
298  interface->phyDriver->tick(interface);
299  }
300  else if(interface->switchDriver != NULL)
301  {
302  //Handle periodic operations
303  interface->switchDriver->tick(interface);
304  }
305  else
306  {
307  //Just for sanity
308  }
309 }
310 
311 
312 /**
313  * @brief Enable interrupts
314  * @param[in] interface Underlying network interface
315  **/
316 
318 {
319  //Enable Ethernet MAC interrupts
320  Enable_global_interrupt();
321 
322  //Valid Ethernet PHY or switch driver?
323  if(interface->phyDriver != NULL)
324  {
325  //Enable Ethernet PHY interrupts
326  interface->phyDriver->enableIrq(interface);
327  }
328  else if(interface->switchDriver != NULL)
329  {
330  //Enable Ethernet switch interrupts
331  interface->switchDriver->enableIrq(interface);
332  }
333  else
334  {
335  //Just for sanity
336  }
337 }
338 
339 
340 /**
341  * @brief Disable interrupts
342  * @param[in] interface Underlying network interface
343  **/
344 
346 {
347  //Disable Ethernet MAC interrupts
348  Disable_global_interrupt();
349 
350  //Valid Ethernet PHY or switch driver?
351  if(interface->phyDriver != NULL)
352  {
353  //Disable Ethernet PHY interrupts
354  interface->phyDriver->disableIrq(interface);
355  }
356  else if(interface->switchDriver != NULL)
357  {
358  //Disable Ethernet switch interrupts
359  interface->switchDriver->disableIrq(interface);
360  }
361  else
362  {
363  //Just for sanity
364  }
365 }
366 
367 
368 /**
369  * @brief AVR32 Ethernet MAC interrupt wrapper
370  **/
371 
372  __attribute__((naked)) void avr32EthIrqWrapper(void)
373 {
374  //Interrupt service routine prologue
375  osEnterIsr();
376 
377  //Call Ethernet MAC interrupt handler
379 
380  //Interrupt service routine epilogue
381  osExitIsr(flag);
382 }
383 
384 
385 /**
386  * @brief AVR32 Ethernet MAC interrupt service routine
387  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
388  **/
389 
391 {
392  bool_t flag;
393  volatile uint32_t isr;
394  volatile uint32_t tsr;
395  volatile uint32_t rsr;
396 
397  //This flag will be set if a higher priority task must be woken
398  flag = FALSE;
399 
400  //Each time the software reads EMAC_ISR, it has to check the contents
401  //of EMAC_TSR, EMAC_RSR and EMAC_NSR
402  isr = AVR32_MACB.isr;
403  tsr = AVR32_MACB.tsr;
404  rsr = AVR32_MACB.rsr;
405  (void) isr;
406 
407  //Packet transmitted?
408  if((tsr & (AVR32_MACB_TSR_UND_MASK | AVR32_MACB_TSR_COMP_MASK |
409  AVR32_MACB_TSR_BEX_MASK | AVR32_MACB_TSR_TGO_MASK | AVR32_MACB_TSR_RLE_MASK |
410  AVR32_MACB_TSR_COL_MASK | AVR32_MACB_TSR_UBR_MASK)) != 0)
411  {
412  //Only clear TSR flags that are currently set
413  AVR32_MACB.tsr = tsr;
414 
415  //Check whether the TX buffer is available for writing
416  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) != 0)
417  {
418  //Notify the TCP/IP stack that the transmitter is ready to send
419  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
420  }
421  }
422 
423  //Packet received?
424  if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK |
425  AVR32_MACB_RSR_BNA_MASK)) != 0)
426  {
427  //Set event flag
428  nicDriverInterface->nicEvent = TRUE;
429  //Notify the TCP/IP stack of the event
430  flag |= osSetEventFromIsr(&netEvent);
431  }
432 
433  //A higher priority task must be woken?
434  return flag;
435 }
436 
437 
438 /**
439  * @brief AVR32 Ethernet MAC event handler
440  * @param[in] interface Underlying network interface
441  **/
442 
444 {
445  error_t error;
446  uint32_t rsr;
447 
448  //Read receive status
449  rsr = AVR32_MACB.rsr;
450 
451  //Packet received?
452  if((rsr & (AVR32_MACB_RSR_OVR_MASK | AVR32_MACB_RSR_REC_MASK | AVR32_MACB_RSR_BNA_MASK)) != 0)
453  {
454  //Only clear RSR flags that are currently set
455  AVR32_MACB.rsr = rsr;
456 
457  //Process all pending packets
458  do
459  {
460  //Read incoming packet
461  error = avr32EthReceivePacket(interface);
462 
463  //No more data in the receive buffer?
464  } while(error != ERROR_BUFFER_EMPTY);
465  }
466 }
467 
468 
469 /**
470  * @brief Send a packet
471  * @param[in] interface Underlying network interface
472  * @param[in] buffer Multi-part buffer containing the data to send
473  * @param[in] offset Offset to the first data byte
474  * @param[in] ancillary Additional options passed to the stack along with
475  * the packet
476  * @return Error code
477  **/
478 
480  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
481 {
482  size_t length;
483 
484  //Retrieve the length of the packet
485  length = netBufferGetLength(buffer) - offset;
486 
487  //Check the frame length
489  {
490  //The transmitter can accept another packet
491  osSetEvent(&interface->nicTxEvent);
492  //Report an error
493  return ERROR_INVALID_LENGTH;
494  }
495 
496  //Make sure the current buffer is available for writing
497  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) == 0)
498  {
499  return ERROR_FAILURE;
500  }
501 
502  //Copy user data to the transmit buffer
503  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
504 
505  //Set the necessary flags in the descriptor entry
506  if(txBufferIndex < (AVR32_ETH_TX_BUFFER_COUNT - 1))
507  {
508  //Write the status word
509  txBufferDesc[txBufferIndex].status = MACB_TX_LAST |
511 
512  //Point to the next buffer
513  txBufferIndex++;
514  }
515  else
516  {
517  //Write the status word
518  txBufferDesc[txBufferIndex].status = MACB_TX_WRAP | MACB_TX_LAST |
520 
521  //Wrap around
522  txBufferIndex = 0;
523  }
524 
525  //Set the TSTART bit to initiate transmission
526  AVR32_MACB.ncr |= AVR32_MACB_NCR_TSTART_MASK;
527 
528  //Check whether the next buffer is available for writing
529  if((txBufferDesc[txBufferIndex].status & MACB_TX_USED) != 0)
530  {
531  //The transmitter can accept another packet
532  osSetEvent(&interface->nicTxEvent);
533  }
534 
535  //Successful processing
536  return NO_ERROR;
537 }
538 
539 
540 /**
541  * @brief Receive a packet
542  * @param[in] interface Underlying network interface
543  * @return Error code
544  **/
545 
547 {
548  static uint8_t temp[ETH_MAX_FRAME_SIZE];
549  error_t error;
550  uint_t i;
551  uint_t j;
552  uint_t sofIndex;
553  uint_t eofIndex;
554  size_t n;
555  size_t size;
556  size_t length;
557 
558  //Initialize variables
559  size = 0;
560  sofIndex = UINT_MAX;
561  eofIndex = UINT_MAX;
562 
563  //Search for SOF and EOF flags
564  for(i = 0; i < AVR32_ETH_RX_BUFFER_COUNT; i++)
565  {
566  //Point to the current entry
567  j = rxBufferIndex + i;
568 
569  //Wrap around to the beginning of the buffer if necessary
571  {
573  }
574 
575  //No more entries to process?
576  if((rxBufferDesc[j].address & MACB_RX_OWNERSHIP) == 0)
577  {
578  //Stop processing
579  break;
580  }
581 
582  //A valid SOF has been found?
583  if((rxBufferDesc[j].status & MACB_RX_SOF) != 0)
584  {
585  //Save the position of the SOF
586  sofIndex = i;
587  }
588 
589  //A valid EOF has been found?
590  if((rxBufferDesc[j].status & MACB_RX_EOF) != 0 && sofIndex != UINT_MAX)
591  {
592  //Save the position of the EOF
593  eofIndex = i;
594  //Retrieve the length of the frame
595  size = rxBufferDesc[j].status & MACB_RX_LENGTH;
596  //Limit the number of data to read
597  size = MIN(size, ETH_MAX_FRAME_SIZE);
598  //Stop processing since we have reached the end of the frame
599  break;
600  }
601  }
602 
603  //Determine the number of entries to process
604  if(eofIndex != UINT_MAX)
605  {
606  j = eofIndex + 1;
607  }
608  else if(sofIndex != UINT_MAX)
609  {
610  j = sofIndex;
611  }
612  else
613  {
614  j = i;
615  }
616 
617  //Total number of bytes that have been copied from the receive buffer
618  length = 0;
619 
620  //Process incoming frame
621  for(i = 0; i < j; i++)
622  {
623  //Any data to copy from current buffer?
624  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
625  {
626  //Calculate the number of bytes to read at a time
627  n = MIN(size, AVR32_ETH_RX_BUFFER_SIZE);
628  //Copy data from receive buffer
629  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
630  //Update byte counters
631  length += n;
632  size -= n;
633  }
634 
635  //Mark the current buffer as free
636  rxBufferDesc[rxBufferIndex].address &= ~MACB_RX_OWNERSHIP;
637 
638  //Point to the following entry
639  rxBufferIndex++;
640 
641  //Wrap around to the beginning of the buffer if necessary
642  if(rxBufferIndex >= AVR32_ETH_RX_BUFFER_COUNT)
643  {
644  rxBufferIndex = 0;
645  }
646  }
647 
648  //Any packet to process?
649  if(length > 0)
650  {
651  NetRxAncillary ancillary;
652 
653  //Additional options can be passed to the stack along with the packet
654  ancillary = NET_DEFAULT_RX_ANCILLARY;
655 
656  //Pass the packet to the upper layer
657  nicProcessPacket(interface, temp, length, &ancillary);
658  //Valid packet received
659  error = NO_ERROR;
660  }
661  else
662  {
663  //No more data in the receive buffer
664  error = ERROR_BUFFER_EMPTY;
665  }
666 
667  //Return status code
668  return error;
669 }
670 
671 
672 /**
673  * @brief Configure MAC address filtering
674  * @param[in] interface Underlying network interface
675  * @return Error code
676  **/
677 
679 {
680  uint_t i;
681  uint_t k;
682  uint8_t *p;
683  uint32_t hashTable[2];
684  MacFilterEntry *entry;
685 
686  //Debug message
687  TRACE_DEBUG("Updating MAC filter...\r\n");
688 
689  //Set the MAC address of the station
690  AVR32_MACB.sa1b = interface->macAddr.b[0] |
691  (interface->macAddr.b[1] << 8) |
692  (interface->macAddr.b[2] << 16) |
693  (interface->macAddr.b[3] << 24);
694 
695  AVR32_MACB.sa1t = interface->macAddr.b[4] |
696  (interface->macAddr.b[5] << 8);
697 
698  //Clear hash table
699  hashTable[0] = 0;
700  hashTable[1] = 0;
701 
702  //The MAC address filter contains the list of MAC addresses to accept
703  //when receiving an Ethernet frame
704  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
705  {
706  //Point to the current entry
707  entry = &interface->macAddrFilter[i];
708 
709  //Valid entry?
710  if(entry->refCount > 0)
711  {
712  //Point to the MAC address
713  p = entry->addr.b;
714 
715  //Apply the hash function
716  k = (p[0] >> 6) ^ p[0];
717  k ^= (p[1] >> 4) ^ (p[1] << 2);
718  k ^= (p[2] >> 2) ^ (p[2] << 4);
719  k ^= (p[3] >> 6) ^ p[3];
720  k ^= (p[4] >> 4) ^ (p[4] << 2);
721  k ^= (p[5] >> 2) ^ (p[5] << 4);
722 
723  //The hash value is reduced to a 6-bit index
724  k &= 0x3F;
725 
726  //Update hash table contents
727  hashTable[k / 32] |= (1 << (k % 32));
728  }
729  }
730 
731  //Write the hash table
732  AVR32_MACB.hrb = hashTable[0];
733  AVR32_MACB.hrt = hashTable[1];
734 
735  //Debug message
736  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", AVR32_MACB.hrb);
737  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", AVR32_MACB.hrt);
738 
739  //Successful processing
740  return NO_ERROR;
741 }
742 
743 
744 /**
745  * @brief Adjust MAC configuration parameters for proper operation
746  * @param[in] interface Underlying network interface
747  * @return Error code
748  **/
749 
751 {
752  uint32_t config;
753 
754  //Read network configuration register
755  config = AVR32_MACB.ncfgr;
756 
757  //10BASE-T or 100BASE-TX operation mode?
758  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
759  {
760  config |= AVR32_MACB_NCFGR_SPD_MASK;
761  }
762  else
763  {
764  config &= ~AVR32_MACB_NCFGR_SPD_MASK;
765  }
766 
767  //Half-duplex or full-duplex mode?
768  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
769  {
770  config |= AVR32_MACB_NCFGR_FD_MASK;
771  }
772  else
773  {
774  config &= ~AVR32_MACB_NCFGR_FD_MASK;
775  }
776 
777  //Write configuration value back to NCFGR register
778  AVR32_MACB.ncfgr = config;
779 
780  //Successful processing
781  return NO_ERROR;
782 }
783 
784 
785 /**
786  * @brief Write PHY register
787  * @param[in] opcode Access type (2 bits)
788  * @param[in] phyAddr PHY address (5 bits)
789  * @param[in] regAddr Register address (5 bits)
790  * @param[in] data Register value
791  **/
792 
793 void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
794  uint8_t regAddr, uint16_t data)
795 {
796  uint32_t temp;
797 
798  //Valid opcode?
799  if(opcode == SMI_OPCODE_WRITE)
800  {
801  //Set up a write operation
803  //PHY address
804  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
805  //Register address
806  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
807  //Register value
808  temp |= data & AVR32_MACB_MAN_DATA_MASK;
809 
810  //Start a write operation
811  AVR32_MACB.man = temp;
812  //Wait for the write to complete
813  while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
814  {
815  }
816  }
817  else
818  {
819  //The MAC peripheral only supports standard Clause 22 opcodes
820  }
821 }
822 
823 
824 /**
825  * @brief Read PHY register
826  * @param[in] opcode Access type (2 bits)
827  * @param[in] phyAddr PHY address (5 bits)
828  * @param[in] regAddr Register address (5 bits)
829  * @return Register value
830  **/
831 
832 uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
833  uint8_t regAddr)
834 {
835  uint16_t data;
836  uint32_t temp;
837 
838  //Valid opcode?
839  if(opcode == SMI_OPCODE_READ)
840  {
841  //Set up a read operation
843  //PHY address
844  temp |= (phyAddr << AVR32_MACB_MAN_PHYA_OFFSET) & AVR32_MACB_MAN_PHYA_MASK;
845  //Register address
846  temp |= (regAddr << AVR32_MACB_MAN_REGA_OFFSET) & AVR32_MACB_MAN_REGA_MASK;
847 
848  //Start a read operation
849  AVR32_MACB.man = temp;
850  //Wait for the read to complete
851  while((AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK) == 0)
852  {
853  }
854 
855  //Get register value
856  data = AVR32_MACB.man & AVR32_MACB_MAN_DATA_MASK;
857  }
858  else
859  {
860  //The MAC peripheral only supports standard Clause 22 opcodes
861  data = 0;
862  }
863 
864  //Return the value of the PHY register
865  return data;
866 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
__weak_func void avr32EthInitGpio(NetInterface *interface)
GPIO configuration.
void avr32EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint8_t opcode
Definition: dns_common.h:186
int bool_t
Definition: compiler_port.h:53
#define AVR32_ETH_TX_BUFFER_COUNT
#define MACB_RMII_MASK
#define netEvent
Definition: net_legacy.h:196
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
#define AVR32_ETH_RX_BUFFER_COUNT
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
#define MACB_TX_LENGTH
#define MACB_MAN_SOF_01
uint8_t p
Definition: ndp.h:298
void avr32EthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
#define TRUE
Definition: os_port.h:52
uint8_t data[]
Definition: ethernet.h:220
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
uint_t avr32EthReceivePacket(NetInterface *interface)
Receive a packet.
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:260
bool_t avr32EthIrqHandler(void)
AVR32 Ethernet MAC interrupt service routine.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define osExitIsr(flag)
#define MACB_RX_LENGTH
#define SMI_OPCODE_WRITE
Definition: nic.h:66
AVR32 Ethernet MAC driver.
#define MACB_RX_WRAP
#define MACB_RX_SOF
#define AVR32_ETH_IRQ_PRIORITY
Transmit buffer descriptor.
#define FALSE
Definition: os_port.h:48
#define osMemcpy(dest, src, length)
Definition: os_port.h:143
#define MACB_RX_OWNERSHIP
error_t
Error codes.
Definition: error.h:43
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:100
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
Receive buffer descriptor.
#define txBuffer
error_t avr32EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
MacAddr addr
MAC address.
Definition: ethernet.h:259
#define MACB_RX_EOF
@ ERROR_INVALID_LENGTH
Definition: error.h:111
void avr32EthEnableIrq(NetInterface *interface)
Enable interrupts.
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
void avr32EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define NetTxAncillary
Definition: net_misc.h:36
#define SMI_OPCODE_READ
Definition: nic.h:67
#define TRACE_INFO(...)
Definition: debug.h:95
#define AVR32_ETH_TX_BUFFER_SIZE
uint8_t length
Definition: tcp.h:366
#define MACB_MAN_CODE_10
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void avr32EthEventHandler(NetInterface *interface)
AVR32 Ethernet MAC event handler.
error_t avr32EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define MIN(a, b)
Definition: os_port.h:65
#define rxBuffer
void avr32EthTick(NetInterface *interface)
AVR32 Ethernet MAC timer handler.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define MACB_TX_WRAP
uint16_t regAddr
#define MACB_RX_ADDRESS
#define ETH_MTU
Definition: ethernet.h:116
uint8_t n
MAC filter table entry.
Definition: ethernet.h:258
Ipv6Addr address[]
Definition: ipv6.h:314
#define osEnterIsr()
uint16_t avr32EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define MACB_MAN_RW_01
#define MACB_TX_LAST
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define MACB_MAN_RW_10
error_t avr32EthInit(NetInterface *interface)
AVR32 Ethernet MAC initialization.
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define AVR32_ETH_RX_BUFFER_SIZE
const NicDriver avr32EthDriver
AVR32 Ethernet MAC driver.
void avr32EthIrqWrapper(void)
error_t avr32EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
unsigned int uint_t
Definition: compiler_port.h:50
TCP/IP stack core.
NIC driver.
Definition: nic.h:283
@ NO_ERROR
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define MACB_TX_USED
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83