rm57_eth_driver.h
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1 /**
2  * @file rm57_eth_driver.h
3  * @brief RM57 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _RM57_ETH_DRIVER_H
32 #define _RM57_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef RM57_ETH_TX_BUFFER_COUNT
39  #define RM57_ETH_TX_BUFFER_COUNT 8
40 #elif (RM57_ETH_TX_BUFFER_COUNT < 1)
41  #error RM57_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef RM57_ETH_TX_BUFFER_SIZE
46  #define RM57_ETH_TX_BUFFER_SIZE 1536
47 #elif (RM57_ETH_TX_BUFFER_SIZE != 1536)
48  #error RM57_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef RM57_ETH_RX_BUFFER_COUNT
53  #define RM57_ETH_RX_BUFFER_COUNT 8
54 #elif (RM57_ETH_RX_BUFFER_COUNT < 1)
55  #error RM57_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef RM57_ETH_RX_BUFFER_SIZE
60  #define RM57_ETH_RX_BUFFER_SIZE 1536
61 #elif (RM57_ETH_RX_BUFFER_SIZE != 1536)
62  #error RM57_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Channel number for the TX interrupt
66 #ifndef RM57_ETH_TX_IRQ_CHANNEL
67  #define RM57_ETH_TX_IRQ_CHANNEL 77
68 #elif (RM57_ETH_TX_IRQ_CHANNEL < 0 || RM57_ETH_TX_IRQ_CHANNEL > 95)
69  #error RM57_ETH_TX_IRQ_CHANNEL parameter is not valid
70 #endif
71 
72 //Channel number for the RX interrupt
73 #ifndef RM57_ETH_RX_IRQ_CHANNEL
74  #define RM57_ETH_RX_IRQ_CHANNEL 79
75 #elif (RM57_ETH_RX_IRQ_CHANNEL < 0 || RM57_ETH_RX_IRQ_CHANNEL > 95)
76  #error RM57_ETH_RX_IRQ_CHANNEL parameter is not valid
77 #endif
78 
79 //Name of the section where to place DMA buffers
80 #ifndef RM57_ETH_RAM_SECTION
81  #define RM57_ETH_RAM_SECTION ".ram_no_cache"
82 #endif
83 
84 //Name of the section where to place DMA descriptors
85 #ifndef RM57_ETH_RAM_CPPI_SECTION
86  #define RM57_ETH_RAM_CPPI_SECTION ".ram_cppi"
87 #endif
88 
89 //EMAC cores
90 #define EMAC_CORE0 0
91 #define EMAC_CORE1 1
92 #define EMAC_CORE2 2
93 
94 //EMAC channels
95 #define EMAC_CH0 0
96 #define EMAC_CH1 1
97 #define EMAC_CH2 2
98 #define EMAC_CH3 3
99 #define EMAC_CH4 4
100 #define EMAC_CH5 5
101 #define EMAC_CH6 6
102 #define EMAC_CH7 7
103 
104 //SYSCFG0 registers
105 #define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
106 #define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
107 
108 //EMAC registers
109 #define EMAC_TXREVID_R HWREG(EMAC_BASE + EMAC_TXREVID)
110 #define EMAC_TXCONTROL_R HWREG(EMAC_BASE + EMAC_TXCONTROL)
111 #define EMAC_TXTEARDOWN_R HWREG(EMAC_BASE + EMAC_TXTEARDOWN)
112 #define EMAC_RXREVID_R HWREG(EMAC_BASE + EMAC_RXREVID)
113 #define EMAC_RXCONTROL_R HWREG(EMAC_BASE + EMAC_RXCONTROL)
114 #define EMAC_RXTEARDOWN_R HWREG(EMAC_BASE + EMAC_RXTEARDOWN)
115 #define EMAC_TXINTSTATRAW_R HWREG(EMAC_BASE + EMAC_TXINTSTATRAW)
116 #define EMAC_TXINTSTATMASKED_R HWREG(EMAC_BASE + EMAC_TXINTSTATMASKED)
117 #define EMAC_TXINTMASKSET_R HWREG(EMAC_BASE + EMAC_TXINTMASKSET)
118 #define EMAC_TXINTMASKCLEAR_R HWREG(EMAC_BASE + EMAC_TXINTMASKCLEAR)
119 #define EMAC_MACINVECTOR_R HWREG(EMAC_BASE + EMAC_MACINVECTOR)
120 #define EMAC_MACEOIVECTOR_R HWREG(EMAC_BASE + EMAC_MACEOIVECTOR)
121 #define EMAC_RXINTSTATRAW_R HWREG(EMAC_BASE + EMAC_RXINTSTATRAW)
122 #define EMAC_RXINTSTATMASKED_R HWREG(EMAC_BASE + EMAC_RXINTSTATMASKED)
123 #define EMAC_RXINTMASKSET_R HWREG(EMAC_BASE + EMAC_RXINTMASKSET)
124 #define EMAC_RXINTMASKCLEAR_R HWREG(EMAC_BASE + EMAC_RXINTMASKCLEAR)
125 #define EMAC_MACINTSTATRAW_R HWREG(EMAC_BASE + EMAC_MACINTSTATRAW)
126 #define EMAC_MACINTSTATMASKED_R HWREG(EMAC_BASE + EMAC_MACINTSTATMASKED)
127 #define EMAC_MACINTMASKSET_R HWREG(EMAC_BASE + EMAC_MACINTMASKSET)
128 #define EMAC_MACINTMASKCLEAR_R HWREG(EMAC_BASE + EMAC_MACINTMASKCLEAR)
129 #define EMAC_RXMBPENABLE_R HWREG(EMAC_BASE + EMAC_RXMBPENABLE)
130 #define EMAC_RXUNICASTSET_R HWREG(EMAC_BASE + EMAC_RXUNICASTSET)
131 #define EMAC_RXUNICASTCLEAR_R HWREG(EMAC_BASE + EMAC_RXUNICASTCLEAR)
132 #define EMAC_RXMAXLEN_R HWREG(EMAC_BASE + EMAC_RXMAXLEN)
133 #define EMAC_RXBUFFEROFFSET_R HWREG(EMAC_BASE + EMAC_RXBUFFEROFFSET)
134 #define EMAC_RXFILTERLOWTHRESH_R HWREG(EMAC_BASE + EMAC_RXFILTERLOWTHRESH)
135 #define EMAC_RXFLOWTHRESH_R(n) HWREG(EMAC_BASE + EMAC_RXFLOWTHRESH(n))
136 #define EMAC_RXFREEBUFFER_R(n) HWREG(EMAC_BASE + EMAC_RXFREEBUFFER(n))
137 #define EMAC_MACCONTROL_R HWREG(EMAC_BASE + EMAC_MACCONTROL)
138 #define EMAC_MACSTATUS_R HWREG(EMAC_BASE + EMAC_MACSTATUS)
139 #define EMAC_EMCONTROL_R HWREG(EMAC_BASE + EMAC_EMCONTROL)
140 #define EMAC_FIFOCONTROL_R HWREG(EMAC_BASE + EMAC_FIFOCONTROL)
141 #define EMAC_MACCONFIG_R HWREG(EMAC_BASE + EMAC_MACCONFIG)
142 #define EMAC_SOFTRESET_R HWREG(EMAC_BASE + EMAC_SOFTRESET)
143 #define EMAC_MACSRCADDRLO_R HWREG(EMAC_BASE + EMAC_MACSRCADDRLO)
144 #define EMAC_MACSRCADDRHI_R HWREG(EMAC_BASE + EMAC_MACSRCADDRHI)
145 #define EMAC_MACHASH1_R HWREG(EMAC_BASE + EMAC_MACHASH1)
146 #define EMAC_MACHASH2_R HWREG(EMAC_BASE + EMAC_MACHASH2)
147 #define EMAC_BOFFTEST_R HWREG(EMAC_BASE + EMAC_BOFFTEST)
148 #define EMAC_TPACETEST_R HWREG(EMAC_BASE + EMAC_TPACETEST)
149 #define EMAC_RXPAUSE_R HWREG(EMAC_BASE + EMAC_RXPAUSE)
150 #define EMAC_TXPAUSE_R HWREG(EMAC_BASE + EMAC_TXPAUSE)
151 #define EMAC_RXGOODFRAMES_R HWREG(EMAC_BASE + EMAC_RXGOODFRAMES)
152 #define EMAC_RXBCASTFRAMES_R HWREG(EMAC_BASE + EMAC_RXBCASTFRAMES)
153 #define EMAC_RXMCASTFRAMES_R HWREG(EMAC_BASE + EMAC_RXMCASTFRAMES)
154 #define EMAC_RXPAUSEFRAMES_R HWREG(EMAC_BASE + EMAC_RXPAUSEFRAMES)
155 #define EMAC_RXCRCERRORS_R HWREG(EMAC_BASE + EMAC_RXCRCERRORS)
156 #define EMAC_RXALIGNCODEERRORS_R HWREG(EMAC_BASE + EMACEMAC_RXOVERSIZED)
157 #define EMAC_RXJABBER_R HWREG(EMAC_BASE + EMAC_RXJABBER)
158 #define EMAC_RXUNDERSIZED_R HWREG(EMAC_BASE + EMAC_RXUNDERSIZED)
159 #define EMAC_RXFRAGMENTS_R HWREG(EMAC_BASE + EMAC_RXFRAGMENTS)
160 #define EMAC_RXFILTERED_R HWREG(EMAC_BASE + EMAC_RXFILTERED)
161 #define EMAC_RXQOSFILTERED_R HWREG(EMAC_BASE + EMAC_RXQOSFILTERED)
162 #define EMAC_RXOCTETS_R HWREG(EMAC_BASE + EMAC_RXOCTETS)
163 #define EMAC_TXGOODFRAMES_R HWREG(EMAC_BASE + EMAC_TXGOODFRAMES)
164 #define EMAC_TXBCASTFRAMES_R HWREG(EMAC_BASE + EMAC_TXBCASTFRAMES)
165 #define EMAC_TXMCASTFRAMES_R HWREG(EMAC_BASE + EMAC_TXMCASTFRAMES)
166 #define EMAC_TXPAUSEFRAMES_R HWREG(EMAC_BASE + EMAC_TXPAUSEFRAMES)
167 #define EMAC_TXDEFERRED_R HWREG(EMAC_BASE + EMAC_TXDEFERRED)
168 #define EMAC_TXCOLLISION_R HWREG(EMAC_BASE + EMAC_TXCOLLISION)
169 #define EMAC_TXSINGLECOLL_R HWREG(EMAC_BASE + EMAC_TXSINGLECOLL)
170 #define EMAC_TXMULTICOLL_R HWREG(EMAC_BASE + EMAC_TXMULTICOLL)
171 #define EMAC_TXEXCESSIVECOLL_R HWREG(EMAC_BASE + EMAC_TXEXCESSIVECOLL)
172 #define EMAC_TXLATECOLL_R HWREG(EMAC_BASE + EMAC_TXLATECOLL)
173 #define EMAC_TXUNDERRUN_R HWREG(EMAC_BASE + EMAC_TXUNDERRUN)
174 #define EMAC_TXCARRIERSENSE_R HWREG(EMAC_BASE + EMAC_TXCARRIERSENSE)
175 #define EMAC_TXOCTETS_R HWREG(EMAC_BASE + EMAC_TXOCTETS)
176 #define EMAC_FRAME64_R HWREG(EMAC_BASE + EMAC_FRAME64)
177 #define EMAC_FRAME65T127_R HWREG(EMAC_BASE + EMAC_FRAME65T127)
178 #define EMAC_FRAME128T255_R HWREG(EMAC_BASE + EMAC_FRAME128T255)
179 #define EMAC_FRAME256T511_R HWREG(EMAC_BASE + EMAC_FRAME256T511)
180 #define EMAC_FRAME512T1023_R HWREG(EMAC_BASE + EMAC_FRAME512T1023)
181 #define EMAC_FRAME1024TUP_R HWREG(EMAC_BASE + EMAC_FRAME1024TUP)
182 #define EMAC_NETOCTETS_R HWREG(EMAC_BASE + EMAC_NETOCTETS)
183 #define EMAC_RXSOFOVERRUNS_R HWREG(EMAC_BASE + EMAC_RXSOFOVERRUNS)
184 #define EMAC_RXMOFOVERRUNS_R HWREG(EMAC_BASE + EMAC_RXMOFOVERRUNS)
185 #define EMAC_RXDMAOVERRUNS_R HWREG(EMAC_BASE + EMAC_RXDMAOVERRUNS)
186 #define EMAC_MACADDRLO_R HWREG(EMAC_BASE + EMAC_MACADDRLO)
187 #define EMAC_MACADDRHI_R HWREG(EMAC_BASE + EMAC_MACADDRHI)
188 #define EMAC_MACINDEX_R HWREG(EMAC_BASE + EMAC_MACINDEX)
189 #define EMAC_TXHDP_R(n) HWREG(EMAC_BASE + EMAC_TXHDP(n))
190 #define EMAC_RXHDP_R(n) HWREG(EMAC_BASE + EMAC_RXHDP(n))
191 #define EMAC_TXCP_R(n) HWREG(EMAC_BASE + EMAC_TXCP(n))
192 #define EMAC_RXCP_R(n) HWREG(EMAC_BASE + EMAC_RXCP(n))
193 
194 //EMAC control registers
195 #define EMAC_CTRL_REVID_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_REVID)
196 #define EMAC_CTRL_SOFTRESET_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_SOFTRESET)
197 #define EMAC_CTRL_INTCONTRO_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_INTCONTROL)
198 #define EMAC_CTRL_C0RXTHRESHEN_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0RXTHRESHEN)
199 #define EMAC_CTRL_CnRXEN_R(n) HWREG(EMAC_CTRL_BASE + EMAC_CTRL_CnRXEN(n))
200 #define EMAC_CTRL_CnTXEN_R(n) HWREG(EMAC_CTRL_BASE + EMAC_CTRL_CnTXEN(n))
201 #define EMAC_CTRL_CnMISCEN_R(n) HWREG(EMAC_CTRL_BASE + EMAC_CTRL_CnMISCEN(n))
202 #define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(EMAC_CTRL_BASE + EMAC_CTRL_CnRXTHRESHEN(n))
203 #define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0RXTHRESHSTAT)
204 #define EMAC_CTRL_C0RXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0RXSTAT)
205 #define EMAC_CTRL_C0TXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0TXSTAT)
206 #define EMAC_CTRL_C0MISCSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0MISCSTAT)
207 #define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1RXTHRESHSTAT)
208 #define EMAC_CTRL_C1RXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1RXTHRESHSTAT)
209 #define EMAC_CTRL_C1TXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1TXSTAT)
210 #define EMAC_CTRL_C1MISCSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1MISCSTAT)
211 #define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2RXTHRESHSTAT)
212 #define EMAC_CTRL_C2RXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2RXSTAT)
213 #define EMAC_CTRL_C2TXSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2TXSTAT)
214 #define EMAC_CTRL_C2MISCSTAT_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2MISCSTAT)
215 #define EMAC_CTRL_C0RXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0RXIMAX)
216 #define EMAC_CTRL_C0TXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C0TXIMAX)
217 #define EMAC_CTRL_C1RXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1RXIMAX)
218 #define EMAC_CTRL_C1TXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C1TXIMAX)
219 #define EMAC_CTRL_C2RXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2RXIMAX)
220 #define EMAC_CTRL_C2TXIMAX_R HWREG(EMAC_CTRL_BASE + EMAC_CTRL_C2TXIMAX)
221 
222 //MDIO registers
223 #define MDIO_REVID_R HWREG(MDIO_BASE + MDIO_REVID)
224 #define MDIO_CONTROL_R HWREG(MDIO_BASE + MDIO_CONTROL)
225 #define MDIO_ALIVE_R HWREG(MDIO_BASE + MDIO_ALIVE)
226 #define MDIO_LINK_R HWREG(MDIO_BASE + MDIO_LINK)
227 #define MDIO_LINKINTRAW_R HWREG(MDIO_BASE + MDIO_LINKINTRAW)
228 #define MDIO_LINKINTMASKED_R HWREG(MDIO_BASE + MDIO_LINKINTMASKED)
229 #define MDIO_USERINTRAW_R HWREG(MDIO_BASE + MDIO_USERINTRAW)
230 #define MDIO_USERINTMASKED_R HWREG(MDIO_BASE + MDIO_USERINTMASKED)
231 #define MDIO_USERINTMASKSET_R HWREG(MDIO_BASE + MDIO_USERINTMASKSET)
232 #define MDIO_USERINTMASKCLEAR_R HWREG(MDIO_BASE + MDIO_USERINTMASKCLEAR)
233 #define MDIO_USERACCESS0_R HWREG(MDIO_BASE + MDIO_USERACCESS0)
234 #define MDIO_USERPHYSEL0_R HWREG(MDIO_BASE + MDIO_USERPHYSEL0)
235 #define MDIO_USERACCESS1_R HWREG(MDIO_BASE + MDIO_USERACCESS1)
236 #define MDIO_USERPHYSEL1_R HWREG(MDIO_BASE + MDIO_USERPHYSEL1)
237 
238 //MACEOIVECTOR register
239 #define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
240 #define EMAC_MACEOIVECTOR_C0RX 0x00000001
241 #define EMAC_MACEOIVECTOR_C0TX 0x00000002
242 #define EMAC_MACEOIVECTOR_C0MISC 0x00000003
243 #define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
244 #define EMAC_MACEOIVECTOR_C1RX 0x00000005
245 #define EMAC_MACEOIVECTOR_C1TX 0x00000006
246 #define EMAC_MACEOIVECTOR_C1MISC 0x00000007
247 #define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
248 #define EMAC_MACEOIVECTOR_C2RX 0x00000009
249 #define EMAC_MACEOIVECTOR_C2TX 0x0000000A
250 #define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
251 
252 //TX buffer descriptor flags
253 #define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
254 #define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
255 #define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
256 #define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
257 #define EMAC_TX_WORD3_SOP 0x80000000
258 #define EMAC_TX_WORD3_EOP 0x40000000
259 #define EMAC_TX_WORD3_OWNER 0x20000000
260 #define EMAC_TX_WORD3_EOQ 0x10000000
261 #define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
262 #define EMAC_TX_WORD3_PASSCRC 0x04000000
263 #define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
264 
265 //RX buffer descriptor flags
266 #define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
267 #define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
268 #define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
269 #define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
270 #define EMAC_RX_WORD3_SOP 0x80000000
271 #define EMAC_RX_WORD3_EOP 0x40000000
272 #define EMAC_RX_WORD3_OWNER 0x20000000
273 #define EMAC_RX_WORD3_EOQ 0x10000000
274 #define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
275 #define EMAC_RX_WORD3_PASSCRC 0x04000000
276 #define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
277 #define EMAC_RX_WORD3_JABBER 0x02000000
278 #define EMAC_RX_WORD3_OVERSIZE 0x01000000
279 #define EMAC_RX_WORD3_FRAGMENT 0x00800000
280 #define EMAC_RX_WORD3_UNDERSIZED 0x00400000
281 #define EMAC_RX_WORD3_CONTROL 0x00200000
282 #define EMAC_RX_WORD3_OVERRUN 0x00100000
283 #define EMAC_RX_WORD3_CODEERROR 0x00080000
284 #define EMAC_RX_WORD3_ALIGNERROR 0x00040000
285 #define EMAC_RX_WORD3_CRCERROR 0x00020000
286 #define EMAC_RX_WORD3_NOMATCH 0x00010000
287 #define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
288 
289 //C++ guard
290 #ifdef __cplusplus
291 extern "C" {
292 #endif
293 
294 
295 /**
296  * @brief TX buffer descriptor
297  **/
298 
299 typedef struct _Rm57TxBufferDesc
300 {
301  uint32_t word0;
302  uint32_t word1;
303  uint32_t word2;
304  uint32_t word3;
308 
309 
310 /**
311  * @brief RX buffer descriptor
312  **/
313 
314 typedef struct _Rm57RxBufferDesc
315 {
316  uint32_t word0;
317  uint32_t word1;
318  uint32_t word2;
319  uint32_t word3;
323 
324 
325 //AM335x Ethernet MAC driver
326 extern const NicDriver rm57EthDriver;
327 
328 //AM335x Ethernet MAC related functions
329 error_t rm57EthInit(NetInterface *interface);
330 void rm57EthInitGpio(NetInterface *interface);
331 void rm57EthInitBufferDesc(NetInterface *interface);
332 
333 void rm57EthTick(NetInterface *interface);
334 
335 void rm57EthEnableIrq(NetInterface *interface);
336 void rm57EthDisableIrq(NetInterface *interface);
337 
338 #if defined(__ICCARM__)
339  __irq __arm void rm57EthTxIrqHandler(void);
340  __irq __arm void rm57EthRxIrqHandler(void);
341 #else
342  void rm57EthTxIrqHandler(void);
343  void rm57EthRxIrqHandler(void);
344 #endif
345 
346 void rm57EthEventHandler(NetInterface *interface);
347 
349  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
350 
352 
355 
356 void rm57EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
357  uint8_t regAddr, uint16_t data);
358 
359 uint16_t rm57EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
360  uint8_t regAddr);
361 
362 //C++ guard
363 #ifdef __cplusplus
364 }
365 #endif
366 
367 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
void rm57EthTxIrqHandler(void)
Ethernet MAC transmit interrupt.
void rm57EthTick(NetInterface *interface)
RM57 Ethernet MAC timer handler.
const NicDriver rm57EthDriver
RM57 Ethernet MAC driver.
void rm57EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptor lists.
void rm57EthEnableIrq(NetInterface *interface)
Enable interrupts.
struct _Rm57RxBufferDesc Rm57RxBufferDesc
RX buffer descriptor.
void rm57EthEventHandler(NetInterface *interface)
RM57 Ethernet MAC event handler.
error_t rm57EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t rm57EthReceivePacket(NetInterface *interface)
Receive a packet.
struct _Rm57TxBufferDesc Rm57TxBufferDesc
TX buffer descriptor.
error_t rm57EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void rm57EthInitGpio(NetInterface *interface)
GPIO configuration.
void rm57EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t rm57EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void rm57EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t rm57EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t rm57EthInit(NetInterface *interface)
RM57 Ethernet MAC initialization.
void rm57EthRxIrqHandler(void)
Ethernet MAC receive interrupt.
RX buffer descriptor.
struct _Rm57RxBufferDesc * next
struct _Rm57RxBufferDesc * prev
TX buffer descriptor.
struct _Rm57TxBufferDesc * next
struct _Rm57TxBufferDesc * prev
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283