s7g2_eth2_driver.h
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1 /**
2  * @file s7g2_eth2_driver.h
3  * @brief Renesas Synergy S7G2 Ethernet MAC driver (ETHERC1 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _S7G2_ETH2_DRIVER_H
32 #define _S7G2_ETH2_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef S7G2_ETH2_TX_BUFFER_COUNT
39  #define S7G2_ETH2_TX_BUFFER_COUNT 3
40 #elif (S7G2_ETH2_TX_BUFFER_COUNT < 1)
41  #error S7G2_ETH2_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef S7G2_ETH2_TX_BUFFER_SIZE
46  #define S7G2_ETH2_TX_BUFFER_SIZE 1536
47 #elif (S7G2_ETH2_TX_BUFFER_SIZE != 1536)
48  #error S7G2_ETH2_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef S7G2_ETH2_RX_BUFFER_COUNT
53  #define S7G2_ETH2_RX_BUFFER_COUNT 6
54 #elif (S7G2_ETH2_RX_BUFFER_COUNT < 1)
55  #error S7G2_ETH2_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef S7G2_ETH2_RX_BUFFER_SIZE
60  #define S7G2_ETH2_RX_BUFFER_SIZE 1536
61 #elif (S7G2_ETH2_RX_BUFFER_SIZE != 1536)
62  #error S7G2_ETH2_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef S7G2_ETH2_IRQ_PRIORITY_GROUPING
67  #define S7G2_ETH2_IRQ_PRIORITY_GROUPING 3
68 #elif (S7G2_ETH2_IRQ_PRIORITY_GROUPING < 0)
69  #error S7G2_ETH2_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef S7G2_ETH2_IRQ_GROUP_PRIORITY
74  #define S7G2_ETH2_IRQ_GROUP_PRIORITY 12
75 #elif (S7G2_ETH2_IRQ_GROUP_PRIORITY < 0)
76  #error S7G2_ETH2_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef S7G2_ETH2_IRQ_SUB_PRIORITY
81  #define S7G2_ETH2_IRQ_SUB_PRIORITY 0
82 #elif (S7G2_ETH2_IRQ_SUB_PRIORITY < 0)
83  #error S7G2_ETH2_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //ECMR register
87 #define ETHERC_ECMR_TPC 0x00100000
88 #define ETHERC_ECMR_ZPF 0x00080000
89 #define ETHERC_ECMR_PFR 0x00040000
90 #define ETHERC_ECMR_RXF 0x00020000
91 #define ETHERC_ECMR_TXF 0x00010000
92 #define ETHERC_ECMR_PRCEF 0x00001000
93 #define ETHERC_ECMR_MPDE 0x00000200
94 #define ETHERC_ECMR_RE 0x00000040
95 #define ETHERC_ECMR_TE 0x00000020
96 #define ETHERC_ECMR_ILB 0x00000008
97 #define ETHERC_ECMR_RTM 0x00000004
98 #define ETHERC_ECMR_DM 0x00000002
99 #define ETHERC_ECMR_PRM 0x00000001
100 
101 //PIR register
102 #define ETHERC_PIR_MDI 0x00000008
103 #define ETHERC_PIR_MDO 0x00000004
104 #define ETHERC_PIR_MMD 0x00000002
105 #define ETHERC_PIR_MDC 0x00000001
106 
107 //EDMR register
108 #define EDMAC_EDMR_DE 0x00000040
109 #define EDMAC_EDMR_DL 0x00000030
110 #define EDMAC_EDMR_DL_16 0x00000000
111 #define EDMAC_EDMR_DL_32 0x00000010
112 #define EDMAC_EDMR_DL_64 0x00000020
113 #define EDMAC_EDMR_SWR 0x00000001
114 
115 //EDTRR register
116 #define EDMAC_EDTRR_TR 0x00000001
117 
118 //EDRRR register
119 #define EDMAC_EDRRR_RR 0x00000001
120 
121 //EESR register
122 #define EDMAC_EESR_TWB 0x40000000
123 #define EDMAC_EESR_TABT 0x04000000
124 #define EDMAC_EESR_RABT 0x02000000
125 #define EDMAC_EESR_RFCOF 0x01000000
126 #define EDMAC_EESR_ADE 0x00800000
127 #define EDMAC_EESR_ECI 0x00400000
128 #define EDMAC_EESR_TC 0x00200000
129 #define EDMAC_EESR_TDE 0x00100000
130 #define EDMAC_EESR_TFUF 0x00080000
131 #define EDMAC_EESR_FR 0x00040000
132 #define EDMAC_EESR_RDE 0x00020000
133 #define EDMAC_EESR_RFOF 0x00010000
134 #define EDMAC_EESR_CND 0x00000800
135 #define EDMAC_EESR_DLC 0x00000400
136 #define EDMAC_EESR_CD 0x00000200
137 #define EDMAC_EESR_TRO 0x00000100
138 #define EDMAC_EESR_RMAF 0x00000080
139 #define EDMAC_EESR_RRF 0x00000010
140 #define EDMAC_EESR_RTLF 0x00000008
141 #define EDMAC_EESR_RTSF 0x00000004
142 #define EDMAC_EESR_PRE 0x00000002
143 #define EDMAC_EESR_CERF 0x00000001
144 
145 //EESIPR register
146 #define EDMAC_EESIPR_TWBIP 0x40000000
147 #define EDMAC_EESIPR_TABTIP 0x04000000
148 #define EDMAC_EESIPR_RABTIP 0x02000000
149 #define EDMAC_EESIPR_RFCOFIP 0x01000000
150 #define EDMAC_EESIPR_ADEIP 0x00800000
151 #define EDMAC_EESIPR_ECIIP 0x00400000
152 #define EDMAC_EESIPR_TCIP 0x00200000
153 #define EDMAC_EESIPR_TDEIP 0x00100000
154 #define EDMAC_EESIPR_TFUFIP 0x00080000
155 #define EDMAC_EESIPR_FRIP 0x00040000
156 #define EDMAC_EESIPR_RDEIP 0x00020000
157 #define EDMAC_EESIPR_RFOFIP 0x00010000
158 #define EDMAC_EESIPR_CNDIP 0x00000800
159 #define EDMAC_EESIPR_DLCIP 0x00000400
160 #define EDMAC_EESIPR_CDIP 0x00000200
161 #define EDMAC_EESIPR_TROIP 0x00000100
162 #define EDMAC_EESIPR_RMAFIP 0x00000080
163 #define EDMAC_EESIPR_RRFIP 0x00000010
164 #define EDMAC_EESIPR_RTLFIP 0x00000008
165 #define EDMAC_EESIPR_RTSFIP 0x00000004
166 #define EDMAC_EESIPR_PREIP 0x00000002
167 #define EDMAC_EESIPR_CERFIP 0x00000001
168 
169 //FDR register
170 #define EDMAC_FDR_TFD 0x00001F00
171 #define EDMAC_FDR_TFD_2048 0x00000700
172 #define EDMAC_FDR_RFD 0x0000001F
173 #define EDMAC_FDR_RFD_4096 0x0000000F
174 
175 //RMCR register
176 #define EDMAC_RMCR_RNR 0x00000001
177 
178 //TRIMD register
179 #define EDMAC_TRIMD_TIM 0x00000010
180 #define EDMAC_TRIMD_TIS 0x00000001
181 
182 //Transmit DMA descriptor flags
183 #define EDMAC_TD0_TACT 0x80000000
184 #define EDMAC_TD0_TDLE 0x40000000
185 #define EDMAC_TD0_TFP_SOF 0x20000000
186 #define EDMAC_TD0_TFP_EOF 0x10000000
187 #define EDMAC_TD0_TFE 0x08000000
188 #define EDMAC_TD0_TWBI 0x04000000
189 #define EDMAC_TD0_TFS_MASK 0x0000010F
190 #define EDMAC_TD0_TFS_TABT 0x00000100
191 #define EDMAC_TD0_TFS_CND 0x00000008
192 #define EDMAC_TD0_TFS_DLC 0x00000004
193 #define EDMAC_TD0_TFS_CD 0x00000002
194 #define EDMAC_TD0_TFS_TRO 0x00000001
195 #define EDMAC_TD1_TBL 0xFFFF0000
196 #define EDMAC_TD2_TBA 0xFFFFFFFF
197 
198 //Receive DMA descriptor flags
199 #define EDMAC_RD0_RACT 0x80000000
200 #define EDMAC_RD0_RDLE 0x40000000
201 #define EDMAC_RD0_RFP_SOF 0x20000000
202 #define EDMAC_RD0_RFP_EOF 0x10000000
203 #define EDMAC_RD0_RFE 0x08000000
204 #define EDMAC_RD0_RFS_MASK 0x0000039F
205 #define EDMAC_RD0_RFS_RFOF 0x00000200
206 #define EDMAC_RD0_RFS_RABT 0x00000100
207 #define EDMAC_RD0_RFS_RMAF 0x00000080
208 #define EDMAC_RD0_RFS_RRF 0x00000010
209 #define EDMAC_RD0_RFS_RTLF 0x00000008
210 #define EDMAC_RD0_RFS_RTSF 0x00000004
211 #define EDMAC_RD0_RFS_PRE 0x00000002
212 #define EDMAC_RD0_RFS_CERF 0x00000001
213 #define EDMAC_RD1_RBL 0xFFFF0000
214 #define EDMAC_RD1_RFL 0x0000FFFF
215 #define EDMAC_RD2_RBA 0xFFFFFFFF
216 
217 //C++ guard
218 #ifdef __cplusplus
219 extern "C" {
220 #endif
221 
222 
223 /**
224  * @brief Transmit DMA descriptor
225  **/
226 
227 typedef struct
228 {
229  uint32_t td0;
230  uint32_t td1;
231  uint32_t td2;
232  uint32_t padding;
234 
235 
236 /**
237  * @brief Receive DMA descriptor
238  **/
239 
240 typedef struct
241 {
242  uint32_t rd0;
243  uint32_t rd1;
244  uint32_t rd2;
245  uint32_t padding;
247 
248 
249 //S7G2 Ethernet MAC driver (ETHERC1 instance)
250 extern const NicDriver s7g2Eth2Driver;
251 
252 //S7G2 Ethernet MAC related functions
253 error_t s7g2Eth2Init(NetInterface *interface);
254 void s7g2Eth2InitGpio(NetInterface *interface);
255 void s7g2Eth2InitDmaDesc(NetInterface *interface);
256 
257 void s7g2Eth2Tick(NetInterface *interface);
258 
259 void s7g2Eth2EnableIrq(NetInterface *interface);
260 void s7g2Eth2DisableIrq(NetInterface *interface);
261 void s7g2Eth2EventHandler(NetInterface *interface);
262 
264  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
265 
267 
270 
271 void s7g2Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
272  uint8_t regAddr, uint16_t data);
273 
274 uint16_t s7g2Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
275  uint8_t regAddr);
276 
277 void s7g2Eth2WriteSmi(uint32_t data, uint_t length);
278 uint32_t s7g2Eth2ReadSmi(uint_t length);
279 
280 //C++ guard
281 #ifdef __cplusplus
282 }
283 #endif
284 
285 #endif
unsigned int uint_t
Definition: compiler_port.h:50
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
void s7g2Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint16_t s7g2Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void s7g2Eth2InitGpio(NetInterface *interface)
GPIO configuration.
error_t s7g2Eth2Init(NetInterface *interface)
S7G2 Ethernet MAC initialization.
void s7g2Eth2DisableIrq(NetInterface *interface)
Disable interrupts.
void s7g2Eth2Tick(NetInterface *interface)
S7G2 Ethernet MAC timer handler.
error_t s7g2Eth2ReceivePacket(NetInterface *interface)
Receive a packet.
void s7g2Eth2EventHandler(NetInterface *interface)
S7G2 Ethernet MAC event handler.
void s7g2Eth2WriteSmi(uint32_t data, uint_t length)
SMI write operation.
void s7g2Eth2InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
const NicDriver s7g2Eth2Driver
S7G2 Ethernet MAC driver (ETHERC1 instance)
void s7g2Eth2EnableIrq(NetInterface *interface)
Enable interrupts.
error_t s7g2Eth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t s7g2Eth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t s7g2Eth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint32_t s7g2Eth2ReadSmi(uint_t length)
SMI read operation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive DMA descriptor.
Transmit DMA descriptor.
uint8_t length
Definition: tcp.h:368