stm32mp1xx_eth_driver.h
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1 /**
2  * @file stm32mp1xx_eth_driver.h
3  * @brief STM32MP1 Gigabit Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _STM32MP1XX_ETH_DRIVER_H
32 #define _STM32MP1XX_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef STM32MP1XX_ETH_TX_BUFFER_COUNT
39  #define STM32MP1XX_ETH_TX_BUFFER_COUNT 3
40 #elif (STM32MP1XX_ETH_TX_BUFFER_COUNT < 1)
41  #error STM32MP1XX_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef STM32MP1XX_ETH_TX_BUFFER_SIZE
46  #define STM32MP1XX_ETH_TX_BUFFER_SIZE 1536
47 #elif (STM32MP1XX_ETH_TX_BUFFER_SIZE != 1536)
48  #error STM32MP1XX_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef STM32MP1XX_ETH_RX_BUFFER_COUNT
53  #define STM32MP1XX_ETH_RX_BUFFER_COUNT 6
54 #elif (STM32MP1XX_ETH_RX_BUFFER_COUNT < 1)
55  #error STM32MP1XX_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef STM32MP1XX_ETH_RX_BUFFER_SIZE
60  #define STM32MP1XX_ETH_RX_BUFFER_SIZE 1536
61 #elif (STM32MP1XX_ETH_RX_BUFFER_SIZE != 1536)
62  #error STM32MP1XX_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING
67  #define STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error STM32MP1XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef STM32MP1XX_ETH_IRQ_GROUP_PRIORITY
74  #define STM32MP1XX_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (STM32MP1XX_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error STM32MP1XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef STM32MP1XX_ETH_IRQ_SUB_PRIORITY
81  #define STM32MP1XX_ETH_IRQ_SUB_PRIORITY 0
82 #elif (STM32MP1XX_ETH_IRQ_SUB_PRIORITY < 0)
83  #error STM32MP1XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //ETH_MMCTXIMR register
87 #ifndef ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk
88  #define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk
89 #endif
90 
91 //Register access macros
92 #define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
93 #define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
94 #define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
95 #define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
96 #define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
97 #define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
98 #define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
99 #define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)
100 #define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
101 #define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
102 #define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
103 #define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
104 
105 //Transmit normal descriptor (read format)
106 #define ETH_TDES0_BUF1AP 0xFFFFFFFF
107 #define ETH_TDES1_BUF2AP 0xFFFFFFFF
108 #define ETH_TDES2_IOC 0x80000000
109 #define ETH_TDES2_TTSE 0x40000000
110 #define ETH_TDES2_B2L 0x3FFF0000
111 #define ETH_TDES2_VTIR 0x0000C000
112 #define ETH_TDES2_B1L 0x00003FFF
113 #define ETH_TDES3_OWN 0x80000000
114 #define ETH_TDES3_CTXT 0x40000000
115 #define ETH_TDES3_FD 0x20000000
116 #define ETH_TDES3_LD 0x10000000
117 #define ETH_TDES3_CPC 0x0C000000
118 #define ETH_TDES3_SAIC 0x03800000
119 #define ETH_TDES3_THL 0x00780000
120 #define ETH_TDES3_TSE 0x00040000
121 #define ETH_TDES3_CIC 0x00030000
122 #define ETH_TDES3_FL 0x00007FFF
123 
124 //Transmit normal descriptor (write-back format)
125 #define ETH_TDES0_TTSL 0xFFFFFFFF
126 #define ETH_TDES1_TTSH 0xFFFFFFFF
127 #define ETH_TDES3_OWN 0x80000000
128 #define ETH_TDES3_CTXT 0x40000000
129 #define ETH_TDES3_FD 0x20000000
130 #define ETH_TDES3_LD 0x10000000
131 #define ETH_TDES3_TTSS 0x00020000
132 #define ETH_TDES3_ES 0x00008000
133 #define ETH_TDES3_JT 0x00004000
134 #define ETH_TDES3_FF 0x00002000
135 #define ETH_TDES3_PCE 0x00001000
136 #define ETH_TDES3_LOC 0x00000800
137 #define ETH_TDES3_NC 0x00000400
138 #define ETH_TDES3_LC 0x00000200
139 #define ETH_TDES3_EC 0x00000100
140 #define ETH_TDES3_CC 0x000000F0
141 #define ETH_TDES3_ED 0x00000008
142 #define ETH_TDES3_UF 0x00000004
143 #define ETH_TDES3_DB 0x00000002
144 #define ETH_TDES3_IHE 0x00000001
145 
146 //Transmit context descriptor
147 #define ETH_TDES0_TTSL 0xFFFFFFFF
148 #define ETH_TDES1_TTSH 0xFFFFFFFF
149 #define ETH_TDES2_IVT 0xFFFF0000
150 #define ETH_TDES2_MSS 0x00003FFF
151 #define ETH_TDES3_OWN 0x80000000
152 #define ETH_TDES3_CTXT 0x40000000
153 #define ETH_TDES3_OSTC 0x08000000
154 #define ETH_TDES3_TCMSSV 0x04000000
155 #define ETH_TDES3_CDE 0x00800000
156 #define ETH_TDES3_IVLTV 0x00020000
157 #define ETH_TDES3_VLTV 0x00010000
158 #define ETH_TDES3_VT 0x0000FFFF
159 
160 //Receive normal descriptor (read format)
161 #define ETH_RDES0_BUF1AP 0xFFFFFFFF
162 #define ETH_RDES2_BUF2AP 0xFFFFFFFF
163 #define ETH_RDES3_OWN 0x80000000
164 #define ETH_RDES3_IOC 0x40000000
165 #define ETH_RDES3_BUF2V 0x02000000
166 #define ETH_RDES3_BUF1V 0x01000000
167 
168 //Receive normal descriptor (write-back format)
169 #define ETH_RDES0_IVT 0xFFFF0000
170 #define ETH_RDES0_OVT 0x0000FFFF
171 #define ETH_RDES1_OPC 0xFFFF0000
172 #define ETH_RDES1_TD 0x00008000
173 #define ETH_RDES1_TSA 0x00004000
174 #define ETH_RDES1_PV 0x00002000
175 #define ETH_RDES1_PFT 0x00001000
176 #define ETH_RDES1_PMT 0x00000F00
177 #define ETH_RDES1_IPCE 0x00000080
178 #define ETH_RDES1_IPCB 0x00000040
179 #define ETH_RDES1_IPV6 0x00000020
180 #define ETH_RDES1_IPV4 0x00000010
181 #define ETH_RDES1_IPHE 0x00000008
182 #define ETH_RDES1_PT 0x00000007
183 #define ETH_RDES2_L3L4FM 0xE0000000
184 #define ETH_RDES2_L4FM 0x10000000
185 #define ETH_RDES2_L3FM 0x08000000
186 #define ETH_RDES2_MADRM 0x07F80000
187 #define ETH_RDES2_HF 0x00040000
188 #define ETH_RDES2_DAF 0x00020000
189 #define ETH_RDES2_SAF 0x00010000
190 #define ETH_RDES2_VF 0x00008000
191 #define ETH_RDES2_ARPRN 0x00000400
192 #define ETH_RDES3_OWN 0x80000000
193 #define ETH_RDES3_CTXT 0x40000000
194 #define ETH_RDES3_FD 0x20000000
195 #define ETH_RDES3_LD 0x10000000
196 #define ETH_RDES3_RS2V 0x08000000
197 #define ETH_RDES3_RS1V 0x04000000
198 #define ETH_RDES3_RS0V 0x02000000
199 #define ETH_RDES3_CE 0x01000000
200 #define ETH_RDES3_GP 0x00800000
201 #define ETH_RDES3_RWT 0x00400000
202 #define ETH_RDES3_OE 0x00200000
203 #define ETH_RDES3_RE 0x00100000
204 #define ETH_RDES3_DE 0x00080000
205 #define ETH_RDES3_LT 0x00070000
206 #define ETH_RDES3_ES 0x00008000
207 #define ETH_RDES3_PL 0x00007FFF
208 
209 //Receive context descriptor
210 #define ETH_RDES0_RTSL 0xFFFFFFFF
211 #define ETH_RDES1_RTSH 0xFFFFFFFF
212 #define ETH_RDES3_OWN 0x80000000
213 #define ETH_RDES3_CTXT 0x40000000
214 
215 //C++ guard
216 #ifdef __cplusplus
217 extern "C" {
218 #endif
219 
220 
221 /**
222  * @brief Transmit descriptor
223  **/
224 
225 typedef struct
226 {
227  uint32_t tdes0;
228  uint32_t tdes1;
229  uint32_t tdes2;
230  uint32_t tdes3;
232 
233 
234 /**
235  * @brief Receive descriptor
236  **/
237 
238 typedef struct
239 {
240  uint32_t rdes0;
241  uint32_t rdes1;
242  uint32_t rdes2;
243  uint32_t rdes3;
245 
246 
247 //STM32MP1 Ethernet MAC driver
248 extern const NicDriver stm32mp1xxEthDriver;
249 
250 //STM32MP1 Ethernet MAC related functions
252 void stm32mp1xxEthInitGpio(NetInterface *interface);
253 void stm32mp1xxEthInitDmaDesc(NetInterface *interface);
254 
255 void stm32mp1xxEthTick(NetInterface *interface);
256 
257 void stm32mp1xxEthEnableIrq(NetInterface *interface);
258 void stm32mp1xxEthDisableIrq(NetInterface *interface);
259 void stm32mp1xxEthEventHandler(NetInterface *interface);
260 
262  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
263 
265 
268 
269 void stm32mp1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
270  uint8_t regAddr, uint16_t data);
271 
272 uint16_t stm32mp1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
273  uint8_t regAddr);
274 
275 uint32_t stm32mp1xxEthCalcCrc(const void *data, size_t length);
276 
277 //C++ guard
278 #ifdef __cplusplus
279 }
280 #endif
281 
282 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
void stm32mp1xxEthInitGpio(NetInterface *interface)
GPIO configuration.
void stm32mp1xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t stm32mp1xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t stm32mp1xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t stm32mp1xxEthInit(NetInterface *interface)
STM32MP1 Ethernet MAC initialization.
uint32_t stm32mp1xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
const NicDriver stm32mp1xxEthDriver
STM32MP1 Ethernet MAC driver.
void stm32mp1xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t stm32mp1xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void stm32mp1xxEthTick(NetInterface *interface)
STM32MP1 Ethernet MAC timer handler.
void stm32mp1xxEthEventHandler(NetInterface *interface)
STM32MP1 Ethernet MAC event handler.
uint16_t stm32mp1xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32mp1xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
void stm32mp1xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t stm32mp1xxEthReceivePacket(NetInterface *interface)
Receive a packet.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive descriptor.
Transmit descriptor.
uint8_t length
Definition: tcp.h:368