tm4c129_eth_driver.h
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1 /**
2  * @file tm4c129_eth_driver.h
3  * @brief Tiva TM4C129 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _TM4C129_ETH_DRIVER_H
32 #define _TM4C129_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef TM4C129_ETH_TX_BUFFER_COUNT
39  #define TM4C129_ETH_TX_BUFFER_COUNT 3
40 #elif (TM4C129_ETH_TX_BUFFER_COUNT < 1)
41  #error TM4C129_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef TM4C129_ETH_TX_BUFFER_SIZE
46  #define TM4C129_ETH_TX_BUFFER_SIZE 1536
47 #elif (TM4C129_ETH_TX_BUFFER_SIZE != 1536)
48  #error TM4C129_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef TM4C129_ETH_RX_BUFFER_COUNT
53  #define TM4C129_ETH_RX_BUFFER_COUNT 6
54 #elif (TM4C129_ETH_RX_BUFFER_COUNT < 1)
55  #error TM4C129_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef TM4C129_ETH_RX_BUFFER_SIZE
60  #define TM4C129_ETH_RX_BUFFER_SIZE 1536
61 #elif (TM4C129_ETH_RX_BUFFER_SIZE != 1536)
62  #error TM4C129_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef TM4C129_ETH_IRQ_PRIORITY_GROUPING
67  #define TM4C129_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (TM4C129_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error TM4C129_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt priority
73 #ifndef TM4C129_ETH_IRQ_PRIORITY
74  #define TM4C129_ETH_IRQ_PRIORITY 192
75 #elif (TM4C129_ETH_IRQ_PRIORITY < 0)
76  #error TM4C129_ETH_IRQ_PRIORITY parameter is not valid
77 #endif
78 
79 //TM4C129 Flash registers
80 #ifndef FLASH_CONF_R
81  #define FLASH_CONF_R HWREG(FLASH_CONF)
82 #endif
83 
84 //TM4C129 Ethernet MAC registers
85 #ifndef EMAC0_CFG_R
86  #define EMAC0_CFG_R HWREG(EMAC0_BASE + EMAC_O_CFG)
87  #define EMAC0_FRAMEFLTR_R HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR)
88  #define EMAC0_HASHTBLH_R HWREG(EMAC0_BASE + EMAC_O_HASHTBLH)
89  #define EMAC0_HASHTBLL_R HWREG(EMAC0_BASE + EMAC_O_HASHTBLL)
90  #define EMAC0_MIIADDR_R HWREG(EMAC0_BASE + EMAC_O_MIIADDR)
91  #define EMAC0_MIIDATA_R HWREG(EMAC0_BASE + EMAC_O_MIIDATA)
92  #define EMAC0_FLOWCTL_R HWREG(EMAC0_BASE + EMAC_O_FLOWCTL)
93  #define EMAC0_VLANTG_R HWREG(EMAC0_BASE + EMAC_O_VLANTG)
94  #define EMAC0_STATUS_R HWREG(EMAC0_BASE + EMAC_O_STATUS)
95  #define EMAC0_RWUFF_R HWREG(EMAC0_BASE + EMAC_O_RWUFF)
96  #define EMAC0_PMTCTLSTAT_R HWREG(EMAC0_BASE + EMAC_O_PMTCTLSTAT)
97  #define EMAC0_RIS_R HWREG(EMAC0_BASE + EMAC_O_RIS)
98  #define EMAC0_IM_R HWREG(EMAC0_BASE + EMAC_O_IM)
99  #define EMAC0_ADDR0H_R HWREG(EMAC0_BASE + EMAC_O_ADDR0H)
100  #define EMAC0_ADDR0L_R HWREG(EMAC0_BASE + EMAC_O_ADDR0L)
101  #define EMAC0_ADDR1H_R HWREG(EMAC0_BASE + EMAC_O_ADDR1H)
102  #define EMAC0_ADDR1L_R HWREG(EMAC0_BASE + EMAC_O_ADDR1L)
103  #define EMAC0_ADDR2H_R HWREG(EMAC0_BASE + EMAC_O_ADDR2H)
104  #define EMAC0_ADDR2L_R HWREG(EMAC0_BASE + EMAC_O_ADDR2L)
105  #define EMAC0_ADDR3H_R HWREG(EMAC0_BASE + EMAC_O_ADDR3H)
106  #define EMAC0_ADDR3L_R HWREG(EMAC0_BASE + EMAC_O_ADDR3L)
107  #define EMAC0_WDOGTO_R HWREG(EMAC0_BASE + EMAC_O_WDOGTO)
108  #define EMAC0_MMCCTRL_R HWREG(EMAC0_BASE + EMAC_O_MMCCTRL)
109  #define EMAC0_MMCRXRIS_R HWREG(EMAC0_BASE + EMAC_O_MMCRXRIS)
110  #define EMAC0_MMCTXRIS_R HWREG(EMAC0_BASE + EMAC_O_MMCTXRIS)
111  #define EMAC0_MMCRXIM_R HWREG(EMAC0_BASE + EMAC_O_MMCRXIM)
112  #define EMAC0_MMCTXIM_R HWREG(EMAC0_BASE + EMAC_O_MMCTXIM)
113  #define EMAC0_TXCNTGB_R HWREG(EMAC0_BASE + EMAC_O_TXCNTGB)
114  #define EMAC0_TXCNTSCOL_R HWREG(EMAC0_BASE + EMAC_O_TXCNTSCOL)
115  #define EMAC0_TXCNTMCOL_R HWREG(EMAC0_BASE + EMAC_O_TXCNTMCOL)
116  #define EMAC0_TXOCTCNTG_R HWREG(EMAC0_BASE + EMAC_O_TXOCTCNTG)
117  #define EMAC0_RXCNTGB_R HWREG(EMAC0_BASE + EMAC_O_RXCNTGB)
118  #define EMAC0_RXCNTCRCERR_R HWREG(EMAC0_BASE + EMAC_O_RXCNTCRCERR)
119  #define EMAC0_RXCNTALGNERR_R HWREG(EMAC0_BASE + EMAC_O_RXCNTALGNERR)
120  #define EMAC0_RXCNTGUNI_R HWREG(EMAC0_BASE + EMAC_O_RXCNTGUNI)
121  #define EMAC0_VLNINCREP_R HWREG(EMAC0_BASE + EMAC_O_VLNINCREP)
122  #define EMAC0_VLANHASH_R HWREG(EMAC0_BASE + EMAC_O_VLANHASH)
123  #define EMAC0_TIMSTCTRL_R HWREG(EMAC0_BASE + EMAC_O_TIMSTCTRL)
124  #define EMAC0_SUBSECINC_R HWREG(EMAC0_BASE + EMAC_O_SUBSECINC)
125  #define EMAC0_TIMSEC_R HWREG(EMAC0_BASE + EMAC_O_TIMSEC)
126  #define EMAC0_TIMNANO_R HWREG(EMAC0_BASE + EMAC_O_TIMNANO)
127  #define EMAC0_TIMSECU_R HWREG(EMAC0_BASE + EMAC_O_TIMSECU)
128  #define EMAC0_TIMNANOU_R HWREG(EMAC0_BASE + EMAC_O_TIMNANOU)
129  #define EMAC0_TIMADD_R HWREG(EMAC0_BASE + EMAC_O_TIMADD)
130  #define EMAC0_TARGSEC_R HWREG(EMAC0_BASE + EMAC_O_TARGSEC)
131  #define EMAC0_TARGNANO_R HWREG(EMAC0_BASE + EMAC_O_TARGNANO)
132  #define EMAC0_HWORDSEC_R HWREG(EMAC0_BASE + EMAC_O_HWORDSEC)
133  #define EMAC0_TIMSTAT_R HWREG(EMAC0_BASE + EMAC_O_TIMSTAT)
134  #define EMAC0_PPSCTRL_R HWREG(EMAC0_BASE + EMAC_O_PPSCTRL)
135  #define EMAC0_PPS0INTVL_R HWREG(EMAC0_BASE + EMAC_O_PPS0INTVL)
136  #define EMAC0_PPS0WIDTH_R HWREG(EMAC0_BASE + EMAC_O_PPS0WIDTH)
137  #define EMAC0_DMABUSMOD_R HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD)
138  #define EMAC0_TXPOLLD_R HWREG(EMAC0_BASE + EMAC_O_TXPOLLD)
139  #define EMAC0_RXPOLLD_R HWREG(EMAC0_BASE + EMAC_O_RXPOLLD)
140  #define EMAC0_RXDLADDR_R HWREG(EMAC0_BASE + EMAC_O_RXDLADDR)
141  #define EMAC0_TXDLADDR_R HWREG(EMAC0_BASE + EMAC_O_TXDLADDR)
142  #define EMAC0_DMARIS_R HWREG(EMAC0_BASE + EMAC_O_DMARIS)
143  #define EMAC0_DMAOPMODE_R HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE)
144  #define EMAC0_DMAIM_R HWREG(EMAC0_BASE + EMAC_O_DMAIM)
145  #define EMAC0_MFBOC_R HWREG(EMAC0_BASE + EMAC_O_MFBOC)
146  #define EMAC0_RXINTWDT_R HWREG(EMAC0_BASE + EMAC_O_RXINTWDT)
147  #define EMAC0_HOSTXDESC_R HWREG(EMAC0_BASE + EMAC_O_HOSTXDESC)
148  #define EMAC0_HOSRXDESC_R HWREG(EMAC0_BASE + EMAC_O_HOSRXDESC)
149  #define EMAC0_HOSTXBA_R HWREG(EMAC0_BASE + EMAC_O_HOSTXBA)
150  #define EMAC0_HOSRXBA_R HWREG(EMAC0_BASE + EMAC_O_HOSRXBA)
151  #define EMAC0_PP_R HWREG(EMAC0_BASE + EMAC_O_PP)
152  #define EMAC0_PC_R HWREG(EMAC0_BASE + EMAC_O_PC)
153  #define EMAC0_CC_R HWREG(EMAC0_BASE + EMAC_O_CC)
154  #define EMAC0_EPHYRIS_R HWREG(EMAC0_BASE + EMAC_O_EPHYRIS)
155  #define EMAC0_EPHYIM_R HWREG(EMAC0_BASE + EMAC_O_EPHYIM)
156  #define EMAC0_EPHYMISC_R HWREG(EMAC0_BASE + EMAC_O_EPHYMISC)
157 #endif
158 
159 //DMABUSMOD register
160 #define EMAC_DMABUSMOD_RPBL_1 (1 << EMAC_DMABUSMOD_RPBL_S)
161 #define EMAC_DMABUSMOD_RPBL_2 (2 << EMAC_DMABUSMOD_RPBL_S)
162 #define EMAC_DMABUSMOD_RPBL_4 (4 << EMAC_DMABUSMOD_RPBL_S)
163 #define EMAC_DMABUSMOD_RPBL_8 (8 << EMAC_DMABUSMOD_RPBL_S)
164 #define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
165 #define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
166 
167 #define EMAC_DMABUSMOD_PR_1_1 (0 << EMAC_DMABUSMOD_PR_S)
168 #define EMAC_DMABUSMOD_PR_2_1 (1 << EMAC_DMABUSMOD_PR_S)
169 #define EMAC_DMABUSMOD_PR_3_1 (2 << EMAC_DMABUSMOD_PR_S)
170 #define EMAC_DMABUSMOD_PR_4_1 (3 << EMAC_DMABUSMOD_PR_S)
171 
172 #define EMAC_DMABUSMOD_PBL_1 (1 << EMAC_DMABUSMOD_PBL_S)
173 #define EMAC_DMABUSMOD_PBL_2 (2 << EMAC_DMABUSMOD_PBL_S)
174 #define EMAC_DMABUSMOD_PBL_4 (4 << EMAC_DMABUSMOD_PBL_S)
175 #define EMAC_DMABUSMOD_PBL_8 (8 << EMAC_DMABUSMOD_PBL_S)
176 #define EMAC_DMABUSMOD_PBL_16 (16 << EMAC_DMABUSMOD_PBL_S)
177 #define EMAC_DMABUSMOD_PBL_32 (32 << EMAC_DMABUSMOD_PBL_S)
178 
179 //Transmit DMA descriptor flags
180 #define EMAC_TDES0_OWN 0x80000000
181 #define EMAC_TDES0_IC 0x40000000
182 #define EMAC_TDES0_LS 0x20000000
183 #define EMAC_TDES0_FS 0x10000000
184 #define EMAC_TDES0_DC 0x08000000
185 #define EMAC_TDES0_DP 0x04000000
186 #define EMAC_TDES0_TTSE 0x02000000
187 #define EMAC_TDES0_CRCR 0x01000000
188 #define EMAC_TDES0_CIC 0x00C00000
189 #define EMAC_TDES0_TER 0x00200000
190 #define EMAC_TDES0_TCH 0x00100000
191 #define EMAC_TDES0_VLIC 0x000C0000
192 #define EMAC_TDES0_TTSS 0x00020000
193 #define EMAC_TDES0_IHE 0x00010000
194 #define EMAC_TDES0_ES 0x00008000
195 #define EMAC_TDES0_JT 0x00004000
196 #define EMAC_TDES0_FF 0x00002000
197 #define EMAC_TDES0_IPE 0x00001000
198 #define EMAC_TDES0_LCA 0x00000800
199 #define EMAC_TDES0_NC 0x00000400
200 #define EMAC_TDES0_LCO 0x00000200
201 #define EMAC_TDES0_EC 0x00000100
202 #define EMAC_TDES0_VF 0x00000080
203 #define EMAC_TDES0_CC 0x00000078
204 #define EMAC_TDES0_ED 0x00000004
205 #define EMAC_TDES0_UF 0x00000002
206 #define EMAC_TDES0_DB 0x00000001
207 #define EMAC_TDES1_SAIC 0xE0000000
208 #define EMAC_TDES1_TBS2 0x1FFF0000
209 #define EMAC_TDES1_TBS1 0x00001FFF
210 #define EMAC_TDES2_TBAP1 0xFFFFFFFF
211 #define EMAC_TDES3_TBAP2 0xFFFFFFFF
212 #define EMAC_TDES6_TTSL 0xFFFFFFFF
213 #define EMAC_TDES7_TTSH 0xFFFFFFFF
214 
215 //Receive DMA descriptor flags
216 #define EMAC_RDES0_OWN 0x80000000
217 #define EMAC_RDES0_AFM 0x40000000
218 #define EMAC_RDES0_FL 0x3FFF0000
219 #define EMAC_RDES0_ES 0x00008000
220 #define EMAC_RDES0_DE 0x00004000
221 #define EMAC_RDES0_SAF 0x00002000
222 #define EMAC_RDES0_LE 0x00001000
223 #define EMAC_RDES0_OE 0x00000800
224 #define EMAC_RDES0_VLAN 0x00000400
225 #define EMAC_RDES0_FS 0x00000200
226 #define EMAC_RDES0_LS 0x00000100
227 #define EMAC_RDES0_TSA_GF 0x00000080
228 #define EMAC_RDES0_LCO 0x00000040
229 #define EMAC_RDES0_FT 0x00000020
230 #define EMAC_RDES0_RWT 0x00000010
231 #define EMAC_RDES0_RE 0x00000008
232 #define EMAC_RDES0_DBE 0x00000004
233 #define EMAC_RDES0_CE 0x00000002
234 #define EMAC_RDES0_ESA 0x00000001
235 #define EMAC_RDES1_DIC 0x80000000
236 #define EMAC_RDES1_RBS2 0x1FFF0000
237 #define EMAC_RDES1_RER 0x00008000
238 #define EMAC_RDES1_RCH 0x00004000
239 #define EMAC_RDES1_RBS1 0x00001FFF
240 #define EMAC_RDES2_RBAP1 0xFFFFFFFF
241 #define EMAC_RDES3_RBAP2 0xFFFFFFFF
242 #define EMAC_RDES4_TSD 0x00004000
243 #define EMAC_RDES4_PV 0x00002000
244 #define EMAC_RDES4_PFT 0x00001000
245 #define EMAC_RDES4_PMT 0x00000F00
246 #define EMAC_RDES4_IPV6PR 0x00000080
247 #define EMAC_RDES4_IPV4PR 0x00000040
248 #define EMAC_RDES4_IPCB 0x00000020
249 #define EMAC_RDES4_IPPE 0x00000010
250 #define EMAC_RDES4_IPHE 0x00000008
251 #define EMAC_RDES4_IPPT 0x00000007
252 #define EMAC_RDES6_RTSL 0xFFFFFFFF
253 #define EMAC_RDES7_RTSH 0xFFFFFFFF
254 
255 #ifndef ti_sysbios_BIOS___VERS
256  #define tm4c129EthIrqHandler EMAC0_Handler
257 #endif
258 
259 //C++ guard
260 #ifdef __cplusplus
261 extern "C" {
262 #endif
263 
264 
265 /**
266  * @brief Enhanced TX DMA descriptor
267  **/
268 
269 typedef struct
270 {
271  uint32_t tdes0;
272  uint32_t tdes1;
273  uint32_t tdes2;
274  uint32_t tdes3;
275  uint32_t tdes4;
276  uint32_t tdes5;
277  uint32_t tdes6;
278  uint32_t tdes7;
280 
281 
282 /**
283  * @brief Enhanced RX DMA descriptor
284  **/
285 
286 typedef struct
287 {
288  uint32_t rdes0;
289  uint32_t rdes1;
290  uint32_t rdes2;
291  uint32_t rdes3;
292  uint32_t rdes4;
293  uint32_t rdes5;
294  uint32_t rdes6;
295  uint32_t rdes7;
297 
298 
299 //TM4C129 Ethernet MAC driver
300 extern const NicDriver tm4c129EthDriver;
301 
302 //TM4C129 Ethernet MAC related functions
304 void tm4c129EthInitGpio(NetInterface *interface);
305 void tm4c129EthInitDmaDesc(NetInterface *interface);
306 
307 void tm4c129EthTick(NetInterface *interface);
308 
309 void tm4c129EthEnableIrq(NetInterface *interface);
310 void tm4c129EthDisableIrq(NetInterface *interface);
311 void tm4c129EthIrqHandler(void);
312 void tm4c129EthEventHandler(NetInterface *interface);
313 
315  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
316 
318 
321 
322 void tm4c129EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
323  uint8_t regAddr, uint16_t data);
324 
325 uint16_t tm4c129EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
326  uint8_t regAddr);
327 
328 void tm4c129EthDumpPhyReg(void);
329 
330 uint32_t tm4c129EthCalcCrc(const void *data, size_t length);
331 
332 //C++ guard
333 #ifdef __cplusplus
334 }
335 #endif
336 
337 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Enhanced RX DMA descriptor.
Enhanced TX DMA descriptor.
uint8_t length
Definition: tcp.h:368
error_t tm4c129EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint32_t tm4c129EthCalcCrc(const void *data, size_t length)
CRC calculation.
void tm4c129EthDumpPhyReg(void)
Dump PHY registers for debugging purpose.
void tm4c129EthEventHandler(NetInterface *interface)
TM4C129 Ethernet MAC event handler.
void tm4c129EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define tm4c129EthIrqHandler
void tm4c129EthInitGpio(NetInterface *interface)
GPIO configuration.
void tm4c129EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void tm4c129EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t tm4c129EthReceivePacket(NetInterface *interface)
Receive a packet.
void tm4c129EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void tm4c129EthTick(NetInterface *interface)
TM4C129 Ethernet MAC timer handler.
error_t tm4c129EthInit(NetInterface *interface)
TM4C129 Ethernet MAC initialization.
error_t tm4c129EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t tm4c129EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
const NicDriver tm4c129EthDriver
TM4C129 Ethernet MAC driver.
error_t tm4c129EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.