w5500_driver.c
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1 /**
2  * @file w5500_driver.c
3  * @brief WIZnet W5500 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
37 #include "debug.h"
38 
39 
40 /**
41  * @brief W5500 driver
42  **/
43 
45 {
47  ETH_MTU,
48  w5500Init,
49  w5500Tick,
55  NULL,
56  NULL,
57  NULL,
58  TRUE,
59  TRUE,
60  TRUE,
61  TRUE
62 };
63 
64 
65 /**
66  * @brief W5500 controller initialization
67  * @param[in] interface Underlying network interface
68  * @return Error code
69  **/
70 
72 {
73  uint_t i;
74  uint8_t value;
75 
76  //Debug message
77  TRACE_INFO("Initializing W5500 Ethernet controller...\r\n");
78 
79  //Initialize SPI interface
80  interface->spiDriver->init();
81 
82  //Initialize external interrupt line driver
83  if(interface->extIntDriver != NULL)
84  {
85  interface->extIntDriver->init();
86  }
87 
88  //Perform software reset
90  W5500_MR_RST);
91 
92  //Wait for reset completion
93  do
94  {
95  //Read mode register
97 
98  //The RST bit is automatically cleared after reset completion
99  } while((value & W5500_MR_RST) != 0);
100 
101  //Set the MAC address of the station
103  interface->macAddr.b[0]);
105  interface->macAddr.b[1]);
107  interface->macAddr.b[2]);
109  interface->macAddr.b[3]);
111  interface->macAddr.b[4]);
113  interface->macAddr.b[5]);
114 
115  //Set TX and RX buffer size for socket 0
120 
121  //Sockets 1 to 7 are not used
122  for(i = 1; i <= 7; i++)
123  {
128  }
129 
130  //Configure socket 0 in MACRAW mode
133 
134  //Open socket 0
137 
138  //Wait for command completion
139  do
140  {
141  //Read status register
143 
144  //Check the status of the socket
145  } while(value != W5500_Sn_SR_SOCK_MACRAW);
146 
147  //Configure socket 0 interrupts
150 
151  //Enable socket 0 interrupts
154 
155  //Disable unused interrupts
157 
158  //Perform custom configuration
159  w5500InitHook(interface);
160 
161  //Dump registers for debugging purpose
162  w5500DumpReg(interface);
163 
164  //Accept any packets from the upper layer
165  osSetEvent(&interface->nicTxEvent);
166 
167  //Force the TCP/IP stack to poll the link state at startup
168  interface->nicEvent = TRUE;
169  //Notify the TCP/IP stack of the event
171 
172  //Successful initialization
173  return NO_ERROR;
174 }
175 
176 
177 /**
178  * @brief W5500 custom configuration
179  * @param[in] interface Underlying network interface
180  **/
181 
182 __weak_func void w5500InitHook(NetInterface *interface)
183 {
184 }
185 
186 
187 /**
188  * @brief W5500 timer handler
189  * @param[in] interface Underlying network interface
190  **/
191 
192 void w5500Tick(NetInterface *interface)
193 {
194  uint8_t value;
195  bool_t linkState;
196 
197  //Read PHY configuration register
199  //Retrieve current link state
200  linkState = (value & W5500_PHYCFGR_LNK) ? TRUE : FALSE;
201 
202  //Check link state
203  if(linkState && !interface->linkState)
204  {
205  //Get current speed
206  if((value & W5500_PHYCFGR_SPD) != 0)
207  {
208  interface->linkSpeed = NIC_LINK_SPEED_100MBPS;
209  }
210  else
211  {
212  interface->linkSpeed = NIC_LINK_SPEED_10MBPS;
213  }
214 
215  //Determine the new duplex mode
216  if((value & W5500_PHYCFGR_DPX) != 0)
217  {
218  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
219  }
220  else
221  {
222  interface->duplexMode = NIC_HALF_DUPLEX_MODE;
223  }
224 
225  //Link is up
226  interface->linkState = TRUE;
227  //Process link state change event
228  nicNotifyLinkChange(interface);
229  }
230  else if(!linkState && interface->linkState)
231  {
232  //Link is down
233  interface->linkState = FALSE;
234  //Process link state change event
235  nicNotifyLinkChange(interface);
236  }
237  else
238  {
239  //No link change detected
240  }
241 }
242 
243 
244 /**
245  * @brief Enable interrupts
246  * @param[in] interface Underlying network interface
247  **/
248 
249 void w5500EnableIrq(NetInterface *interface)
250 {
251  //Enable interrupts
252  if(interface->extIntDriver != NULL)
253  {
254  interface->extIntDriver->enableIrq();
255  }
256 }
257 
258 
259 /**
260  * @brief Disable interrupts
261  * @param[in] interface Underlying network interface
262  **/
263 
265 {
266  //Disable interrupts
267  if(interface->extIntDriver != NULL)
268  {
269  interface->extIntDriver->disableIrq();
270  }
271 }
272 
273 
274 /**
275  * @brief W5500 interrupt service routine
276  * @param[in] interface Underlying network interface
277  * @return TRUE if a higher priority task must be woken. Else FALSE is returned
278  **/
279 
281 {
282  bool_t flag;
283  uint16_t n;
284  uint8_t isr;
285 
286  //This flag will be set if a higher priority task must be woken
287  flag = FALSE;
288 
289  //Read socket interrupt register
291  //Disable interrupts to release the interrupt line
293 
294  //Socket 0 interrupt?
295  if((isr & W5500_SIR_S0_INT) != 0)
296  {
297  //Read socket 0 interrupt register
299 
300  //Packet transmission complete?
301  if((isr & W5500_Sn_IR_SEND_OK) != 0)
302  {
303  //Get the amount of free memory available in the TX buffer
305 
306  //Check whether the TX buffer is available for writing
307  if(n >= ETH_MAX_FRAME_SIZE)
308  {
309  //The transmitter can accept another packet
310  osSetEvent(&interface->nicTxEvent);
311  }
312  }
313 
314  //Packet received?
315  if((isr & W5500_Sn_IR_RECV) != 0)
316  {
317  //Set event flag
318  interface->nicEvent = TRUE;
319  //Notify the TCP/IP stack of the event
320  flag |= osSetEventFromIsr(&netEvent);
321  }
322 
323  //Clear interrupt flags
326  }
327 
328  //Re-enable interrupts once the interrupt has been serviced
331 
332  //A higher priority task must be woken?
333  return flag;
334 }
335 
336 
337 /**
338  * @brief W5500 event handler
339  * @param[in] interface Underlying network interface
340  **/
341 
343 {
344  error_t error;
345 
346  //Process all pending packets
347  do
348  {
349  //Read incoming packet
350  error = w5500ReceivePacket(interface);
351 
352  //No more data in the receive buffer?
353  } while(error != ERROR_BUFFER_EMPTY);
354 }
355 
356 
357 /**
358  * @brief Send a packet
359  * @param[in] interface Underlying network interface
360  * @param[in] buffer Multi-part buffer containing the data to send
361  * @param[in] offset Offset to the first data byte
362  * @param[in] ancillary Additional options passed to the stack along with
363  * the packet
364  * @return Error code
365  **/
366 
368  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
369 {
370  static uint8_t temp[W5500_ETH_TX_BUFFER_SIZE];
371  uint16_t n;
372  uint16_t p;
373  size_t length;
374 
375  //Retrieve the length of the packet
376  length = netBufferGetLength(buffer) - offset;
377 
378  //Check the frame length
380  {
381  //The transmitter can accept another packet
382  osSetEvent(&interface->nicTxEvent);
383  //Report an error
384  return ERROR_INVALID_LENGTH;
385  }
386 
387  //Get the amount of free memory available in the TX buffer
389 
390  //Make sure the TX buffer is available for writing
391  if(n < length)
392  return ERROR_FAILURE;
393 
394  //Copy user data
395  netBufferRead(temp, buffer, offset, length);
396 
397  //Get TX write pointer
399 
400  //Write TX buffer
402 
403  //Increment TX write pointer
405  p + length);
406 
407  //Start packet transmission
410 
411  //Get the amount of free memory available in the TX buffer
413 
414  //Check whether the TX buffer is available for writing
415  if(n >= ETH_MAX_FRAME_SIZE)
416  {
417  //The transmitter can accept another packet
418  osSetEvent(&interface->nicTxEvent);
419  }
420 
421  //Successful processing
422  return NO_ERROR;
423 }
424 
425 
426 /**
427  * @brief Receive a packet
428  * @param[in] interface Underlying network interface
429  * @return Error code
430  **/
431 
433 {
434  static uint8_t temp[W5500_ETH_RX_BUFFER_SIZE];
435  error_t error;
436  uint16_t p;
437  size_t length;
438 
439  //Get the amount of data in the RX buffer
441 
442  //Any packet pending in the receive buffer?
443  if(length > 0)
444  {
445  //Get RX read pointer
447 
448  //Read packet header
449  w5500ReadBuffer(interface, W5500_CTRL_BSB_S0_RX_BUFFER, p, temp, 2);
450 
451  //Retrieve the length of the received packet
452  length = LOAD16BE(temp);
453 
454  //Ensure the packet size is acceptable
455  if(length >= 2 && length <= (ETH_MAX_FRAME_SIZE + 2))
456  {
457  //Calculate the length of the packet data
458  length -= 2;
459 
460  //Read packet data
461  w5500ReadBuffer(interface, W5500_CTRL_BSB_S0_RX_BUFFER, p + 2, temp,
462  length);
463 
464  //Increment RX read pointer
466  p + length + 2);
467 
468  //Complete the processing of the receive data
471 
472  //Successful processing
473  error = NO_ERROR;
474  }
475  else
476  {
477  //The packet length is not valid
478  error = ERROR_INVALID_LENGTH;
479  }
480  }
481  else
482  {
483  //No more data in the receive buffer
484  error = ERROR_BUFFER_EMPTY;
485  }
486 
487  //Check whether a valid packet has been received
488  if(!error)
489  {
490  NetRxAncillary ancillary;
491 
492  //Additional options can be passed to the stack along with the packet
493  ancillary = NET_DEFAULT_RX_ANCILLARY;
494 
495  //Pass the packet to the upper layer
496  nicProcessPacket(interface, temp, length, &ancillary);
497  }
498 
499  //Return status code
500  return error;
501 }
502 
503 
504 /**
505  * @brief Configure MAC address filtering
506  * @param[in] interface Underlying network interface
507  * @return Error code
508  **/
509 
511 {
512  //Not implemented
513  return NO_ERROR;
514 }
515 
516 
517 /**
518  * @brief Write 8-bit register
519  * @param[in] interface Underlying network interface
520  * @param[in] control Control byte
521  * @param[in] address Register address
522  * @param[in] data Register value
523  **/
524 
525 void w5500WriteReg8(NetInterface *interface, uint8_t control,
526  uint16_t address, uint8_t data)
527 {
528  //Pull the CS pin low
529  interface->spiDriver->assertCs();
530 
531  //Address phase
532  interface->spiDriver->transfer(MSB(address));
533  interface->spiDriver->transfer(LSB(address));
534 
535  //Control phase
536  interface->spiDriver->transfer(control | W5500_CTRL_RWB_WRITE |
538 
539  //Data phase
540  interface->spiDriver->transfer(data);
541 
542  //Terminate the operation by raising the CS pin
543  interface->spiDriver->deassertCs();
544 }
545 
546 
547 /**
548  * @brief Read 8-bit register
549  * @param[in] interface Underlying network interface
550  * @param[in] control Control byte
551  * @param[in] address Register address
552  * @return Register value
553  **/
554 
555 uint8_t w5500ReadReg8(NetInterface *interface, uint8_t control,
556  uint16_t address)
557 {
558  uint8_t data;
559 
560  //Pull the CS pin low
561  interface->spiDriver->assertCs();
562 
563  //Address phase
564  interface->spiDriver->transfer(MSB(address));
565  interface->spiDriver->transfer(LSB(address));
566 
567  //Control phase
568  interface->spiDriver->transfer(control | W5500_CTRL_RWB_READ |
570 
571  //Data phase
572  data = interface->spiDriver->transfer(0x00);
573 
574  //Terminate the operation by raising the CS pin
575  interface->spiDriver->deassertCs();
576 
577  //Return register value
578  return data;
579 }
580 
581 
582 /**
583  * @brief Write 16-bit register
584  * @param[in] interface Underlying network interface
585  * @param[in] control Control byte
586  * @param[in] address Register address
587  * @param[in] data Register value
588  **/
589 
590 void w5500WriteReg16(NetInterface *interface, uint8_t control,
591  uint16_t address, uint16_t data)
592 {
593  //Pull the CS pin low
594  interface->spiDriver->assertCs();
595 
596  //Address phase
597  interface->spiDriver->transfer(MSB(address));
598  interface->spiDriver->transfer(LSB(address));
599 
600  //Control phase
601  interface->spiDriver->transfer(control | W5500_CTRL_RWB_WRITE |
603 
604  //Data phase
605  interface->spiDriver->transfer(MSB(data));
606  interface->spiDriver->transfer(LSB(data));
607 
608  //Terminate the operation by raising the CS pin
609  interface->spiDriver->deassertCs();
610 }
611 
612 
613 /**
614  * @brief Read 16-bit register
615  * @param[in] interface Underlying network interface
616  * @param[in] control Control byte
617  * @param[in] address Register address
618  * @return Register value
619  **/
620 
621 uint16_t w5500ReadReg16(NetInterface *interface, uint8_t control,
622  uint16_t address)
623 {
624  uint16_t data;
625 
626  //Pull the CS pin low
627  interface->spiDriver->assertCs();
628 
629  //Address phase
630  interface->spiDriver->transfer(MSB(address));
631  interface->spiDriver->transfer(LSB(address));
632 
633  //Control phase
634  interface->spiDriver->transfer(control | W5500_CTRL_RWB_READ |
636 
637  //Data phase
638  data = interface->spiDriver->transfer(0x00) << 8;
639  data |= interface->spiDriver->transfer(0x00);
640 
641  //Terminate the operation by raising the CS pin
642  interface->spiDriver->deassertCs();
643 
644  //Return register value
645  return data;
646 }
647 
648 
649 /**
650  * @brief Write TX buffer
651  * @param[in] interface Underlying network interface
652  * @param[in] control Control byte
653  * @param[in] address Buffer address
654  * @param[in] data Pointer to the data being written
655  * @param[in] length Number of data to write
656  **/
657 
658 void w5500WriteBuffer(NetInterface *interface, uint8_t control,
659  uint16_t address, const uint8_t *data, size_t length)
660 {
661  size_t i;
662 
663  //Pull the CS pin low
664  interface->spiDriver->assertCs();
665 
666  //Address phase
667  interface->spiDriver->transfer(MSB(address));
668  interface->spiDriver->transfer(LSB(address));
669 
670  //Control phase
671  interface->spiDriver->transfer(control | W5500_CTRL_RWB_WRITE |
673 
674  //Data phase
675  for(i = 0; i < length; i++)
676  {
677  interface->spiDriver->transfer(data[i]);
678  }
679 
680  //Terminate the operation by raising the CS pin
681  interface->spiDriver->deassertCs();
682 }
683 
684 
685 /**
686  * @brief Read RX buffer
687  * @param[in] interface Underlying network interface
688  * @param[in] control Control byte
689  * @param[in] address Buffer address
690  * @param[out] data Buffer where to store the incoming data
691  * @param[in] length Number of data to read
692  **/
693 
694 void w5500ReadBuffer(NetInterface *interface, uint8_t control,
695  uint16_t address, uint8_t *data, size_t length)
696 {
697  size_t i;
698 
699  //Pull the CS pin low
700  interface->spiDriver->assertCs();
701 
702  //Address phase
703  interface->spiDriver->transfer(MSB(address));
704  interface->spiDriver->transfer(LSB(address));
705 
706  //Control phase
707  interface->spiDriver->transfer(control | W5500_CTRL_RWB_READ |
709 
710  //Data phase
711  for(i = 0; i < length; i++)
712  {
713  data[i] = interface->spiDriver->transfer(0x00);
714  }
715 
716  //Terminate the operation by raising the CS pin
717  interface->spiDriver->deassertCs();
718 }
719 
720 
721 /**
722  * @brief Dump registers for debugging purpose
723  * @param[in] interface Underlying network interface
724  **/
725 
726 void w5500DumpReg(NetInterface *interface)
727 {
728  uint16_t i;
729 
730  //Loop through registers
731  for(i = 0; i < 64; i++)
732  {
733  //Display current host MAC register
734  TRACE_DEBUG("%02" PRIX16 ": 0x%02" PRIX8 "\r\n", i,
736  }
737 
738  //Terminate with a line feed
739  TRACE_DEBUG("\r\n");
740 }
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
#define LOAD16BE(p)
Definition: cpu_endian.h:186
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
uint8_t control
Definition: ethernet.h:234
Ipv6Addr address[]
Definition: ipv6.h:316
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:548
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_HALF_DUPLEX_MODE
Definition: nic.h:124
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
@ NIC_LINK_SPEED_10MBPS
Definition: nic.h:111
#define LSB(x)
Definition: os_port.h:55
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define MSB(x)
Definition: os_port.h:59
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint8_t value[]
Definition: tcp.h:369
void w5500ReadBuffer(NetInterface *interface, uint8_t control, uint16_t address, uint8_t *data, size_t length)
Read RX buffer.
Definition: w5500_driver.c:694
error_t w5500ReceivePacket(NetInterface *interface)
Receive a packet.
Definition: w5500_driver.c:432
void w5500WriteReg8(NetInterface *interface, uint8_t control, uint16_t address, uint8_t data)
Write 8-bit register.
Definition: w5500_driver.c:525
void w5500EventHandler(NetInterface *interface)
W5500 event handler.
Definition: w5500_driver.c:342
uint8_t w5500ReadReg8(NetInterface *interface, uint8_t control, uint16_t address)
Read 8-bit register.
Definition: w5500_driver.c:555
void w5500Tick(NetInterface *interface)
W5500 timer handler.
Definition: w5500_driver.c:192
error_t w5500SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Definition: w5500_driver.c:367
error_t w5500UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Definition: w5500_driver.c:510
error_t w5500Init(NetInterface *interface)
W5500 controller initialization.
Definition: w5500_driver.c:71
__weak_func void w5500InitHook(NetInterface *interface)
W5500 custom configuration.
Definition: w5500_driver.c:182
void w5500WriteBuffer(NetInterface *interface, uint8_t control, uint16_t address, const uint8_t *data, size_t length)
Write TX buffer.
Definition: w5500_driver.c:658
void w5500WriteReg16(NetInterface *interface, uint8_t control, uint16_t address, uint16_t data)
Write 16-bit register.
Definition: w5500_driver.c:590
const NicDriver w5500Driver
W5500 driver.
Definition: w5500_driver.c:44
void w5500EnableIrq(NetInterface *interface)
Enable interrupts.
Definition: w5500_driver.c:249
void w5500DisableIrq(NetInterface *interface)
Disable interrupts.
Definition: w5500_driver.c:264
bool_t w5500IrqHandler(NetInterface *interface)
W5500 interrupt service routine.
Definition: w5500_driver.c:280
void w5500DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
Definition: w5500_driver.c:726
uint16_t w5500ReadReg16(NetInterface *interface, uint8_t control, uint16_t address)
Read 16-bit register.
Definition: w5500_driver.c:621
WIZnet W5500 Ethernet controller.
#define W5500_PHYCFGR_DPX
Definition: w5500_driver.h:229
#define W5500_Sn_CR_OPEN
Definition: w5500_driver.h:252
#define W5500_Sn_TXBUF_SIZE
Definition: w5500_driver.h:161
#define W5500_ETH_TX_BUFFER_SIZE
Definition: w5500_driver.h:39
#define W5500_PHYCFGR_SPD
Definition: w5500_driver.h:230
#define W5500_Sn_CR_SEND
Definition: w5500_driver.h:257
#define W5500_Sn_MR_MFEN
Definition: w5500_driver.h:238
#define W5500_Sn_RXBUF_SIZE_16KB
Definition: w5500_driver.h:290
#define W5500_Sn_TXBUF_SIZE_0KB
Definition: w5500_driver.h:293
#define W5500_CTRL_OM_VDM
Definition: w5500_driver.h:82
#define W5500_MR
Definition: w5500_driver.h:88
#define W5500_Sn_TX_FSR0
Definition: w5500_driver.h:162
#define W5500_Sn_SR_SOCK_MACRAW
Definition: w5500_driver.h:282
#define W5500_CTRL_BSB_S0_REG
Definition: w5500_driver.h:54
#define W5500_SHAR4
Definition: w5500_driver.h:101
#define W5500_CTRL_BSB_COMMON_REG
Definition: w5500_driver.h:53
#define W5500_SIR
Definition: w5500_driver.h:111
#define W5500_IMR
Definition: w5500_driver.h:110
#define W5500_SIMR_S0_IMR
Definition: w5500_driver.h:216
#define W5500_Sn_RX_RD0
Definition: w5500_driver.h:170
#define W5500_Sn_RX_RSR0
Definition: w5500_driver.h:168
#define W5500_CTRL_RWB_READ
Definition: w5500_driver.h:79
#define W5500_SHAR5
Definition: w5500_driver.h:102
#define W5500_Sn_IMR_SEND_OK
Definition: w5500_driver.h:301
#define W5500_Sn_IR_SEND_OK
Definition: w5500_driver.h:263
#define W5500_Sn_SR
Definition: w5500_driver.h:141
#define W5500_Sn_IMR
Definition: w5500_driver.h:174
#define W5500_Sn_MR
Definition: w5500_driver.h:138
#define W5500_SIMR
Definition: w5500_driver.h:112
#define W5500_Sn_IR_RECV
Definition: w5500_driver.h:265
#define W5500_CTRL_BSB_S0_TX_BUFFER
Definition: w5500_driver.h:55
#define W5500_Sn_CR_RECV
Definition: w5500_driver.h:260
#define W5500_Sn_RXBUF_SIZE_0KB
Definition: w5500_driver.h:285
#define W5500_PHYCFGR_LNK
Definition: w5500_driver.h:231
#define W5500_SHAR0
Definition: w5500_driver.h:97
#define W5500_CTRL_BSB_Sn_REG(n)
Definition: w5500_driver.h:308
#define W5500_CTRL_OM_FDM1
Definition: w5500_driver.h:83
#define W5500_Sn_MR_PROTOCOL_MACRAW
Definition: w5500_driver.h:249
#define W5500_Sn_CR
Definition: w5500_driver.h:139
#define W5500_CTRL_OM_FDM2
Definition: w5500_driver.h:84
#define W5500_PHYCFGR
Definition: w5500_driver.h:134
#define W5500_Sn_IR
Definition: w5500_driver.h:140
#define W5500_CTRL_BSB_S0_RX_BUFFER
Definition: w5500_driver.h:56
#define W5500_MR_RST
Definition: w5500_driver.h:180
#define W5500_Sn_TXBUF_SIZE_16KB
Definition: w5500_driver.h:298
#define W5500_Sn_TX_WR0
Definition: w5500_driver.h:166
#define W5500_SHAR3
Definition: w5500_driver.h:100
#define W5500_SHAR1
Definition: w5500_driver.h:98
#define W5500_Sn_IMR_RECV
Definition: w5500_driver.h:303
#define W5500_Sn_RXBUF_SIZE
Definition: w5500_driver.h:160
#define W5500_CTRL_RWB_WRITE
Definition: w5500_driver.h:80
#define W5500_SHAR2
Definition: w5500_driver.h:99
#define W5500_SIR_S0_INT
Definition: w5500_driver.h:206
#define W5500_ETH_RX_BUFFER_SIZE
Definition: w5500_driver.h:46