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31 #ifndef _EFM32GG11_ETH_DRIVER_H
32 #define _EFM32GG11_ETH_DRIVER_H
38 #ifndef EFM32GG11_ETH_TX_BUFFER_COUNT
39 #define EFM32GG11_ETH_TX_BUFFER_COUNT 2
40 #elif (EFM32GG11_ETH_TX_BUFFER_COUNT < 1)
41 #error EFM32GG11_ETH_TX_BUFFER_COUNT parameter is not valid
45 #ifndef EFM32GG11_ETH_TX_BUFFER_SIZE
46 #define EFM32GG11_ETH_TX_BUFFER_SIZE 1536
47 #elif (EFM32GG11_ETH_TX_BUFFER_SIZE != 1536)
48 #error EFM32GG11_ETH_TX_BUFFER_SIZE parameter is not valid
52 #ifndef EFM32GG11_ETH_RX_BUFFER_COUNT
53 #define EFM32GG11_ETH_RX_BUFFER_COUNT 48
54 #elif (EFM32GG11_ETH_RX_BUFFER_COUNT < 12)
55 #error EFM32GG11_ETH_RX_BUFFER_COUNT parameter is not valid
59 #ifndef EFM32GG11_ETH_RX_BUFFER_SIZE
60 #define EFM32GG11_ETH_RX_BUFFER_SIZE 128
61 #elif (EFM32GG11_ETH_RX_BUFFER_SIZE != 128)
62 #error EFM32GG11_ETH_RX_BUFFER_SIZE parameter is not valid
66 #ifndef EFM32GG11_ETH_IRQ_PRIORITY_GROUPING
67 #define EFM32GG11_ETH_IRQ_PRIORITY_GROUPING 4
68 #elif (EFM32GG11_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error EFM32GG11_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73 #ifndef EFM32GG11_ETH_IRQ_GROUP_PRIORITY
74 #define EFM32GG11_ETH_IRQ_GROUP_PRIORITY 6
75 #elif (EFM32GG11_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error EFM32GG11_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80 #ifndef EFM32GG11_ETH_IRQ_SUB_PRIORITY
81 #define EFM32GG11_ETH_IRQ_SUB_PRIORITY 0
82 #elif (EFM32GG11_ETH_IRQ_SUB_PRIORITY < 0)
83 #error EFM32GG11_ETH_IRQ_SUB_PRIORITY parameter is not valid
87 #define ETH_TX_USED 0x80000000
88 #define ETH_TX_WRAP 0x40000000
89 #define ETH_TX_ERROR 0x20000000
90 #define ETH_TX_UNDERRUN 0x10000000
91 #define ETH_TX_EXHAUSTED 0x08000000
92 #define ETH_TX_NO_CRC 0x00010000
93 #define ETH_TX_LAST 0x00008000
94 #define ETH_TX_LENGTH 0x000007FF
97 #define ETH_RX_ADDRESS 0xFFFFFFFC
98 #define ETH_RX_WRAP 0x00000002
99 #define ETH_RX_OWNERSHIP 0x00000001
100 #define ETH_RX_BROADCAST 0x80000000
101 #define ETH_RX_MULTICAST_HASH 0x40000000
102 #define ETH_RX_UNICAST_HASH 0x20000000
103 #define ETH_RX_EXT_ADDR 0x10000000
104 #define ETH_RX_SAR1 0x04000000
105 #define ETH_RX_SAR2 0x02000000
106 #define ETH_RX_SAR3 0x01000000
107 #define ETH_RX_SAR4 0x00800000
108 #define ETH_RX_TYPE_ID 0x00400000
109 #define ETH_RX_VLAN_TAG 0x00200000
110 #define ETH_RX_PRIORITY_TAG 0x00100000
111 #define ETH_RX_VLAN_PRIORITY 0x000E0000
112 #define ETH_RX_CFI 0x00010000
113 #define ETH_RX_EOF 0x00008000
114 #define ETH_RX_SOF 0x00004000
115 #define ETH_RX_OFFSET 0x00003000
116 #define ETH_RX_LENGTH 0x00000FFF
void efm32gg11EthTick(NetInterface *interface)
EFM32GG11 Ethernet MAC timer handler.
Structure describing a buffer that spans multiple chunks.
error_t efm32gg11EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void efm32gg11EthEventHandler(NetInterface *interface)
EFM32GG11 Ethernet MAC event handler.
void efm32gg11EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t efm32gg11EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t efm32gg11EthInit(NetInterface *interface)
EFM32GG11 Ethernet MAC initialization.
error_t efm32gg11EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Receive buffer descriptor.
void efm32gg11EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void efm32gg11EthEnableIrq(NetInterface *interface)
Enable interrupts.
Network interface controller abstraction layer.
error_t efm32gg11EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void efm32gg11EthInitGpio(NetInterface *interface)
GPIO configuration.
void efm32gg11EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t efm32gg11EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Transmit buffer descriptor.
const NicDriver efm32gg11EthDriver
EFM32GG11 Ethernet MAC driver.