efm32gg11_eth_driver.c
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1 /**
2  * @file efm32gg11_eth_driver.c
3  * @brief EFM32 Giant Gecko 11 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "em_device.h"
37 #include "em_cmu.h"
38 #include "em_gpio.h"
39 #include "core/net.h"
41 #include "debug.h"
42 
43 //Underlying network interface
44 static NetInterface *nicDriverInterface;
45 
46 //IAR EWARM compiler?
47 #if defined(__ICCARM__)
48 
49 //TX buffer
50 #pragma data_alignment = 8
52 //RX buffer
53 #pragma data_alignment = 8
55 //TX buffer descriptors
56 #pragma data_alignment = 4
58 //RX buffer descriptors
59 #pragma data_alignment = 4
61 
62 //Keil MDK-ARM or GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(8)));
68 //RX buffer
70  __attribute__((aligned(8)));
71 //TX buffer descriptors
73  __attribute__((aligned(4)));
74 //RX buffer descriptors
76  __attribute__((aligned(4)));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief EFM32GG11 Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief EFM32GG11 Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing EFM32GG11 Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Enable high-frequency peripheral clock
129  CMU_ClockEnable(cmuClock_HFPER, true);
130  //Enable Ethernet peripheral clock
131  CMU_ClockEnable(cmuClock_ETH, true);
132 
133  //Disable transmit and receive circuits
134  ETH->NETWORKCTRL = 0;
135 
136  //GPIO configuration
137  efm32gg11EthInitGpio(interface);
138 
139  //Configure MDC clock speed
140  ETH->NETWORKCFG = (4 << _ETH_NETWORKCFG_MDCCLKDIV_SHIFT) &
141  _ETH_NETWORKCFG_MDCCLKDIV_MASK;
142 
143  //Enable management port (MDC and MDIO)
144  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_MANPORTEN_MASK;
145 
146  //Valid Ethernet PHY or switch driver?
147  if(interface->phyDriver != NULL)
148  {
149  //Ethernet PHY initialization
150  error = interface->phyDriver->init(interface);
151  }
152  else if(interface->switchDriver != NULL)
153  {
154  //Ethernet switch initialization
155  error = interface->switchDriver->init(interface);
156  }
157  else
158  {
159  //The interface is not properly configured
160  error = ERROR_FAILURE;
161  }
162 
163  //Any error to report?
164  if(error)
165  {
166  return error;
167  }
168 
169  //Set the MAC address of the station
170  ETH->SPECADDR1BOTTOM = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171  ETH->SPECADDR1TOP = interface->macAddr.w[2];
172 
173  //The MAC supports 3 additional addresses for unicast perfect filtering
174  ETH->SPECADDR2BOTTOM = 0;
175  ETH->SPECADDR3BOTTOM = 0;
176  ETH->SPECADDR4BOTTOM = 0;
177 
178  //Initialize hash table
179  ETH->HASHBOTTOM = 0;
180  ETH->HASHTOP = 0;
181 
182  //Configure the receive filter
183  ETH->NETWORKCFG |= _ETH_NETWORKCFG_RX1536BYTEFRAMES_MASK |
184  _ETH_NETWORKCFG_MULTICASTHASHEN_MASK;
185 
186  //Initialize buffer descriptors
187  efm32gg11EthInitBufferDesc(interface);
188 
189  //Clear transmit status register
190  ETH->TXSTATUS = _ETH_TXSTATUS_TXUNDERRUN_MASK |
191  _ETH_TXSTATUS_TXCMPLT_MASK | _ETH_TXSTATUS_AMBAERR_MASK |
192  _ETH_TXSTATUS_TXGO_MASK | _ETH_TXSTATUS_RETRYLMTEXCD_MASK |
193  _ETH_TXSTATUS_COLOCCRD_MASK | _ETH_TXSTATUS_USEDBITREAD_MASK;
194 
195  //Clear receive status register
196  ETH->RXSTATUS = _ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
197  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK;
198 
199  //First disable all interrupts
200  ETH->IENC = 0xFFFFFFFF;
201 
202  //Only the desired ones are enabled
203  ETH->IENS = _ETH_IENS_RXOVERRUN_MASK |
204  _ETH_IENS_TXCMPLT_MASK | _ETH_IENS_AMBAERR_MASK |
205  _ETH_IENS_RTRYLMTORLATECOL_MASK | _ETH_IENS_TXUNDERRUN_MASK |
206  _ETH_IENS_RXUSEDBITREAD_MASK | _ETH_IENS_RXCMPLT_MASK;
207 
208  //Read ETH_IFCR register to clear any pending interrupt
209  status = ETH->IFCR;
210  (void) status;
211 
212  //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
213  NVIC_SetPriorityGrouping(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING);
214 
215  //Configure Ethernet interrupt priority
216  NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(EFM32GG11_ETH_IRQ_PRIORITY_GROUPING,
218 
219  //Enable the transmitter and the receiver
220  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_ENBTX_MASK | _ETH_NETWORKCTRL_ENBRX_MASK;
221 
222  //Accept any packets from the upper layer
223  osSetEvent(&interface->nicTxEvent);
224 
225  //Successful initialization
226  return NO_ERROR;
227 }
228 
229 
230 /**
231  * @brief GPIO configuration
232  * @param[in] interface Underlying network interface
233  **/
234 
235 __weak_func void efm32gg11EthInitGpio(NetInterface *interface)
236 {
237 //EFM32 Giant Gecko 11 Starter Kit?
238 #if defined(USE_EFM32_GIANT_GECKO_11_SK)
239  uint32_t temp;
240 
241  //Enable GPIO clock
242  CMU_ClockEnable(cmuClock_GPIO, true);
243  //Enable external oscillator
244  CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
245 
246  //Select CMU_CLK2 clock source
247  CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
248 
249  //Configure CMU_CLK2 (PD10)
250  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_CMU_CLK2_PORT(5),
251  AF_CMU_CLK2_PIN(5), gpioModePushPull, 0);
252 
253  //Remap CMU_CLK2 pin
254  temp = CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK;
255  CMU->ROUTELOC0 = temp | CMU_ROUTELOC0_CLKOUT2LOC_LOC5;
256 
257  //Enable CMU_CLK2 pin
258  CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
259 
260  //Select RMII operation mode and enable transceiver clock
261  ETH->CTRL = ETH_CTRL_GBLCLKEN | ETH_CTRL_MIISEL_RMII;
262 
263  //Configure ETH_RMII_TXD0 (PF7)
264  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD0_PORT(1),
265  AF_ETH_RMIITXD0_PIN(1), gpioModePushPull, 0);
266 
267  //Configure ETH_RMII_TXD1 (PF6)
268  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXD1_PORT(1),
269  AF_ETH_RMIITXD1_PIN(1), gpioModePushPull, 0);
270 
271  //Configure ETH_RMII_TXEN (PF8)
272  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIITXEN_PORT(1),
273  AF_ETH_RMIITXEN_PIN(1), gpioModePushPull, 0);
274 
275  //Configure ETH_RMII_RXD0 (PD9)
276  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD0_PORT(1),
277  AF_ETH_RMIIRXD0_PIN(1), gpioModeInput, 0);
278 
279  //Configure ETH_RMII_RXD1 (PF9)
280  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXD1_PORT(1),
281  AF_ETH_RMIIRXD1_PIN(1), gpioModeInput, 0);
282 
283  //Configure ETH_RMII_CRSDV (PD11)
284  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIICRSDV_PORT(1),
285  AF_ETH_RMIICRSDV_PIN(1), gpioModeInput, 0);
286 
287  //Configure ETH_RMII_RXER (PD12)
288  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_RMIIRXER_PORT(1),
289  AF_ETH_RMIIRXER_PIN(1), gpioModeInput, 0);
290 
291  //Configure ETH_MDIO (PD13)
292  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDIO_PORT(1),
293  AF_ETH_MDIO_PIN(1), gpioModePushPull, 0);
294 
295  //Configure ETH_MDC (PD14)
296  GPIO_PinModeSet((GPIO_Port_TypeDef) AF_ETH_MDC_PORT(1),
297  AF_ETH_MDC_PIN(1), gpioModePushPull, 0);
298 
299  //Remap RMII pins
300  temp = ETH->ROUTELOC1 & ~(_ETH_ROUTELOC1_RMIILOC_MASK & _ETH_ROUTELOC1_MDIOLOC_MASK);
301  ETH->ROUTELOC1 = temp | (ETH_ROUTELOC1_RMIILOC_LOC1 | ETH_ROUTELOC1_MDIOLOC_LOC1);
302 
303  //Enable RMII pins
304  ETH->ROUTEPEN = ETH_ROUTEPEN_RMIIPEN | ETH_ROUTEPEN_MDIOPEN;
305 
306  //Configure ETH_PWR_ENABLE (PI10)
307  GPIO_PinModeSet(gpioPortI, 10, gpioModePushPull, 0);
308  //Configure ETH_RESET_N (PH7)
309  GPIO_PinModeSet(gpioPortH, 7, gpioModePushPull, 0);
310  //Configure ETH_INTRP (PG15)
311  GPIO_PinModeSet(gpioPortG, 15, gpioModeInput, 0);
312 
313  //Power on PHY transceiver
314  GPIO_PinOutSet(gpioPortI, 10);
315  sleep(10);
316 
317  //Reset PHY transceiver (hard reset)
318  GPIO_PinOutClear(gpioPortH, 7);
319  sleep(10);
320  GPIO_PinOutSet(gpioPortH, 7);
321  sleep(10);
322 #endif
323 }
324 
325 
326 /**
327  * @brief Initialize buffer descriptors
328  * @param[in] interface Underlying network interface
329  **/
330 
332 {
333  uint_t i;
334  uint32_t address;
335 
336  //Initialize TX buffer descriptors
337  for(i = 0; i < EFM32GG11_ETH_TX_BUFFER_COUNT; i++)
338  {
339  //Calculate the address of the current TX buffer
340  address = (uint32_t) txBuffer[i];
341  //Write the address to the descriptor entry
342  txBufferDesc[i].address = address;
343  //Initialize status field
344  txBufferDesc[i].status = ETH_TX_USED;
345  }
346 
347  //Mark the last descriptor entry with the wrap flag
348  txBufferDesc[i - 1].status |= ETH_TX_WRAP;
349  //Initialize TX buffer index
350  txBufferIndex = 0;
351 
352  //Initialize RX buffer descriptors
353  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
354  {
355  //Calculate the address of the current RX buffer
356  address = (uint32_t) rxBuffer[i];
357  //Write the address to the descriptor entry
358  rxBufferDesc[i].address = address & ETH_RX_ADDRESS;
359  //Clear status field
360  rxBufferDesc[i].status = 0;
361  }
362 
363  //Mark the last descriptor entry with the wrap flag
364  rxBufferDesc[i - 1].address |= ETH_RX_WRAP;
365  //Initialize RX buffer index
366  rxBufferIndex = 0;
367 
368  //Start location of the TX descriptor list
369  ETH->TXQPTR = (uint32_t) txBufferDesc;
370  //Start location of the RX descriptor list
371  ETH->RXQPTR = (uint32_t) rxBufferDesc;
372 }
373 
374 
375 /**
376  * @brief EFM32GG11 Ethernet MAC timer handler
377  *
378  * This routine is periodically called by the TCP/IP stack to handle periodic
379  * operations such as polling the link state
380  *
381  * @param[in] interface Underlying network interface
382  **/
383 
385 {
386  //Valid Ethernet PHY or switch driver?
387  if(interface->phyDriver != NULL)
388  {
389  //Handle periodic operations
390  interface->phyDriver->tick(interface);
391  }
392  else if(interface->switchDriver != NULL)
393  {
394  //Handle periodic operations
395  interface->switchDriver->tick(interface);
396  }
397  else
398  {
399  //Just for sanity
400  }
401 }
402 
403 
404 /**
405  * @brief Enable interrupts
406  * @param[in] interface Underlying network interface
407  **/
408 
410 {
411  //Enable Ethernet MAC interrupts
412  NVIC_EnableIRQ(ETH_IRQn);
413 
414  //Valid Ethernet PHY or switch driver?
415  if(interface->phyDriver != NULL)
416  {
417  //Enable Ethernet PHY interrupts
418  interface->phyDriver->enableIrq(interface);
419  }
420  else if(interface->switchDriver != NULL)
421  {
422  //Enable Ethernet switch interrupts
423  interface->switchDriver->enableIrq(interface);
424  }
425  else
426  {
427  //Just for sanity
428  }
429 }
430 
431 
432 /**
433  * @brief Disable interrupts
434  * @param[in] interface Underlying network interface
435  **/
436 
438 {
439  //Disable Ethernet MAC interrupts
440  NVIC_DisableIRQ(ETH_IRQn);
441 
442  //Valid Ethernet PHY or switch driver?
443  if(interface->phyDriver != NULL)
444  {
445  //Disable Ethernet PHY interrupts
446  interface->phyDriver->disableIrq(interface);
447  }
448  else if(interface->switchDriver != NULL)
449  {
450  //Disable Ethernet switch interrupts
451  interface->switchDriver->disableIrq(interface);
452  }
453  else
454  {
455  //Just for sanity
456  }
457 }
458 
459 
460 /**
461  * @brief EFM32GG11 Ethernet MAC interrupt service routine
462  **/
463 
464 void ETH_IRQHandler(void)
465 {
466  bool_t flag;
467  volatile uint32_t isr;
468  volatile uint32_t tsr;
469  volatile uint32_t rsr;
470 
471  //Interrupt service routine prologue
472  osEnterIsr();
473 
474  //This flag will be set if a higher priority task must be woken
475  flag = FALSE;
476 
477  //Each time the software reads ETH_IFCR, it has to check the contents
478  //of ETH_TXSTATUS, ETH_RXSTATUS and ETH_NETWORKSTATUS
479  isr = ETH->IFCR;
480  tsr = ETH->TXSTATUS;
481  rsr = ETH->RXSTATUS;
482 
483  //Clear interrupt flags
484  ETH->IFCR = isr;
485 
486  //Packet transmitted?
487  if((tsr & (_ETH_TXSTATUS_TXUNDERRUN_MASK | _ETH_TXSTATUS_TXCMPLT_MASK |
488  _ETH_TXSTATUS_AMBAERR_MASK | _ETH_TXSTATUS_TXGO_MASK |
489  _ETH_TXSTATUS_RETRYLMTEXCD_MASK | _ETH_TXSTATUS_COLOCCRD_MASK |
490  _ETH_TXSTATUS_USEDBITREAD_MASK)) != 0)
491  {
492  //Only clear TXSTATUS flags that are currently set
493  ETH->TXSTATUS = tsr;
494 
495  //Check whether the TX buffer is available for writing
496  if((txBufferDesc[txBufferIndex].status & ETH_TX_USED) != 0)
497  {
498  //Notify the TCP/IP stack that the transmitter is ready to send
499  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
500  }
501  }
502 
503  //Packet received?
504  if((rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
505  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK)) != 0)
506  {
507  //Set event flag
508  nicDriverInterface->nicEvent = TRUE;
509  //Notify the TCP/IP stack of the event
510  flag |= osSetEventFromIsr(&netEvent);
511  }
512 
513  //Interrupt service routine epilogue
514  osExitIsr(flag);
515 }
516 
517 
518 /**
519  * @brief EFM32GG11 Ethernet MAC event handler
520  * @param[in] interface Underlying network interface
521  **/
522 
524 {
525  error_t error;
526  uint32_t rsr;
527 
528  //Read receive status
529  rsr = ETH->RXSTATUS;
530 
531  //Packet received?
532  if((rsr & (_ETH_RXSTATUS_RXOVERRUN_MASK | _ETH_RXSTATUS_FRMRX_MASK |
533  _ETH_RXSTATUS_BUFFNOTAVAIL_MASK)) != 0)
534  {
535  //Only clear RXSTATUS flags that are currently set
536  ETH->RXSTATUS = rsr;
537 
538  //Process all pending packets
539  do
540  {
541  //Read incoming packet
542  error = efm32gg11EthReceivePacket(interface);
543 
544  //No more data in the receive buffer?
545  } while(error != ERROR_BUFFER_EMPTY);
546  }
547 }
548 
549 
550 /**
551  * @brief Send a packet
552  * @param[in] interface Underlying network interface
553  * @param[in] buffer Multi-part buffer containing the data to send
554  * @param[in] offset Offset to the first data byte
555  * @param[in] ancillary Additional options passed to the stack along with
556  * the packet
557  * @return Error code
558  **/
559 
561  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
562 {
563  size_t length;
564 
565  //Retrieve the length of the packet
566  length = netBufferGetLength(buffer) - offset;
567 
568  //Check the frame length
570  {
571  //The transmitter can accept another packet
572  osSetEvent(&interface->nicTxEvent);
573  //Report an error
574  return ERROR_INVALID_LENGTH;
575  }
576 
577  //Make sure the current buffer is available for writing
578  if((txBufferDesc[txBufferIndex].status & ETH_TX_USED) == 0)
579  {
580  return ERROR_FAILURE;
581  }
582 
583  //Copy user data to the transmit buffer
584  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
585 
586  //Set the necessary flags in the descriptor entry
587  if(txBufferIndex < (EFM32GG11_ETH_TX_BUFFER_COUNT - 1))
588  {
589  //Write the status word
590  txBufferDesc[txBufferIndex].status = ETH_TX_LAST |
591  (length & ETH_TX_LENGTH);
592 
593  //Point to the next buffer
594  txBufferIndex++;
595  }
596  else
597  {
598  //Write the status word
599  txBufferDesc[txBufferIndex].status = ETH_TX_WRAP | ETH_TX_LAST |
600  (length & ETH_TX_LENGTH);
601 
602  //Wrap around
603  txBufferIndex = 0;
604  }
605 
606  //Set the TSTART bit to initiate transmission
607  ETH->NETWORKCTRL |= _ETH_NETWORKCTRL_TXSTRT_MASK;
608 
609  //Check whether the next buffer is available for writing
610  if((txBufferDesc[txBufferIndex].status & ETH_TX_USED) != 0)
611  {
612  //The transmitter can accept another packet
613  osSetEvent(&interface->nicTxEvent);
614  }
615 
616  //Successful processing
617  return NO_ERROR;
618 }
619 
620 
621 /**
622  * @brief Receive a packet
623  * @param[in] interface Underlying network interface
624  * @return Error code
625  **/
626 
628 {
629  static uint32_t temp[ETH_MAX_FRAME_SIZE / 4];
630  error_t error;
631  uint_t i;
632  uint_t j;
633  uint_t sofIndex;
634  uint_t eofIndex;
635  size_t n;
636  size_t size;
637  size_t length;
638 
639  //Initialize variables
640  size = 0;
641  sofIndex = UINT_MAX;
642  eofIndex = UINT_MAX;
643 
644  //Search for SOF and EOF flags
645  for(i = 0; i < EFM32GG11_ETH_RX_BUFFER_COUNT; i++)
646  {
647  //Point to the current entry
648  j = rxBufferIndex + i;
649 
650  //Wrap around to the beginning of the buffer if necessary
652  {
654  }
655 
656  //No more entries to process?
657  if((rxBufferDesc[j].address & ETH_RX_OWNERSHIP) == 0)
658  {
659  //Stop processing
660  break;
661  }
662 
663  //A valid SOF has been found?
664  if((rxBufferDesc[j].status & ETH_RX_SOF) != 0)
665  {
666  //Save the position of the SOF
667  sofIndex = i;
668  }
669 
670  //A valid EOF has been found?
671  if((rxBufferDesc[j].status & ETH_RX_EOF) != 0 && sofIndex != UINT_MAX)
672  {
673  //Save the position of the EOF
674  eofIndex = i;
675  //Retrieve the length of the frame
676  size = rxBufferDesc[j].status & ETH_RX_LENGTH;
677  //Limit the number of data to read
678  size = MIN(size, ETH_MAX_FRAME_SIZE);
679  //Stop processing since we have reached the end of the frame
680  break;
681  }
682  }
683 
684  //Determine the number of entries to process
685  if(eofIndex != UINT_MAX)
686  {
687  j = eofIndex + 1;
688  }
689  else if(sofIndex != UINT_MAX)
690  {
691  j = sofIndex;
692  }
693  else
694  {
695  j = i;
696  }
697 
698  //Total number of bytes that have been copied from the receive buffer
699  length = 0;
700 
701  //Process incoming frame
702  for(i = 0; i < j; i++)
703  {
704  //Any data to copy from current buffer?
705  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
706  {
707  //Calculate the number of bytes to read at a time
709  //Copy data from receive buffer
710  osMemcpy((uint8_t *) temp + length, rxBuffer[rxBufferIndex], n);
711  //Update byte counters
712  length += n;
713  size -= n;
714  }
715 
716  //Mark the current buffer as free
717  rxBufferDesc[rxBufferIndex].address &= ~ETH_RX_OWNERSHIP;
718 
719  //Point to the following entry
720  rxBufferIndex++;
721 
722  //Wrap around to the beginning of the buffer if necessary
723  if(rxBufferIndex >= EFM32GG11_ETH_RX_BUFFER_COUNT)
724  {
725  rxBufferIndex = 0;
726  }
727  }
728 
729  //Any packet to process?
730  if(length > 0)
731  {
732  NetRxAncillary ancillary;
733 
734  //Additional options can be passed to the stack along with the packet
735  ancillary = NET_DEFAULT_RX_ANCILLARY;
736 
737  //Pass the packet to the upper layer
738  nicProcessPacket(interface, (uint8_t *) temp, length, &ancillary);
739  //Valid packet received
740  error = NO_ERROR;
741  }
742  else
743  {
744  //No more data in the receive buffer
745  error = ERROR_BUFFER_EMPTY;
746  }
747 
748  //Return status code
749  return error;
750 }
751 
752 
753 /**
754  * @brief Configure MAC address filtering
755  * @param[in] interface Underlying network interface
756  * @return Error code
757  **/
758 
760 {
761  uint_t i;
762  uint_t j;
763  uint_t k;
764  uint8_t *p;
765  uint32_t hashTable[2];
766  MacAddr unicastMacAddr[3];
767  MacFilterEntry *entry;
768 
769  //Debug message
770  TRACE_DEBUG("Updating MAC filter...\r\n");
771 
772  //Set the MAC address of the station
773  ETH->SPECADDR1BOTTOM = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
774  ETH->SPECADDR1TOP = interface->macAddr.w[2];
775 
776  //The MAC supports 3 additional addresses for unicast perfect filtering
777  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
778  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
779  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
780 
781  //The hash table is used for multicast address filtering
782  hashTable[0] = 0;
783  hashTable[1] = 0;
784 
785  //The MAC address filter contains the list of MAC addresses to accept
786  //when receiving an Ethernet frame
787  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
788  {
789  //Point to the current entry
790  entry = &interface->macAddrFilter[i];
791 
792  //Valid entry?
793  if(entry->refCount > 0)
794  {
795  //Multicast address?
796  if(macIsMulticastAddr(&entry->addr))
797  {
798  //Point to the MAC address
799  p = entry->addr.b;
800 
801  //Apply the hash function
802  k = (p[0] >> 6) ^ p[0];
803  k ^= (p[1] >> 4) ^ (p[1] << 2);
804  k ^= (p[2] >> 2) ^ (p[2] << 4);
805  k ^= (p[3] >> 6) ^ p[3];
806  k ^= (p[4] >> 4) ^ (p[4] << 2);
807  k ^= (p[5] >> 2) ^ (p[5] << 4);
808 
809  //The hash value is reduced to a 6-bit index
810  k &= 0x3F;
811 
812  //Update hash table contents
813  hashTable[k / 32] |= (1 << (k % 32));
814  }
815  else
816  {
817  //Up to 3 additional MAC addresses can be specified
818  if(j < 3)
819  {
820  //Save the unicast address
821  unicastMacAddr[j++] = entry->addr;
822  }
823  }
824  }
825  }
826 
827  //Configure the first unicast address filter
828  if(j >= 1)
829  {
830  //The address is activated when SAT register is written
831  ETH->SPECADDR2BOTTOM = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
832  ETH->SPECADDR2TOP = unicastMacAddr[0].w[2];
833  }
834  else
835  {
836  //The address is deactivated when SAB register is written
837  ETH->SPECADDR2BOTTOM = 0;
838  }
839 
840  //Configure the second unicast address filter
841  if(j >= 2)
842  {
843  //The address is activated when SAT register is written
844  ETH->SPECADDR3BOTTOM = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
845  ETH->SPECADDR3TOP = unicastMacAddr[1].w[2];
846  }
847  else
848  {
849  //The address is deactivated when SAB register is written
850  ETH->SPECADDR3BOTTOM = 0;
851  }
852 
853  //Configure the third unicast address filter
854  if(j >= 3)
855  {
856  //The address is activated when SAT register is written
857  ETH->SPECADDR4BOTTOM = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
858  ETH->SPECADDR4TOP = unicastMacAddr[2].w[2];
859  }
860  else
861  {
862  //The address is deactivated when SAB register is written
863  ETH->SPECADDR4BOTTOM = 0;
864  }
865 
866  //Configure the multicast hash table
867  ETH->HASHBOTTOM = hashTable[0];
868  ETH->HASHTOP = hashTable[1];
869 
870  //Debug message
871  TRACE_DEBUG(" HASHBOTTOM = %08" PRIX32 "\r\n", ETH->HASHBOTTOM);
872  TRACE_DEBUG(" HASHTOP = %08" PRIX32 "\r\n", ETH->HASHTOP);
873 
874  //Successful processing
875  return NO_ERROR;
876 }
877 
878 
879 /**
880  * @brief Adjust MAC configuration parameters for proper operation
881  * @param[in] interface Underlying network interface
882  * @return Error code
883  **/
884 
886 {
887  uint32_t config;
888 
889  //Read network configuration register
890  config = ETH->NETWORKCFG;
891 
892  //10BASE-T or 100BASE-TX operation mode?
893  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
894  {
895  config |= _ETH_NETWORKCFG_SPEED_MASK;
896  }
897  else
898  {
899  config &= ~_ETH_NETWORKCFG_SPEED_MASK;
900  }
901 
902  //Half-duplex or full-duplex mode?
903  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
904  {
905  config |= _ETH_NETWORKCFG_FULLDUPLEX_MASK;
906  }
907  else
908  {
909  config &= ~_ETH_NETWORKCFG_FULLDUPLEX_MASK;
910  }
911 
912  //Write configuration value back to ETH_NETWORKCFG register
913  ETH->NETWORKCFG = config;
914 
915  //Successful processing
916  return NO_ERROR;
917 }
918 
919 
920 /**
921  * @brief Write PHY register
922  * @param[in] opcode Access type (2 bits)
923  * @param[in] phyAddr PHY address (5 bits)
924  * @param[in] regAddr Register address (5 bits)
925  * @param[in] data Register value
926  **/
927 
928 void efm32gg11EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
929  uint8_t regAddr, uint16_t data)
930 {
931  uint32_t temp;
932 
933  //Valid opcode?
934  if(opcode == SMI_OPCODE_WRITE)
935  {
936  //Set up a write operation
937  temp = _ETH_PHYMNGMNT_WRITE1_MASK;
938  temp |= (1 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
939  temp |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
940 
941  //PHY address
942  temp |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
943  //Register address
944  temp |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
945  //Register value
946  temp |= data & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
947 
948  //Start a write operation
949  ETH->PHYMNGMNT = temp;
950  //Wait for the write to complete
951  while((ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK) == 0)
952  {
953  }
954  }
955  else
956  {
957  //The MAC peripheral only supports standard Clause 22 opcodes
958  }
959 }
960 
961 
962 /**
963  * @brief Read PHY register
964  * @param[in] opcode Access type (2 bits)
965  * @param[in] phyAddr PHY address (5 bits)
966  * @param[in] regAddr Register address (5 bits)
967  * @return Register value
968  **/
969 
970 uint16_t efm32gg11EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
971  uint8_t regAddr)
972 {
973  uint16_t data;
974  uint32_t temp;
975 
976  //Valid opcode?
977  if(opcode == SMI_OPCODE_READ)
978  {
979  //Set up a read operation
980  temp = _ETH_PHYMNGMNT_WRITE1_MASK;
981  temp |= (2 << _ETH_PHYMNGMNT_OPERATION_SHIFT) & _ETH_PHYMNGMNT_OPERATION_MASK;
982  temp |= (2 << _ETH_PHYMNGMNT_WRITE10_SHIFT) & _ETH_PHYMNGMNT_WRITE10_MASK;
983 
984  //PHY address
985  temp |= (phyAddr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) & _ETH_PHYMNGMNT_PHYADDR_MASK;
986  //Register address
987  temp |= (regAddr << _ETH_PHYMNGMNT_REGADDR_SHIFT) & _ETH_PHYMNGMNT_REGADDR_MASK;
988 
989  //Start a read operation
990  ETH->PHYMNGMNT = temp;
991  //Wait for the read to complete
992  while((ETH->NETWORKSTATUS & _ETH_NETWORKSTATUS_MANDONE_MASK) == 0)
993  {
994  }
995 
996  //Get register value
997  data = ETH->PHYMNGMNT & _ETH_PHYMNGMNT_PHYRWDATA_MASK;
998  }
999  else
1000  {
1001  //The MAC peripheral only supports standard Clause 22 opcodes
1002  data = 0;
1003  }
1004 
1005  //Return the value of the PHY register
1006  return data;
1007 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
void efm32gg11EthTick(NetInterface *interface)
EFM32GG11 Ethernet MAC timer handler.
uint16_t efm32gg11EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t efm32gg11EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t efm32gg11EthReceivePacket(NetInterface *interface)
Receive a packet.
void efm32gg11EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t efm32gg11EthInit(NetInterface *interface)
EFM32GG11 Ethernet MAC initialization.
error_t efm32gg11EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t efm32gg11EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void ETH_IRQHandler(void)
EFM32GG11 Ethernet MAC interrupt service routine.
void efm32gg11EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
const NicDriver efm32gg11EthDriver
EFM32GG11 Ethernet MAC driver.
void efm32gg11EthEnableIrq(NetInterface *interface)
Enable interrupts.
void efm32gg11EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
__weak_func void efm32gg11EthInitGpio(NetInterface *interface)
GPIO configuration.
void efm32gg11EthEventHandler(NetInterface *interface)
EFM32GG11 Ethernet MAC event handler.
EFM32 Giant Gecko 11 Ethernet MAC driver.
#define EFM32GG11_ETH_TX_BUFFER_COUNT
#define ETH_TX_LAST
#define EFM32GG11_ETH_RX_BUFFER_SIZE
#define ETH_TX_WRAP
#define EFM32GG11_ETH_IRQ_SUB_PRIORITY
#define ETH_RX_EOF
#define ETH_RX_SOF
#define ETH_TX_LENGTH
#define EFM32GG11_ETH_IRQ_PRIORITY_GROUPING
#define EFM32GG11_ETH_RX_BUFFER_COUNT
#define ETH_TX_USED
#define ETH_RX_ADDRESS
#define EFM32GG11_ETH_IRQ_GROUP_PRIORITY
#define EFM32GG11_ETH_TX_BUFFER_SIZE
#define ETH_RX_WRAP
#define ETH_RX_OWNERSHIP
#define ETH_RX_LENGTH
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
Receive buffer descriptor.
Transmit buffer descriptor.
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368