32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "esp_crypto_lock.h"
36 #include "soc/hwcrypto_reg.h"
37 #include "soc/dport_access.h"
38 #include "esp_private/periph_ctrl.h"
47 #if (ESP32_CRYPTO_PKC_SUPPORT == ENABLED)
57 periph_module_enable(PERIPH_RSA_MODULE);
62 while(DPORT_REG_READ(RSA_CLEAN_REG) == 0)
68 #if (MPI_SUPPORT == ENABLED)
92 if(aLen <= 64 && bLen <= 64)
101 esp_crypto_mpi_lock_acquire();
104 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
106 DPORT_REG_WRITE(RSA_MULT_MODE_REG, (
n / 8) - 1 + 8);
109 for(i = 0; i <
n; i++)
113 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a->data[i]);
117 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
123 for(i = 0; i <
n; i++)
125 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
130 for(i = 0; i <
n; i++)
134 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4,
b->data[i]);
138 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4, 0);
143 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
146 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
151 r->sign = (
a->sign ==
b->sign) ? 1 : -1;
160 DPORT_INTERRUPT_DISABLE();
163 for(i = 0; i <
r->size; i++)
167 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
176 DPORT_INTERRUPT_RESTORE();
180 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
183 esp_crypto_mpi_lock_release();
226 if(modLen > 0 && modLen <= 128 && expLen > 0 && expLen <= 128)
229 n =
MAX(modLen, expLen);
255 esp_crypto_mpi_lock_acquire();
258 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
260 DPORT_REG_WRITE(RSA_MODEXP_MODE_REG, (
n / 16) - 1);
263 for(i = 0; i <
n; i++)
267 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
t.data[i]);
271 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
276 for(i = 0; i <
n; i++)
280 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, e->
data[i]);
284 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, 0);
289 for(i = 0; i <
n; i++)
293 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4,
p->data[i]);
297 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, 0);
302 for(i = 0; i <
n; i++)
306 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2.
data[i]);
310 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0);
315 for(
m =
p->data[0], i = 0; i < 4; i++)
317 m =
m * (2U -
m *
p->data[0]);
324 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
327 DPORT_REG_WRITE(RSA_MODEXP_START_REG, 1);
330 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
341 DPORT_INTERRUPT_DISABLE();
344 for(i = 0; i <
r->size; i++)
348 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
357 DPORT_INTERRUPT_RESTORE();
361 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
364 esp_crypto_mpi_lock_release();
382 #if (EC_SUPPORT == ENABLED)
404 esp_crypto_mpi_lock_acquire();
407 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
409 DPORT_REG_WRITE(RSA_MULT_MODE_REG, (
m / 8) - 1 + 8);
412 for(i = 0; i <
m; i++)
416 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
420 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
426 for(i = 0; i <
m; i++)
428 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
433 for(i = 0; i <
m; i++)
437 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
m + i) * 4,
b[i]);
441 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
m + i) * 4, 0);
446 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
449 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
454 DPORT_INTERRUPT_DISABLE();
460 for(i = 0; i <
n; i++)
462 rl[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
470 for(i = 0; i <
n; i++)
472 rh[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4);
477 DPORT_INTERRUPT_RESTORE();
479 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
482 esp_crypto_mpi_lock_release();