32 #define TRACE_LEVEL NIC_TRACE_LEVEL
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 4
50 #pragma data_alignment = 4
53 #pragma data_alignment = 4
56 #pragma data_alignment = 4
119 TRACE_INFO(
"Initializing FM3 Ethernet MAC (ETHER0)...\r\n");
122 nicDriverInterface = interface;
128 FM3_ETHERNET_CONTROL->ETH_CLKG_f.MACEN0 = 1;
131 FM3_ETHERNET_CONTROL->ETH_MODE_f.RST0 = 1;
132 FM3_ETHERNET_CONTROL->ETH_MODE_f.RST0 = 0;
135 FM3_ETHERNET_MAC0->BMR_f.SWR = 1;
137 while(FM3_ETHERNET_MAC0->BMR_f.SWR)
142 while(FM3_ETHERNET_MAC0->AHBSR_f.AHBS)
147 FM3_ETHERNET_MAC0->GAR_f.CR = 5;
150 if(interface->phyDriver != NULL)
153 error = interface->phyDriver->init(interface);
155 else if(interface->switchDriver != NULL)
158 error = interface->switchDriver->init(interface);
173 FM3_ETHERNET_MAC0->MCR = 0;
174 FM3_ETHERNET_MAC0->MCR_f.PS = 1;
175 FM3_ETHERNET_MAC0->MCR_f.DO = 1;
178 FM3_ETHERNET_MAC0->MAR0L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
179 FM3_ETHERNET_MAC0->MAR0H = interface->macAddr.w[2];
182 FM3_ETHERNET_MAC0->MHTRL = 0;
183 FM3_ETHERNET_MAC0->MHTRH = 0;
186 FM3_ETHERNET_MAC0->MFFR = 0;
187 FM3_ETHERNET_MAC0->MFFR_f.HPF = 1;
188 FM3_ETHERNET_MAC0->MFFR_f.HMC = 1;
191 FM3_ETHERNET_MAC0->FCR = 0;
194 FM3_ETHERNET_MAC0->OMR = 0;
195 FM3_ETHERNET_MAC0->OMR_f.RSF = 1;
196 FM3_ETHERNET_MAC0->OMR_f.TSF = 1;
199 FM3_ETHERNET_MAC0->BMR = 0;
200 FM3_ETHERNET_MAC0->BMR_f.TXPR = 0;
201 FM3_ETHERNET_MAC0->BMR_f.MB = 1;
202 FM3_ETHERNET_MAC0->BMR_f.AAL = 0;
203 FM3_ETHERNET_MAC0->BMR_f._8XPBL = 0;
204 FM3_ETHERNET_MAC0->BMR_f.USP = 1;
205 FM3_ETHERNET_MAC0->BMR_f.RPBL = 32;
206 FM3_ETHERNET_MAC0->BMR_f.FB = 0;
207 FM3_ETHERNET_MAC0->BMR_f.PR = 0;
208 FM3_ETHERNET_MAC0->BMR_f.PBL = 32;
209 FM3_ETHERNET_MAC0->BMR_f.ATDS = 1;
210 FM3_ETHERNET_MAC0->BMR_f.DSL = 0;
211 FM3_ETHERNET_MAC0->BMR_f.DA = 0;
218 FM3_ETHERNET_MAC0->mmc_intr_mask_tx = 0xFFFFFFFF;
219 FM3_ETHERNET_MAC0->mmc_intr_mask_rx = 0xFFFFFFFF;
220 FM3_ETHERNET_MAC0->mmc_ipc_intr_mask_rx = 0xFFFFFFFF;
223 bFM3_ETHERNET_MAC0_IMR_LPIIM = 1;
224 bFM3_ETHERNET_MAC0_IMR_TSIM = 1;
225 bFM3_ETHERNET_MAC0_IMR_PIM = 1;
226 bFM3_ETHERNET_MAC0_IMR_RGIM = 1;
229 bFM3_ETHERNET_MAC0_IER_TIE = 1;
230 bFM3_ETHERNET_MAC0_IER_RIE = 1;
231 bFM3_ETHERNET_MAC0_IER_NIE = 1;
241 bFM3_ETHERNET_MAC0_MCR_TE = 1;
242 bFM3_ETHERNET_MAC0_MCR_RE = 1;
245 bFM3_ETHERNET_MAC0_OMR_ST = 1;
246 bFM3_ETHERNET_MAC0_OMR_SR = 1;
264 #if defined(USE_SK_FM3_176PMC_ETH)
266 FM3_ETHERNET_CONTROL->ETH_MODE_f.IFMODE = 1;
269 FM3_GPIO->PFRC_f.P3 = 1;
271 FM3_GPIO->PFRC_f.P4 = 1;
273 FM3_GPIO->PFRC_f.P5 = 1;
275 FM3_GPIO->PFRC_f.P6 = 1;
277 FM3_GPIO->PFRC_f.P7 = 1;
279 FM3_GPIO->PFRC_f.P8 = 1;
281 FM3_GPIO->PFRD_f.P1 = 1;
283 FM3_GPIO->PFRD_f.P2 = 1;
285 FM3_GPIO->PFRD_f.P3 = 1;
288 FM3_GPIO->EPFR14_f.E_TD0E = 1;
289 FM3_GPIO->EPFR14_f.E_TE0E = 1;
290 FM3_GPIO->EPFR14_f.E_MC0E = 1;
291 FM3_GPIO->EPFR14_f.E_MD0B = 1;
292 FM3_GPIO->EPFR14_f.E_SPLC0 = 0;
293 FM3_GPIO->EPFR14_f.E_SPLC1 = 1;
296 FM3_GPIO->PFR4_f.P5 = 0;
297 FM3_GPIO->DDR4_f.P5 = 1;
300 FM3_GPIO->PDOR4_f.P5 = 0;
302 FM3_GPIO->PDOR4_f.P5 = 1;
367 FM3_ETHERNET_MAC0->TDLAR = (uint32_t)
txDmaDesc;
369 FM3_ETHERNET_MAC0->RDLAR = (uint32_t)
rxDmaDesc;
385 if(interface->phyDriver != NULL)
388 interface->phyDriver->tick(interface);
390 else if(interface->switchDriver != NULL)
393 interface->switchDriver->tick(interface);
410 NVIC_EnableIRQ(ETHER0_CAN0_IRQn);
413 if(interface->phyDriver != NULL)
416 interface->phyDriver->enableIrq(interface);
418 else if(interface->switchDriver != NULL)
421 interface->switchDriver->enableIrq(interface);
438 NVIC_DisableIRQ(ETHER0_CAN0_IRQn);
441 if(interface->phyDriver != NULL)
444 interface->phyDriver->disableIrq(interface);
446 else if(interface->switchDriver != NULL)
449 interface->switchDriver->disableIrq(interface);
474 status = FM3_ETHERNET_MAC0->SR;
497 nicDriverInterface->nicEvent =
TRUE;
576 FM3_ETHERNET_MAC0->TPDR = 0;
656 FM3_ETHERNET_MAC0->RPDR = 0;
674 uint32_t hashTable[2];
681 FM3_ETHERNET_MAC0->MAR0L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
682 FM3_ETHERNET_MAC0->MAR0H = interface->macAddr.w[2];
693 entry = &interface->macAddrFilter[i];
703 k = (crc >> 26) & 0x3F;
706 hashTable[k / 32] |= (1 << (k % 32));
711 FM3_ETHERNET_MAC0->MHTRL = hashTable[0];
712 FM3_ETHERNET_MAC0->MHTRH = hashTable[1];
715 TRACE_DEBUG(
" MACHTLR = %08" PRIX32
"\r\n", FM3_ETHERNET_MAC0->MHTRL);
716 TRACE_DEBUG(
" MACHTHR = %08" PRIX32
"\r\n", FM3_ETHERNET_MAC0->MHTRH);
731 stc_ethernet_mac_mcr_field_t config;
734 config = FM3_ETHERNET_MAC0->MCR_f;
757 FM3_ETHERNET_MAC0->MCR_f = config;
779 FM3_ETHERNET_MAC0->GAR_f.GW = 1;
781 FM3_ETHERNET_MAC0->GAR_f.PA = phyAddr;
783 FM3_ETHERNET_MAC0->GAR_f.GR =
regAddr;
786 FM3_ETHERNET_MAC0->GDR_f.GD =
data;
789 FM3_ETHERNET_MAC0->GAR_f.GB = 1;
791 while(FM3_ETHERNET_MAC0->GAR_f.GB)
819 FM3_ETHERNET_MAC0->GAR_f.GW = 0;
821 FM3_ETHERNET_MAC0->GAR_f.PA = phyAddr;
823 FM3_ETHERNET_MAC0->GAR_f.GR =
regAddr;
826 FM3_ETHERNET_MAC0->GAR_f.GB = 1;
828 while(FM3_ETHERNET_MAC0->GAR_f.GB)
833 data = FM3_ETHERNET_MAC0->GDR_f.GD;
861 p = (uint8_t *)
data;
866 for(i = 0; i <
length; i++)
869 for(j = 0; j < 8; j++)
872 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
874 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
error_t fm3Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void fm3Eth1InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void fm3Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
void fm3Eth1Tick(NetInterface *interface)
FM3 Ethernet MAC timer handler.
error_t fm3Eth1Init(NetInterface *interface)
FM3 Ethernet MAC initialization.
void ETHER0_CAN0_IRQHandler(void)
FM3 Ethernet MAC interrupt service routine.
error_t fm3Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
__weak_func void fm3Eth1InitGpio(NetInterface *interface)
GPIO configuration.
void fm3Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t fm3Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t fm3Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
const NicDriver fm3Eth1Driver
FM3 Ethernet MAC driver (ETHER0 instance)
void fm3Eth1EventHandler(NetInterface *interface)
FM3 Ethernet MAC event handler.
uint16_t fm3Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t fm3Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void fm3Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
Cypress FM3 Ethernet MAC driver (ETHER0 instance)
#define FM3_ETH1_IRQ_PRIORITY_GROUPING
#define FM3_ETH1_IRQ_SUB_PRIORITY
#define FM3_ETH1_RX_BUFFER_SIZE
#define FM3_ETH1_IRQ_GROUP_PRIORITY
#define FM3_ETH1_RX_BUFFER_COUNT
#define FM3_ETH1_TX_BUFFER_COUNT
#define FM3_ETH1_TX_BUFFER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
Enhanced RX DMA descriptor.
Enhanced TX DMA descriptor.
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.