SmartFusion2 (M2Sxxx) Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	M2sxxxTxDmaDesc
	Transmit DMA descriptor. More...

struct	M2sxxxRxDmaDesc
	Receive DMA descriptor. More...

Macros
#define	M2SXXX_ETH_TX_BUFFER_COUNT 2

#define	M2SXXX_ETH_TX_BUFFER_SIZE 1536

#define	M2SXXX_ETH_RX_BUFFER_COUNT 4

#define	M2SXXX_ETH_RX_BUFFER_SIZE 1536

#define	M2SXXX_ETH_IRQ_PRIORITY_GROUPING 3

#define	M2SXXX_ETH_IRQ_GROUP_PRIORITY 12

#define	M2SXXX_ETH_IRQ_SUB_PRIORITY 0

#define	EDAC_CR_CAN_EDAC_EN 0x00000040

#define	EDAC_CR_USB_EDAC_EN 0x00000020

#define	EDAC_CR_MAC_EDAC_RX_EN 0x00000010

#define	EDAC_CR_MAC_EDAC_TX_EN 0x00000008

#define	EDAC_CR_ESRAM1_EDAC_EN 0x00000002

#define	EDAC_CR_ESRAM0_EDAC_EN 0x00000001

#define	MAC_CR_RGMII_TXC_DELAY_SEL 0x000001E0

#define	MAC_CR_ETH_PHY_MODE 0x0000001C

#define	MAC_CR_ETH_LINE_SPEED 0x00000003

#define	MAC_CR_ETH_PHY_MODE_RMII 0x00000000

#define	MAC_CR_ETH_PHY_MODE_TBI 0x00000008

#define	MAC_CR_ETH_PHY_MODE_MII 0x0000000C

#define	MAC_CR_ETH_PHY_MODE_GMII 0x00000010

#define	MAC_CR_ETH_LINE_SPEED_10MBPS 0x00000000

#define	MAC_CR_ETH_LINE_SPEED_100MBPS 0x00000001

#define	MAC_CR_ETH_LINE_SPEED_1000MBPS 0x00000002

#define	DMA_TX_CTRL_TX_EN 0x00000001

#define	DMA_TX_STATUS_TX_PKT_COUNT 0x00FF0000

#define	DMA_TX_STATUS_TX_BUS_ERROR 0x00000008

#define	DMA_TX_STATUS_TX_UNDERRUN 0x00000002

#define	DMA_TX_STATUS_TX_PKT_SENT 0x00000001

#define	DMA_RX_CTRL_RX_EN 0x00000001

#define	DMA_RX_STATUS_RX_PKT_COUNT 0x00FF0000

#define	DMA_RX_STATUS_RX_BUS_ERROR 0x00000008

#define	DMA_RX_STATUS_RX_OVERFLOW 0x00000004

#define	DMA_RX_STATUS_RX_PKT_RECEIVED 0x00000001

#define	DMA_IRQ_MASK_RX_BUS_ERROR 0x00000080

#define	DMA_IRQ_MASK_RX_OVERFLOW 0x00000040

#define	DMA_IRQ_MASK_RX_PKT_RECEIVED 0x00000010

#define	DMA_IRQ_MASK_TX_BUS_ERROR 0x00000008

#define	DMA_IRQ_MASK_TX_UNDERRUN 0x00000002

#define	DMA_IRQ_MASK_TX_PKT_SENT 0x00000001

#define	DMA_IRQ_RX_BUS_ERROR 0x00000080

#define	DMA_IRQ_RX_OVERFLOW 0x00000040

#define	DMA_IRQ_RX_PKT_RECEIVED 0x00000010

#define	DMA_IRQ_TX_BUS_ERROR 0x00000008

#define	DMA_IRQ_TX_UNDERRUN 0x00000002

#define	DMA_IRQ_TX_PKT_SENT 0x00000001

#define	CFG1_SOFT_RESET 0x80000000

#define	CFG1_SIMULATION_RESET 0x40000000

#define	CFG1_RESET_RX_MAC_CTRL 0x00080000

#define	CFG1_RESET_TX_MAC_CTRL 0x00040000

#define	CFG1_RESET_RX_FUNCTION 0x00020000

#define	CFG1_RESET_TX_FUNCTION 0x00010000

#define	CFG1_LOOP_BACK 0x00000100

#define	CFG1_RX_FLOW_CTRL_EN 0x00000020

#define	CFG1_TX_FLOW_CTRL_EN 0x00000010

#define	CFG1_SYNC_RX_EN 0x00000008

#define	CFG1_RX_EN 0x00000004

#define	CFG1_SYNC_TX_EN 0x00000002

#define	CFG1_TX_EN 0x00000001

#define	CFG2_PREAMBLE_LENGTH 0x0000F000

#define	CFG2_INTERFACE_MODE 0x00000300

#define	CFG2_HUGE FRAME_EN 0x00000020

#define	CFG2_LENGTH_FIELD_CHECK 0x00000010

#define	CFG2_PAD_CRC_EN 0x00000004

#define	CFG2_CRC_EN 0x00000002

#define	CFG2_FULL_DUPLEX 0x00000001

#define	CFG2_PREAMBLE_7 0x00007000

#define	CFG2_INTERFACE_MODE_NIBBLE 0x00000100

#define	CFG2_INTERFACE_MODE_BYTE 0x00000200

#define	MII_CONFIG_CLKSEL_DIV4 0x00000000

#define	MII_CONFIG_CLKSEL_DIV6 0x00000002

#define	MII_CONFIG_CLKSEL_DIV8 0x00000003

#define	MII_CONFIG_CLKSEL_DIV10 0x00000004

#define	MII_CONFIG_CLKSEL_DIV14 0x00000005

#define	MII_CONFIG_CLKSEL_DIV20 0x00000006

#define	MII_CONFIG_CLKSEL_DIV28 0x00000007

#define	MII_COMMAND_SCAN 0x00000002

#define	MII_COMMAND_READ 0x00000001

#define	MII_ADDRESS_PHY_ADDR 0x00001F00

#define	MII_ADDRESS_REG_ADDR 0x0000001F

#define	MII_ADDRESS_PHY_ADDR_POS 8

#define	MII_ADDRESS_REG_ADDR_POS 0

#define	MII_INDICATORS_NOT_VALID 0x00000004

#define	MII_INDICATORS_SCANNING 0x00000002

#define	MII_INDICATORS_BUSY 0x00000001

#define	INTERFACE_CTRL_RESET 0x80000000

#define	INTERFACE_CTRL_TBI_MODE 0x08000000

#define	INTERFACE_CTRL_GHD_MODE 0x04000000

#define	INTERFACE_CTRL_LHD_MODE 0x02000000

#define	INTERFACE_CTRL_PHY_MODE 0x01000000

#define	INTERFACE_CTRL_RESET_PERMII 0x00800000

#define	INTERFACE_CTRL_SPEED 0x00010000

#define	INTERFACE_CTRL_RESET_PE100X 0x00008000

#define	INTERFACE_CTRL_FORCE_QUIET 0x00000400

#define	INTERFACE_CTRL_NO_CIPHER 0x00000200

#define	INTERFACE_CTRL_DISABLE_LINK_FAIL 0x00000100

#define	INTERFACE_CTRL_EN_JABBER_PROTECT 0x00000001

#define	FIFO_CFG0_STFENRPLY 0x00080000

#define	FIFO_CFG0_FRFENRPLY 0x00040000

#define	FIFO_CFG0_SRFENRPLY 0x00020000

#define	FIFO_CFG0_WTMENRPLY 0x00010000

#define	FIFO_CFG0_FTFENREQ 0x00001000

#define	FIFO_CFG0_STFENREQ 0x00000800

#define	FIFO_CFG0_FRFENREQ 0x00000400

#define	FIFO_CFG0_SRFENREQ 0x00000200

#define	FIFO_CFG0_WTMENREQ 0x00000100

#define	FIFO_CFG0_HSTRSTFT 0x00000010

#define	FIFO_CFG0_HSTRSTST 0x00000008

#define	FIFO_CFG0_HSTRSTFR 0x00000004

#define	FIFO_CFG0_HSTRSTSR 0x00000002

#define	FIFO_CFG0_HSTRSTWT 0x00000001

#define	FIFO_CFG1_CFGSRTH 0x0FFF0000

#define	FIFO_CFG1_CFGXOFFRTX 0x0000FFFF

#define	FIFO_CFG1_DEFAULT_VALUE 0x0FFF0000

#define	FIFO_CFG2_CFGHWM 0x1FFF0000

#define	FIFO_CFG2_CFGLWM 0x00001FFF

#define	FIFO_CFG2_DEFAULT_VALUE 0x04000180

#define	FIFO_CFG3_CFGHWMFT 0x0FFF0000

#define	FIFO_CFG3_CFGFTTH 0x00000FFF

#define	FIFO_CFG3_DEFAULT_VALUE 0x0258FFFF

#define	FIFO_CFG4_HSTFLTRFRM 0x0003FFFF

#define	FIFO_CFG4_RECEIVE_LONG_EVENT 0x00020000

#define	FIFO_CFG4_VLAN 0x00010000

#define	FIFO_CFG4_CONTROL_NOT_PAUSE 0x00008000

#define	FIFO_CFG4_CONTROL_PAUSE 0x00004000

#define	FIFO_CFG4_CONTROL 0x00002000

#define	FIFO_CFG4_TRUNCATED 0x00001000

#define	FIFO_CFG4_LONG_EVENT 0x00000800

#define	FIFO_CFG4_DRIBBLE_NIBBLE 0x00000400

#define	FIFO_CFG4_BROADCAST 0x00000200

#define	FIFO_CFG4_MULTICAST 0x00000100

#define	FIFO_CFG4_RECEPTION_OK 0x00000080

#define	FIFO_CFG4_TYPE_ERROR 0x00000040

#define	FIFO_CFG4_LENGTH_ERROR 0x00000020

#define	FIFO_CFG4_INVALID_CRC 0x00000010

#define	FIFO_CFG4_RECEIVE_ERROR 0x00000008

#define	FIFO_CFG4_FALSE_CARRIER 0x00000004

#define	FIFO_CFG4_RX_DV_EVENT 0x00000002

#define	FIFO_CFG4_PRIOR_PKT_DROPPED 0x00000001

#define	FIFO_CFG5_CFGHDPLX 0x00400000

#define	FIFO_CFG5_SRFULL 0x00200000

#define	FIFO_CFG5_HSTSRFULLCLR 0x00100000

#define	FIFO_CFG5_CFGBYTMODE 0x00080000

#define	FIFO_CFG5_HSTDRPLT64 0x00040000

#define	FIFO_CFG5_HSTFLTRFRMDC 0x0003FFFF

#define	FIFO_CFG5_RECEIVE_LONG_EVENT 0x00020000

#define	FIFO_CFG5_VLAN 0x00010000

#define	FIFO_CFG5_CONTROL_NOT_PAUSE 0x00008000

#define	FIFO_CFG5_CONTROL_PAUSE 0x00004000

#define	FIFO_CFG5_CONTROL 0x00002000

#define	FIFO_CFG5_TRUNCATED 0x00001000

#define	FIFO_CFG5_LONG_EVENT 0x00000800

#define	FIFO_CFG5_DRIBBLE_NIBBLE 0x00000400

#define	FIFO_CFG5_BROADCAST 0x00000200

#define	FIFO_CFG5_MULTICAST 0x00000100

#define	FIFO_CFG5_RECEPTION_OK 0x00000080

#define	FIFO_CFG5_TYPE_ERROR 0x00000040

#define	FIFO_CFG5_LENGTH_ERROR 0x00000020

#define	FIFO_CFG5_INVALID_CRC 0x00000010

#define	FIFO_CFG5_RECEIVE_ERROR 0x00000008

#define	FIFO_CFG5_FALSE_CARRIER 0x00000004

#define	FIFO_CFG5_RX_DV_EVENT 0x00000002

#define	FIFO_CFG5_PRIOR_PKT_DROPPED 0x00000001

#define	DMA_DESC_EMPTY_FLAG 0x80000000

#define	DMA_DESC_SIZE_MASK 0x00000FFF

Functions
error_t	m2sxxxEthInit (NetInterface *interface)
	M2Sxxx Ethernet MAC initialization. More...

void	m2sxxxEthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	m2sxxxEthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	m2sxxxEthTick (NetInterface *interface)
	M2Sxxx Ethernet MAC timer handler. More...

void	m2sxxxEthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	m2sxxxEthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	m2sxxxEthEventHandler (NetInterface *interface)
	M2Sxxx Ethernet MAC event handler. More...

error_t	m2sxxxEthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	m2sxxxEthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	m2sxxxEthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	m2sxxxEthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	m2sxxxEthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	m2sxxxEthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

Variables
const NicDriver	m2sxxxEthDriver
	M2Sxxx Ethernet MAC driver. More...

Detailed Description

SmartFusion2 (M2Sxxx) Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.5.4

Definition in file m2sxxx_eth_driver.h.

Macro Definition Documentation

◆ CFG1_LOOP_BACK

#define CFG1_LOOP_BACK 0x00000100

Definition at line 149 of file m2sxxx_eth_driver.h.

◆ CFG1_RESET_RX_FUNCTION

#define CFG1_RESET_RX_FUNCTION 0x00020000

Definition at line 147 of file m2sxxx_eth_driver.h.

◆ CFG1_RESET_RX_MAC_CTRL

#define CFG1_RESET_RX_MAC_CTRL 0x00080000

Definition at line 145 of file m2sxxx_eth_driver.h.

◆ CFG1_RESET_TX_FUNCTION

#define CFG1_RESET_TX_FUNCTION 0x00010000

Definition at line 148 of file m2sxxx_eth_driver.h.

◆ CFG1_RESET_TX_MAC_CTRL

#define CFG1_RESET_TX_MAC_CTRL 0x00040000

Definition at line 146 of file m2sxxx_eth_driver.h.

◆ CFG1_RX_EN

#define CFG1_RX_EN 0x00000004

Definition at line 153 of file m2sxxx_eth_driver.h.

◆ CFG1_RX_FLOW_CTRL_EN

#define CFG1_RX_FLOW_CTRL_EN 0x00000020

Definition at line 150 of file m2sxxx_eth_driver.h.

◆ CFG1_SIMULATION_RESET

#define CFG1_SIMULATION_RESET 0x40000000

Definition at line 144 of file m2sxxx_eth_driver.h.

◆ CFG1_SOFT_RESET

#define CFG1_SOFT_RESET 0x80000000

Definition at line 143 of file m2sxxx_eth_driver.h.

◆ CFG1_SYNC_RX_EN

#define CFG1_SYNC_RX_EN 0x00000008

Definition at line 152 of file m2sxxx_eth_driver.h.

◆ CFG1_SYNC_TX_EN

#define CFG1_SYNC_TX_EN 0x00000002

Definition at line 154 of file m2sxxx_eth_driver.h.

◆ CFG1_TX_EN

#define CFG1_TX_EN 0x00000001

Definition at line 155 of file m2sxxx_eth_driver.h.

◆ CFG1_TX_FLOW_CTRL_EN

#define CFG1_TX_FLOW_CTRL_EN 0x00000010

Definition at line 151 of file m2sxxx_eth_driver.h.

◆ CFG2_CRC_EN

#define CFG2_CRC_EN 0x00000002

Definition at line 163 of file m2sxxx_eth_driver.h.

◆ CFG2_FULL_DUPLEX

#define CFG2_FULL_DUPLEX 0x00000001

Definition at line 164 of file m2sxxx_eth_driver.h.

◆ CFG2_HUGE

#define CFG2_HUGE FRAME_EN 0x00000020

Definition at line 160 of file m2sxxx_eth_driver.h.

◆ CFG2_INTERFACE_MODE

#define CFG2_INTERFACE_MODE 0x00000300

Definition at line 159 of file m2sxxx_eth_driver.h.

◆ CFG2_INTERFACE_MODE_BYTE

#define CFG2_INTERFACE_MODE_BYTE 0x00000200

Definition at line 169 of file m2sxxx_eth_driver.h.

◆ CFG2_INTERFACE_MODE_NIBBLE

#define CFG2_INTERFACE_MODE_NIBBLE 0x00000100

Definition at line 168 of file m2sxxx_eth_driver.h.

◆ CFG2_LENGTH_FIELD_CHECK

#define CFG2_LENGTH_FIELD_CHECK 0x00000010

Definition at line 161 of file m2sxxx_eth_driver.h.

◆ CFG2_PAD_CRC_EN

#define CFG2_PAD_CRC_EN 0x00000004

Definition at line 162 of file m2sxxx_eth_driver.h.

◆ CFG2_PREAMBLE_7

#define CFG2_PREAMBLE_7 0x00007000

Definition at line 166 of file m2sxxx_eth_driver.h.

◆ CFG2_PREAMBLE_LENGTH

#define CFG2_PREAMBLE_LENGTH 0x0000F000

Definition at line 158 of file m2sxxx_eth_driver.h.

◆ DMA_DESC_EMPTY_FLAG

#define DMA_DESC_EMPTY_FLAG 0x80000000

Definition at line 292 of file m2sxxx_eth_driver.h.

◆ DMA_DESC_SIZE_MASK

#define DMA_DESC_SIZE_MASK 0x00000FFF

Definition at line 293 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_RX_BUS_ERROR

#define DMA_IRQ_MASK_RX_BUS_ERROR 0x00000080

Definition at line 127 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_RX_OVERFLOW

#define DMA_IRQ_MASK_RX_OVERFLOW 0x00000040

Definition at line 128 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_RX_PKT_RECEIVED

#define DMA_IRQ_MASK_RX_PKT_RECEIVED 0x00000010

Definition at line 129 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_TX_BUS_ERROR

#define DMA_IRQ_MASK_TX_BUS_ERROR 0x00000008

Definition at line 130 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_TX_PKT_SENT

#define DMA_IRQ_MASK_TX_PKT_SENT 0x00000001

Definition at line 132 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_MASK_TX_UNDERRUN

#define DMA_IRQ_MASK_TX_UNDERRUN 0x00000002

Definition at line 131 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_RX_BUS_ERROR

#define DMA_IRQ_RX_BUS_ERROR 0x00000080

Definition at line 135 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_RX_OVERFLOW

#define DMA_IRQ_RX_OVERFLOW 0x00000040

Definition at line 136 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_RX_PKT_RECEIVED

#define DMA_IRQ_RX_PKT_RECEIVED 0x00000010

Definition at line 137 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_TX_BUS_ERROR

#define DMA_IRQ_TX_BUS_ERROR 0x00000008

Definition at line 138 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_TX_PKT_SENT

#define DMA_IRQ_TX_PKT_SENT 0x00000001

Definition at line 140 of file m2sxxx_eth_driver.h.

◆ DMA_IRQ_TX_UNDERRUN

#define DMA_IRQ_TX_UNDERRUN 0x00000002

Definition at line 139 of file m2sxxx_eth_driver.h.

◆ DMA_RX_CTRL_RX_EN

#define DMA_RX_CTRL_RX_EN 0x00000001

Definition at line 118 of file m2sxxx_eth_driver.h.

◆ DMA_RX_STATUS_RX_BUS_ERROR

#define DMA_RX_STATUS_RX_BUS_ERROR 0x00000008

Definition at line 122 of file m2sxxx_eth_driver.h.

◆ DMA_RX_STATUS_RX_OVERFLOW

#define DMA_RX_STATUS_RX_OVERFLOW 0x00000004

Definition at line 123 of file m2sxxx_eth_driver.h.

◆ DMA_RX_STATUS_RX_PKT_COUNT

#define DMA_RX_STATUS_RX_PKT_COUNT 0x00FF0000

Definition at line 121 of file m2sxxx_eth_driver.h.

◆ DMA_RX_STATUS_RX_PKT_RECEIVED

#define DMA_RX_STATUS_RX_PKT_RECEIVED 0x00000001

Definition at line 124 of file m2sxxx_eth_driver.h.

◆ DMA_TX_CTRL_TX_EN

#define DMA_TX_CTRL_TX_EN 0x00000001

Definition at line 109 of file m2sxxx_eth_driver.h.

◆ DMA_TX_STATUS_TX_BUS_ERROR

#define DMA_TX_STATUS_TX_BUS_ERROR 0x00000008

Definition at line 113 of file m2sxxx_eth_driver.h.

◆ DMA_TX_STATUS_TX_PKT_COUNT

#define DMA_TX_STATUS_TX_PKT_COUNT 0x00FF0000

Definition at line 112 of file m2sxxx_eth_driver.h.

◆ DMA_TX_STATUS_TX_PKT_SENT

#define DMA_TX_STATUS_TX_PKT_SENT 0x00000001

Definition at line 115 of file m2sxxx_eth_driver.h.

◆ DMA_TX_STATUS_TX_UNDERRUN

#define DMA_TX_STATUS_TX_UNDERRUN 0x00000002

Definition at line 114 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_CAN_EDAC_EN

#define EDAC_CR_CAN_EDAC_EN 0x00000040

Definition at line 87 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_ESRAM0_EDAC_EN

#define EDAC_CR_ESRAM0_EDAC_EN 0x00000001

Definition at line 92 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_ESRAM1_EDAC_EN

#define EDAC_CR_ESRAM1_EDAC_EN 0x00000002

Definition at line 91 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_MAC_EDAC_RX_EN

#define EDAC_CR_MAC_EDAC_RX_EN 0x00000010

Definition at line 89 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_MAC_EDAC_TX_EN

#define EDAC_CR_MAC_EDAC_TX_EN 0x00000008

Definition at line 90 of file m2sxxx_eth_driver.h.

◆ EDAC_CR_USB_EDAC_EN

#define EDAC_CR_USB_EDAC_EN 0x00000020

Definition at line 88 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_FRFENREQ

#define FIFO_CFG0_FRFENREQ 0x00000400

Definition at line 217 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_FRFENRPLY

#define FIFO_CFG0_FRFENRPLY 0x00040000

Definition at line 212 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_FTFENREQ

#define FIFO_CFG0_FTFENREQ 0x00001000

Definition at line 215 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_HSTRSTFR

#define FIFO_CFG0_HSTRSTFR 0x00000004

Definition at line 222 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_HSTRSTFT

#define FIFO_CFG0_HSTRSTFT 0x00000010

Definition at line 220 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_HSTRSTSR

#define FIFO_CFG0_HSTRSTSR 0x00000002

Definition at line 223 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_HSTRSTST

#define FIFO_CFG0_HSTRSTST 0x00000008

Definition at line 221 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_HSTRSTWT

#define FIFO_CFG0_HSTRSTWT 0x00000001

Definition at line 224 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_SRFENREQ

#define FIFO_CFG0_SRFENREQ 0x00000200

Definition at line 218 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_SRFENRPLY

#define FIFO_CFG0_SRFENRPLY 0x00020000

Definition at line 213 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_STFENREQ

#define FIFO_CFG0_STFENREQ 0x00000800

Definition at line 216 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_STFENRPLY

#define FIFO_CFG0_STFENRPLY 0x00080000

Definition at line 211 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_WTMENREQ

#define FIFO_CFG0_WTMENREQ 0x00000100

Definition at line 219 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG0_WTMENRPLY

#define FIFO_CFG0_WTMENRPLY 0x00010000

Definition at line 214 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG1_CFGSRTH

#define FIFO_CFG1_CFGSRTH 0x0FFF0000

Definition at line 227 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG1_CFGXOFFRTX

#define FIFO_CFG1_CFGXOFFRTX 0x0000FFFF

Definition at line 228 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG1_DEFAULT_VALUE

#define FIFO_CFG1_DEFAULT_VALUE 0x0FFF0000

Definition at line 230 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG2_CFGHWM

#define FIFO_CFG2_CFGHWM 0x1FFF0000

Definition at line 233 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG2_CFGLWM

#define FIFO_CFG2_CFGLWM 0x00001FFF

Definition at line 234 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG2_DEFAULT_VALUE

#define FIFO_CFG2_DEFAULT_VALUE 0x04000180

Definition at line 236 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG3_CFGFTTH

#define FIFO_CFG3_CFGFTTH 0x00000FFF

Definition at line 240 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG3_CFGHWMFT

#define FIFO_CFG3_CFGHWMFT 0x0FFF0000

Definition at line 239 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG3_DEFAULT_VALUE

#define FIFO_CFG3_DEFAULT_VALUE 0x0258FFFF

Definition at line 242 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_BROADCAST

#define FIFO_CFG4_BROADCAST 0x00000200

Definition at line 254 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_CONTROL

#define FIFO_CFG4_CONTROL 0x00002000

Definition at line 250 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_CONTROL_NOT_PAUSE

#define FIFO_CFG4_CONTROL_NOT_PAUSE 0x00008000

Definition at line 248 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_CONTROL_PAUSE

#define FIFO_CFG4_CONTROL_PAUSE 0x00004000

Definition at line 249 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_DRIBBLE_NIBBLE

#define FIFO_CFG4_DRIBBLE_NIBBLE 0x00000400

Definition at line 253 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_FALSE_CARRIER

#define FIFO_CFG4_FALSE_CARRIER 0x00000004

Definition at line 261 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_HSTFLTRFRM

#define FIFO_CFG4_HSTFLTRFRM 0x0003FFFF

Definition at line 245 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_INVALID_CRC

#define FIFO_CFG4_INVALID_CRC 0x00000010

Definition at line 259 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_LENGTH_ERROR

#define FIFO_CFG4_LENGTH_ERROR 0x00000020

Definition at line 258 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_LONG_EVENT

#define FIFO_CFG4_LONG_EVENT 0x00000800

Definition at line 252 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_MULTICAST

#define FIFO_CFG4_MULTICAST 0x00000100

Definition at line 255 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_PRIOR_PKT_DROPPED

#define FIFO_CFG4_PRIOR_PKT_DROPPED 0x00000001

Definition at line 263 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_RECEIVE_ERROR

#define FIFO_CFG4_RECEIVE_ERROR 0x00000008

Definition at line 260 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_RECEIVE_LONG_EVENT

#define FIFO_CFG4_RECEIVE_LONG_EVENT 0x00020000

Definition at line 246 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_RECEPTION_OK

#define FIFO_CFG4_RECEPTION_OK 0x00000080

Definition at line 256 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_RX_DV_EVENT

#define FIFO_CFG4_RX_DV_EVENT 0x00000002

Definition at line 262 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_TRUNCATED

#define FIFO_CFG4_TRUNCATED 0x00001000

Definition at line 251 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_TYPE_ERROR

#define FIFO_CFG4_TYPE_ERROR 0x00000040

Definition at line 257 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG4_VLAN

#define FIFO_CFG4_VLAN 0x00010000

Definition at line 247 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_BROADCAST

#define FIFO_CFG5_BROADCAST 0x00000200

Definition at line 280 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_CFGBYTMODE

#define FIFO_CFG5_CFGBYTMODE 0x00080000

Definition at line 269 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_CFGHDPLX

#define FIFO_CFG5_CFGHDPLX 0x00400000

Definition at line 266 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_CONTROL

#define FIFO_CFG5_CONTROL 0x00002000

Definition at line 276 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_CONTROL_NOT_PAUSE

#define FIFO_CFG5_CONTROL_NOT_PAUSE 0x00008000

Definition at line 274 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_CONTROL_PAUSE

#define FIFO_CFG5_CONTROL_PAUSE 0x00004000

Definition at line 275 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_DRIBBLE_NIBBLE

#define FIFO_CFG5_DRIBBLE_NIBBLE 0x00000400

Definition at line 279 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_FALSE_CARRIER

#define FIFO_CFG5_FALSE_CARRIER 0x00000004

Definition at line 287 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_HSTDRPLT64

#define FIFO_CFG5_HSTDRPLT64 0x00040000

Definition at line 270 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_HSTFLTRFRMDC

#define FIFO_CFG5_HSTFLTRFRMDC 0x0003FFFF

Definition at line 271 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_HSTSRFULLCLR

#define FIFO_CFG5_HSTSRFULLCLR 0x00100000

Definition at line 268 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_INVALID_CRC

#define FIFO_CFG5_INVALID_CRC 0x00000010

Definition at line 285 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_LENGTH_ERROR

#define FIFO_CFG5_LENGTH_ERROR 0x00000020

Definition at line 284 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_LONG_EVENT

#define FIFO_CFG5_LONG_EVENT 0x00000800

Definition at line 278 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_MULTICAST

#define FIFO_CFG5_MULTICAST 0x00000100

Definition at line 281 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_PRIOR_PKT_DROPPED

#define FIFO_CFG5_PRIOR_PKT_DROPPED 0x00000001

Definition at line 289 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_RECEIVE_ERROR

#define FIFO_CFG5_RECEIVE_ERROR 0x00000008

Definition at line 286 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_RECEIVE_LONG_EVENT

#define FIFO_CFG5_RECEIVE_LONG_EVENT 0x00020000

Definition at line 272 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_RECEPTION_OK

#define FIFO_CFG5_RECEPTION_OK 0x00000080

Definition at line 282 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_RX_DV_EVENT

#define FIFO_CFG5_RX_DV_EVENT 0x00000002

Definition at line 288 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_SRFULL

#define FIFO_CFG5_SRFULL 0x00200000

Definition at line 267 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_TRUNCATED

#define FIFO_CFG5_TRUNCATED 0x00001000

Definition at line 277 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_TYPE_ERROR

#define FIFO_CFG5_TYPE_ERROR 0x00000040

Definition at line 283 of file m2sxxx_eth_driver.h.

◆ FIFO_CFG5_VLAN

#define FIFO_CFG5_VLAN 0x00010000

Definition at line 273 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_DISABLE_LINK_FAIL

#define INTERFACE_CTRL_DISABLE_LINK_FAIL 0x00000100

Definition at line 207 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_EN_JABBER_PROTECT

#define INTERFACE_CTRL_EN_JABBER_PROTECT 0x00000001

Definition at line 208 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_FORCE_QUIET

#define INTERFACE_CTRL_FORCE_QUIET 0x00000400

Definition at line 205 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_GHD_MODE

#define INTERFACE_CTRL_GHD_MODE 0x04000000

Definition at line 199 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_LHD_MODE

#define INTERFACE_CTRL_LHD_MODE 0x02000000

Definition at line 200 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_NO_CIPHER

#define INTERFACE_CTRL_NO_CIPHER 0x00000200

Definition at line 206 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_PHY_MODE

#define INTERFACE_CTRL_PHY_MODE 0x01000000

Definition at line 201 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_RESET

#define INTERFACE_CTRL_RESET 0x80000000

Definition at line 197 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_RESET_PE100X

#define INTERFACE_CTRL_RESET_PE100X 0x00008000

Definition at line 204 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_RESET_PERMII

#define INTERFACE_CTRL_RESET_PERMII 0x00800000

Definition at line 202 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_SPEED

#define INTERFACE_CTRL_SPEED 0x00010000

Definition at line 203 of file m2sxxx_eth_driver.h.

◆ INTERFACE_CTRL_TBI_MODE

#define INTERFACE_CTRL_TBI_MODE 0x08000000

Definition at line 198 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_IRQ_GROUP_PRIORITY

#define M2SXXX_ETH_IRQ_GROUP_PRIORITY 12

Definition at line 74 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_IRQ_PRIORITY_GROUPING

#define M2SXXX_ETH_IRQ_PRIORITY_GROUPING 3

Definition at line 67 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_IRQ_SUB_PRIORITY

#define M2SXXX_ETH_IRQ_SUB_PRIORITY 0

Definition at line 81 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_RX_BUFFER_COUNT

#define M2SXXX_ETH_RX_BUFFER_COUNT 4

Definition at line 53 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_RX_BUFFER_SIZE

#define M2SXXX_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_TX_BUFFER_COUNT

#define M2SXXX_ETH_TX_BUFFER_COUNT 2

Definition at line 39 of file m2sxxx_eth_driver.h.

◆ M2SXXX_ETH_TX_BUFFER_SIZE

#define M2SXXX_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_LINE_SPEED

#define MAC_CR_ETH_LINE_SPEED 0x00000003

Definition at line 97 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_LINE_SPEED_1000MBPS

#define MAC_CR_ETH_LINE_SPEED_1000MBPS 0x00000002

Definition at line 106 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_LINE_SPEED_100MBPS

#define MAC_CR_ETH_LINE_SPEED_100MBPS 0x00000001

Definition at line 105 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_LINE_SPEED_10MBPS

#define MAC_CR_ETH_LINE_SPEED_10MBPS 0x00000000

Definition at line 104 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_PHY_MODE

#define MAC_CR_ETH_PHY_MODE 0x0000001C

Definition at line 96 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_PHY_MODE_GMII

#define MAC_CR_ETH_PHY_MODE_GMII 0x00000010

Definition at line 102 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_PHY_MODE_MII

#define MAC_CR_ETH_PHY_MODE_MII 0x0000000C

Definition at line 101 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_PHY_MODE_RMII

#define MAC_CR_ETH_PHY_MODE_RMII 0x00000000

Definition at line 99 of file m2sxxx_eth_driver.h.

◆ MAC_CR_ETH_PHY_MODE_TBI

#define MAC_CR_ETH_PHY_MODE_TBI 0x00000008

Definition at line 100 of file m2sxxx_eth_driver.h.

◆ MAC_CR_RGMII_TXC_DELAY_SEL

#define MAC_CR_RGMII_TXC_DELAY_SEL 0x000001E0

Definition at line 95 of file m2sxxx_eth_driver.h.

◆ MII_ADDRESS_PHY_ADDR

#define MII_ADDRESS_PHY_ADDR 0x00001F00

Definition at line 185 of file m2sxxx_eth_driver.h.

◆ MII_ADDRESS_PHY_ADDR_POS

#define MII_ADDRESS_PHY_ADDR_POS 8

Definition at line 188 of file m2sxxx_eth_driver.h.

◆ MII_ADDRESS_REG_ADDR

#define MII_ADDRESS_REG_ADDR 0x0000001F

Definition at line 186 of file m2sxxx_eth_driver.h.

◆ MII_ADDRESS_REG_ADDR_POS

#define MII_ADDRESS_REG_ADDR_POS 0

Definition at line 189 of file m2sxxx_eth_driver.h.

◆ MII_COMMAND_READ

#define MII_COMMAND_READ 0x00000001

Definition at line 182 of file m2sxxx_eth_driver.h.

◆ MII_COMMAND_SCAN

#define MII_COMMAND_SCAN 0x00000002

Definition at line 181 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV10

#define MII_CONFIG_CLKSEL_DIV10 0x00000004

Definition at line 175 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV14

#define MII_CONFIG_CLKSEL_DIV14 0x00000005

Definition at line 176 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV20

#define MII_CONFIG_CLKSEL_DIV20 0x00000006

Definition at line 177 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV28

#define MII_CONFIG_CLKSEL_DIV28 0x00000007

Definition at line 178 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV4

#define MII_CONFIG_CLKSEL_DIV4 0x00000000

Definition at line 172 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV6

#define MII_CONFIG_CLKSEL_DIV6 0x00000002

Definition at line 173 of file m2sxxx_eth_driver.h.

◆ MII_CONFIG_CLKSEL_DIV8

#define MII_CONFIG_CLKSEL_DIV8 0x00000003

Definition at line 174 of file m2sxxx_eth_driver.h.

◆ MII_INDICATORS_BUSY

#define MII_INDICATORS_BUSY 0x00000001

Definition at line 194 of file m2sxxx_eth_driver.h.

◆ MII_INDICATORS_NOT_VALID

#define MII_INDICATORS_NOT_VALID 0x00000004

Definition at line 192 of file m2sxxx_eth_driver.h.

◆ MII_INDICATORS_SCANNING

#define MII_INDICATORS_SCANNING 0x00000002

Definition at line 193 of file m2sxxx_eth_driver.h.

Function Documentation

◆ m2sxxxEthDisableIrq()

void m2sxxxEthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 366 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthEnableIrq()

void m2sxxxEthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 338 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthEventHandler()

void m2sxxxEthEventHandler ( NetInterface * interface )

M2Sxxx Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 443 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthInit()

error_t m2sxxxEthInit ( NetInterface * interface )

M2Sxxx Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 114 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthInitDmaDesc()

void m2sxxxEthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 261 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthInitGpio()

void m2sxxxEthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 246 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthReadPhyReg()

uint16_t m2sxxxEthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 709 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthReceivePacket()

error_t m2sxxxEthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 533 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthSendPacket()

error_t m2sxxxEthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 473 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthTick()

void m2sxxxEthTick ( NetInterface * interface )

M2Sxxx Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 313 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthUpdateMacAddrFilter()

error_t m2sxxxEthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 598 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthUpdateMacConfig()

error_t m2sxxxEthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 611 of file m2sxxx_eth_driver.c.

◆ m2sxxxEthWritePhyReg()

void m2sxxxEthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 678 of file m2sxxx_eth_driver.c.

Variable Documentation

◆ m2sxxxEthDriver

const NicDriver m2sxxxEthDriver

extern

M2Sxxx Ethernet MAC driver.

Definition at line 87 of file m2sxxx_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ CFG1_LOOP_BACK

◆ CFG1_RESET_RX_FUNCTION

◆ CFG1_RESET_RX_MAC_CTRL

◆ CFG1_RESET_TX_FUNCTION

◆ CFG1_RESET_TX_MAC_CTRL

◆ CFG1_RX_EN

◆ CFG1_RX_FLOW_CTRL_EN

◆ CFG1_SIMULATION_RESET

◆ CFG1_SOFT_RESET

◆ CFG1_SYNC_RX_EN

◆ CFG1_SYNC_TX_EN

◆ CFG1_TX_EN

◆ CFG1_TX_FLOW_CTRL_EN

◆ CFG2_CRC_EN

◆ CFG2_FULL_DUPLEX

◆ CFG2_HUGE

◆ CFG2_INTERFACE_MODE

◆ CFG2_INTERFACE_MODE_BYTE

◆ CFG2_INTERFACE_MODE_NIBBLE

◆ CFG2_LENGTH_FIELD_CHECK

◆ CFG2_PAD_CRC_EN

◆ CFG2_PREAMBLE_7

◆ CFG2_PREAMBLE_LENGTH

◆ DMA_DESC_EMPTY_FLAG

◆ DMA_DESC_SIZE_MASK

◆ DMA_IRQ_MASK_RX_BUS_ERROR

◆ DMA_IRQ_MASK_RX_OVERFLOW

◆ DMA_IRQ_MASK_RX_PKT_RECEIVED

◆ DMA_IRQ_MASK_TX_BUS_ERROR

◆ DMA_IRQ_MASK_TX_PKT_SENT

◆ DMA_IRQ_MASK_TX_UNDERRUN

◆ DMA_IRQ_RX_BUS_ERROR

◆ DMA_IRQ_RX_OVERFLOW

◆ DMA_IRQ_RX_PKT_RECEIVED

◆ DMA_IRQ_TX_BUS_ERROR

◆ DMA_IRQ_TX_PKT_SENT

◆ DMA_IRQ_TX_UNDERRUN

◆ DMA_RX_CTRL_RX_EN

◆ DMA_RX_STATUS_RX_BUS_ERROR

◆ DMA_RX_STATUS_RX_OVERFLOW

◆ DMA_RX_STATUS_RX_PKT_COUNT

◆ DMA_RX_STATUS_RX_PKT_RECEIVED

◆ DMA_TX_CTRL_TX_EN

◆ DMA_TX_STATUS_TX_BUS_ERROR

◆ DMA_TX_STATUS_TX_PKT_COUNT

◆ DMA_TX_STATUS_TX_PKT_SENT

◆ DMA_TX_STATUS_TX_UNDERRUN

◆ EDAC_CR_CAN_EDAC_EN

◆ EDAC_CR_ESRAM0_EDAC_EN

◆ EDAC_CR_ESRAM1_EDAC_EN

◆ EDAC_CR_MAC_EDAC_RX_EN

◆ EDAC_CR_MAC_EDAC_TX_EN

◆ EDAC_CR_USB_EDAC_EN

◆ FIFO_CFG0_FRFENREQ

◆ FIFO_CFG0_FRFENRPLY

◆ FIFO_CFG0_FTFENREQ

◆ FIFO_CFG0_HSTRSTFR

◆ FIFO_CFG0_HSTRSTFT

◆ FIFO_CFG0_HSTRSTSR

◆ FIFO_CFG0_HSTRSTST

◆ FIFO_CFG0_HSTRSTWT

◆ FIFO_CFG0_SRFENREQ

◆ FIFO_CFG0_SRFENRPLY

◆ FIFO_CFG0_STFENREQ

◆ FIFO_CFG0_STFENRPLY

◆ FIFO_CFG0_WTMENREQ

◆ FIFO_CFG0_WTMENRPLY

◆ FIFO_CFG1_CFGSRTH

◆ FIFO_CFG1_CFGXOFFRTX

◆ FIFO_CFG1_DEFAULT_VALUE

◆ FIFO_CFG2_CFGHWM

◆ FIFO_CFG2_CFGLWM

◆ FIFO_CFG2_DEFAULT_VALUE