Nuvoton M467 Ethernet MAC driver. More...
#include "core/nic.h"Go to the source code of this file.
Data Structures | |
| struct | M467TxDmaDesc |
| Enhanced TX DMA descriptor. More... | |
| struct | M467RxDmaDesc |
| Enhanced RX DMA descriptor. More... | |
Macros | |
| #define | M467_ETH_TX_BUFFER_COUNT 3 |
| #define | M467_ETH_TX_BUFFER_SIZE 1536 |
| #define | M467_ETH_RX_BUFFER_COUNT 6 |
| #define | M467_ETH_RX_BUFFER_SIZE 1536 |
| #define | M467_ETH_IRQ_PRIORITY_GROUPING 3 |
| #define | M467_ETH_IRQ_GROUP_PRIORITY 12 |
| #define | M467_ETH_IRQ_SUB_PRIORITY 0 |
| #define | EMAC_MAC_CONFIG *((volatile uint32_t *) (EMAC_BASE + 0x0000)) |
| #define | EMAC_MAC_FRAME_FILTER *((volatile uint32_t *) (EMAC_BASE + 0x0004)) |
| #define | EMAC_GMII_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x0010)) |
| #define | EMAC_GMII_DATA *((volatile uint32_t *) (EMAC_BASE + 0x0014)) |
| #define | EMAC_FLOW_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x0018)) |
| #define | EMAC_VLAN_TAG *((volatile uint32_t *) (EMAC_BASE + 0x001C)) |
| #define | EMAC_VERSION *((volatile uint32_t *) (EMAC_BASE + 0x0020)) |
| #define | EMAC_DEBUG *((volatile uint32_t *) (EMAC_BASE + 0x0024)) |
| #define | EMAC_PMT_CONTROL_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x002C)) |
| #define | EMAC_INTERRUPT_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x0038)) |
| #define | EMAC_INTERRUPT_MASK *((volatile uint32_t *) (EMAC_BASE + 0x003C)) |
| #define | EMAC_MAC_ADDR0_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0040)) |
| #define | EMAC_MAC_ADDR0_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0044)) |
| #define | EMAC_MAC_ADDR1_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0048)) |
| #define | EMAC_MAC_ADDR1_LOW *((volatile uint32_t *) (EMAC_BASE + 0x004C)) |
| #define | EMAC_MAC_ADDR2_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0050)) |
| #define | EMAC_MAC_ADDR2_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0054)) |
| #define | EMAC_MAC_ADDR3_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0058)) |
| #define | EMAC_MAC_ADDR3_LOW *((volatile uint32_t *) (EMAC_BASE + 0x005C)) |
| #define | EMAC_MAC_ADDR4_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0060)) |
| #define | EMAC_MAC_ADDR4_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0064)) |
| #define | EMAC_MAC_ADDR5_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0068)) |
| #define | EMAC_MAC_ADDR5_LOW *((volatile uint32_t *) (EMAC_BASE + 0x006C)) |
| #define | EMAC_MAC_ADDR6_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0070)) |
| #define | EMAC_MAC_ADDR6_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0074)) |
| #define | EMAC_MAC_ADDR7_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0078)) |
| #define | EMAC_MAC_ADDR7_LOW *((volatile uint32_t *) (EMAC_BASE + 0x007C)) |
| #define | EMAC_MAC_ADDR8_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0080)) |
| #define | EMAC_MAC_ADDR8_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0084)) |
| #define | EMAC_WDOG_TIMEOUT *((volatile uint32_t *) (EMAC_BASE + 0x00DC)) |
| #define | EMAC_VLAN_INCL_REG *((volatile uint32_t *) (EMAC_BASE + 0x0584)) |
| #define | EMAC_TIMESTAMP_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x0700)) |
| #define | EMAC_SUB_SECOND_INCREMENT *((volatile uint32_t *) (EMAC_BASE + 0x0704)) |
| #define | EMAC_SYSTEM_TIME_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0708)) |
| #define | EMAC_SYSTEM_TIME_NANOSECONDS *((volatile uint32_t *) (EMAC_BASE + 0x070C)) |
| #define | EMAC_SYSTEM_TIME_SECONDS_UPDATE *((volatile uint32_t *) (EMAC_BASE + 0x0710)) |
| #define | EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE *((volatile uint32_t *) (EMAC_BASE + 0x0714)) |
| #define | EMAC_TIMESTAMP_ADDEND *((volatile uint32_t *) (EMAC_BASE + 0x0718)) |
| #define | EMAC_TARGET_TIME_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x071C)) |
| #define | EMAC_TARGET_TIME_NANOSECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0720)) |
| #define | EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0724)) |
| #define | EMAC_TIMESTAMP_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x0728)) |
| #define | EMAC_PPS_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x072C)) |
| #define | EMAC_PPS0_INTERVAL *((volatile uint32_t *) (EMAC_BASE + 0x0760)) |
| #define | EMAC_PPS0_WIDTH *((volatile uint32_t *) (EMAC_BASE + 0x0764)) |
| #define | EMAC_BUS_MODE *((volatile uint32_t *) (EMAC_BASE + 0x1000)) |
| #define | EMAC_TRANSMIT_POLL_DEMAND *((volatile uint32_t *) (EMAC_BASE + 0x1004)) |
| #define | EMAC_RECEIVE_POLL_DEMAND *((volatile uint32_t *) (EMAC_BASE + 0x1008)) |
| #define | EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x100C)) |
| #define | EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1010)) |
| #define | EMAC_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x1014)) |
| #define | EMAC_OPERATION_MODE *((volatile uint32_t *) (EMAC_BASE + 0x1018)) |
| #define | EMAC_INTERRUPT_ENABLE *((volatile uint32_t *) (EMAC_BASE + 0x101C)) |
| #define | EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT *((volatile uint32_t *) (EMAC_BASE + 0x1020)) |
| #define | EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER *((volatile uint32_t *) (EMAC_BASE + 0x1024)) |
| #define | EMAC_AHB_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x102C)) |
| #define | EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR *((volatile uint32_t *) (EMAC_BASE + 0x1048)) |
| #define | EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR *((volatile uint32_t *) (EMAC_BASE + 0x104C)) |
| #define | EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1050)) |
| #define | EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1054)) |
| #define | EMAC_HW_FEATURE *((volatile uint32_t *) (EMAC_BASE + 0x1058)) |
| #define | EMAC_MAC_CONFIG_SARC 0xF0000000 |
| #define | EMAC_MAC_CONFIG_TWOKPE 0x08000000 |
| #define | EMAC_MAC_CONFIG_CST 0x02000000 |
| #define | EMAC_MAC_CONFIG_WD 0x00800000 |
| #define | EMAC_MAC_CONFIG_JD 0x00400000 |
| #define | EMAC_MAC_CONFIG_JE 0x00100000 |
| #define | EMAC_MAC_CONFIG_IFG 0x000E0000 |
| #define | EMAC_MAC_CONFIG_DCRS 0x00010000 |
| #define | EMAC_MAC_CONFIG_FES 0x00004000 |
| #define | EMAC_MAC_CONFIG_DO 0x00002000 |
| #define | EMAC_MAC_CONFIG_LM 0x00001000 |
| #define | EMAC_MAC_CONFIG_DM 0x00000800 |
| #define | EMAC_MAC_CONFIG_IPC 0x00000400 |
| #define | EMAC_MAC_CONFIG_DR 0x00000200 |
| #define | EMAC_MAC_CONFIG_ACS 0x00000080 |
| #define | EMAC_MAC_CONFIG_BL 0x00000060 |
| #define | EMAC_MAC_CONFIG_DC 0x00000010 |
| #define | EMAC_MAC_CONFIG_TE 0x00000008 |
| #define | EMAC_MAC_CONFIG_RE 0x00000004 |
| #define | EMAC_MAC_CONFIG_PRELEN 0x00000003 |
| #define | EMAC_MAC_FRAME_FILTER_RA 0x80000000 |
| #define | EMAC_MAC_FRAME_FILTER_VTFE 0x00010000 |
| #define | EMAC_MAC_FRAME_FILTER_SAF 0x00000200 |
| #define | EMAC_MAC_FRAME_FILTER_SAIF 0x00000100 |
| #define | EMAC_MAC_FRAME_FILTER_PCF 0x000000C0 |
| #define | EMAC_MAC_FRAME_FILTER_DBF 0x00000020 |
| #define | EMAC_MAC_FRAME_FILTER_PM 0x00000010 |
| #define | EMAC_MAC_FRAME_FILTER_DAIF 0x00000008 |
| #define | EMAC_MAC_FRAME_FILTER_PR 0x00000001 |
| #define | EMAC_GMII_ADDR_PA 0x0000F800 |
| #define | EMAC_GMII_ADDR_GR 0x000007C0 |
| #define | EMAC_GMII_ADDR_CR 0x0000003C |
| #define | EMAC_GMII_ADDR_CR_DIV_42 0x00000000 |
| #define | EMAC_GMII_ADDR_CR_DIV_62 0x00000004 |
| #define | EMAC_GMII_ADDR_CR_DIV_16 0x00000008 |
| #define | EMAC_GMII_ADDR_CR_DIV_26 0x0000000C |
| #define | EMAC_GMII_ADDR_CR_DIV_102 0x00000010 |
| #define | EMAC_GMII_ADDR_CR_DIV_124 0x00000014 |
| #define | EMAC_GMII_ADDR_GW 0x00000002 |
| #define | EMAC_GMII_ADDR_GB 0x00000001 |
| #define | EMAC_GMII_DATA_GD 0x0000FFFF |
| #define | EMAC_FLOW_CONTROL_PT 0xFFFF0000 |
| #define | EMAC_FLOW_CONTROL_DZQP 0x00000080 |
| #define | EMAC_FLOW_CONTROL_PLT 0x00000030 |
| #define | EMAC_FLOW_CONTROL_UP 0x00000008 |
| #define | EMAC_FLOW_CONTROL_RFE 0x00000004 |
| #define | EMAC_FLOW_CONTROL_TFE 0x00000002 |
| #define | EMAC_FLOW_CONTROL_FCA_BPA 0x00000001 |
| #define | EMAC_VLAN_TAG_ESVL 0x00040000 |
| #define | EMAC_VLAN_TAG_VTIM 0x00020000 |
| #define | EMAC_VLAN_TAG_ETV 0x00010000 |
| #define | EMAC_VLAN_TAG_VL 0x0000FFFF |
| #define | EMAC_DEBUG_TXSTSFSTS 0x02000000 |
| #define | EMAC_DEBUG_TXFSTS 0x01000000 |
| #define | EMAC_DEBUG_TWCSTS 0x00400000 |
| #define | EMAC_DEBUG_TRCSTS 0x00300000 |
| #define | EMAC_DEBUG_TXPAUSED 0x00080000 |
| #define | EMAC_DEBUG_TFCSTS 0x00060000 |
| #define | EMAC_DEBUG_TPESTS 0x00010000 |
| #define | EMAC_DEBUG_RXFSTS 0x00000300 |
| #define | EMAC_DEBUG_RRCSTS 0x00000060 |
| #define | EMAC_DEBUG_RWCSTS 0x00000010 |
| #define | EMAC_DEBUG_RFCFCSTS 0x00000006 |
| #define | EMAC_DEBUG_RPESTS 0x00000001 |
| #define | EMAC_PMT_CONTROL_STATUS_MGKPRCVD 0x00000020 |
| #define | EMAC_PMT_CONTROL_STATUS_MGKPKTEN 0x00000002 |
| #define | EMAC_PMT_CONTROL_STATUS_PWRDWN 0x00000001 |
| #define | EMAC_INTERRUPT_STATUS_TSIS 0x00000200 |
| #define | EMAC_INTERRUPT_STATUS_PMTIS 0x00000008 |
| #define | EMAC_INTERRUPT_MASK_TSIM 0x00000200 |
| #define | EMAC_INTERRUPT_MASK_PMTIM 0x00000008 |
| #define | EMAC_MAC_ADDR0_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR0_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR0_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR1_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR1_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR1_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR1_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR1_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR2_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR2_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR2_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR2_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR2_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR3_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR3_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR3_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR3_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR3_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR4_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR4_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR4_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR4_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR4_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR5_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR5_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR5_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR5_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR5_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR6_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR6_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR6_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR6_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR6_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR7_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR7_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR7_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR7_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR7_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_MAC_ADDR8_HIGH_AE 0x80000000 |
| #define | EMAC_MAC_ADDR8_HIGH_SA 0x40000000 |
| #define | EMAC_MAC_ADDR8_HIGH_MBC 0x3F000000 |
| #define | EMAC_MAC_ADDR8_HIGH_ADDRHI 0x0000FFFF |
| #define | EMAC_MAC_ADDR8_LOW_ADDRLO 0xFFFFFFFF |
| #define | EMAC_WDOG_TIMEOUT_PWE 0x00010000 |
| #define | EMAC_WDOG_TIMEOUT_WTO 0x00003FFF |
| #define | EMAC_VLAN_INCL_REG_CSVL 0x00080000 |
| #define | EMAC_VLAN_INCL_REG_VLP 0x00040000 |
| #define | EMAC_VLAN_INCL_REG_VLC 0x00030000 |
| #define | EMAC_VLAN_INCL_REG_VLT 0x0000FFFF |
| #define | EMAC_TIMESTAMP_CONTROL_TSENMACADDR 0x00040000 |
| #define | EMAC_TIMESTAMP_CONTROL_SNAPTYPSEL 0x00030000 |
| #define | EMAC_TIMESTAMP_CONTROL_TSMSTRENA 0x00008000 |
| #define | EMAC_TIMESTAMP_CONTROL_TSEVNTENA 0x00004000 |
| #define | EMAC_TIMESTAMP_CONTROL_TSIPV4ENA 0x00002000 |
| #define | EMAC_TIMESTAMP_CONTROL_TSIPV6ENA 0x00001000 |
| #define | EMAC_TIMESTAMP_CONTROL_TSIPENA 0x00000800 |
| #define | EMAC_TIMESTAMP_CONTROL_TSVER2ENA 0x00000400 |
| #define | EMAC_TIMESTAMP_CONTROL_TSCTRLSSR 0x00000200 |
| #define | EMAC_TIMESTAMP_CONTROL_TSENALL 0x00000100 |
| #define | EMAC_TIMESTAMP_CONTROL_TSADDREG 0x00000020 |
| #define | EMAC_TIMESTAMP_CONTROL_TSTRIG 0x00000010 |
| #define | EMAC_TIMESTAMP_CONTROL_TSUPDT 0x00000008 |
| #define | EMAC_TIMESTAMP_CONTROL_TSINIT 0x00000004 |
| #define | EMAC_TIMESTAMP_CONTROL_TSCFUPDT 0x00000002 |
| #define | EMAC_TIMESTAMP_CONTROL_TSENA 0x00000001 |
| #define | EMAC_SUB_SECOND_INCREMENT_SSINC 0x000000FF |
| #define | EMAC_SYSTEM_TIME_SECONDS_TSS 0xFFFFFFFF |
| #define | EMAC_SYSTEM_TIME_NANOSECONDS_TSSS 0x7FFFFFFF |
| #define | EMAC_SYSTEM_TIME_SECONDS_UPDATE_TSS 0xFFFFFFFF |
| #define | EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB 0x80000000 |
| #define | EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS 0x7FFFFFFF |
| #define | EMAC_TIMESTAMP_ADDEND_TSAR 0xFFFFFFFF |
| #define | EMAC_TARGET_TIME_SECONDS_TSTR 0xFFFFFFFF |
| #define | EMAC_TARGET_TIME_NANOSECONDS_TTSLO 0xFFFFFFFF |
| #define | EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR 0x0000FFFF |
| #define | EMAC_TIMESTAMP_STATUS_ATSSTN 0x000F0000 |
| #define | EMAC_TIMESTAMP_STATUS_TSTRGTERR 0x00000008 |
| #define | EMAC_TIMESTAMP_STATUS_TSTARGT 0x00000002 |
| #define | EMAC_TIMESTAMP_STATUS_TSSOVF 0x00000001 |
| #define | EMAC_PPS_CONTROL_TRGTMODSEL0 0x00000060 |
| #define | EMAC_PPS_CONTROL_PPSEN0 0x00000010 |
| #define | EMAC_PPS_CONTROL_PPSCTRL_PPSCMD 0x0000000F |
| #define | EMAC_PPS0_INTERVAL_PPSINT 0xFFFFFFFF |
| #define | EMAC_PPS0_WIDTH_PPSWIDTH 0xFFFFFFFF |
| #define | EMAC_BUS_MODE_AAB 0x02000000 |
| #define | EMAC_BUS_MODE_PBLX8 0x01000000 |
| #define | EMAC_BUS_MODE_USP 0x00800000 |
| #define | EMAC_BUS_MODE_RPBL 0x007E0000 |
| #define | EMAC_BUS_MODE_RPBL_1 0x00020000 |
| #define | EMAC_BUS_MODE_RPBL_2 0x00040000 |
| #define | EMAC_BUS_MODE_RPBL_4 0x00080000 |
| #define | EMAC_BUS_MODE_RPBL_8 0x00100000 |
| #define | EMAC_BUS_MODE_RPBL_16 0x00200000 |
| #define | EMAC_BUS_MODE_RPBL_32 0x00400000 |
| #define | EMAC_BUS_MODE_FB 0x00010000 |
| #define | EMAC_BUS_MODE_PBL 0x00003F00 |
| #define | EMAC_BUS_MODE_PBL_1 0x00000100 |
| #define | EMAC_BUS_MODE_PBL_2 0x00000200 |
| #define | EMAC_BUS_MODE_PBL_4 0x00000400 |
| #define | EMAC_BUS_MODE_PBL_8 0x00000800 |
| #define | EMAC_BUS_MODE_PBL_16 0x00001000 |
| #define | EMAC_BUS_MODE_PBL_32 0x00002000 |
| #define | EMAC_BUS_MODE_ATDS 0x00000080 |
| #define | EMAC_BUS_MODE_DSL 0x0000007C |
| #define | EMAC_BUS_MODE_DSL_0 0x00000000 |
| #define | EMAC_BUS_MODE_DSL_1 0x00000004 |
| #define | EMAC_BUS_MODE_DSL_2 0x00000008 |
| #define | EMAC_BUS_MODE_DSL_4 0x00000010 |
| #define | EMAC_BUS_MODE_DSL_8 0x00000020 |
| #define | EMAC_BUS_MODE_DSL_16 0x00000040 |
| #define | EMAC_BUS_MODE_SWR 0x00000001 |
| #define | EMAC_TRANSMIT_POLL_DEMAND_TPD 0xFFFFFFFF |
| #define | EMAC_RECEIVE_POLL_DEMAND_RPD 0xFFFFFFFF |
| #define | EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR_RDESLA 0xFFFFFFFF |
| #define | EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR_TDESLA 0xFFFFFFFF |
| #define | EMAC_STATUS_TTI 0x20000000 |
| #define | EMAC_STATUS_GPI 0x10000000 |
| #define | EMAC_STATUS_EB 0x03800000 |
| #define | EMAC_STATUS_TS 0x00700000 |
| #define | EMAC_STATUS_RS 0x000E0000 |
| #define | EMAC_STATUS_NIS 0x00010000 |
| #define | EMAC_STATUS_AIS 0x00008000 |
| #define | EMAC_STATUS_ERI 0x00004000 |
| #define | EMAC_STATUS_FBI 0x00002000 |
| #define | EMAC_STATUS_ETI 0x00000400 |
| #define | EMAC_STATUS_RWT 0x00000200 |
| #define | EMAC_STATUS_RPS 0x00000100 |
| #define | EMAC_STATUS_RU 0x00000080 |
| #define | EMAC_STATUS_RI 0x00000040 |
| #define | EMAC_STATUS_UNF 0x00000020 |
| #define | EMAC_STATUS_OVF 0x00000010 |
| #define | EMAC_STATUS_TJT 0x00000008 |
| #define | EMAC_STATUS_TU 0x00000004 |
| #define | EMAC_STATUS_TPS 0x00000002 |
| #define | EMAC_STATUS_TI 0x00000001 |
| #define | EMAC_OPERATION_MODE_DT 0x04000000 |
| #define | EMAC_OPERATION_MODE_RSF 0x02000000 |
| #define | EMAC_OPERATION_MODE_DFF 0x01000000 |
| #define | EMAC_OPERATION_MODE_TSF 0x00200000 |
| #define | EMAC_OPERATION_MODE_FTF 0x00100000 |
| #define | EMAC_OPERATION_MODE_TTC 0x0001C000 |
| #define | EMAC_OPERATION_MODE_ST 0x00002000 |
| #define | EMAC_OPERATION_MODE_RFD 0x00001800 |
| #define | EMAC_OPERATION_MODE_RFA 0x00000600 |
| #define | EMAC_OPERATION_MODE_EFC 0x00000100 |
| #define | EMAC_OPERATION_MODE_FEF 0x00000080 |
| #define | EMAC_OPERATION_MODE_FUF 0x00000040 |
| #define | EMAC_OPERATION_MODE_DGF 0x00000020 |
| #define | EMAC_OPERATION_MODE_RTC 0x00000018 |
| #define | EMAC_OPERATION_MODE_OSF 0x00000004 |
| #define | EMAC_OPERATION_MODE_SR 0x00000002 |
| #define | EMAC_INTERRUPT_ENABLE_NIE 0x00010000 |
| #define | EMAC_INTERRUPT_ENABLE_AIE 0x00008000 |
| #define | EMAC_INTERRUPT_ENABLE_ERE 0x00004000 |
| #define | EMAC_INTERRUPT_ENABLE_FBE 0x00002000 |
| #define | EMAC_INTERRUPT_ENABLE_ETE 0x00000400 |
| #define | EMAC_INTERRUPT_ENABLE_RWE 0x00000200 |
| #define | EMAC_INTERRUPT_ENABLE_RSE 0x00000100 |
| #define | EMAC_INTERRUPT_ENABLE_RUE 0x00000080 |
| #define | EMAC_INTERRUPT_ENABLE_RIE 0x00000040 |
| #define | EMAC_INTERRUPT_ENABLE_UNE 0x00000020 |
| #define | EMAC_INTERRUPT_ENABLE_OVE 0x00000010 |
| #define | EMAC_INTERRUPT_ENABLE_TJE 0x00000008 |
| #define | EMAC_INTERRUPT_ENABLE_TUE 0x00000004 |
| #define | EMAC_INTERRUPT_ENABLE_TSE 0x00000002 |
| #define | EMAC_INTERRUPT_ENABLE_TIE 0x00000001 |
| #define | EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFCNTOVF 0x10000000 |
| #define | EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFFRMCNT 0x0FFE0000 |
| #define | EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISCNTOVF 0x00010000 |
| #define | EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISFRMCNT 0x0000FFFF |
| #define | EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT 0x000000FF |
| #define | EMAC_AHB_STATUS_AXIRDSTS 0x00000002 |
| #define | EMAC_AHB_STATUS_AXWHSTS 0x00000001 |
| #define | EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR 0xFFFFFFFF |
| #define | EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR 0xFFFFFFFF |
| #define | EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR_CURTBUFAPTR 0xFFFFFFFF |
| #define | EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR_CURRBUFAPTR 0xFFFFFFFF |
| #define | EMAC_HW_FEATURE_ACTPHYIF 0x70000000 |
| #define | EMAC_HW_FEATURE_SAVLANINS 0x08000000 |
| #define | EMAC_HW_FEATURE_FLEXIPPSEN 0x04000000 |
| #define | EMAC_HW_FEATURE_INTTSEN 0x02000000 |
| #define | EMAC_HW_FEATURE_ENHDESSEL 0x01000000 |
| #define | EMAC_HW_FEATURE_TXCHCNT 0x00C00000 |
| #define | EMAC_HW_FEATURE_RXCHCNT 0x00300000 |
| #define | EMAC_HW_FEATURE_RXFIFOSIZE 0x00080000 |
| #define | EMAC_HW_FEATURE_RXTYP2COE 0x00040000 |
| #define | EMAC_HW_FEATURE_RXTYP1COE 0x00020000 |
| #define | EMAC_HW_FEATURE_TXCOESEL 0x00010000 |
| #define | EMAC_HW_FEATURE_EEESEL 0x00004000 |
| #define | EMAC_HW_FEATURE_TSVER2SEL 0x00002000 |
| #define | EMAC_HW_FEATURE_TSVER1SEL 0x00001000 |
| #define | EMAC_HW_FEATURE_MMCSEL 0x00000800 |
| #define | EMAC_HW_FEATURE_MGKSEL 0x00000400 |
| #define | EMAC_HW_FEATURE_RWKSEL 0x00000200 |
| #define | EMAC_HW_FEATURE_SMASEL 0x00000100 |
| #define | EMAC_HW_FEATURE_L3L4FLTREN 0x00000080 |
| #define | EMAC_HW_FEATURE_PCSSEL 0x00000040 |
| #define | EMAC_HW_FEATURE_ADDMACADRSEL 0x00000020 |
| #define | EMAC_HW_FEATURE_HASHSEL 0x00000010 |
| #define | EMAC_HW_FEATURE_EXTHASHEN 0x00000008 |
| #define | EMAC_HW_FEATURE_HDSEL 0x00000004 |
| #define | EMAC_HW_FEATURE_MIISEL 0x00000001 |
| #define | EMAC_TDES0_OWN 0x80000000 |
| #define | EMAC_TDES0_IC 0x40000000 |
| #define | EMAC_TDES0_LS 0x20000000 |
| #define | EMAC_TDES0_FS 0x10000000 |
| #define | EMAC_TDES0_DC 0x08000000 |
| #define | EMAC_TDES0_DP 0x04000000 |
| #define | EMAC_TDES0_TTSE 0x02000000 |
| #define | EMAC_TDES0_CRCR 0x01000000 |
| #define | EMAC_TDES0_CIC 0x00C00000 |
| #define | EMAC_TDES0_TER 0x00200000 |
| #define | EMAC_TDES0_TCH 0x00100000 |
| #define | EMAC_TDES0_VLIC 0x000C0000 |
| #define | EMAC_TDES0_TTSS 0x00020000 |
| #define | EMAC_TDES0_IHE 0x00010000 |
| #define | EMAC_TDES0_ES 0x00008000 |
| #define | EMAC_TDES0_JT 0x00004000 |
| #define | EMAC_TDES0_FF 0x00002000 |
| #define | EMAC_TDES0_IPE 0x00001000 |
| #define | EMAC_TDES0_LOC 0x00000800 |
| #define | EMAC_TDES0_NC 0x00000400 |
| #define | EMAC_TDES0_LC 0x00000200 |
| #define | EMAC_TDES0_EC 0x00000100 |
| #define | EMAC_TDES0_VF 0x00000080 |
| #define | EMAC_TDES0_CC 0x00000078 |
| #define | EMAC_TDES0_ED 0x00000004 |
| #define | EMAC_TDES0_UF 0x00000002 |
| #define | EMAC_TDES0_DB 0x00000001 |
| #define | EMAC_TDES1_SAIC 0xE0000000 |
| #define | EMAC_TDES1_TBS2 0x1FFF0000 |
| #define | EMAC_TDES1_TBS1 0x00001FFF |
| #define | EMAC_TDES2_TBAP1 0xFFFFFFFF |
| #define | EMAC_TDES3_TBAP2 0xFFFFFFFF |
| #define | EMAC_TDES6_TTSL 0xFFFFFFFF |
| #define | EMAC_TDES7_TTSH 0xFFFFFFFF |
| #define | EMAC_RDES0_OWN 0x80000000 |
| #define | EMAC_RDES0_AFM 0x40000000 |
| #define | EMAC_RDES0_FL 0x3FFF0000 |
| #define | EMAC_RDES0_ES 0x00008000 |
| #define | EMAC_RDES0_DE 0x00004000 |
| #define | EMAC_RDES0_SAF 0x00002000 |
| #define | EMAC_RDES0_LE 0x00001000 |
| #define | EMAC_RDES0_OE 0x00000800 |
| #define | EMAC_RDES0_VLAN 0x00000400 |
| #define | EMAC_RDES0_FS 0x00000200 |
| #define | EMAC_RDES0_LS 0x00000100 |
| #define | EMAC_RDES0_IPHCE_TSV 0x00000080 |
| #define | EMAC_RDES0_LC 0x00000040 |
| #define | EMAC_RDES0_FT 0x00000020 |
| #define | EMAC_RDES0_RWT 0x00000010 |
| #define | EMAC_RDES0_RE 0x00000008 |
| #define | EMAC_RDES0_DBE 0x00000004 |
| #define | EMAC_RDES0_CE 0x00000002 |
| #define | EMAC_RDES0_PCE_ESA 0x00000001 |
| #define | EMAC_RDES1_DIC 0x80000000 |
| #define | EMAC_RDES1_RBS2 0x1FFF0000 |
| #define | EMAC_RDES1_RER 0x00008000 |
| #define | EMAC_RDES1_RCH 0x00004000 |
| #define | EMAC_RDES1_RBS1 0x00001FFF |
| #define | EMAC_RDES2_RBAP1 0xFFFFFFFF |
| #define | EMAC_RDES3_RBAP2 0xFFFFFFFF |
| #define | EMAC_RDES4_L3L4FNM 0x0C000000 |
| #define | EMAC_RDES4_L4FM 0x02000000 |
| #define | EMAC_RDES4_L3FM 0x01000000 |
| #define | EMAC_RDES4_TSD 0x00004000 |
| #define | EMAC_RDES4_PV 0x00002000 |
| #define | EMAC_RDES4_PFT 0x00001000 |
| #define | EMAC_RDES4_PMT 0x00000F00 |
| #define | EMAC_RDES4_IPV6PR 0x00000080 |
| #define | EMAC_RDES4_IPV4PR 0x00000040 |
| #define | EMAC_RDES4_IPCB 0x00000020 |
| #define | EMAC_RDES4_IPPE 0x00000010 |
| #define | EMAC_RDES4_IPHE 0x00000008 |
| #define | EMAC_RDES4_IPPT 0x00000007 |
| #define | EMAC_RDES6_RTSL 0xFFFFFFFF |
| #define | EMAC_RDES7_RTSH 0xFFFFFFFF |
Functions | |
| error_t | m467EthInit (NetInterface *interface) |
| M467 Ethernet MAC initialization. More... | |
| void | m467EthInitGpio (NetInterface *interface) |
| GPIO configuration. More... | |
| void | m467EthInitDmaDesc (NetInterface *interface) |
| Initialize DMA descriptor lists. More... | |
| void | m467EthTick (NetInterface *interface) |
| M467 Ethernet MAC timer handler. More... | |
| void | m467EthEnableIrq (NetInterface *interface) |
| Enable interrupts. More... | |
| void | m467EthDisableIrq (NetInterface *interface) |
| Disable interrupts. More... | |
| void | m467EthEventHandler (NetInterface *interface) |
| M467 Ethernet MAC event handler. More... | |
| error_t | m467EthSendPacket (NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary) |
| Send a packet. More... | |
| error_t | m467EthReceivePacket (NetInterface *interface) |
| Receive a packet. More... | |
| error_t | m467EthUpdateMacAddrFilter (NetInterface *interface) |
| Configure MAC address filtering. More... | |
| error_t | m467EthUpdateMacConfig (NetInterface *interface) |
| Adjust MAC configuration parameters for proper operation. More... | |
| void | m467EthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data) |
| Write PHY register. More... | |
| uint16_t | m467EthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr) |
| Read PHY register. More... | |
Variables | |
| const NicDriver | m467EthDriver |
| M467 Ethernet MAC driver. More... | |
Detailed Description
Nuvoton M467 Ethernet MAC driver.
License
SPDX-License-Identifier: GPL-2.0-or-later
Copyright (C) 2010-2025 Oryx Embedded SARL. All rights reserved.
This file is part of CycloneTCP Open.
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- Version
- 2.5.4
Definition in file m467_eth_driver.h.
Macro Definition Documentation
◆ EMAC_AHB_STATUS
| #define EMAC_AHB_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x102C)) |
Definition at line 142 of file m467_eth_driver.h.
◆ EMAC_AHB_STATUS_AXIRDSTS
| #define EMAC_AHB_STATUS_AXIRDSTS 0x00000002 |
Definition at line 500 of file m467_eth_driver.h.
◆ EMAC_AHB_STATUS_AXWHSTS
| #define EMAC_AHB_STATUS_AXWHSTS 0x00000001 |
Definition at line 501 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE
| #define EMAC_BUS_MODE *((volatile uint32_t *) (EMAC_BASE + 0x1000)) |
Definition at line 132 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_AAB
| #define EMAC_BUS_MODE_AAB 0x02000000 |
Definition at line 393 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_ATDS
| #define EMAC_BUS_MODE_ATDS 0x00000080 |
Definition at line 411 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL
| #define EMAC_BUS_MODE_DSL 0x0000007C |
Definition at line 412 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_0
| #define EMAC_BUS_MODE_DSL_0 0x00000000 |
Definition at line 413 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_1
| #define EMAC_BUS_MODE_DSL_1 0x00000004 |
Definition at line 414 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_16
| #define EMAC_BUS_MODE_DSL_16 0x00000040 |
Definition at line 418 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_2
| #define EMAC_BUS_MODE_DSL_2 0x00000008 |
Definition at line 415 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_4
| #define EMAC_BUS_MODE_DSL_4 0x00000010 |
Definition at line 416 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_DSL_8
| #define EMAC_BUS_MODE_DSL_8 0x00000020 |
Definition at line 417 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_FB
| #define EMAC_BUS_MODE_FB 0x00010000 |
Definition at line 403 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL
| #define EMAC_BUS_MODE_PBL 0x00003F00 |
Definition at line 404 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_1
| #define EMAC_BUS_MODE_PBL_1 0x00000100 |
Definition at line 405 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_16
| #define EMAC_BUS_MODE_PBL_16 0x00001000 |
Definition at line 409 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_2
| #define EMAC_BUS_MODE_PBL_2 0x00000200 |
Definition at line 406 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_32
| #define EMAC_BUS_MODE_PBL_32 0x00002000 |
Definition at line 410 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_4
| #define EMAC_BUS_MODE_PBL_4 0x00000400 |
Definition at line 407 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBL_8
| #define EMAC_BUS_MODE_PBL_8 0x00000800 |
Definition at line 408 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_PBLX8
| #define EMAC_BUS_MODE_PBLX8 0x01000000 |
Definition at line 394 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL
| #define EMAC_BUS_MODE_RPBL 0x007E0000 |
Definition at line 396 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_1
| #define EMAC_BUS_MODE_RPBL_1 0x00020000 |
Definition at line 397 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_16
| #define EMAC_BUS_MODE_RPBL_16 0x00200000 |
Definition at line 401 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_2
| #define EMAC_BUS_MODE_RPBL_2 0x00040000 |
Definition at line 398 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_32
| #define EMAC_BUS_MODE_RPBL_32 0x00400000 |
Definition at line 402 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_4
| #define EMAC_BUS_MODE_RPBL_4 0x00080000 |
Definition at line 399 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_RPBL_8
| #define EMAC_BUS_MODE_RPBL_8 0x00100000 |
Definition at line 400 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_SWR
| #define EMAC_BUS_MODE_SWR 0x00000001 |
Definition at line 419 of file m467_eth_driver.h.
◆ EMAC_BUS_MODE_USP
| #define EMAC_BUS_MODE_USP 0x00800000 |
Definition at line 395 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR
| #define EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1054)) |
Definition at line 146 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR_CURRBUFAPTR
| #define EMAC_CURRENT_HOST_RECEIVE_BUFFER_ADDR_CURRBUFAPTR 0xFFFFFFFF |
Definition at line 513 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR
| #define EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR *((volatile uint32_t *) (EMAC_BASE + 0x104C)) |
Definition at line 144 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR
| #define EMAC_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR 0xFFFFFFFF |
Definition at line 507 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR
| #define EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1050)) |
Definition at line 145 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR_CURTBUFAPTR
| #define EMAC_CURRENT_HOST_TRANSMIT_BUFFER_ADDR_CURTBUFAPTR 0xFFFFFFFF |
Definition at line 510 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR
| #define EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR *((volatile uint32_t *) (EMAC_BASE + 0x1048)) |
Definition at line 143 of file m467_eth_driver.h.
◆ EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR
| #define EMAC_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR 0xFFFFFFFF |
Definition at line 504 of file m467_eth_driver.h.
◆ EMAC_DEBUG
| #define EMAC_DEBUG *((volatile uint32_t *) (EMAC_BASE + 0x0024)) |
Definition at line 94 of file m467_eth_driver.h.
◆ EMAC_DEBUG_RFCFCSTS
| #define EMAC_DEBUG_RFCFCSTS 0x00000006 |
Definition at line 224 of file m467_eth_driver.h.
◆ EMAC_DEBUG_RPESTS
| #define EMAC_DEBUG_RPESTS 0x00000001 |
Definition at line 225 of file m467_eth_driver.h.
◆ EMAC_DEBUG_RRCSTS
| #define EMAC_DEBUG_RRCSTS 0x00000060 |
Definition at line 222 of file m467_eth_driver.h.
◆ EMAC_DEBUG_RWCSTS
| #define EMAC_DEBUG_RWCSTS 0x00000010 |
Definition at line 223 of file m467_eth_driver.h.
◆ EMAC_DEBUG_RXFSTS
| #define EMAC_DEBUG_RXFSTS 0x00000300 |
Definition at line 221 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TFCSTS
| #define EMAC_DEBUG_TFCSTS 0x00060000 |
Definition at line 219 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TPESTS
| #define EMAC_DEBUG_TPESTS 0x00010000 |
Definition at line 220 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TRCSTS
| #define EMAC_DEBUG_TRCSTS 0x00300000 |
Definition at line 217 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TWCSTS
| #define EMAC_DEBUG_TWCSTS 0x00400000 |
Definition at line 216 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TXFSTS
| #define EMAC_DEBUG_TXFSTS 0x01000000 |
Definition at line 215 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TXPAUSED
| #define EMAC_DEBUG_TXPAUSED 0x00080000 |
Definition at line 218 of file m467_eth_driver.h.
◆ EMAC_DEBUG_TXSTSFSTS
| #define EMAC_DEBUG_TXSTSFSTS 0x02000000 |
Definition at line 214 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL
| #define EMAC_FLOW_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x0018)) |
Definition at line 91 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_DZQP
| #define EMAC_FLOW_CONTROL_DZQP 0x00000080 |
Definition at line 200 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_FCA_BPA
| #define EMAC_FLOW_CONTROL_FCA_BPA 0x00000001 |
Definition at line 205 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_PLT
| #define EMAC_FLOW_CONTROL_PLT 0x00000030 |
Definition at line 201 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_PT
| #define EMAC_FLOW_CONTROL_PT 0xFFFF0000 |
Definition at line 199 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_RFE
| #define EMAC_FLOW_CONTROL_RFE 0x00000004 |
Definition at line 203 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_TFE
| #define EMAC_FLOW_CONTROL_TFE 0x00000002 |
Definition at line 204 of file m467_eth_driver.h.
◆ EMAC_FLOW_CONTROL_UP
| #define EMAC_FLOW_CONTROL_UP 0x00000008 |
Definition at line 202 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR
| #define EMAC_GMII_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x0010)) |
Definition at line 89 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR
| #define EMAC_GMII_ADDR_CR 0x0000003C |
Definition at line 185 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_102
| #define EMAC_GMII_ADDR_CR_DIV_102 0x00000010 |
Definition at line 190 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_124
| #define EMAC_GMII_ADDR_CR_DIV_124 0x00000014 |
Definition at line 191 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_16
| #define EMAC_GMII_ADDR_CR_DIV_16 0x00000008 |
Definition at line 188 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_26
| #define EMAC_GMII_ADDR_CR_DIV_26 0x0000000C |
Definition at line 189 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_42
| #define EMAC_GMII_ADDR_CR_DIV_42 0x00000000 |
Definition at line 186 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_CR_DIV_62
| #define EMAC_GMII_ADDR_CR_DIV_62 0x00000004 |
Definition at line 187 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_GB
| #define EMAC_GMII_ADDR_GB 0x00000001 |
Definition at line 193 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_GR
| #define EMAC_GMII_ADDR_GR 0x000007C0 |
Definition at line 184 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_GW
| #define EMAC_GMII_ADDR_GW 0x00000002 |
Definition at line 192 of file m467_eth_driver.h.
◆ EMAC_GMII_ADDR_PA
| #define EMAC_GMII_ADDR_PA 0x0000F800 |
Definition at line 183 of file m467_eth_driver.h.
◆ EMAC_GMII_DATA
| #define EMAC_GMII_DATA *((volatile uint32_t *) (EMAC_BASE + 0x0014)) |
Definition at line 90 of file m467_eth_driver.h.
◆ EMAC_GMII_DATA_GD
| #define EMAC_GMII_DATA_GD 0x0000FFFF |
Definition at line 196 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE
| #define EMAC_HW_FEATURE *((volatile uint32_t *) (EMAC_BASE + 0x1058)) |
Definition at line 147 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_ACTPHYIF
| #define EMAC_HW_FEATURE_ACTPHYIF 0x70000000 |
Definition at line 516 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_ADDMACADRSEL
| #define EMAC_HW_FEATURE_ADDMACADRSEL 0x00000020 |
Definition at line 536 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_EEESEL
| #define EMAC_HW_FEATURE_EEESEL 0x00004000 |
Definition at line 527 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_ENHDESSEL
| #define EMAC_HW_FEATURE_ENHDESSEL 0x01000000 |
Definition at line 520 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_EXTHASHEN
| #define EMAC_HW_FEATURE_EXTHASHEN 0x00000008 |
Definition at line 538 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_FLEXIPPSEN
| #define EMAC_HW_FEATURE_FLEXIPPSEN 0x04000000 |
Definition at line 518 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_HASHSEL
| #define EMAC_HW_FEATURE_HASHSEL 0x00000010 |
Definition at line 537 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_HDSEL
| #define EMAC_HW_FEATURE_HDSEL 0x00000004 |
Definition at line 539 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_INTTSEN
| #define EMAC_HW_FEATURE_INTTSEN 0x02000000 |
Definition at line 519 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_L3L4FLTREN
| #define EMAC_HW_FEATURE_L3L4FLTREN 0x00000080 |
Definition at line 534 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_MGKSEL
| #define EMAC_HW_FEATURE_MGKSEL 0x00000400 |
Definition at line 531 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_MIISEL
| #define EMAC_HW_FEATURE_MIISEL 0x00000001 |
Definition at line 540 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_MMCSEL
| #define EMAC_HW_FEATURE_MMCSEL 0x00000800 |
Definition at line 530 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_PCSSEL
| #define EMAC_HW_FEATURE_PCSSEL 0x00000040 |
Definition at line 535 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_RWKSEL
| #define EMAC_HW_FEATURE_RWKSEL 0x00000200 |
Definition at line 532 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_RXCHCNT
| #define EMAC_HW_FEATURE_RXCHCNT 0x00300000 |
Definition at line 522 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_RXFIFOSIZE
| #define EMAC_HW_FEATURE_RXFIFOSIZE 0x00080000 |
Definition at line 523 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_RXTYP1COE
| #define EMAC_HW_FEATURE_RXTYP1COE 0x00020000 |
Definition at line 525 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_RXTYP2COE
| #define EMAC_HW_FEATURE_RXTYP2COE 0x00040000 |
Definition at line 524 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_SAVLANINS
| #define EMAC_HW_FEATURE_SAVLANINS 0x08000000 |
Definition at line 517 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_SMASEL
| #define EMAC_HW_FEATURE_SMASEL 0x00000100 |
Definition at line 533 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_TSVER1SEL
| #define EMAC_HW_FEATURE_TSVER1SEL 0x00001000 |
Definition at line 529 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_TSVER2SEL
| #define EMAC_HW_FEATURE_TSVER2SEL 0x00002000 |
Definition at line 528 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_TXCHCNT
| #define EMAC_HW_FEATURE_TXCHCNT 0x00C00000 |
Definition at line 521 of file m467_eth_driver.h.
◆ EMAC_HW_FEATURE_TXCOESEL
| #define EMAC_HW_FEATURE_TXCOESEL 0x00010000 |
Definition at line 526 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE
| #define EMAC_INTERRUPT_ENABLE *((volatile uint32_t *) (EMAC_BASE + 0x101C)) |
Definition at line 139 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_AIE
| #define EMAC_INTERRUPT_ENABLE_AIE 0x00008000 |
Definition at line 475 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_ERE
| #define EMAC_INTERRUPT_ENABLE_ERE 0x00004000 |
Definition at line 476 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_ETE
| #define EMAC_INTERRUPT_ENABLE_ETE 0x00000400 |
Definition at line 478 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_FBE
| #define EMAC_INTERRUPT_ENABLE_FBE 0x00002000 |
Definition at line 477 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_NIE
| #define EMAC_INTERRUPT_ENABLE_NIE 0x00010000 |
Definition at line 474 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_OVE
| #define EMAC_INTERRUPT_ENABLE_OVE 0x00000010 |
Definition at line 484 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_RIE
| #define EMAC_INTERRUPT_ENABLE_RIE 0x00000040 |
Definition at line 482 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_RSE
| #define EMAC_INTERRUPT_ENABLE_RSE 0x00000100 |
Definition at line 480 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_RUE
| #define EMAC_INTERRUPT_ENABLE_RUE 0x00000080 |
Definition at line 481 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_RWE
| #define EMAC_INTERRUPT_ENABLE_RWE 0x00000200 |
Definition at line 479 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_TIE
| #define EMAC_INTERRUPT_ENABLE_TIE 0x00000001 |
Definition at line 488 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_TJE
| #define EMAC_INTERRUPT_ENABLE_TJE 0x00000008 |
Definition at line 485 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_TSE
| #define EMAC_INTERRUPT_ENABLE_TSE 0x00000002 |
Definition at line 487 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_TUE
| #define EMAC_INTERRUPT_ENABLE_TUE 0x00000004 |
Definition at line 486 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_ENABLE_UNE
| #define EMAC_INTERRUPT_ENABLE_UNE 0x00000020 |
Definition at line 483 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_MASK
| #define EMAC_INTERRUPT_MASK *((volatile uint32_t *) (EMAC_BASE + 0x003C)) |
Definition at line 97 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_MASK_PMTIM
| #define EMAC_INTERRUPT_MASK_PMTIM 0x00000008 |
Definition at line 238 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_MASK_TSIM
| #define EMAC_INTERRUPT_MASK_TSIM 0x00000200 |
Definition at line 237 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_STATUS
| #define EMAC_INTERRUPT_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x0038)) |
Definition at line 96 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_STATUS_PMTIS
| #define EMAC_INTERRUPT_STATUS_PMTIS 0x00000008 |
Definition at line 234 of file m467_eth_driver.h.
◆ EMAC_INTERRUPT_STATUS_TSIS
| #define EMAC_INTERRUPT_STATUS_TSIS 0x00000200 |
Definition at line 233 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR0_HIGH
| #define EMAC_MAC_ADDR0_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0040)) |
Definition at line 98 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR0_HIGH_ADDRHI
| #define EMAC_MAC_ADDR0_HIGH_ADDRHI 0x0000FFFF |
Definition at line 242 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR0_HIGH_AE
| #define EMAC_MAC_ADDR0_HIGH_AE 0x80000000 |
Definition at line 241 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR0_LOW
| #define EMAC_MAC_ADDR0_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0044)) |
Definition at line 99 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR0_LOW_ADDRLO
| #define EMAC_MAC_ADDR0_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 245 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_HIGH
| #define EMAC_MAC_ADDR1_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0048)) |
Definition at line 100 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_HIGH_ADDRHI
| #define EMAC_MAC_ADDR1_HIGH_ADDRHI 0x0000FFFF |
Definition at line 251 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_HIGH_AE
| #define EMAC_MAC_ADDR1_HIGH_AE 0x80000000 |
Definition at line 248 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_HIGH_MBC
| #define EMAC_MAC_ADDR1_HIGH_MBC 0x3F000000 |
Definition at line 250 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_HIGH_SA
| #define EMAC_MAC_ADDR1_HIGH_SA 0x40000000 |
Definition at line 249 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_LOW
| #define EMAC_MAC_ADDR1_LOW *((volatile uint32_t *) (EMAC_BASE + 0x004C)) |
Definition at line 101 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR1_LOW_ADDRLO
| #define EMAC_MAC_ADDR1_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 254 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_HIGH
| #define EMAC_MAC_ADDR2_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0050)) |
Definition at line 102 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_HIGH_ADDRHI
| #define EMAC_MAC_ADDR2_HIGH_ADDRHI 0x0000FFFF |
Definition at line 260 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_HIGH_AE
| #define EMAC_MAC_ADDR2_HIGH_AE 0x80000000 |
Definition at line 257 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_HIGH_MBC
| #define EMAC_MAC_ADDR2_HIGH_MBC 0x3F000000 |
Definition at line 259 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_HIGH_SA
| #define EMAC_MAC_ADDR2_HIGH_SA 0x40000000 |
Definition at line 258 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_LOW
| #define EMAC_MAC_ADDR2_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0054)) |
Definition at line 103 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR2_LOW_ADDRLO
| #define EMAC_MAC_ADDR2_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 263 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_HIGH
| #define EMAC_MAC_ADDR3_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0058)) |
Definition at line 104 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_HIGH_ADDRHI
| #define EMAC_MAC_ADDR3_HIGH_ADDRHI 0x0000FFFF |
Definition at line 269 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_HIGH_AE
| #define EMAC_MAC_ADDR3_HIGH_AE 0x80000000 |
Definition at line 266 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_HIGH_MBC
| #define EMAC_MAC_ADDR3_HIGH_MBC 0x3F000000 |
Definition at line 268 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_HIGH_SA
| #define EMAC_MAC_ADDR3_HIGH_SA 0x40000000 |
Definition at line 267 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_LOW
| #define EMAC_MAC_ADDR3_LOW *((volatile uint32_t *) (EMAC_BASE + 0x005C)) |
Definition at line 105 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR3_LOW_ADDRLO
| #define EMAC_MAC_ADDR3_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 272 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_HIGH
| #define EMAC_MAC_ADDR4_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0060)) |
Definition at line 106 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_HIGH_ADDRHI
| #define EMAC_MAC_ADDR4_HIGH_ADDRHI 0x0000FFFF |
Definition at line 278 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_HIGH_AE
| #define EMAC_MAC_ADDR4_HIGH_AE 0x80000000 |
Definition at line 275 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_HIGH_MBC
| #define EMAC_MAC_ADDR4_HIGH_MBC 0x3F000000 |
Definition at line 277 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_HIGH_SA
| #define EMAC_MAC_ADDR4_HIGH_SA 0x40000000 |
Definition at line 276 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_LOW
| #define EMAC_MAC_ADDR4_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0064)) |
Definition at line 107 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR4_LOW_ADDRLO
| #define EMAC_MAC_ADDR4_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 281 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_HIGH
| #define EMAC_MAC_ADDR5_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0068)) |
Definition at line 108 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_HIGH_ADDRHI
| #define EMAC_MAC_ADDR5_HIGH_ADDRHI 0x0000FFFF |
Definition at line 287 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_HIGH_AE
| #define EMAC_MAC_ADDR5_HIGH_AE 0x80000000 |
Definition at line 284 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_HIGH_MBC
| #define EMAC_MAC_ADDR5_HIGH_MBC 0x3F000000 |
Definition at line 286 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_HIGH_SA
| #define EMAC_MAC_ADDR5_HIGH_SA 0x40000000 |
Definition at line 285 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_LOW
| #define EMAC_MAC_ADDR5_LOW *((volatile uint32_t *) (EMAC_BASE + 0x006C)) |
Definition at line 109 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR5_LOW_ADDRLO
| #define EMAC_MAC_ADDR5_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 290 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_HIGH
| #define EMAC_MAC_ADDR6_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0070)) |
Definition at line 110 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_HIGH_ADDRHI
| #define EMAC_MAC_ADDR6_HIGH_ADDRHI 0x0000FFFF |
Definition at line 296 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_HIGH_AE
| #define EMAC_MAC_ADDR6_HIGH_AE 0x80000000 |
Definition at line 293 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_HIGH_MBC
| #define EMAC_MAC_ADDR6_HIGH_MBC 0x3F000000 |
Definition at line 295 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_HIGH_SA
| #define EMAC_MAC_ADDR6_HIGH_SA 0x40000000 |
Definition at line 294 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_LOW
| #define EMAC_MAC_ADDR6_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0074)) |
Definition at line 111 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR6_LOW_ADDRLO
| #define EMAC_MAC_ADDR6_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 299 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_HIGH
| #define EMAC_MAC_ADDR7_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0078)) |
Definition at line 112 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_HIGH_ADDRHI
| #define EMAC_MAC_ADDR7_HIGH_ADDRHI 0x0000FFFF |
Definition at line 305 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_HIGH_AE
| #define EMAC_MAC_ADDR7_HIGH_AE 0x80000000 |
Definition at line 302 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_HIGH_MBC
| #define EMAC_MAC_ADDR7_HIGH_MBC 0x3F000000 |
Definition at line 304 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_HIGH_SA
| #define EMAC_MAC_ADDR7_HIGH_SA 0x40000000 |
Definition at line 303 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_LOW
| #define EMAC_MAC_ADDR7_LOW *((volatile uint32_t *) (EMAC_BASE + 0x007C)) |
Definition at line 113 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR7_LOW_ADDRLO
| #define EMAC_MAC_ADDR7_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 308 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_HIGH
| #define EMAC_MAC_ADDR8_HIGH *((volatile uint32_t *) (EMAC_BASE + 0x0080)) |
Definition at line 114 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_HIGH_ADDRHI
| #define EMAC_MAC_ADDR8_HIGH_ADDRHI 0x0000FFFF |
Definition at line 314 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_HIGH_AE
| #define EMAC_MAC_ADDR8_HIGH_AE 0x80000000 |
Definition at line 311 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_HIGH_MBC
| #define EMAC_MAC_ADDR8_HIGH_MBC 0x3F000000 |
Definition at line 313 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_HIGH_SA
| #define EMAC_MAC_ADDR8_HIGH_SA 0x40000000 |
Definition at line 312 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_LOW
| #define EMAC_MAC_ADDR8_LOW *((volatile uint32_t *) (EMAC_BASE + 0x0084)) |
Definition at line 115 of file m467_eth_driver.h.
◆ EMAC_MAC_ADDR8_LOW_ADDRLO
| #define EMAC_MAC_ADDR8_LOW_ADDRLO 0xFFFFFFFF |
Definition at line 317 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG
| #define EMAC_MAC_CONFIG *((volatile uint32_t *) (EMAC_BASE + 0x0000)) |
Definition at line 87 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_ACS
| #define EMAC_MAC_CONFIG_ACS 0x00000080 |
Definition at line 164 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_BL
| #define EMAC_MAC_CONFIG_BL 0x00000060 |
Definition at line 165 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_CST
| #define EMAC_MAC_CONFIG_CST 0x02000000 |
Definition at line 152 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_DC
| #define EMAC_MAC_CONFIG_DC 0x00000010 |
Definition at line 166 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_DCRS
| #define EMAC_MAC_CONFIG_DCRS 0x00010000 |
Definition at line 157 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_DM
| #define EMAC_MAC_CONFIG_DM 0x00000800 |
Definition at line 161 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_DO
| #define EMAC_MAC_CONFIG_DO 0x00002000 |
Definition at line 159 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_DR
| #define EMAC_MAC_CONFIG_DR 0x00000200 |
Definition at line 163 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_FES
| #define EMAC_MAC_CONFIG_FES 0x00004000 |
Definition at line 158 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_IFG
| #define EMAC_MAC_CONFIG_IFG 0x000E0000 |
Definition at line 156 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_IPC
| #define EMAC_MAC_CONFIG_IPC 0x00000400 |
Definition at line 162 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_JD
| #define EMAC_MAC_CONFIG_JD 0x00400000 |
Definition at line 154 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_JE
| #define EMAC_MAC_CONFIG_JE 0x00100000 |
Definition at line 155 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_LM
| #define EMAC_MAC_CONFIG_LM 0x00001000 |
Definition at line 160 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_PRELEN
| #define EMAC_MAC_CONFIG_PRELEN 0x00000003 |
Definition at line 169 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_RE
| #define EMAC_MAC_CONFIG_RE 0x00000004 |
Definition at line 168 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_SARC
| #define EMAC_MAC_CONFIG_SARC 0xF0000000 |
Definition at line 150 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_TE
| #define EMAC_MAC_CONFIG_TE 0x00000008 |
Definition at line 167 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_TWOKPE
| #define EMAC_MAC_CONFIG_TWOKPE 0x08000000 |
Definition at line 151 of file m467_eth_driver.h.
◆ EMAC_MAC_CONFIG_WD
| #define EMAC_MAC_CONFIG_WD 0x00800000 |
Definition at line 153 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER
| #define EMAC_MAC_FRAME_FILTER *((volatile uint32_t *) (EMAC_BASE + 0x0004)) |
Definition at line 88 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_DAIF
| #define EMAC_MAC_FRAME_FILTER_DAIF 0x00000008 |
Definition at line 179 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_DBF
| #define EMAC_MAC_FRAME_FILTER_DBF 0x00000020 |
Definition at line 177 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_PCF
| #define EMAC_MAC_FRAME_FILTER_PCF 0x000000C0 |
Definition at line 176 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_PM
| #define EMAC_MAC_FRAME_FILTER_PM 0x00000010 |
Definition at line 178 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_PR
| #define EMAC_MAC_FRAME_FILTER_PR 0x00000001 |
Definition at line 180 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_RA
| #define EMAC_MAC_FRAME_FILTER_RA 0x80000000 |
Definition at line 172 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_SAF
| #define EMAC_MAC_FRAME_FILTER_SAF 0x00000200 |
Definition at line 174 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_SAIF
| #define EMAC_MAC_FRAME_FILTER_SAIF 0x00000100 |
Definition at line 175 of file m467_eth_driver.h.
◆ EMAC_MAC_FRAME_FILTER_VTFE
| #define EMAC_MAC_FRAME_FILTER_VTFE 0x00010000 |
Definition at line 173 of file m467_eth_driver.h.
◆ EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT
| #define EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT *((volatile uint32_t *) (EMAC_BASE + 0x1020)) |
Definition at line 140 of file m467_eth_driver.h.
◆ EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISCNTOVF
| #define EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISCNTOVF 0x00010000 |
Definition at line 493 of file m467_eth_driver.h.
◆ EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISFRMCNT
| #define EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_MISFRMCNT 0x0000FFFF |
Definition at line 494 of file m467_eth_driver.h.
◆ EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFCNTOVF
| #define EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFCNTOVF 0x10000000 |
Definition at line 491 of file m467_eth_driver.h.
◆ EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFFRMCNT
| #define EMAC_MISSED_FRAME_AND_BUFFER_OVERFLOW_CNT_OVFFRMCNT 0x0FFE0000 |
Definition at line 492 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE
| #define EMAC_OPERATION_MODE *((volatile uint32_t *) (EMAC_BASE + 0x1018)) |
Definition at line 138 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_DFF
| #define EMAC_OPERATION_MODE_DFF 0x01000000 |
Definition at line 458 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_DGF
| #define EMAC_OPERATION_MODE_DGF 0x00000020 |
Definition at line 468 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_DT
| #define EMAC_OPERATION_MODE_DT 0x04000000 |
Definition at line 456 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_EFC
| #define EMAC_OPERATION_MODE_EFC 0x00000100 |
Definition at line 465 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_FEF
| #define EMAC_OPERATION_MODE_FEF 0x00000080 |
Definition at line 466 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_FTF
| #define EMAC_OPERATION_MODE_FTF 0x00100000 |
Definition at line 460 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_FUF
| #define EMAC_OPERATION_MODE_FUF 0x00000040 |
Definition at line 467 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_OSF
| #define EMAC_OPERATION_MODE_OSF 0x00000004 |
Definition at line 470 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_RFA
| #define EMAC_OPERATION_MODE_RFA 0x00000600 |
Definition at line 464 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_RFD
| #define EMAC_OPERATION_MODE_RFD 0x00001800 |
Definition at line 463 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_RSF
| #define EMAC_OPERATION_MODE_RSF 0x02000000 |
Definition at line 457 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_RTC
| #define EMAC_OPERATION_MODE_RTC 0x00000018 |
Definition at line 469 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_SR
| #define EMAC_OPERATION_MODE_SR 0x00000002 |
Definition at line 471 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_ST
| #define EMAC_OPERATION_MODE_ST 0x00002000 |
Definition at line 462 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_TSF
| #define EMAC_OPERATION_MODE_TSF 0x00200000 |
Definition at line 459 of file m467_eth_driver.h.
◆ EMAC_OPERATION_MODE_TTC
| #define EMAC_OPERATION_MODE_TTC 0x0001C000 |
Definition at line 461 of file m467_eth_driver.h.
◆ EMAC_PMT_CONTROL_STATUS
| #define EMAC_PMT_CONTROL_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x002C)) |
Definition at line 95 of file m467_eth_driver.h.
◆ EMAC_PMT_CONTROL_STATUS_MGKPKTEN
| #define EMAC_PMT_CONTROL_STATUS_MGKPKTEN 0x00000002 |
Definition at line 229 of file m467_eth_driver.h.
◆ EMAC_PMT_CONTROL_STATUS_MGKPRCVD
| #define EMAC_PMT_CONTROL_STATUS_MGKPRCVD 0x00000020 |
Definition at line 228 of file m467_eth_driver.h.
◆ EMAC_PMT_CONTROL_STATUS_PWRDWN
| #define EMAC_PMT_CONTROL_STATUS_PWRDWN 0x00000001 |
Definition at line 230 of file m467_eth_driver.h.
◆ EMAC_PPS0_INTERVAL
| #define EMAC_PPS0_INTERVAL *((volatile uint32_t *) (EMAC_BASE + 0x0760)) |
Definition at line 130 of file m467_eth_driver.h.
◆ EMAC_PPS0_INTERVAL_PPSINT
| #define EMAC_PPS0_INTERVAL_PPSINT 0xFFFFFFFF |
Definition at line 387 of file m467_eth_driver.h.
◆ EMAC_PPS0_WIDTH
| #define EMAC_PPS0_WIDTH *((volatile uint32_t *) (EMAC_BASE + 0x0764)) |
Definition at line 131 of file m467_eth_driver.h.
◆ EMAC_PPS0_WIDTH_PPSWIDTH
| #define EMAC_PPS0_WIDTH_PPSWIDTH 0xFFFFFFFF |
Definition at line 390 of file m467_eth_driver.h.
◆ EMAC_PPS_CONTROL
| #define EMAC_PPS_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x072C)) |
Definition at line 129 of file m467_eth_driver.h.
◆ EMAC_PPS_CONTROL_PPSCTRL_PPSCMD
| #define EMAC_PPS_CONTROL_PPSCTRL_PPSCMD 0x0000000F |
Definition at line 384 of file m467_eth_driver.h.
◆ EMAC_PPS_CONTROL_PPSEN0
| #define EMAC_PPS_CONTROL_PPSEN0 0x00000010 |
Definition at line 383 of file m467_eth_driver.h.
◆ EMAC_PPS_CONTROL_TRGTMODSEL0
| #define EMAC_PPS_CONTROL_TRGTMODSEL0 0x00000060 |
Definition at line 382 of file m467_eth_driver.h.
◆ EMAC_RDES0_AFM
| #define EMAC_RDES0_AFM 0x40000000 |
Definition at line 580 of file m467_eth_driver.h.
◆ EMAC_RDES0_CE
| #define EMAC_RDES0_CE 0x00000002 |
Definition at line 596 of file m467_eth_driver.h.
◆ EMAC_RDES0_DBE
| #define EMAC_RDES0_DBE 0x00000004 |
Definition at line 595 of file m467_eth_driver.h.
◆ EMAC_RDES0_DE
| #define EMAC_RDES0_DE 0x00004000 |
Definition at line 583 of file m467_eth_driver.h.
◆ EMAC_RDES0_ES
| #define EMAC_RDES0_ES 0x00008000 |
Definition at line 582 of file m467_eth_driver.h.
◆ EMAC_RDES0_FL
| #define EMAC_RDES0_FL 0x3FFF0000 |
Definition at line 581 of file m467_eth_driver.h.
◆ EMAC_RDES0_FS
| #define EMAC_RDES0_FS 0x00000200 |
Definition at line 588 of file m467_eth_driver.h.
◆ EMAC_RDES0_FT
| #define EMAC_RDES0_FT 0x00000020 |
Definition at line 592 of file m467_eth_driver.h.
◆ EMAC_RDES0_IPHCE_TSV
| #define EMAC_RDES0_IPHCE_TSV 0x00000080 |
Definition at line 590 of file m467_eth_driver.h.
◆ EMAC_RDES0_LC
| #define EMAC_RDES0_LC 0x00000040 |
Definition at line 591 of file m467_eth_driver.h.
◆ EMAC_RDES0_LE
| #define EMAC_RDES0_LE 0x00001000 |
Definition at line 585 of file m467_eth_driver.h.
◆ EMAC_RDES0_LS
| #define EMAC_RDES0_LS 0x00000100 |
Definition at line 589 of file m467_eth_driver.h.
◆ EMAC_RDES0_OE
| #define EMAC_RDES0_OE 0x00000800 |
Definition at line 586 of file m467_eth_driver.h.
◆ EMAC_RDES0_OWN
| #define EMAC_RDES0_OWN 0x80000000 |
Definition at line 579 of file m467_eth_driver.h.
◆ EMAC_RDES0_PCE_ESA
| #define EMAC_RDES0_PCE_ESA 0x00000001 |
Definition at line 597 of file m467_eth_driver.h.
◆ EMAC_RDES0_RE
| #define EMAC_RDES0_RE 0x00000008 |
Definition at line 594 of file m467_eth_driver.h.
◆ EMAC_RDES0_RWT
| #define EMAC_RDES0_RWT 0x00000010 |
Definition at line 593 of file m467_eth_driver.h.
◆ EMAC_RDES0_SAF
| #define EMAC_RDES0_SAF 0x00002000 |
Definition at line 584 of file m467_eth_driver.h.
◆ EMAC_RDES0_VLAN
| #define EMAC_RDES0_VLAN 0x00000400 |
Definition at line 587 of file m467_eth_driver.h.
◆ EMAC_RDES1_DIC
| #define EMAC_RDES1_DIC 0x80000000 |
Definition at line 598 of file m467_eth_driver.h.
◆ EMAC_RDES1_RBS1
| #define EMAC_RDES1_RBS1 0x00001FFF |
Definition at line 602 of file m467_eth_driver.h.
◆ EMAC_RDES1_RBS2
| #define EMAC_RDES1_RBS2 0x1FFF0000 |
Definition at line 599 of file m467_eth_driver.h.
◆ EMAC_RDES1_RCH
| #define EMAC_RDES1_RCH 0x00004000 |
Definition at line 601 of file m467_eth_driver.h.
◆ EMAC_RDES1_RER
| #define EMAC_RDES1_RER 0x00008000 |
Definition at line 600 of file m467_eth_driver.h.
◆ EMAC_RDES2_RBAP1
| #define EMAC_RDES2_RBAP1 0xFFFFFFFF |
Definition at line 603 of file m467_eth_driver.h.
◆ EMAC_RDES3_RBAP2
| #define EMAC_RDES3_RBAP2 0xFFFFFFFF |
Definition at line 604 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPCB
| #define EMAC_RDES4_IPCB 0x00000020 |
Definition at line 614 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPHE
| #define EMAC_RDES4_IPHE 0x00000008 |
Definition at line 616 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPPE
| #define EMAC_RDES4_IPPE 0x00000010 |
Definition at line 615 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPPT
| #define EMAC_RDES4_IPPT 0x00000007 |
Definition at line 617 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPV4PR
| #define EMAC_RDES4_IPV4PR 0x00000040 |
Definition at line 613 of file m467_eth_driver.h.
◆ EMAC_RDES4_IPV6PR
| #define EMAC_RDES4_IPV6PR 0x00000080 |
Definition at line 612 of file m467_eth_driver.h.
◆ EMAC_RDES4_L3FM
| #define EMAC_RDES4_L3FM 0x01000000 |
Definition at line 607 of file m467_eth_driver.h.
◆ EMAC_RDES4_L3L4FNM
| #define EMAC_RDES4_L3L4FNM 0x0C000000 |
Definition at line 605 of file m467_eth_driver.h.
◆ EMAC_RDES4_L4FM
| #define EMAC_RDES4_L4FM 0x02000000 |
Definition at line 606 of file m467_eth_driver.h.
◆ EMAC_RDES4_PFT
| #define EMAC_RDES4_PFT 0x00001000 |
Definition at line 610 of file m467_eth_driver.h.
◆ EMAC_RDES4_PMT
| #define EMAC_RDES4_PMT 0x00000F00 |
Definition at line 611 of file m467_eth_driver.h.
◆ EMAC_RDES4_PV
| #define EMAC_RDES4_PV 0x00002000 |
Definition at line 609 of file m467_eth_driver.h.
◆ EMAC_RDES4_TSD
| #define EMAC_RDES4_TSD 0x00004000 |
Definition at line 608 of file m467_eth_driver.h.
◆ EMAC_RDES6_RTSL
| #define EMAC_RDES6_RTSL 0xFFFFFFFF |
Definition at line 618 of file m467_eth_driver.h.
◆ EMAC_RDES7_RTSH
| #define EMAC_RDES7_RTSH 0xFFFFFFFF |
Definition at line 619 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR
| #define EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x100C)) |
Definition at line 135 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR_RDESLA
| #define EMAC_RECEIVE_DESCRIPTOR_LIST_ADDR_RDESLA 0xFFFFFFFF |
Definition at line 428 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER
| #define EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER *((volatile uint32_t *) (EMAC_BASE + 0x1024)) |
Definition at line 141 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT
| #define EMAC_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT 0x000000FF |
Definition at line 497 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_POLL_DEMAND
| #define EMAC_RECEIVE_POLL_DEMAND *((volatile uint32_t *) (EMAC_BASE + 0x1008)) |
Definition at line 134 of file m467_eth_driver.h.
◆ EMAC_RECEIVE_POLL_DEMAND_RPD
| #define EMAC_RECEIVE_POLL_DEMAND_RPD 0xFFFFFFFF |
Definition at line 425 of file m467_eth_driver.h.
◆ EMAC_STATUS
| #define EMAC_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x1014)) |
Definition at line 137 of file m467_eth_driver.h.
◆ EMAC_STATUS_AIS
| #define EMAC_STATUS_AIS 0x00008000 |
Definition at line 440 of file m467_eth_driver.h.
◆ EMAC_STATUS_EB
| #define EMAC_STATUS_EB 0x03800000 |
Definition at line 436 of file m467_eth_driver.h.
◆ EMAC_STATUS_ERI
| #define EMAC_STATUS_ERI 0x00004000 |
Definition at line 441 of file m467_eth_driver.h.
◆ EMAC_STATUS_ETI
| #define EMAC_STATUS_ETI 0x00000400 |
Definition at line 443 of file m467_eth_driver.h.
◆ EMAC_STATUS_FBI
| #define EMAC_STATUS_FBI 0x00002000 |
Definition at line 442 of file m467_eth_driver.h.
◆ EMAC_STATUS_GPI
| #define EMAC_STATUS_GPI 0x10000000 |
Definition at line 435 of file m467_eth_driver.h.
◆ EMAC_STATUS_NIS
| #define EMAC_STATUS_NIS 0x00010000 |
Definition at line 439 of file m467_eth_driver.h.
◆ EMAC_STATUS_OVF
| #define EMAC_STATUS_OVF 0x00000010 |
Definition at line 449 of file m467_eth_driver.h.
◆ EMAC_STATUS_RI
| #define EMAC_STATUS_RI 0x00000040 |
Definition at line 447 of file m467_eth_driver.h.
◆ EMAC_STATUS_RPS
| #define EMAC_STATUS_RPS 0x00000100 |
Definition at line 445 of file m467_eth_driver.h.
◆ EMAC_STATUS_RS
| #define EMAC_STATUS_RS 0x000E0000 |
Definition at line 438 of file m467_eth_driver.h.
◆ EMAC_STATUS_RU
| #define EMAC_STATUS_RU 0x00000080 |
Definition at line 446 of file m467_eth_driver.h.
◆ EMAC_STATUS_RWT
| #define EMAC_STATUS_RWT 0x00000200 |
Definition at line 444 of file m467_eth_driver.h.
◆ EMAC_STATUS_TI
| #define EMAC_STATUS_TI 0x00000001 |
Definition at line 453 of file m467_eth_driver.h.
◆ EMAC_STATUS_TJT
| #define EMAC_STATUS_TJT 0x00000008 |
Definition at line 450 of file m467_eth_driver.h.
◆ EMAC_STATUS_TPS
| #define EMAC_STATUS_TPS 0x00000002 |
Definition at line 452 of file m467_eth_driver.h.
◆ EMAC_STATUS_TS
| #define EMAC_STATUS_TS 0x00700000 |
Definition at line 437 of file m467_eth_driver.h.
◆ EMAC_STATUS_TTI
| #define EMAC_STATUS_TTI 0x20000000 |
Definition at line 434 of file m467_eth_driver.h.
◆ EMAC_STATUS_TU
| #define EMAC_STATUS_TU 0x00000004 |
Definition at line 451 of file m467_eth_driver.h.
◆ EMAC_STATUS_UNF
| #define EMAC_STATUS_UNF 0x00000020 |
Definition at line 448 of file m467_eth_driver.h.
◆ EMAC_SUB_SECOND_INCREMENT
| #define EMAC_SUB_SECOND_INCREMENT *((volatile uint32_t *) (EMAC_BASE + 0x0704)) |
Definition at line 119 of file m467_eth_driver.h.
◆ EMAC_SUB_SECOND_INCREMENT_SSINC
| #define EMAC_SUB_SECOND_INCREMENT_SSINC 0x000000FF |
Definition at line 348 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS
| #define EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0724)) |
Definition at line 127 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR
| #define EMAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR 0x0000FFFF |
Definition at line 373 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_NANOSECONDS
| #define EMAC_SYSTEM_TIME_NANOSECONDS *((volatile uint32_t *) (EMAC_BASE + 0x070C)) |
Definition at line 121 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_NANOSECONDS_TSSS
| #define EMAC_SYSTEM_TIME_NANOSECONDS_TSSS 0x7FFFFFFF |
Definition at line 354 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE
| #define EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE *((volatile uint32_t *) (EMAC_BASE + 0x0714)) |
Definition at line 123 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB
| #define EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB 0x80000000 |
Definition at line 360 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS
| #define EMAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS 0x7FFFFFFF |
Definition at line 361 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_SECONDS
| #define EMAC_SYSTEM_TIME_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0708)) |
Definition at line 120 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_SECONDS_TSS
| #define EMAC_SYSTEM_TIME_SECONDS_TSS 0xFFFFFFFF |
Definition at line 351 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_SECONDS_UPDATE
| #define EMAC_SYSTEM_TIME_SECONDS_UPDATE *((volatile uint32_t *) (EMAC_BASE + 0x0710)) |
Definition at line 122 of file m467_eth_driver.h.
◆ EMAC_SYSTEM_TIME_SECONDS_UPDATE_TSS
| #define EMAC_SYSTEM_TIME_SECONDS_UPDATE_TSS 0xFFFFFFFF |
Definition at line 357 of file m467_eth_driver.h.
◆ EMAC_TARGET_TIME_NANOSECONDS
| #define EMAC_TARGET_TIME_NANOSECONDS *((volatile uint32_t *) (EMAC_BASE + 0x0720)) |
Definition at line 126 of file m467_eth_driver.h.
◆ EMAC_TARGET_TIME_NANOSECONDS_TTSLO
| #define EMAC_TARGET_TIME_NANOSECONDS_TTSLO 0xFFFFFFFF |
Definition at line 370 of file m467_eth_driver.h.
◆ EMAC_TARGET_TIME_SECONDS
| #define EMAC_TARGET_TIME_SECONDS *((volatile uint32_t *) (EMAC_BASE + 0x071C)) |
Definition at line 125 of file m467_eth_driver.h.
◆ EMAC_TARGET_TIME_SECONDS_TSTR
| #define EMAC_TARGET_TIME_SECONDS_TSTR 0xFFFFFFFF |
Definition at line 367 of file m467_eth_driver.h.
◆ EMAC_TDES0_CC
| #define EMAC_TDES0_CC 0x00000078 |
Definition at line 566 of file m467_eth_driver.h.
◆ EMAC_TDES0_CIC
| #define EMAC_TDES0_CIC 0x00C00000 |
Definition at line 551 of file m467_eth_driver.h.
◆ EMAC_TDES0_CRCR
| #define EMAC_TDES0_CRCR 0x01000000 |
Definition at line 550 of file m467_eth_driver.h.
◆ EMAC_TDES0_DB
| #define EMAC_TDES0_DB 0x00000001 |
Definition at line 569 of file m467_eth_driver.h.
◆ EMAC_TDES0_DC
| #define EMAC_TDES0_DC 0x08000000 |
Definition at line 547 of file m467_eth_driver.h.
◆ EMAC_TDES0_DP
| #define EMAC_TDES0_DP 0x04000000 |
Definition at line 548 of file m467_eth_driver.h.
◆ EMAC_TDES0_EC
| #define EMAC_TDES0_EC 0x00000100 |
Definition at line 564 of file m467_eth_driver.h.
◆ EMAC_TDES0_ED
| #define EMAC_TDES0_ED 0x00000004 |
Definition at line 567 of file m467_eth_driver.h.
◆ EMAC_TDES0_ES
| #define EMAC_TDES0_ES 0x00008000 |
Definition at line 557 of file m467_eth_driver.h.
◆ EMAC_TDES0_FF
| #define EMAC_TDES0_FF 0x00002000 |
Definition at line 559 of file m467_eth_driver.h.
◆ EMAC_TDES0_FS
| #define EMAC_TDES0_FS 0x10000000 |
Definition at line 546 of file m467_eth_driver.h.
◆ EMAC_TDES0_IC
| #define EMAC_TDES0_IC 0x40000000 |
Definition at line 544 of file m467_eth_driver.h.
◆ EMAC_TDES0_IHE
| #define EMAC_TDES0_IHE 0x00010000 |
Definition at line 556 of file m467_eth_driver.h.
◆ EMAC_TDES0_IPE
| #define EMAC_TDES0_IPE 0x00001000 |
Definition at line 560 of file m467_eth_driver.h.
◆ EMAC_TDES0_JT
| #define EMAC_TDES0_JT 0x00004000 |
Definition at line 558 of file m467_eth_driver.h.
◆ EMAC_TDES0_LC
| #define EMAC_TDES0_LC 0x00000200 |
Definition at line 563 of file m467_eth_driver.h.
◆ EMAC_TDES0_LOC
| #define EMAC_TDES0_LOC 0x00000800 |
Definition at line 561 of file m467_eth_driver.h.
◆ EMAC_TDES0_LS
| #define EMAC_TDES0_LS 0x20000000 |
Definition at line 545 of file m467_eth_driver.h.
◆ EMAC_TDES0_NC
| #define EMAC_TDES0_NC 0x00000400 |
Definition at line 562 of file m467_eth_driver.h.
◆ EMAC_TDES0_OWN
| #define EMAC_TDES0_OWN 0x80000000 |
Definition at line 543 of file m467_eth_driver.h.
◆ EMAC_TDES0_TCH
| #define EMAC_TDES0_TCH 0x00100000 |
Definition at line 553 of file m467_eth_driver.h.
◆ EMAC_TDES0_TER
| #define EMAC_TDES0_TER 0x00200000 |
Definition at line 552 of file m467_eth_driver.h.
◆ EMAC_TDES0_TTSE
| #define EMAC_TDES0_TTSE 0x02000000 |
Definition at line 549 of file m467_eth_driver.h.
◆ EMAC_TDES0_TTSS
| #define EMAC_TDES0_TTSS 0x00020000 |
Definition at line 555 of file m467_eth_driver.h.
◆ EMAC_TDES0_UF
| #define EMAC_TDES0_UF 0x00000002 |
Definition at line 568 of file m467_eth_driver.h.
◆ EMAC_TDES0_VF
| #define EMAC_TDES0_VF 0x00000080 |
Definition at line 565 of file m467_eth_driver.h.
◆ EMAC_TDES0_VLIC
| #define EMAC_TDES0_VLIC 0x000C0000 |
Definition at line 554 of file m467_eth_driver.h.
◆ EMAC_TDES1_SAIC
| #define EMAC_TDES1_SAIC 0xE0000000 |
Definition at line 570 of file m467_eth_driver.h.
◆ EMAC_TDES1_TBS1
| #define EMAC_TDES1_TBS1 0x00001FFF |
Definition at line 572 of file m467_eth_driver.h.
◆ EMAC_TDES1_TBS2
| #define EMAC_TDES1_TBS2 0x1FFF0000 |
Definition at line 571 of file m467_eth_driver.h.
◆ EMAC_TDES2_TBAP1
| #define EMAC_TDES2_TBAP1 0xFFFFFFFF |
Definition at line 573 of file m467_eth_driver.h.
◆ EMAC_TDES3_TBAP2
| #define EMAC_TDES3_TBAP2 0xFFFFFFFF |
Definition at line 574 of file m467_eth_driver.h.
◆ EMAC_TDES6_TTSL
| #define EMAC_TDES6_TTSL 0xFFFFFFFF |
Definition at line 575 of file m467_eth_driver.h.
◆ EMAC_TDES7_TTSH
| #define EMAC_TDES7_TTSH 0xFFFFFFFF |
Definition at line 576 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_ADDEND
| #define EMAC_TIMESTAMP_ADDEND *((volatile uint32_t *) (EMAC_BASE + 0x0718)) |
Definition at line 124 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_ADDEND_TSAR
| #define EMAC_TIMESTAMP_ADDEND_TSAR 0xFFFFFFFF |
Definition at line 364 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL
| #define EMAC_TIMESTAMP_CONTROL *((volatile uint32_t *) (EMAC_BASE + 0x0700)) |
Definition at line 118 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_SNAPTYPSEL
| #define EMAC_TIMESTAMP_CONTROL_SNAPTYPSEL 0x00030000 |
Definition at line 331 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSADDREG
| #define EMAC_TIMESTAMP_CONTROL_TSADDREG 0x00000020 |
Definition at line 340 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSCFUPDT
| #define EMAC_TIMESTAMP_CONTROL_TSCFUPDT 0x00000002 |
Definition at line 344 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSCTRLSSR
| #define EMAC_TIMESTAMP_CONTROL_TSCTRLSSR 0x00000200 |
Definition at line 338 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSENA
| #define EMAC_TIMESTAMP_CONTROL_TSENA 0x00000001 |
Definition at line 345 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSENALL
| #define EMAC_TIMESTAMP_CONTROL_TSENALL 0x00000100 |
Definition at line 339 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSENMACADDR
| #define EMAC_TIMESTAMP_CONTROL_TSENMACADDR 0x00040000 |
Definition at line 330 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSEVNTENA
| #define EMAC_TIMESTAMP_CONTROL_TSEVNTENA 0x00004000 |
Definition at line 333 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSINIT
| #define EMAC_TIMESTAMP_CONTROL_TSINIT 0x00000004 |
Definition at line 343 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSIPENA
| #define EMAC_TIMESTAMP_CONTROL_TSIPENA 0x00000800 |
Definition at line 336 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSIPV4ENA
| #define EMAC_TIMESTAMP_CONTROL_TSIPV4ENA 0x00002000 |
Definition at line 334 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSIPV6ENA
| #define EMAC_TIMESTAMP_CONTROL_TSIPV6ENA 0x00001000 |
Definition at line 335 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSMSTRENA
| #define EMAC_TIMESTAMP_CONTROL_TSMSTRENA 0x00008000 |
Definition at line 332 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSTRIG
| #define EMAC_TIMESTAMP_CONTROL_TSTRIG 0x00000010 |
Definition at line 341 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSUPDT
| #define EMAC_TIMESTAMP_CONTROL_TSUPDT 0x00000008 |
Definition at line 342 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_CONTROL_TSVER2ENA
| #define EMAC_TIMESTAMP_CONTROL_TSVER2ENA 0x00000400 |
Definition at line 337 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_STATUS
| #define EMAC_TIMESTAMP_STATUS *((volatile uint32_t *) (EMAC_BASE + 0x0728)) |
Definition at line 128 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_STATUS_ATSSTN
| #define EMAC_TIMESTAMP_STATUS_ATSSTN 0x000F0000 |
Definition at line 376 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_STATUS_TSSOVF
| #define EMAC_TIMESTAMP_STATUS_TSSOVF 0x00000001 |
Definition at line 379 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_STATUS_TSTARGT
| #define EMAC_TIMESTAMP_STATUS_TSTARGT 0x00000002 |
Definition at line 378 of file m467_eth_driver.h.
◆ EMAC_TIMESTAMP_STATUS_TSTRGTERR
| #define EMAC_TIMESTAMP_STATUS_TSTRGTERR 0x00000008 |
Definition at line 377 of file m467_eth_driver.h.
◆ EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR
| #define EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR *((volatile uint32_t *) (EMAC_BASE + 0x1010)) |
Definition at line 136 of file m467_eth_driver.h.
◆ EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR_TDESLA
| #define EMAC_TRANSMIT_DESCRIPTOR_LIST_ADDR_TDESLA 0xFFFFFFFF |
Definition at line 431 of file m467_eth_driver.h.
◆ EMAC_TRANSMIT_POLL_DEMAND
| #define EMAC_TRANSMIT_POLL_DEMAND *((volatile uint32_t *) (EMAC_BASE + 0x1004)) |
Definition at line 133 of file m467_eth_driver.h.
◆ EMAC_TRANSMIT_POLL_DEMAND_TPD
| #define EMAC_TRANSMIT_POLL_DEMAND_TPD 0xFFFFFFFF |
Definition at line 422 of file m467_eth_driver.h.
◆ EMAC_VERSION
| #define EMAC_VERSION *((volatile uint32_t *) (EMAC_BASE + 0x0020)) |
Definition at line 93 of file m467_eth_driver.h.
◆ EMAC_VLAN_INCL_REG
| #define EMAC_VLAN_INCL_REG *((volatile uint32_t *) (EMAC_BASE + 0x0584)) |
Definition at line 117 of file m467_eth_driver.h.
◆ EMAC_VLAN_INCL_REG_CSVL
| #define EMAC_VLAN_INCL_REG_CSVL 0x00080000 |
Definition at line 324 of file m467_eth_driver.h.
◆ EMAC_VLAN_INCL_REG_VLC
| #define EMAC_VLAN_INCL_REG_VLC 0x00030000 |
Definition at line 326 of file m467_eth_driver.h.
◆ EMAC_VLAN_INCL_REG_VLP
| #define EMAC_VLAN_INCL_REG_VLP 0x00040000 |
Definition at line 325 of file m467_eth_driver.h.
◆ EMAC_VLAN_INCL_REG_VLT
| #define EMAC_VLAN_INCL_REG_VLT 0x0000FFFF |
Definition at line 327 of file m467_eth_driver.h.
◆ EMAC_VLAN_TAG
| #define EMAC_VLAN_TAG *((volatile uint32_t *) (EMAC_BASE + 0x001C)) |
Definition at line 92 of file m467_eth_driver.h.
◆ EMAC_VLAN_TAG_ESVL
| #define EMAC_VLAN_TAG_ESVL 0x00040000 |
Definition at line 208 of file m467_eth_driver.h.
◆ EMAC_VLAN_TAG_ETV
| #define EMAC_VLAN_TAG_ETV 0x00010000 |
Definition at line 210 of file m467_eth_driver.h.
◆ EMAC_VLAN_TAG_VL
| #define EMAC_VLAN_TAG_VL 0x0000FFFF |
Definition at line 211 of file m467_eth_driver.h.
◆ EMAC_VLAN_TAG_VTIM
| #define EMAC_VLAN_TAG_VTIM 0x00020000 |
Definition at line 209 of file m467_eth_driver.h.
◆ EMAC_WDOG_TIMEOUT
| #define EMAC_WDOG_TIMEOUT *((volatile uint32_t *) (EMAC_BASE + 0x00DC)) |
Definition at line 116 of file m467_eth_driver.h.
◆ EMAC_WDOG_TIMEOUT_PWE
| #define EMAC_WDOG_TIMEOUT_PWE 0x00010000 |
Definition at line 320 of file m467_eth_driver.h.
◆ EMAC_WDOG_TIMEOUT_WTO
| #define EMAC_WDOG_TIMEOUT_WTO 0x00003FFF |
Definition at line 321 of file m467_eth_driver.h.
◆ M467_ETH_IRQ_GROUP_PRIORITY
| #define M467_ETH_IRQ_GROUP_PRIORITY 12 |
Definition at line 74 of file m467_eth_driver.h.
◆ M467_ETH_IRQ_PRIORITY_GROUPING
| #define M467_ETH_IRQ_PRIORITY_GROUPING 3 |
Definition at line 67 of file m467_eth_driver.h.
◆ M467_ETH_IRQ_SUB_PRIORITY
| #define M467_ETH_IRQ_SUB_PRIORITY 0 |
Definition at line 81 of file m467_eth_driver.h.
◆ M467_ETH_RX_BUFFER_COUNT
| #define M467_ETH_RX_BUFFER_COUNT 6 |
Definition at line 53 of file m467_eth_driver.h.
◆ M467_ETH_RX_BUFFER_SIZE
| #define M467_ETH_RX_BUFFER_SIZE 1536 |
Definition at line 60 of file m467_eth_driver.h.
◆ M467_ETH_TX_BUFFER_COUNT
| #define M467_ETH_TX_BUFFER_COUNT 3 |
Definition at line 39 of file m467_eth_driver.h.
◆ M467_ETH_TX_BUFFER_SIZE
| #define M467_ETH_TX_BUFFER_SIZE 1536 |
Definition at line 46 of file m467_eth_driver.h.
Function Documentation
◆ m467EthDisableIrq()
| void m467EthDisableIrq | ( | NetInterface * | interface | ) |
Disable interrupts.
- Parameters
-
[in] interface Underlying network interface
Definition at line 383 of file m467_eth_driver.c.
◆ m467EthEnableIrq()
| void m467EthEnableIrq | ( | NetInterface * | interface | ) |
Enable interrupts.
- Parameters
-
[in] interface Underlying network interface
Definition at line 355 of file m467_eth_driver.c.
◆ m467EthEventHandler()
| void m467EthEventHandler | ( | NetInterface * | interface | ) |
M467 Ethernet MAC event handler.
- Parameters
-
[in] interface Underlying network interface
Definition at line 463 of file m467_eth_driver.c.
◆ m467EthInit()
| error_t m467EthInit | ( | NetInterface * | interface | ) |
M467 Ethernet MAC initialization.
- Parameters
-
[in] interface Underlying network interface
- Returns
- Error code
Definition at line 114 of file m467_eth_driver.c.
◆ m467EthInitDmaDesc()
| void m467EthInitDmaDesc | ( | NetInterface * | interface | ) |
Initialize DMA descriptor lists.
- Parameters
-
[in] interface Underlying network interface
Definition at line 261 of file m467_eth_driver.c.
◆ m467EthInitGpio()
| void m467EthInitGpio | ( | NetInterface * | interface | ) |
GPIO configuration.
- Parameters
-
[in] interface Underlying network interface
Definition at line 214 of file m467_eth_driver.c.
◆ m467EthReadPhyReg()
| uint16_t m467EthReadPhyReg | ( | uint8_t | opcode, |
| uint8_t | phyAddr, | ||
| uint8_t | regAddr | ||
| ) |
Read PHY register.
- Parameters
-
[in] opcode Access type (2 bits) [in] phyAddr PHY address (5 bits) [in] regAddr Register address (5 bits)
- Returns
- Register value
Definition at line 810 of file m467_eth_driver.c.
◆ m467EthReceivePacket()
| error_t m467EthReceivePacket | ( | NetInterface * | interface | ) |
Receive a packet.
- Parameters
-
[in] interface Underlying network interface
- Returns
- Error code
Definition at line 547 of file m467_eth_driver.c.
◆ m467EthSendPacket()
| error_t m467EthSendPacket | ( | NetInterface * | interface, |
| const NetBuffer * | buffer, | ||
| size_t | offset, | ||
| NetTxAncillary * | ancillary | ||
| ) |
Send a packet.
- Parameters
-
[in] interface Underlying network interface [in] buffer Multi-part buffer containing the data to send [in] offset Offset to the first data byte [in] ancillary Additional options passed to the stack along with the packet
- Returns
- Error code
Definition at line 488 of file m467_eth_driver.c.
◆ m467EthTick()
| void m467EthTick | ( | NetInterface * | interface | ) |
M467 Ethernet MAC timer handler.
This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state
- Parameters
-
[in] interface Underlying network interface
Definition at line 330 of file m467_eth_driver.c.
◆ m467EthUpdateMacAddrFilter()
| error_t m467EthUpdateMacAddrFilter | ( | NetInterface * | interface | ) |
Configure MAC address filtering.
- Parameters
-
[in] interface Underlying network interface
- Returns
- Error code
Definition at line 617 of file m467_eth_driver.c.
◆ m467EthUpdateMacConfig()
| error_t m467EthUpdateMacConfig | ( | NetInterface * | interface | ) |
Adjust MAC configuration parameters for proper operation.
- Parameters
-
[in] interface Underlying network interface
- Returns
- Error code
Definition at line 725 of file m467_eth_driver.c.
◆ m467EthWritePhyReg()
| void m467EthWritePhyReg | ( | uint8_t | opcode, |
| uint8_t | phyAddr, | ||
| uint8_t | regAddr, | ||
| uint16_t | data | ||
| ) |
Write PHY register.
- Parameters
-
[in] opcode Access type (2 bits) [in] phyAddr PHY address (5 bits) [in] regAddr Register address (5 bits) [in] data Register value
Definition at line 768 of file m467_eth_driver.c.
Variable Documentation
◆ m467EthDriver
|
extern |
M467 Ethernet MAC driver.
Definition at line 87 of file m467_eth_driver.c.