rx62n_eth_driver.c
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1 /**
2  * @file rx62n_eth_driver.c
3  * @brief Renesas RX62N Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <iorx62n.h>
36 #include <intrinsics.h>
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWRX compiler?
45 #if defined(__ICCRX__)
46 
47 //Transmit buffer
48 #pragma data_alignment = 32
50 //Receive buffer
51 #pragma data_alignment = 32
53 //Transmit DMA descriptors
54 #pragma data_alignment = 32
56 //Receive DMA descriptors
57 #pragma data_alignment = 32
59 
60 //GCC compiler?
61 #else
62 
63 //Transmit buffer
65  __attribute__((aligned(32)));
66 //Receive buffer
68  __attribute__((aligned(32)));
69 //Transmit DMA descriptors
71  __attribute__((aligned(32)));
72 //Receive DMA descriptors
74  __attribute__((aligned(32)));
75 
76 #endif
77 
78 //Current transmit descriptor
79 static uint_t txIndex;
80 //Current receive descriptor
81 static uint_t rxIndex;
82 
83 
84 /**
85  * @brief RX62N Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  TRUE
106 };
107 
108 
109 /**
110  * @brief RX62N Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118 
119  //Debug message
120  TRACE_INFO("Initializing RX62N Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Cancel EDMAC module stop state
126  MSTP(EDMAC) = 0;
127 
128  //GPIO configuration
129  rx62nEthInitGpio(interface);
130 
131  //Reset EDMAC module
132  EDMAC.EDMR.BIT.SWR = 1;
133  //Wait for the reset to complete
134  sleep(10);
135 
136  //Valid Ethernet PHY or switch driver?
137  if(interface->phyDriver != NULL)
138  {
139  //Ethernet PHY initialization
140  error = interface->phyDriver->init(interface);
141  }
142  else if(interface->switchDriver != NULL)
143  {
144  //Ethernet switch initialization
145  error = interface->switchDriver->init(interface);
146  }
147  else
148  {
149  //The interface is not properly configured
150  error = ERROR_FAILURE;
151  }
152 
153  //Any error to report?
154  if(error)
155  {
156  return error;
157  }
158 
159  //Initialize DMA descriptor lists
160  rx62nEthInitDmaDesc(interface);
161 
162  //Maximum frame length that can be accepted
163  ETHERC.RFLR.LONG = RX62N_ETH_RX_BUFFER_SIZE;
164  //Set default inter packet gap (96-bit time)
165  ETHERC.IPGR.LONG = 0x14;
166 
167  //Set the upper 32 bits of the MAC address
168  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
169  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
170 
171  //Set the lower 16 bits of the MAC address
172  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
173 
174  //Set descriptor length (16 bytes)
175  EDMAC.EDMR.BIT.DL = 0;
176 
177 #ifdef _CPU_BIG_ENDIAN
178  //Select big endian mode
179  EDMAC.EDMR.BIT.DE = 0;
180 #else
181  //Select little endian mode
182  EDMAC.EDMR.BIT.DE = 1;
183 #endif
184 
185  //Use store and forward mode
186  EDMAC.TFTR.BIT.TFT = 0;
187 
188  //Set transmit FIFO size (2048 bytes)
189  EDMAC.FDR.BIT.TFD = 7;
190  //Set receive FIFO size (2048 bytes)
191  EDMAC.FDR.BIT.RFD = 7;
192 
193  //Enable continuous reception of multiple frames
194  EDMAC.RMCR.BIT.RNR = 1;
195 
196  //Accept transmit interrupt notifications
197  EDMAC.TRIMD.BIT.TIM = 0;
198  EDMAC.TRIMD.BIT.TIS = 1;
199 
200  //Disable all EDMAC interrupts
201  EDMAC.EESIPR.LONG = 0;
202  //Enable only the desired EDMAC interrupts
203  EDMAC.EESIPR.BIT.TWBIP = 1;
204  EDMAC.EESIPR.BIT.FRIP = 1;
205 
206  //Configure EDMAC interrupt priority
207  IPR(ETHER, EINT) = RX62N_ETH_IRQ_PRIORITY;
208 
209  //Enable transmission and reception
210  ETHERC.ECMR.BIT.TE = 1;
211  ETHERC.ECMR.BIT.RE = 1;
212 
213  //Instruct the DMA to poll the receive descriptor list
214  EDMAC.EDRRR.BIT.RR = 1;
215 
216  //Accept any packets from the upper layer
217  osSetEvent(&interface->nicTxEvent);
218 
219  //Successful initialization
220  return NO_ERROR;
221 }
222 
223 
224 /**
225  * @brief GPIO configuration
226  * @param[in] interface Underlying network interface
227  **/
228 
229 __weak_func void rx62nEthInitGpio(NetInterface *interface)
230 {
231 //RDK-RX62N evaluation board?
232 #if defined(USE_RDK_RX62N)
233  //Select RMII interface mode
234  IOPORT.PFENET.BIT.PHYMODE = 0;
235 
236  //Enable Ethernet pins
237  IOPORT.PFENET.BIT.EE = 1;
238  //Disable ET_WOL pin
239  IOPORT.PFENET.BIT.ENETE0 = 0;
240  //Enable ET_LINKSTA pin
241  IOPORT.PFENET.BIT.ENETE1 = 1;
242  //Disable ET_EXOUT pin
243  IOPORT.PFENET.BIT.ENETE2 = 0;
244  //Disable ET_TX_ER pin
245  IOPORT.PFENET.BIT.ENETE3 = 0;
246 
247  //Configure ET_MDIO (PA3)
248  PORTA.ICR.BIT.B3 = 1;
249  //Configure ET_LINKSTA (PA5)
250  PORTA.ICR.BIT.B5 = 1;
251  //Configure RMII_RXD1 (PB0)
252  PORTB.ICR.BIT.B0 = 1;
253  //Configure RMII_RXD0 (PB1)
254  PORTB.ICR.BIT.B1 = 1;
255  //Configure REF50CK (PB2)
256  PORTB.ICR.BIT.B2 = 1;
257  //Configure RMII_RX_ER (PB3)
258  PORTB.ICR.BIT.B3 = 1;
259  //Configure RMII_CRS_DV (PB7)
260  PORTB.ICR.BIT.B7 = 1;
261 #endif
262 }
263 
264 
265 /**
266  * @brief Initialize DMA descriptor lists
267  * @param[in] interface Underlying network interface
268  **/
269 
271 {
272  uint_t i;
273 
274  //Initialize TX descriptors
275  for(i = 0; i < RX62N_ETH_TX_BUFFER_COUNT; i++)
276  {
277  //The descriptor is initially owned by the application
278  txDmaDesc[i].td0 = 0;
279  //Transmit buffer length
280  txDmaDesc[i].td1 = 0;
281  //Transmit buffer address
282  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
283  //Clear padding field
284  txDmaDesc[i].padding = 0;
285  }
286 
287  //Mark the last descriptor entry with the TDLE flag
288  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
289  //Initialize TX descriptor index
290  txIndex = 0;
291 
292  //Initialize RX descriptors
293  for(i = 0; i < RX62N_ETH_RX_BUFFER_COUNT; i++)
294  {
295  //The descriptor is initially owned by the DMA
296  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
297  //Receive buffer length
299  //Receive buffer address
300  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
301  //Clear padding field
302  rxDmaDesc[i].padding = 0;
303  }
304 
305  //Mark the last descriptor entry with the RDLE flag
306  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
307  //Initialize RX descriptor index
308  rxIndex = 0;
309 
310  //Start address of the TX descriptor list
311  EDMAC.TDLAR = txDmaDesc;
312  //Start address of the RX descriptor list
313  EDMAC.RDLAR = rxDmaDesc;
314 }
315 
316 
317 /**
318  * @brief RX62N Ethernet MAC timer handler
319  *
320  * This routine is periodically called by the TCP/IP stack to handle periodic
321  * operations such as polling the link state
322  *
323  * @param[in] interface Underlying network interface
324  **/
325 
326 void rx62nEthTick(NetInterface *interface)
327 {
328  //Valid Ethernet PHY or switch driver?
329  if(interface->phyDriver != NULL)
330  {
331  //Handle periodic operations
332  interface->phyDriver->tick(interface);
333  }
334  else if(interface->switchDriver != NULL)
335  {
336  //Handle periodic operations
337  interface->switchDriver->tick(interface);
338  }
339  else
340  {
341  //Just for sanity
342  }
343 }
344 
345 
346 /**
347  * @brief Enable interrupts
348  * @param[in] interface Underlying network interface
349  **/
350 
352 {
353  //Enable Ethernet MAC interrupts
354  IEN(ETHER, EINT) = 1;
355 
356  //Valid Ethernet PHY or switch driver?
357  if(interface->phyDriver != NULL)
358  {
359  //Enable Ethernet PHY interrupts
360  interface->phyDriver->enableIrq(interface);
361  }
362  else if(interface->switchDriver != NULL)
363  {
364  //Enable Ethernet switch interrupts
365  interface->switchDriver->enableIrq(interface);
366  }
367  else
368  {
369  //Just for sanity
370  }
371 }
372 
373 
374 /**
375  * @brief Disable interrupts
376  * @param[in] interface Underlying network interface
377  **/
378 
380 {
381  //Disable Ethernet MAC interrupts
382  IEN(ETHER, EINT) = 0;
383 
384  //Valid Ethernet PHY or switch driver?
385  if(interface->phyDriver != NULL)
386  {
387  //Disable Ethernet PHY interrupts
388  interface->phyDriver->disableIrq(interface);
389  }
390  else if(interface->switchDriver != NULL)
391  {
392  //Disable Ethernet switch interrupts
393  interface->switchDriver->disableIrq(interface);
394  }
395  else
396  {
397  //Just for sanity
398  }
399 }
400 
401 
402 /**
403  * @brief RX62N Ethernet MAC interrupt service routine
404  **/
405 
406 #pragma vector = VECT_ETHER_EINT
407 __interrupt void rx62nEthIrqHandler(void)
408 {
409  bool_t flag;
410  uint32_t status;
411 
412  //Allow nested interrupts
413  __enable_interrupt();
414 
415  //This flag will be set if a higher priority task must be woken
416  flag = FALSE;
417 
418  //Read interrupt status register
419  status = EDMAC.EESR.LONG;
420 
421  //Packet transmitted?
422  if((status & EDMAC_EESR_TWB) != 0)
423  {
424  //Clear TWB interrupt flag
425  EDMAC.EESR.LONG = EDMAC_EESR_TWB;
426 
427  //Check whether the TX buffer is available for writing
428  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) == 0)
429  {
430  //Notify the TCP/IP stack that the transmitter is ready to send
431  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
432  }
433  }
434 
435  //Packet received?
436  if((status & EDMAC_EESR_FR) != 0)
437  {
438  //Disable FR interrupts
439  EDMAC.EESIPR.BIT.FRIP = 0;
440 
441  //Set event flag
442  nicDriverInterface->nicEvent = TRUE;
443  //Notify the TCP/IP stack of the event
444  flag |= osSetEventFromIsr(&netEvent);
445  }
446 
447  //Interrupt service routine epilogue
448  osExitIsr(flag);
449 }
450 
451 
452 /**
453  * @brief RX62N Ethernet MAC event handler
454  * @param[in] interface Underlying network interface
455  **/
456 
458 {
459  error_t error;
460 
461  //Packet received?
462  if((EDMAC.EESR.LONG & EDMAC_EESR_FR) != 0)
463  {
464  //Clear FR interrupt flag
465  EDMAC.EESR.LONG = EDMAC_EESR_FR;
466 
467  //Process all pending packets
468  do
469  {
470  //Read incoming packet
471  error = rx62nEthReceivePacket(interface);
472 
473  //No more data in the receive buffer?
474  } while(error != ERROR_BUFFER_EMPTY);
475  }
476 
477  //Re-enable EDMAC interrupts
478  EDMAC.EESIPR.BIT.TWBIP = 1;
479  EDMAC.EESIPR.BIT.FRIP = 1;
480 }
481 
482 
483 /**
484  * @brief Send a packet
485  * @param[in] interface Underlying network interface
486  * @param[in] buffer Multi-part buffer containing the data to send
487  * @param[in] offset Offset to the first data byte
488  * @param[in] ancillary Additional options passed to the stack along with
489  * the packet
490  * @return Error code
491  **/
492 
494  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
495 {
496  //Retrieve the length of the packet
497  size_t length = netBufferGetLength(buffer) - offset;
498 
499  //Check the frame length
501  {
502  //The transmitter can accept another packet
503  osSetEvent(&interface->nicTxEvent);
504  //Report an error
505  return ERROR_INVALID_LENGTH;
506  }
507 
508  //Make sure the current buffer is available for writing
509  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) != 0)
510  {
511  return ERROR_FAILURE;
512  }
513 
514  //Copy user data to the transmit buffer
515  netBufferRead(txBuffer[txIndex], buffer, offset, length);
516 
517  //Write the number of bytes to send
518  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
519 
520  //Check current index
521  if(txIndex < (RX62N_ETH_TX_BUFFER_COUNT - 1))
522  {
523  //Give the ownership of the descriptor to the DMA engine
524  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
526 
527  //Point to the next descriptor
528  txIndex++;
529  }
530  else
531  {
532  //Give the ownership of the descriptor to the DMA engine
533  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
535 
536  //Wrap around
537  txIndex = 0;
538  }
539 
540  //Instruct the DMA to poll the transmit descriptor list
541  EDMAC.EDTRR.BIT.TR = 1;
542 
543  //Check whether the next buffer is available for writing
544  if((txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT) == 0)
545  {
546  //The transmitter can accept another packet
547  osSetEvent(&interface->nicTxEvent);
548  }
549 
550  //Successful write operation
551  return NO_ERROR;
552 }
553 
554 
555 /**
556  * @brief Receive a packet
557  * @param[in] interface Underlying network interface
558  * @return Error code
559  **/
560 
562 {
563  error_t error;
564  size_t n;
565  NetRxAncillary ancillary;
566 
567  //Current buffer available for reading?
568  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT) == 0)
569  {
570  //SOF and EOF flags should be set
571  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) != 0 &&
572  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF) != 0)
573  {
574  //Make sure no error occurred
575  if((rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)) == 0)
576  {
577  //Retrieve the length of the frame
578  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
579  //Limit the number of data to read
581 
582  //Additional options can be passed to the stack along with the packet
583  ancillary = NET_DEFAULT_RX_ANCILLARY;
584 
585  //Pass the packet to the upper layer
586  nicProcessPacket(interface, rxBuffer[rxIndex], n, &ancillary);
587 
588  //Valid packet received
589  error = NO_ERROR;
590  }
591  else
592  {
593  //The received packet contains an error
594  error = ERROR_INVALID_PACKET;
595  }
596  }
597  else
598  {
599  //The packet is not valid
600  error = ERROR_INVALID_PACKET;
601  }
602 
603  //Check current index
604  if(rxIndex < (RX62N_ETH_RX_BUFFER_COUNT - 1))
605  {
606  //Give the ownership of the descriptor back to the DMA
607  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
608  //Point to the next descriptor
609  rxIndex++;
610  }
611  else
612  {
613  //Give the ownership of the descriptor back to the DMA
614  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
615  //Wrap around
616  rxIndex = 0;
617  }
618 
619  //Instruct the DMA to poll the receive descriptor list
620  EDMAC.EDRRR.BIT.RR = 1;
621  }
622  else
623  {
624  //No more data in the receive buffer
625  error = ERROR_BUFFER_EMPTY;
626  }
627 
628  //Return status code
629  return error;
630 }
631 
632 
633 /**
634  * @brief Configure MAC address filtering
635  * @param[in] interface Underlying network interface
636  * @return Error code
637  **/
638 
640 {
641  uint_t i;
642  bool_t acceptMulticast;
643 
644  //Debug message
645  TRACE_DEBUG("Updating MAC filter...\r\n");
646 
647  //Set the upper 32 bits of the MAC address
648  ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
649  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
650 
651  //Set the lower 16 bits of the MAC address
652  ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
653 
654  //This flag will be set if multicast addresses should be accepted
655  acceptMulticast = FALSE;
656 
657  //The MAC address filter contains the list of MAC addresses to accept
658  //when receiving an Ethernet frame
659  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
660  {
661  //Valid entry?
662  if(interface->macAddrFilter[i].refCount > 0)
663  {
664  //Accept multicast addresses
665  acceptMulticast = TRUE;
666  //We are done
667  break;
668  }
669  }
670 
671  //Enable or disable the reception of multicast frames
672  if(acceptMulticast)
673  {
674  EDMAC.EESR.BIT.RMAF = 1;
675  }
676  else
677  {
678  EDMAC.EESR.BIT.RMAF = 0;
679  }
680 
681  //Successful processing
682  return NO_ERROR;
683 }
684 
685 
686 /**
687  * @brief Adjust MAC configuration parameters for proper operation
688  * @param[in] interface Underlying network interface
689  * @return Error code
690  **/
691 
693 {
694  //10BASE-T or 100BASE-TX operation mode?
695  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
696  {
697  ETHERC.ECMR.BIT.RTM = 1;
698  }
699  else
700  {
701  ETHERC.ECMR.BIT.RTM = 0;
702  }
703 
704  //Half-duplex or full-duplex mode?
705  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
706  {
707  ETHERC.ECMR.BIT.DM = 1;
708  }
709  else
710  {
711  ETHERC.ECMR.BIT.DM = 0;
712  }
713 
714  //Successful processing
715  return NO_ERROR;
716 }
717 
718 
719 /**
720  * @brief Write PHY register
721  * @param[in] opcode Access type (2 bits)
722  * @param[in] phyAddr PHY address (5 bits)
723  * @param[in] regAddr Register address (5 bits)
724  * @param[in] data Register value
725  **/
726 
727 void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
728  uint8_t regAddr, uint16_t data)
729 {
730  //Synchronization pattern
732  //Start of frame
734  //Set up a write operation
736  //Write PHY address
737  rx62nEthWriteSmi(phyAddr, 5);
738  //Write register address
740  //Turnaround
742  //Write register value
743  rx62nEthWriteSmi(data, 16);
744  //Release MDIO
745  rx62nEthReadSmi(1);
746 }
747 
748 
749 /**
750  * @brief Read PHY register
751  * @param[in] opcode Access type (2 bits)
752  * @param[in] phyAddr PHY address (5 bits)
753  * @param[in] regAddr Register address (5 bits)
754  * @return Register value
755  **/
756 
757 uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
758  uint8_t regAddr)
759 {
760  uint16_t data;
761 
762  //Synchronization pattern
764  //Start of frame
766  //Set up a read operation
768  //Write PHY address
769  rx62nEthWriteSmi(phyAddr, 5);
770  //Write register address
772  //Turnaround to avoid contention
773  rx62nEthReadSmi(1);
774  //Read register value
775  data = rx62nEthReadSmi(16);
776  //Force the PHY to release the MDIO pin
777  rx62nEthReadSmi(1);
778 
779  //Return PHY register contents
780  return data;
781 }
782 
783 
784 /**
785  * @brief SMI write operation
786  * @param[in] data Raw data to be written
787  * @param[in] length Number of bits to be written
788  **/
789 
791 {
792  //Skip the most significant bits since they are meaningless
793  data <<= 32 - length;
794 
795  //Configure MDIO as an output
796  ETHERC.PIR.BIT.MMD = 1;
797 
798  //Write the specified number of bits
799  while(length--)
800  {
801  //Write MDIO
802  if((data & 0x80000000) != 0)
803  {
804  ETHERC.PIR.BIT.MDO = 1;
805  }
806  else
807  {
808  ETHERC.PIR.BIT.MDO = 0;
809  }
810 
811  //Assert MDC
812  usleep(1);
813  ETHERC.PIR.BIT.MDC = 1;
814  //Deassert MDC
815  usleep(1);
816  ETHERC.PIR.BIT.MDC = 0;
817 
818  //Rotate data
819  data <<= 1;
820  }
821 }
822 
823 
824 /**
825  * @brief SMI read operation
826  * @param[in] length Number of bits to be read
827  * @return Data resulting from the MDIO read operation
828  **/
829 
831 {
832  uint32_t data = 0;
833 
834  //Configure MDIO as an input
835  ETHERC.PIR.BIT.MMD = 0;
836 
837  //Read the specified number of bits
838  while(length--)
839  {
840  //Rotate data
841  data <<= 1;
842 
843  //Assert MDC
844  ETHERC.PIR.BIT.MDC = 1;
845  usleep(1);
846  //Deassert MDC
847  ETHERC.PIR.BIT.MDC = 0;
848  usleep(1);
849 
850  //Check MDIO state
851  if(ETHERC.PIR.BIT.MDI != 0)
852  {
853  data |= 0x01;
854  }
855  }
856 
857  //Return the received data
858  return data;
859 }
#define txDmaDesc
#define rxBuffer
#define txBuffer
#define rxDmaDesc
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
uint16_t regAddr
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_SYNC
Definition: nic.h:63
#define SMI_START
Definition: nic.h:64
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_TA
Definition: nic.h:68
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define usleep(delay)
Definition: os_port.h:297
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osExitIsr(flag)
#define EDMAC_TD1_TBL
#define EDMAC_RD0_RFS_MASK
#define EDMAC_RD0_RDLE
#define EDMAC_RD0_RFS_RMAF
#define EDMAC_RD1_RFL
#define EDMAC_TD0_TWBI
#define EDMAC_TD0_TACT
#define EDMAC_RD1_RBL
#define EDMAC_TD0_TDLE
#define EDMAC_TD0_TFP_EOF
#define EDMAC_RD0_RACT
#define EDMAC_RD0_RFP_EOF
#define EDMAC_RD0_RFP_SOF
#define EDMAC_TD0_TFP_SOF
uint32_t rx62nEthReadSmi(uint_t length)
SMI read operation.
void rx62nEthEnableIrq(NetInterface *interface)
Enable interrupts.
void rx62nEthEventHandler(NetInterface *interface)
RX62N Ethernet MAC event handler.
const NicDriver rx62nEthDriver
RX62N Ethernet MAC driver.
error_t rx62nEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t rx62nEthReceivePacket(NetInterface *interface)
Receive a packet.
void rx62nEthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
error_t rx62nEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
__interrupt void rx62nEthIrqHandler(void)
RX62N Ethernet MAC interrupt service routine.
void rx62nEthTick(NetInterface *interface)
RX62N Ethernet MAC timer handler.
void rx62nEthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
__weak_func void rx62nEthInitGpio(NetInterface *interface)
GPIO configuration.
error_t rx62nEthInit(NetInterface *interface)
RX62N Ethernet MAC initialization.
error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void rx62nEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Renesas RX62N Ethernet MAC driver.
#define RX62N_ETH_IRQ_PRIORITY
#define RX62N_ETH_RX_BUFFER_SIZE
#define RX62N_ETH_RX_BUFFER_COUNT
#define EDMAC_EESR_TWB
#define EDMAC_EESR_FR
#define RX62N_ETH_TX_BUFFER_SIZE
#define RX62N_ETH_TX_BUFFER_COUNT
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive DMA descriptor.
Transmit DMA descriptor.
uint8_t length
Definition: tcp.h:368