sam3x_eth_driver.c
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1 /**
2  * @file sam3x_eth_driver.c
3  * @brief SAM3X Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "sam3xa.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
50 //RX buffer
51 #pragma data_alignment = 8
53 //TX buffer descriptors
54 #pragma data_alignment = 4
55 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT];
56 //RX buffer descriptors
57 #pragma data_alignment = 4
58 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT];
59 
60 //Keil MDK-ARM or GCC compiler?
61 #else
62 
63 //TX buffer
65  __attribute__((aligned(8)));
66 //RX buffer
68  __attribute__((aligned(8)));
69 //TX buffer descriptors
71  __attribute__((aligned(4)));
72 //RX buffer descriptors
74  __attribute__((aligned(4)));
75 
76 #endif
77 
78 //TX buffer index
79 static uint_t txBufferIndex;
80 //RX buffer index
81 static uint_t rxBufferIndex;
82 
83 
84 /**
85  * @brief SAM3X Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  FALSE
106 };
107 
108 
109 /**
110  * @brief SAM3X Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118  volatile uint32_t status;
119 
120  //Debug message
121  TRACE_INFO("Initializing SAM3X Ethernet MAC...\r\n");
122 
123  //Save underlying network interface
124  nicDriverInterface = interface;
125 
126  //Enable EMAC peripheral clock
127  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
128 
129  //Disable transmit and receive circuits
130  EMAC->EMAC_NCR = 0;
131 
132  //GPIO configuration
133  sam3xEthInitGpio(interface);
134 
135  //Configure MDC clock speed
136  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
137  //Enable management port (MDC and MDIO)
138  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
139 
140  //Valid Ethernet PHY or switch driver?
141  if(interface->phyDriver != NULL)
142  {
143  //Ethernet PHY initialization
144  error = interface->phyDriver->init(interface);
145  }
146  else if(interface->switchDriver != NULL)
147  {
148  //Ethernet switch initialization
149  error = interface->switchDriver->init(interface);
150  }
151  else
152  {
153  //The interface is not properly configured
154  error = ERROR_FAILURE;
155  }
156 
157  //Any error to report?
158  if(error)
159  {
160  return error;
161  }
162 
163  //Set the MAC address of the station
164  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
165  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
166 
167  //The MAC supports 3 additional addresses for unicast perfect filtering
168  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
169  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
170  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
171 
172  //Initialize hash table
173  EMAC->EMAC_HRB = 0;
174  EMAC->EMAC_HRT = 0;
175 
176  //Configure the receive filter
177  EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
178 
179  //Initialize buffer descriptors
180  sam3xEthInitBufferDesc(interface);
181 
182  //Clear transmit status register
183  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
184  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
185 
186  //Clear receive status register
187  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
188 
189  //First disable all EMAC interrupts
190  EMAC->EMAC_IDR = 0xFFFFFFFF;
191 
192  //Only the desired ones are enabled
193  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
194  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
195 
196  //Read EMAC_ISR register to clear any pending interrupt
197  status = EMAC->EMAC_ISR;
198  (void) status;
199 
200  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
201  NVIC_SetPriorityGrouping(SAM3X_ETH_IRQ_PRIORITY_GROUPING);
202 
203  //Configure EMAC interrupt priority
204  NVIC_SetPriority(EMAC_IRQn, NVIC_EncodePriority(SAM3X_ETH_IRQ_PRIORITY_GROUPING,
206 
207  //Enable the EMAC to transmit and receive data
208  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
209 
210  //Accept any packets from the upper layer
211  osSetEvent(&interface->nicTxEvent);
212 
213  //Successful initialization
214  return NO_ERROR;
215 }
216 
217 
218 /**
219  * @brief GPIO configuration
220  * @param[in] interface Underlying network interface
221  **/
222 
223 __weak_func void sam3xEthInitGpio(NetInterface *interface)
224 {
225 //SAM3X-EK evaluation board?
226 #if defined(USE_SAM3X_EK)
227  //Enable PIO peripheral clock
228  PMC->PMC_PCER0 = (1 << ID_PIOB);
229 
230  //Disable pull-up resistors on RMII pins
231  PIOB->PIO_PUDR = EMAC_RMII_MASK;
232  //Disable interrupts-on-change
233  PIOB->PIO_IDR = EMAC_RMII_MASK;
234  //Assign RMII pins to peripheral A function
235  PIOB->PIO_ABSR &= ~EMAC_RMII_MASK;
236  //Disable the PIO from controlling the corresponding pins
237  PIOB->PIO_PDR = EMAC_RMII_MASK;
238 
239  //Select RMII operation mode and enable transceiver clock
240  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
241 #endif
242 }
243 
244 
245 /**
246  * @brief Initialize buffer descriptors
247  * @param[in] interface Underlying network interface
248  **/
249 
251 {
252  uint_t i;
253  uint32_t address;
254 
255  //Initialize TX buffer descriptors
256  for(i = 0; i < SAM3X_ETH_TX_BUFFER_COUNT; i++)
257  {
258  //Calculate the address of the current TX buffer
259  address = (uint32_t) txBuffer[i];
260  //Write the address to the descriptor entry
261  txBufferDesc[i].address = address;
262  //Initialize status field
263  txBufferDesc[i].status = EMAC_TX_USED;
264  }
265 
266  //Mark the last descriptor entry with the wrap flag
267  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
268  //Initialize TX buffer index
269  txBufferIndex = 0;
270 
271  //Initialize RX buffer descriptors
272  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
273  {
274  //Calculate the address of the current RX buffer
275  address = (uint32_t) rxBuffer[i];
276  //Write the address to the descriptor entry
277  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
278  //Clear status field
279  rxBufferDesc[i].status = 0;
280  }
281 
282  //Mark the last descriptor entry with the wrap flag
283  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
284  //Initialize RX buffer index
285  rxBufferIndex = 0;
286 
287  //Start location of the TX descriptor list
288  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
289  //Start location of the RX descriptor list
290  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
291 }
292 
293 
294 /**
295  * @brief SAM3X Ethernet MAC timer handler
296  *
297  * This routine is periodically called by the TCP/IP stack to handle periodic
298  * operations such as polling the link state
299  *
300  * @param[in] interface Underlying network interface
301  **/
302 
303 void sam3xEthTick(NetInterface *interface)
304 {
305  //Valid Ethernet PHY or switch driver?
306  if(interface->phyDriver != NULL)
307  {
308  //Handle periodic operations
309  interface->phyDriver->tick(interface);
310  }
311  else if(interface->switchDriver != NULL)
312  {
313  //Handle periodic operations
314  interface->switchDriver->tick(interface);
315  }
316  else
317  {
318  //Just for sanity
319  }
320 }
321 
322 
323 /**
324  * @brief Enable interrupts
325  * @param[in] interface Underlying network interface
326  **/
327 
329 {
330  //Enable Ethernet MAC interrupts
331  NVIC_EnableIRQ(EMAC_IRQn);
332 
333  //Valid Ethernet PHY or switch driver?
334  if(interface->phyDriver != NULL)
335  {
336  //Enable Ethernet PHY interrupts
337  interface->phyDriver->enableIrq(interface);
338  }
339  else if(interface->switchDriver != NULL)
340  {
341  //Enable Ethernet switch interrupts
342  interface->switchDriver->enableIrq(interface);
343  }
344  else
345  {
346  //Just for sanity
347  }
348 }
349 
350 
351 /**
352  * @brief Disable interrupts
353  * @param[in] interface Underlying network interface
354  **/
355 
357 {
358  //Disable Ethernet MAC interrupts
359  NVIC_DisableIRQ(EMAC_IRQn);
360 
361  //Valid Ethernet PHY or switch driver?
362  if(interface->phyDriver != NULL)
363  {
364  //Disable Ethernet PHY interrupts
365  interface->phyDriver->disableIrq(interface);
366  }
367  else if(interface->switchDriver != NULL)
368  {
369  //Disable Ethernet switch interrupts
370  interface->switchDriver->disableIrq(interface);
371  }
372  else
373  {
374  //Just for sanity
375  }
376 }
377 
378 
379 /**
380  * @brief SAM3X Ethernet MAC interrupt service routine
381  **/
382 
383 void EMAC_Handler(void)
384 {
385  bool_t flag;
386  volatile uint32_t isr;
387  volatile uint32_t tsr;
388  volatile uint32_t rsr;
389 
390  //Interrupt service routine prologue
391  osEnterIsr();
392 
393  //This flag will be set if a higher priority task must be woken
394  flag = FALSE;
395 
396  //Each time the software reads EMAC_ISR, it has to check the contents
397  //of EMAC_TSR, EMAC_RSR and EMAC_NSR
398  isr = EMAC->EMAC_ISR;
399  tsr = EMAC->EMAC_TSR;
400  rsr = EMAC->EMAC_RSR;
401  (void) isr;
402 
403  //Packet transmitted?
404  if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
405  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
406  {
407  //Only clear TSR flags that are currently set
408  EMAC->EMAC_TSR = tsr;
409 
410  //Check whether the TX buffer is available for writing
411  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
412  {
413  //Notify the TCP/IP stack that the transmitter is ready to send
414  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
415  }
416  }
417 
418  //Packet received?
419  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
420  {
421  //Set event flag
422  nicDriverInterface->nicEvent = TRUE;
423  //Notify the TCP/IP stack of the event
424  flag |= osSetEventFromIsr(&netEvent);
425  }
426 
427  //Interrupt service routine epilogue
428  osExitIsr(flag);
429 }
430 
431 
432 /**
433  * @brief SAM3X Ethernet MAC event handler
434  * @param[in] interface Underlying network interface
435  **/
436 
438 {
439  error_t error;
440  uint32_t rsr;
441 
442  //Read receive status
443  rsr = EMAC->EMAC_RSR;
444 
445  //Packet received?
446  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
447  {
448  //Only clear RSR flags that are currently set
449  EMAC->EMAC_RSR = rsr;
450 
451  //Process all pending packets
452  do
453  {
454  //Read incoming packet
455  error = sam3xEthReceivePacket(interface);
456 
457  //No more data in the receive buffer?
458  } while(error != ERROR_BUFFER_EMPTY);
459  }
460 }
461 
462 
463 /**
464  * @brief Send a packet
465  * @param[in] interface Underlying network interface
466  * @param[in] buffer Multi-part buffer containing the data to send
467  * @param[in] offset Offset to the first data byte
468  * @param[in] ancillary Additional options passed to the stack along with
469  * the packet
470  * @return Error code
471  **/
472 
474  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
475 {
476  size_t length;
477 
478  //Retrieve the length of the packet
479  length = netBufferGetLength(buffer) - offset;
480 
481  //Check the frame length
483  {
484  //The transmitter can accept another packet
485  osSetEvent(&interface->nicTxEvent);
486  //Report an error
487  return ERROR_INVALID_LENGTH;
488  }
489 
490  //Make sure the current buffer is available for writing
491  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) == 0)
492  {
493  return ERROR_FAILURE;
494  }
495 
496  //Copy user data to the transmit buffer
497  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
498 
499  //Set the necessary flags in the descriptor entry
500  if(txBufferIndex < (SAM3X_ETH_TX_BUFFER_COUNT - 1))
501  {
502  //Write the status word
503  txBufferDesc[txBufferIndex].status = EMAC_TX_LAST |
505 
506  //Point to the next buffer
507  txBufferIndex++;
508  }
509  else
510  {
511  //Write the status word
512  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP | EMAC_TX_LAST |
514 
515  //Wrap around
516  txBufferIndex = 0;
517  }
518 
519  //Set the TSTART bit to initiate transmission
520  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
521 
522  //Check whether the next buffer is available for writing
523  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
524  {
525  //The transmitter can accept another packet
526  osSetEvent(&interface->nicTxEvent);
527  }
528 
529  //Successful processing
530  return NO_ERROR;
531 }
532 
533 
534 /**
535  * @brief Receive a packet
536  * @param[in] interface Underlying network interface
537  * @return Error code
538  **/
539 
541 {
542  static uint32_t temp[ETH_MAX_FRAME_SIZE / 4];
543  error_t error;
544  uint_t i;
545  uint_t j;
546  uint_t sofIndex;
547  uint_t eofIndex;
548  size_t n;
549  size_t size;
550  size_t length;
551 
552  //Initialize variables
553  size = 0;
554  sofIndex = UINT_MAX;
555  eofIndex = UINT_MAX;
556 
557  //Search for SOF and EOF flags
558  for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
559  {
560  //Point to the current entry
561  j = rxBufferIndex + i;
562 
563  //Wrap around to the beginning of the buffer if necessary
565  {
567  }
568 
569  //No more entries to process?
570  if((rxBufferDesc[j].address & EMAC_RX_OWNERSHIP) == 0)
571  {
572  //Stop processing
573  break;
574  }
575 
576  //A valid SOF has been found?
577  if((rxBufferDesc[j].status & EMAC_RX_SOF) != 0)
578  {
579  //Save the position of the SOF
580  sofIndex = i;
581  }
582 
583  //A valid EOF has been found?
584  if((rxBufferDesc[j].status & EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
585  {
586  //Save the position of the EOF
587  eofIndex = i;
588  //Retrieve the length of the frame
589  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
590  //Limit the number of data to read
591  size = MIN(size, ETH_MAX_FRAME_SIZE);
592  //Stop processing since we have reached the end of the frame
593  break;
594  }
595  }
596 
597  //Determine the number of entries to process
598  if(eofIndex != UINT_MAX)
599  {
600  j = eofIndex + 1;
601  }
602  else if(sofIndex != UINT_MAX)
603  {
604  j = sofIndex;
605  }
606  else
607  {
608  j = i;
609  }
610 
611  //Total number of bytes that have been copied from the receive buffer
612  length = 0;
613 
614  //Process incoming frame
615  for(i = 0; i < j; i++)
616  {
617  //Any data to copy from current buffer?
618  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
619  {
620  //Calculate the number of bytes to read at a time
621  n = MIN(size, SAM3X_ETH_RX_BUFFER_SIZE);
622  //Copy data from receive buffer
623  osMemcpy((uint8_t *) temp + length, rxBuffer[rxBufferIndex], n);
624  //Update byte counters
625  length += n;
626  size -= n;
627  }
628 
629  //Mark the current buffer as free
630  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
631 
632  //Point to the following entry
633  rxBufferIndex++;
634 
635  //Wrap around to the beginning of the buffer if necessary
636  if(rxBufferIndex >= SAM3X_ETH_RX_BUFFER_COUNT)
637  {
638  rxBufferIndex = 0;
639  }
640  }
641 
642  //Any packet to process?
643  if(length > 0)
644  {
645  NetRxAncillary ancillary;
646 
647  //Additional options can be passed to the stack along with the packet
648  ancillary = NET_DEFAULT_RX_ANCILLARY;
649 
650  //Pass the packet to the upper layer
651  nicProcessPacket(interface, (uint8_t *) temp, length, &ancillary);
652  //Valid packet received
653  error = NO_ERROR;
654  }
655  else
656  {
657  //No more data in the receive buffer
658  error = ERROR_BUFFER_EMPTY;
659  }
660 
661  //Return status code
662  return error;
663 }
664 
665 
666 /**
667  * @brief Configure MAC address filtering
668  * @param[in] interface Underlying network interface
669  * @return Error code
670  **/
671 
673 {
674  uint_t i;
675  uint_t j;
676  uint_t k;
677  uint8_t *p;
678  uint32_t hashTable[2];
679  MacAddr unicastMacAddr[3];
680  MacFilterEntry *entry;
681 
682  //Debug message
683  TRACE_DEBUG("Updating MAC filter...\r\n");
684 
685  //Set the MAC address of the station
686  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
687  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
688 
689  //The MAC supports 3 additional addresses for unicast perfect filtering
690  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
691  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
692  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
693 
694  //The hash table is used for multicast address filtering
695  hashTable[0] = 0;
696  hashTable[1] = 0;
697 
698  //The MAC address filter contains the list of MAC addresses to accept
699  //when receiving an Ethernet frame
700  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
701  {
702  //Point to the current entry
703  entry = &interface->macAddrFilter[i];
704 
705  //Valid entry?
706  if(entry->refCount > 0)
707  {
708  //Multicast address?
709  if(macIsMulticastAddr(&entry->addr))
710  {
711  //Point to the MAC address
712  p = entry->addr.b;
713 
714  //Apply the hash function
715  k = (p[0] >> 6) ^ p[0];
716  k ^= (p[1] >> 4) ^ (p[1] << 2);
717  k ^= (p[2] >> 2) ^ (p[2] << 4);
718  k ^= (p[3] >> 6) ^ p[3];
719  k ^= (p[4] >> 4) ^ (p[4] << 2);
720  k ^= (p[5] >> 2) ^ (p[5] << 4);
721 
722  //The hash value is reduced to a 6-bit index
723  k &= 0x3F;
724 
725  //Update hash table contents
726  hashTable[k / 32] |= (1 << (k % 32));
727  }
728  else
729  {
730  //Up to 3 additional MAC addresses can be specified
731  if(j < 3)
732  {
733  //Save the unicast address
734  unicastMacAddr[j++] = entry->addr;
735  }
736  }
737  }
738  }
739 
740  //Configure the first unicast address filter
741  if(j >= 1)
742  {
743  //The address is activated when SAT register is written
744  EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
745  EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
746  }
747  else
748  {
749  //The address is deactivated when SAB register is written
750  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
751  }
752 
753  //Configure the second unicast address filter
754  if(j >= 2)
755  {
756  //The address is activated when SAT register is written
757  EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
758  EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
759  }
760  else
761  {
762  //The address is deactivated when SAB register is written
763  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
764  }
765 
766  //Configure the third unicast address filter
767  if(j >= 3)
768  {
769  //The address is activated when SAT register is written
770  EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
771  EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
772  }
773  else
774  {
775  //The address is deactivated when SAB register is written
776  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
777  }
778 
779  //Configure the multicast hash table
780  EMAC->EMAC_HRB = hashTable[0];
781  EMAC->EMAC_HRT = hashTable[1];
782 
783  //Debug message
784  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
785  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
786 
787  //Successful processing
788  return NO_ERROR;
789 }
790 
791 
792 /**
793  * @brief Adjust MAC configuration parameters for proper operation
794  * @param[in] interface Underlying network interface
795  * @return Error code
796  **/
797 
799 {
800  uint32_t config;
801 
802  //Read network configuration register
803  config = EMAC->EMAC_NCFGR;
804 
805  //10BASE-T or 100BASE-TX operation mode?
806  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
807  {
808  config |= EMAC_NCFGR_SPD;
809  }
810  else
811  {
812  config &= ~EMAC_NCFGR_SPD;
813  }
814 
815  //Half-duplex or full-duplex mode?
816  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
817  {
818  config |= EMAC_NCFGR_FD;
819  }
820  else
821  {
822  config &= ~EMAC_NCFGR_FD;
823  }
824 
825  //Write configuration value back to NCFGR register
826  EMAC->EMAC_NCFGR = config;
827 
828  //Successful processing
829  return NO_ERROR;
830 }
831 
832 
833 /**
834  * @brief Write PHY register
835  * @param[in] opcode Access type (2 bits)
836  * @param[in] phyAddr PHY address (5 bits)
837  * @param[in] regAddr Register address (5 bits)
838  * @param[in] data Register value
839  **/
840 
841 void sam3xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
842  uint8_t regAddr, uint16_t data)
843 {
844  uint32_t temp;
845 
846  //Valid opcode?
847  if(opcode == SMI_OPCODE_WRITE)
848  {
849  //Set up a write operation
850  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
851  //PHY address
852  temp |= EMAC_MAN_PHYA(phyAddr);
853  //Register address
854  temp |= EMAC_MAN_REGA(regAddr);
855  //Register value
856  temp |= EMAC_MAN_DATA(data);
857 
858  //Start a write operation
859  EMAC->EMAC_MAN = temp;
860  //Wait for the write to complete
861  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
862  {
863  }
864  }
865  else
866  {
867  //The MAC peripheral only supports standard Clause 22 opcodes
868  }
869 }
870 
871 
872 /**
873  * @brief Read PHY register
874  * @param[in] opcode Access type (2 bits)
875  * @param[in] phyAddr PHY address (5 bits)
876  * @param[in] regAddr Register address (5 bits)
877  * @return Register value
878  **/
879 
880 uint16_t sam3xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
881  uint8_t regAddr)
882 {
883  uint16_t data;
884  uint32_t temp;
885 
886  //Valid opcode?
887  if(opcode == SMI_OPCODE_READ)
888  {
889  //Set up a read operation
890  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
891  //PHY address
892  temp |= EMAC_MAN_PHYA(phyAddr);
893  //Register address
894  temp |= EMAC_MAN_REGA(regAddr);
895 
896  //Start a read operation
897  EMAC->EMAC_MAN = temp;
898  //Wait for the read to complete
899  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
900  {
901  }
902 
903  //Get register value
904  data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
905  }
906  else
907  {
908  //The MAC peripheral only supports standard Clause 22 opcodes
909  data = 0;
910  }
911 
912  //Return the value of the PHY register
913  return data;
914 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
const NicDriver sam3xEthDriver
SAM3X Ethernet MAC driver.
error_t sam3xEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sam3xEthTick(NetInterface *interface)
SAM3X Ethernet MAC timer handler.
error_t sam3xEthReceivePacket(NetInterface *interface)
Receive a packet.
error_t sam3xEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t sam3xEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void EMAC_Handler(void)
SAM3X Ethernet MAC interrupt service routine.
__weak_func void sam3xEthInitGpio(NetInterface *interface)
GPIO configuration.
void sam3xEthEventHandler(NetInterface *interface)
SAM3X Ethernet MAC event handler.
void sam3xEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sam3xEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
uint16_t sam3xEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sam3xEthInit(NetInterface *interface)
SAM3X Ethernet MAC initialization.
void sam3xEthDisableIrq(NetInterface *interface)
Disable interrupts.
void sam3xEthEnableIrq(NetInterface *interface)
Enable interrupts.
SAM3X Ethernet MAC driver.
#define EMAC_RX_WRAP
#define EMAC_RX_LENGTH
#define SAM3X_ETH_TX_BUFFER_COUNT
#define SAM3X_ETH_TX_BUFFER_SIZE
#define EMAC_RX_ADDRESS
#define EMAC_RX_OWNERSHIP
#define EMAC_TX_LAST
#define EMAC_RX_EOF
#define SAM3X_ETH_RX_BUFFER_SIZE
#define SAM3X_ETH_IRQ_PRIORITY_GROUPING
#define SAM3X_ETH_RX_BUFFER_COUNT
#define EMAC_TX_USED
#define EMAC_RMII_MASK
#define SAM3X_ETH_IRQ_GROUP_PRIORITY
#define EMAC_RX_SOF
#define EMAC_TX_LENGTH
#define SAM3X_ETH_IRQ_SUB_PRIORITY
#define EMAC_TX_WRAP
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive buffer descriptor.
Transmit buffer descriptor.
uint8_t length
Definition: tcp.h:368