sama5d3_eth_driver.c
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1 /**
2  * @file sama5d3_eth_driver.c
3  * @brief SAMA5D3 Ethernet MAC driver (EMAC instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2023 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.3.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "sama5d3x.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
49 #pragma location = SAMA5D3_ETH_RAM_SECTION
51 //RX buffer
52 #pragma data_alignment = 8
53 #pragma location = SAMA5D3_ETH_RAM_SECTION
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 #pragma location = SAMA5D3_ETH_RAM_SECTION
59 //RX buffer descriptors
60 #pragma data_alignment = 8
61 #pragma location = SAMA5D3_ETH_RAM_SECTION
63 
64 //GCC compiler?
65 #else
66 
67 //TX buffer
69  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
70 //RX buffer
72  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
73 //TX buffer descriptors
75  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
76 //RX buffer descriptors
78  __attribute__((aligned(8), __section__(SAMA5D3_ETH_RAM_SECTION)));
79 
80 #endif
81 
82 //TX buffer index
83 static uint_t txBufferIndex;
84 //RX buffer index
85 static uint_t rxBufferIndex;
86 
87 
88 /**
89  * @brief SAMA5D3 Ethernet MAC driver (EMAC instance)
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief SAMA5D3 Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122  volatile uint32_t status;
123 
124  //Debug message
125  TRACE_INFO("Initializing SAMA5D3 Ethernet MAC (EMAC)...\r\n");
126 
127  //Save underlying network interface
128  nicDriverInterface = interface;
129 
130  //Enable EMAC peripheral clock
131  PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
132  //Enable IRQ controller peripheral clock
133  PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
134 
135  //Disable transmit and receive circuits
136  EMAC->EMAC_NCR = 0;
137 
138  //GPIO configuration
139  sama5d3EthInitGpio(interface);
140 
141  //Configure MDC clock speed
142  EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
143  //Enable management port (MDC and MDIO)
144  EMAC->EMAC_NCR |= EMAC_NCR_MPE;
145 
146  //Valid Ethernet PHY or switch driver?
147  if(interface->phyDriver != NULL)
148  {
149  //Ethernet PHY initialization
150  error = interface->phyDriver->init(interface);
151  }
152  else if(interface->switchDriver != NULL)
153  {
154  //Ethernet switch initialization
155  error = interface->switchDriver->init(interface);
156  }
157  else
158  {
159  //The interface is not properly configured
160  error = ERROR_FAILURE;
161  }
162 
163  //Any error to report?
164  if(error)
165  {
166  return error;
167  }
168 
169  //Set the MAC address of the station
170  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
172 
173  //The MAC supports 3 additional addresses for unicast perfect filtering
174  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
175  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
176  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
177 
178  //Initialize hash table
179  EMAC->EMAC_HRB = 0;
180  EMAC->EMAC_HRT = 0;
181 
182  //Configure the receive filter
183  EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
184 
185  //Initialize buffer descriptors
186  sama5d3EthInitBufferDesc(interface);
187 
188  //Clear transmit status register
189  EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
190  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
191  //Clear receive status register
192  EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
193 
194  //First disable all EMAC interrupts
195  EMAC->EMAC_IDR = 0xFFFFFFFF;
196  //Only the desired ones are enabled
197  EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
198  EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
199 
200  //Read EMAC_ISR register to clear any pending interrupt
201  status = EMAC->EMAC_ISR;
202  (void) status;
203 
204  //Configure interrupt controller
205  AIC->AIC_SSR = ID_EMAC;
206  AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH_IRQ_PRIORITY);
207  AIC->AIC_SVR = (uint32_t) sama5d3EthIrqHandler;
208 
209  //Enable the EMAC to transmit and receive data
210  EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
211 
212  //Accept any packets from the upper layer
213  osSetEvent(&interface->nicTxEvent);
214 
215  //Successful initialization
216  return NO_ERROR;
217 }
218 
219 
220 /**
221  * @brief GPIO configuration
222  * @param[in] interface Underlying network interface
223  **/
224 
225 __weak_func void sama5d3EthInitGpio(NetInterface *interface)
226 {
227 //SAMA5D3-Xplained or SAMA5D3-EDS evaluation board?
228 #if defined(USE_SAMA5D3_XPLAINED) || defined(USE_SAMA5D3_EDS)
229  //Enable PIO peripheral clock
230  PMC->PMC_PCER0 = (1 << ID_PIOC);
231 
232  //Disable pull-up resistors on RMII pins
233  PIOC->PIO_PUDR = EMAC_RMII_MASK;
234  //Disable interrupts-on-change
235  PIOC->PIO_IDR = EMAC_RMII_MASK;
236  //Assign RMII pins to peripheral A function
237  PIOC->PIO_ABCDSR[0] &= ~EMAC_RMII_MASK;
238  PIOC->PIO_ABCDSR[1] &= ~EMAC_RMII_MASK;
239  //Disable the PIO from controlling the corresponding pins
240  PIOC->PIO_PDR = EMAC_RMII_MASK;
241 
242  //Select RMII operation mode and enable transceiver clock
243  EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
244 #endif
245 }
246 
247 
248 /**
249  * @brief Initialize buffer descriptors
250  * @param[in] interface Underlying network interface
251  **/
252 
254 {
255  uint_t i;
256  uint32_t address;
257 
258  //Initialize TX buffer descriptors
259  for(i = 0; i < SAMA5D3_ETH_TX_BUFFER_COUNT; i++)
260  {
261  //Calculate the address of the current TX buffer
262  address = (uint32_t) txBuffer[i];
263  //Write the address to the descriptor entry
264  txBufferDesc[i].address = address;
265  //Initialize status field
266  txBufferDesc[i].status = EMAC_TX_USED;
267  }
268 
269  //Mark the last descriptor entry with the wrap flag
270  txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
271  //Initialize TX buffer index
272  txBufferIndex = 0;
273 
274  //Initialize RX buffer descriptors
275  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
276  {
277  //Calculate the address of the current RX buffer
278  address = (uint32_t) rxBuffer[i];
279  //Write the address to the descriptor entry
280  rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
281  //Clear status field
282  rxBufferDesc[i].status = 0;
283  }
284 
285  //Mark the last descriptor entry with the wrap flag
286  rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
287  //Initialize RX buffer index
288  rxBufferIndex = 0;
289 
290  //Start location of the TX descriptor list
291  EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
292  //Start location of the RX descriptor list
293  EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
294 }
295 
296 
297 /**
298  * @brief SAMA5D3 Ethernet MAC timer handler
299  *
300  * This routine is periodically called by the TCP/IP stack to handle periodic
301  * operations such as polling the link state
302  *
303  * @param[in] interface Underlying network interface
304  **/
305 
306 void sama5d3EthTick(NetInterface *interface)
307 {
308  //Valid Ethernet PHY or switch driver?
309  if(interface->phyDriver != NULL)
310  {
311  //Handle periodic operations
312  interface->phyDriver->tick(interface);
313  }
314  else if(interface->switchDriver != NULL)
315  {
316  //Handle periodic operations
317  interface->switchDriver->tick(interface);
318  }
319  else
320  {
321  //Just for sanity
322  }
323 }
324 
325 
326 /**
327  * @brief Enable interrupts
328  * @param[in] interface Underlying network interface
329  **/
330 
332 {
333  //Enable Ethernet MAC interrupts
334  AIC->AIC_SSR = ID_EMAC;
335  AIC->AIC_IECR = AIC_IECR_INTEN;
336 
337  //Valid Ethernet PHY or switch driver?
338  if(interface->phyDriver != NULL)
339  {
340  //Enable Ethernet PHY interrupts
341  interface->phyDriver->enableIrq(interface);
342  }
343  else if(interface->switchDriver != NULL)
344  {
345  //Enable Ethernet switch interrupts
346  interface->switchDriver->enableIrq(interface);
347  }
348  else
349  {
350  //Just for sanity
351  }
352 }
353 
354 
355 /**
356  * @brief Disable interrupts
357  * @param[in] interface Underlying network interface
358  **/
359 
361 {
362  //Disable Ethernet MAC interrupts
363  AIC->AIC_SSR = ID_EMAC;
364  AIC->AIC_IDCR = AIC_IDCR_INTD;
365 
366  //Valid Ethernet PHY or switch driver?
367  if(interface->phyDriver != NULL)
368  {
369  //Disable Ethernet PHY interrupts
370  interface->phyDriver->disableIrq(interface);
371  }
372  else if(interface->switchDriver != NULL)
373  {
374  //Disable Ethernet switch interrupts
375  interface->switchDriver->disableIrq(interface);
376  }
377  else
378  {
379  //Just for sanity
380  }
381 }
382 
383 
384 /**
385  * @brief SAMA5D3 Ethernet MAC interrupt service routine
386  **/
387 
389 {
390  bool_t flag;
391  volatile uint32_t isr;
392  volatile uint32_t tsr;
393  volatile uint32_t rsr;
394 
395  //Interrupt service routine prologue
396  osEnterIsr();
397 
398  //This flag will be set if a higher priority task must be woken
399  flag = FALSE;
400 
401  //Each time the software reads EMAC_ISR, it has to check the contents
402  //of EMAC_TSR, EMAC_RSR and EMAC_NSR
403  isr = EMAC->EMAC_ISR;
404  tsr = EMAC->EMAC_TSR;
405  rsr = EMAC->EMAC_RSR;
406  (void) isr;
407 
408  //Packet transmitted?
409  if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
410  EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
411  {
412  //Only clear TSR flags that are currently set
413  EMAC->EMAC_TSR = tsr;
414 
415  //Check whether the TX buffer is available for writing
416  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
417  {
418  //Notify the TCP/IP stack that the transmitter is ready to send
419  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
420  }
421  }
422 
423  //Packet received?
424  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
425  {
426  //Set event flag
427  nicDriverInterface->nicEvent = TRUE;
428  //Notify the TCP/IP stack of the event
429  flag |= osSetEventFromIsr(&netEvent);
430  }
431 
432  //Write AIC_EOICR register before exiting
433  AIC->AIC_EOICR = 0;
434 
435  //Interrupt service routine epilogue
436  osExitIsr(flag);
437 }
438 
439 
440 /**
441  * @brief SAMA5D3 Ethernet MAC event handler
442  * @param[in] interface Underlying network interface
443  **/
444 
446 {
447  error_t error;
448  uint32_t rsr;
449 
450  //Read receive status
451  rsr = EMAC->EMAC_RSR;
452 
453  //Packet received?
454  if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
455  {
456  //Only clear RSR flags that are currently set
457  EMAC->EMAC_RSR = rsr;
458 
459  //Process all pending packets
460  do
461  {
462  //Read incoming packet
463  error = sama5d3EthReceivePacket(interface);
464 
465  //No more data in the receive buffer?
466  } while(error != ERROR_BUFFER_EMPTY);
467  }
468 }
469 
470 
471 /**
472  * @brief Send a packet
473  * @param[in] interface Underlying network interface
474  * @param[in] buffer Multi-part buffer containing the data to send
475  * @param[in] offset Offset to the first data byte
476  * @param[in] ancillary Additional options passed to the stack along with
477  * the packet
478  * @return Error code
479  **/
480 
482  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
483 {
484  size_t length;
485 
486  //Retrieve the length of the packet
487  length = netBufferGetLength(buffer) - offset;
488 
489  //Check the frame length
491  {
492  //The transmitter can accept another packet
493  osSetEvent(&interface->nicTxEvent);
494  //Report an error
495  return ERROR_INVALID_LENGTH;
496  }
497 
498  //Make sure the current buffer is available for writing
499  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) == 0)
500  {
501  return ERROR_FAILURE;
502  }
503 
504  //Copy user data to the transmit buffer
505  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
506 
507  //Set the necessary flags in the descriptor entry
508  if(txBufferIndex < (SAMA5D3_ETH_TX_BUFFER_COUNT - 1))
509  {
510  //Write the status word
511  txBufferDesc[txBufferIndex].status = EMAC_TX_LAST |
513 
514  //Point to the next buffer
515  txBufferIndex++;
516  }
517  else
518  {
519  //Write the status word
520  txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP | EMAC_TX_LAST |
522 
523  //Wrap around
524  txBufferIndex = 0;
525  }
526 
527  //Set the TSTART bit to initiate transmission
528  EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
529 
530  //Check whether the next buffer is available for writing
531  if((txBufferDesc[txBufferIndex].status & EMAC_TX_USED) != 0)
532  {
533  //The transmitter can accept another packet
534  osSetEvent(&interface->nicTxEvent);
535  }
536 
537  //Successful processing
538  return NO_ERROR;
539 }
540 
541 
542 /**
543  * @brief Receive a packet
544  * @param[in] interface Underlying network interface
545  * @return Error code
546  **/
547 
549 {
550  static uint8_t temp[ETH_MAX_FRAME_SIZE];
551  error_t error;
552  uint_t i;
553  uint_t j;
554  uint_t sofIndex;
555  uint_t eofIndex;
556  size_t n;
557  size_t size;
558  size_t length;
559 
560  //Initialize variables
561  size = 0;
562  sofIndex = UINT_MAX;
563  eofIndex = UINT_MAX;
564 
565  //Search for SOF and EOF flags
566  for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
567  {
568  //Point to the current entry
569  j = rxBufferIndex + i;
570 
571  //Wrap around to the beginning of the buffer if necessary
573  {
575  }
576 
577  //No more entries to process?
578  if((rxBufferDesc[j].address & EMAC_RX_OWNERSHIP) == 0)
579  {
580  //Stop processing
581  break;
582  }
583 
584  //A valid SOF has been found?
585  if((rxBufferDesc[j].status & EMAC_RX_SOF) != 0)
586  {
587  //Save the position of the SOF
588  sofIndex = i;
589  }
590 
591  //A valid EOF has been found?
592  if((rxBufferDesc[j].status & EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
593  {
594  //Save the position of the EOF
595  eofIndex = i;
596  //Retrieve the length of the frame
597  size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
598  //Limit the number of data to read
599  size = MIN(size, ETH_MAX_FRAME_SIZE);
600  //Stop processing since we have reached the end of the frame
601  break;
602  }
603  }
604 
605  //Determine the number of entries to process
606  if(eofIndex != UINT_MAX)
607  {
608  j = eofIndex + 1;
609  }
610  else if(sofIndex != UINT_MAX)
611  {
612  j = sofIndex;
613  }
614  else
615  {
616  j = i;
617  }
618 
619  //Total number of bytes that have been copied from the receive buffer
620  length = 0;
621 
622  //Process incoming frame
623  for(i = 0; i < j; i++)
624  {
625  //Any data to copy from current buffer?
626  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
627  {
628  //Calculate the number of bytes to read at a time
630  //Copy data from receive buffer
631  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
632  //Update byte counters
633  length += n;
634  size -= n;
635  }
636 
637  //Mark the current buffer as free
638  rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
639 
640  //Point to the following entry
641  rxBufferIndex++;
642 
643  //Wrap around to the beginning of the buffer if necessary
644  if(rxBufferIndex >= SAMA5D3_ETH_RX_BUFFER_COUNT)
645  {
646  rxBufferIndex = 0;
647  }
648  }
649 
650  //Any packet to process?
651  if(length > 0)
652  {
653  NetRxAncillary ancillary;
654 
655  //Additional options can be passed to the stack along with the packet
656  ancillary = NET_DEFAULT_RX_ANCILLARY;
657 
658  //Pass the packet to the upper layer
659  nicProcessPacket(interface, temp, length, &ancillary);
660  //Valid packet received
661  error = NO_ERROR;
662  }
663  else
664  {
665  //No more data in the receive buffer
666  error = ERROR_BUFFER_EMPTY;
667  }
668 
669  //Return status code
670  return error;
671 }
672 
673 
674 /**
675  * @brief Configure MAC address filtering
676  * @param[in] interface Underlying network interface
677  * @return Error code
678  **/
679 
681 {
682  uint_t i;
683  uint_t j;
684  uint_t k;
685  uint8_t *p;
686  uint32_t hashTable[2];
687  MacAddr unicastMacAddr[3];
688  MacFilterEntry *entry;
689 
690  //Debug message
691  TRACE_DEBUG("Updating MAC filter...\r\n");
692 
693  //Set the MAC address of the station
694  EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
695  EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
696 
697  //The MAC supports 3 additional addresses for unicast perfect filtering
698  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
699  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
700  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
701 
702  //The hash table is used for multicast address filtering
703  hashTable[0] = 0;
704  hashTable[1] = 0;
705 
706  //The MAC address filter contains the list of MAC addresses to accept
707  //when receiving an Ethernet frame
708  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
709  {
710  //Point to the current entry
711  entry = &interface->macAddrFilter[i];
712 
713  //Valid entry?
714  if(entry->refCount > 0)
715  {
716  //Multicast address?
717  if(macIsMulticastAddr(&entry->addr))
718  {
719  //Point to the MAC address
720  p = entry->addr.b;
721 
722  //Apply the hash function
723  k = (p[0] >> 6) ^ p[0];
724  k ^= (p[1] >> 4) ^ (p[1] << 2);
725  k ^= (p[2] >> 2) ^ (p[2] << 4);
726  k ^= (p[3] >> 6) ^ p[3];
727  k ^= (p[4] >> 4) ^ (p[4] << 2);
728  k ^= (p[5] >> 2) ^ (p[5] << 4);
729 
730  //The hash value is reduced to a 6-bit index
731  k &= 0x3F;
732 
733  //Update hash table contents
734  hashTable[k / 32] |= (1 << (k % 32));
735  }
736  else
737  {
738  //Up to 3 additional MAC addresses can be specified
739  if(j < 3)
740  {
741  //Save the unicast address
742  unicastMacAddr[j] = entry->addr;
743  }
744  else
745  {
746  //Point to the MAC address
747  p = entry->addr.b;
748 
749  //Apply the hash function
750  k = (p[0] >> 6) ^ p[0];
751  k ^= (p[1] >> 4) ^ (p[1] << 2);
752  k ^= (p[2] >> 2) ^ (p[2] << 4);
753  k ^= (p[3] >> 6) ^ p[3];
754  k ^= (p[4] >> 4) ^ (p[4] << 2);
755  k ^= (p[5] >> 2) ^ (p[5] << 4);
756 
757  //The hash value is reduced to a 6-bit index
758  k &= 0x3F;
759 
760  //Update hash table contents
761  hashTable[k / 32] |= (1 << (k % 32));
762  }
763 
764  //Increment the number of unicast addresses
765  j++;
766  }
767  }
768  }
769 
770  //Configure the first unicast address filter
771  if(j >= 1)
772  {
773  //The address is activated when SAT register is written
774  EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
775  EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
776  }
777  else
778  {
779  //The address is deactivated when SAB register is written
780  EMAC->EMAC_SA[1].EMAC_SAxB = 0;
781  }
782 
783  //Configure the second unicast address filter
784  if(j >= 2)
785  {
786  //The address is activated when SAT register is written
787  EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
788  EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
789  }
790  else
791  {
792  //The address is deactivated when SAB register is written
793  EMAC->EMAC_SA[2].EMAC_SAxB = 0;
794  }
795 
796  //Configure the third unicast address filter
797  if(j >= 3)
798  {
799  //The address is activated when SAT register is written
800  EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
801  EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
802  }
803  else
804  {
805  //The address is deactivated when SAB register is written
806  EMAC->EMAC_SA[3].EMAC_SAxB = 0;
807  }
808 
809  //The perfect MAC filter supports only 3 unicast addresses
810  if(j >= 4)
811  {
812  EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI;
813  }
814  else
815  {
816  EMAC->EMAC_NCFGR &= ~EMAC_NCFGR_UNI;
817  }
818 
819  //Configure the multicast hash table
820  EMAC->EMAC_HRB = hashTable[0];
821  EMAC->EMAC_HRT = hashTable[1];
822 
823  //Debug message
824  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
825  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
826 
827  //Successful processing
828  return NO_ERROR;
829 }
830 
831 
832 /**
833  * @brief Adjust MAC configuration parameters for proper operation
834  * @param[in] interface Underlying network interface
835  * @return Error code
836  **/
837 
839 {
840  uint32_t config;
841 
842  //Read network configuration register
843  config = EMAC->EMAC_NCFGR;
844 
845  //10BASE-T or 100BASE-TX operation mode?
846  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
847  {
848  config |= EMAC_NCFGR_SPD;
849  }
850  else
851  {
852  config &= ~EMAC_NCFGR_SPD;
853  }
854 
855  //Half-duplex or full-duplex mode?
856  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
857  {
858  config |= EMAC_NCFGR_FD;
859  }
860  else
861  {
862  config &= ~EMAC_NCFGR_FD;
863  }
864 
865  //Write configuration value back to NCFGR register
866  EMAC->EMAC_NCFGR = config;
867 
868  //Successful processing
869  return NO_ERROR;
870 }
871 
872 
873 /**
874  * @brief Write PHY register
875  * @param[in] opcode Access type (2 bits)
876  * @param[in] phyAddr PHY address (5 bits)
877  * @param[in] regAddr Register address (5 bits)
878  * @param[in] data Register value
879  **/
880 
881 void sama5d3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
882  uint8_t regAddr, uint16_t data)
883 {
884  uint32_t temp;
885 
886  //Valid opcode?
887  if(opcode == SMI_OPCODE_WRITE)
888  {
889  //Set up a write operation
890  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
891  //PHY address
892  temp |= EMAC_MAN_PHYA(phyAddr);
893  //Register address
894  temp |= EMAC_MAN_REGA(regAddr);
895  //Register value
896  temp |= EMAC_MAN_DATA(data);
897 
898  //Start a write operation
899  EMAC->EMAC_MAN = temp;
900  //Wait for the write to complete
901  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
902  {
903  }
904  }
905  else
906  {
907  //The MAC peripheral only supports standard Clause 22 opcodes
908  }
909 }
910 
911 
912 /**
913  * @brief Read PHY register
914  * @param[in] opcode Access type (2 bits)
915  * @param[in] phyAddr PHY address (5 bits)
916  * @param[in] regAddr Register address (5 bits)
917  * @return Register value
918  **/
919 
920 uint16_t sama5d3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
921  uint8_t regAddr)
922 {
923  uint16_t data;
924  uint32_t temp;
925 
926  //Valid opcode?
927  if(opcode == SMI_OPCODE_READ)
928  {
929  //Set up a read operation
930  temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
931  //PHY address
932  temp |= EMAC_MAN_PHYA(phyAddr);
933  //Register address
934  temp |= EMAC_MAN_REGA(regAddr);
935 
936  //Start a read operation
937  EMAC->EMAC_MAN = temp;
938  //Wait for the read to complete
939  while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
940  {
941  }
942 
943  //Get register value
944  data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
945  }
946  else
947  {
948  //The MAC peripheral only supports standard Clause 22 opcodes
949  data = 0;
950  }
951 
952  //Return the value of the PHY register
953  return data;
954 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:186
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:220
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
MacAddr
Definition: ethernet.h:193
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:314
uint16_t regAddr
uint8_t p
Definition: ndp.h:298
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:100
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemcpy(dest, src, length)
Definition: os_port.h:143
#define MIN(a, b)
Definition: os_port.h:65
#define TRUE
Definition: os_port.h:52
#define FALSE
Definition: os_port.h:48
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
#define EMAC_RX_WRAP
#define EMAC_RX_LENGTH
#define EMAC_RX_ADDRESS
#define EMAC_RX_OWNERSHIP
#define EMAC_TX_LAST
#define EMAC_RX_EOF
#define EMAC_TX_USED
#define EMAC_RMII_MASK
#define EMAC_RX_SOF
#define EMAC_TX_LENGTH
#define EMAC_TX_WRAP
void sama5d3EthTick(NetInterface *interface)
SAMA5D3 Ethernet MAC timer handler.
__weak_func void sama5d3EthInitGpio(NetInterface *interface)
GPIO configuration.
void sama5d3EthIrqHandler(void)
SAMA5D3 Ethernet MAC interrupt service routine.
void sama5d3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sama5d3EthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver sama5d3EthDriver
SAMA5D3 Ethernet MAC driver (EMAC instance)
error_t sama5d3EthReceivePacket(NetInterface *interface)
Receive a packet.
void sama5d3EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t sama5d3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sama5d3EthEventHandler(NetInterface *interface)
SAMA5D3 Ethernet MAC event handler.
error_t sama5d3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t sama5d3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sama5d3EthInit(NetInterface *interface)
SAMA5D3 Ethernet MAC initialization.
error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void sama5d3EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
SAMA5D3 Ethernet MAC driver (EMAC instance)
#define SAMA5D3_ETH_TX_BUFFER_SIZE
#define SAMA5D3_ETH_RX_BUFFER_SIZE
#define SAMA5D3_ETH_IRQ_PRIORITY
#define SAMA5D3_ETH_RAM_SECTION
#define SAMA5D3_ETH_TX_BUFFER_COUNT
#define SAMA5D3_ETH_RX_BUFFER_COUNT
MAC filter table entry.
Definition: ethernet.h:258
MacAddr addr
MAC address.
Definition: ethernet.h:259
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:260
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive buffer descriptor.
Transmit buffer descriptor.
uint8_t length
Definition: tcp.h:366