32 #define TRACE_LEVEL NIC_TRACE_LEVEL
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 8
49 #pragma location = SAMA5D3_ETH_RAM_SECTION
52 #pragma data_alignment = 8
53 #pragma location = SAMA5D3_ETH_RAM_SECTION
56 #pragma data_alignment = 8
57 #pragma location = SAMA5D3_ETH_RAM_SECTION
60 #pragma data_alignment = 8
61 #pragma location = SAMA5D3_ETH_RAM_SECTION
83 static uint_t txBufferIndex;
85 static uint_t rxBufferIndex;
122 volatile uint32_t status;
125 TRACE_INFO(
"Initializing SAMA5D3 Ethernet MAC (EMAC)...\r\n");
128 nicDriverInterface = interface;
131 PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
133 PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
142 EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
144 EMAC->EMAC_NCR |= EMAC_NCR_MPE;
147 if(interface->phyDriver != NULL)
150 error = interface->phyDriver->init(interface);
152 else if(interface->switchDriver != NULL)
155 error = interface->switchDriver->init(interface);
170 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
174 EMAC->EMAC_SA[1].EMAC_SAxB = 0;
175 EMAC->EMAC_SA[2].EMAC_SAxB = 0;
176 EMAC->EMAC_SA[3].EMAC_SAxB = 0;
183 EMAC->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
189 EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
190 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
192 EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
195 EMAC->EMAC_IDR = 0xFFFFFFFF;
197 EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
198 EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
201 status = EMAC->EMAC_ISR;
205 AIC->AIC_SSR = ID_EMAC;
210 EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
228 #if defined(USE_SAMA5D3_XPLAINED) || defined(USE_SAMA5D3_EDS)
230 PMC->PMC_PCER0 = (1 << ID_PIOC);
243 EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
282 rxBufferDesc[i].
status = 0;
291 EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
293 EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
309 if(interface->phyDriver != NULL)
312 interface->phyDriver->tick(interface);
314 else if(interface->switchDriver != NULL)
317 interface->switchDriver->tick(interface);
334 AIC->AIC_SSR = ID_EMAC;
335 AIC->AIC_IECR = AIC_IECR_INTEN;
338 if(interface->phyDriver != NULL)
341 interface->phyDriver->enableIrq(interface);
343 else if(interface->switchDriver != NULL)
346 interface->switchDriver->enableIrq(interface);
363 AIC->AIC_SSR = ID_EMAC;
364 AIC->AIC_IDCR = AIC_IDCR_INTD;
367 if(interface->phyDriver != NULL)
370 interface->phyDriver->disableIrq(interface);
372 else if(interface->switchDriver != NULL)
375 interface->switchDriver->disableIrq(interface);
391 volatile uint32_t isr;
392 volatile uint32_t tsr;
393 volatile uint32_t rsr;
403 isr = EMAC->EMAC_ISR;
404 tsr = EMAC->EMAC_TSR;
405 rsr = EMAC->EMAC_RSR;
409 if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
410 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
413 EMAC->EMAC_TSR = tsr;
416 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
424 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
427 nicDriverInterface->nicEvent =
TRUE;
451 rsr = EMAC->EMAC_RSR;
454 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
457 EMAC->EMAC_RSR = rsr;
499 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) == 0)
528 EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
531 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
569 j = rxBufferIndex + i;
592 if((rxBufferDesc[j].status &
EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
606 if(eofIndex != UINT_MAX)
610 else if(sofIndex != UINT_MAX)
623 for(i = 0; i < j; i++)
626 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
686 uint32_t hashTable[2];
694 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
695 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
711 entry = &interface->macAddrFilter[i];
723 k = (
p[0] >> 6) ^
p[0];
724 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
725 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
726 k ^= (
p[3] >> 6) ^
p[3];
727 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
728 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
734 hashTable[k / 32] |= (1 << (k % 32));
742 unicastMacAddr[j] = entry->
addr;
750 k = (
p[0] >> 6) ^
p[0];
751 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
752 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
753 k ^= (
p[3] >> 6) ^
p[3];
754 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
755 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
761 hashTable[k / 32] |= (1 << (k % 32));
774 EMAC->EMAC_SA[1].EMAC_SAxB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
775 EMAC->EMAC_SA[1].EMAC_SAxT = unicastMacAddr[0].w[2];
780 EMAC->EMAC_SA[1].EMAC_SAxB = 0;
787 EMAC->EMAC_SA[2].EMAC_SAxB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
788 EMAC->EMAC_SA[2].EMAC_SAxT = unicastMacAddr[1].w[2];
793 EMAC->EMAC_SA[2].EMAC_SAxB = 0;
800 EMAC->EMAC_SA[3].EMAC_SAxB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
801 EMAC->EMAC_SA[3].EMAC_SAxT = unicastMacAddr[2].w[2];
806 EMAC->EMAC_SA[3].EMAC_SAxB = 0;
812 EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI;
816 EMAC->EMAC_NCFGR &= ~EMAC_NCFGR_UNI;
820 EMAC->EMAC_HRB = hashTable[0];
821 EMAC->EMAC_HRT = hashTable[1];
824 TRACE_DEBUG(
" HRB = %08" PRIX32
"\r\n", EMAC->EMAC_HRB);
825 TRACE_DEBUG(
" HRT = %08" PRIX32
"\r\n", EMAC->EMAC_HRT);
843 config = EMAC->EMAC_NCFGR;
848 config |= EMAC_NCFGR_SPD;
852 config &= ~EMAC_NCFGR_SPD;
858 config |= EMAC_NCFGR_FD;
862 config &= ~EMAC_NCFGR_FD;
866 EMAC->EMAC_NCFGR = config;
890 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
892 temp |= EMAC_MAN_PHYA(phyAddr);
894 temp |= EMAC_MAN_REGA(
regAddr);
896 temp |= EMAC_MAN_DATA(
data);
899 EMAC->EMAC_MAN = temp;
901 while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
930 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
932 temp |= EMAC_MAN_PHYA(phyAddr);
934 temp |= EMAC_MAN_REGA(
regAddr);
937 EMAC->EMAC_MAN = temp;
939 while((EMAC->EMAC_NSR & EMAC_NSR_IDLE) == 0)
944 data = EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define ETH_MAX_FRAME_SIZE
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EMAC_RX_OWNERSHIP
void sama5d3EthTick(NetInterface *interface)
SAMA5D3 Ethernet MAC timer handler.
__weak_func void sama5d3EthInitGpio(NetInterface *interface)
GPIO configuration.
void sama5d3EthIrqHandler(void)
SAMA5D3 Ethernet MAC interrupt service routine.
void sama5d3EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sama5d3EthDisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver sama5d3EthDriver
SAMA5D3 Ethernet MAC driver (EMAC instance)
error_t sama5d3EthReceivePacket(NetInterface *interface)
Receive a packet.
void sama5d3EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t sama5d3EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void sama5d3EthEventHandler(NetInterface *interface)
SAMA5D3 Ethernet MAC event handler.
error_t sama5d3EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t sama5d3EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sama5d3EthInit(NetInterface *interface)
SAMA5D3 Ethernet MAC initialization.
error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void sama5d3EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
SAMA5D3 Ethernet MAC driver (EMAC instance)
#define SAMA5D3_ETH_TX_BUFFER_SIZE
#define SAMA5D3_ETH_RX_BUFFER_SIZE
#define SAMA5D3_ETH_IRQ_PRIORITY
#define SAMA5D3_ETH_RAM_SECTION
#define SAMA5D3_ETH_TX_BUFFER_COUNT
#define SAMA5D3_ETH_RX_BUFFER_COUNT
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.
Receive buffer descriptor.
Transmit buffer descriptor.