sama5d3_geth_driver.c
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1 /**
2  * @file sama5d3_geth_driver.c
3  * @brief SAMA5D3 Gigabit Ethernet MAC driver (GMAC instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2023 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.3.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include <limits.h>
36 #include "sama5d3x.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //TX buffer
48 #pragma data_alignment = 8
49 #pragma location = SAMA5D3_GETH_RAM_SECTION
51 //RX buffer
52 #pragma data_alignment = 8
53 #pragma location = SAMA5D3_GETH_RAM_SECTION
55 //TX buffer descriptors
56 #pragma data_alignment = 8
57 #pragma location = SAMA5D3_GETH_RAM_SECTION
59 //RX buffer descriptors
60 #pragma data_alignment = 8
61 #pragma location = SAMA5D3_GETH_RAM_SECTION
63 
64 //GCC compiler?
65 #else
66 
67 //TX buffer
69  __attribute__((aligned(8), __section__(SAMA5D3_GETH_RAM_SECTION)));
70 //RX buffer
72  __attribute__((aligned(8), __section__(SAMA5D3_GETH_RAM_SECTION)));
73 //TX buffer descriptors
75  __attribute__((aligned(8), __section__(SAMA5D3_GETH_RAM_SECTION)));
76 //RX buffer descriptors
78  __attribute__((aligned(8), __section__(SAMA5D3_GETH_RAM_SECTION)));
79 
80 #endif
81 
82 //TX buffer index
83 static uint_t txBufferIndex;
84 //RX buffer index
85 static uint_t rxBufferIndex;
86 
87 
88 /**
89  * @brief SAMA5D3 Ethernet MAC driver (GMAC instance)
90  **/
91 
93 {
95  ETH_MTU,
106  TRUE,
107  TRUE,
108  TRUE,
109  FALSE
110 };
111 
112 
113 /**
114  * @brief SAMA5D3 Ethernet MAC initialization
115  * @param[in] interface Underlying network interface
116  * @return Error code
117  **/
118 
120 {
121  error_t error;
122  volatile uint32_t status;
123 
124  //Debug message
125  TRACE_INFO("Initializing SAMA5D3 Ethernet MAC (GMAC)...\r\n");
126 
127  //Save underlying network interface
128  nicDriverInterface = interface;
129 
130  //Enable GMAC peripheral clock
131  PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
132  //Enable IRQ controller peripheral clock
133  PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
134 
135  //Disable transmit and receive circuits
136  GMAC->GMAC_NCR = 0;
137 
138  //GPIO configuration
139  sama5d3GigabitEthInitGpio(interface);
140 
141  //Configure MDC clock speed
142  GMAC->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
143  //Enable management port (MDC and MDIO)
144  GMAC->GMAC_NCR |= GMAC_NCR_MPE;
145 
146  //Valid Ethernet PHY or switch driver?
147  if(interface->phyDriver != NULL)
148  {
149  //Ethernet PHY initialization
150  error = interface->phyDriver->init(interface);
151  }
152  else if(interface->switchDriver != NULL)
153  {
154  //Ethernet switch initialization
155  error = interface->switchDriver->init(interface);
156  }
157  else
158  {
159  //The interface is not properly configured
160  error = ERROR_FAILURE;
161  }
162 
163  //Any error to report?
164  if(error)
165  {
166  return error;
167  }
168 
169  //Set the MAC address of the station
170  GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171  GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
172 
173  //The MAC supports 3 additional addresses for unicast perfect filtering
174  GMAC->GMAC_SA[1].GMAC_SAB = 0;
175  GMAC->GMAC_SA[2].GMAC_SAB = 0;
176  GMAC->GMAC_SA[3].GMAC_SAB = 0;
177 
178  //Initialize hash table
179  GMAC->GMAC_HRB = 0;
180  GMAC->GMAC_HRT = 0;
181 
182  //Configure the receive filter
183  GMAC->GMAC_NCFGR |= GMAC_NCFGR_MAXFS | GMAC_NCFGR_MTIHEN;
184 
185  //Initialize buffer descriptors
187 
188  //Clear transmit status register
189  GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
190  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
191  //Clear receive status register
192  GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
193 
194  //First disable all GMAC interrupts
195  GMAC->GMAC_IDR = 0xFFFFFFFF;
196  //Only the desired ones are enabled
197  GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
198  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
199 
200  //Read GMAC_ISR register to clear any pending interrupt
201  status = GMAC->GMAC_ISR;
202  (void) status;
203 
204  //Configure interrupt controller
205  AIC->AIC_SSR = ID_GMAC;
206  AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_GETH_IRQ_PRIORITY);
207  AIC->AIC_SVR = (uint32_t) sama5d3GigabitEthIrqHandler;
208 
209  //Enable the GMAC to transmit and receive data
210  GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
211 
212  //Accept any packets from the upper layer
213  osSetEvent(&interface->nicTxEvent);
214 
215  //Successful initialization
216  return NO_ERROR;
217 }
218 
219 
220 /**
221  * @brief GPIO configuration
222  * @param[in] interface Underlying network interface
223  **/
224 
225 __weak_func void sama5d3GigabitEthInitGpio(NetInterface *interface)
226 {
227 //SAMA5D3-Xplained, SAMA5D3-EDS or EVB-KSZ9477 evaluation board?
228 #if defined(USE_SAMA5D3_XPLAINED) || defined(USE_SAMA5D3_EDS) || defined(USE_EVB_KSZ9477)
229  //Enable PIO peripheral clock
230  PMC->PMC_PCER0 = (1 << ID_PIOB);
231 
232  //Disable pull-up resistors on RGMII pins
233  PIOB->PIO_PUDR = GMAC_RGMII_MASK;
234  //Disable interrupts-on-change
235  PIOB->PIO_IDR = GMAC_RGMII_MASK;
236  //Assign MII pins to peripheral A function
237  PIOB->PIO_ABCDSR[0] &= ~GMAC_RGMII_MASK;
238  PIOB->PIO_ABCDSR[1] &= ~GMAC_RGMII_MASK;
239  //Disable the PIO from controlling the corresponding pins
240  PIOB->PIO_PDR = GMAC_RGMII_MASK;
241 
242  //Select RGMII operation mode
243  GMAC->GMAC_UR = GMAC_UR_RGMII;
244 #endif
245 }
246 
247 
248 /**
249  * @brief Initialize buffer descriptors
250  * @param[in] interface Underlying network interface
251  **/
252 
254 {
255  uint_t i;
256  uint32_t address;
257 
258  //Initialize TX buffer descriptors
259  for(i = 0; i < SAMA5D3_GETH_TX_BUFFER_COUNT; i++)
260  {
261  //Calculate the address of the current TX buffer
262  address = (uint32_t) txBuffer[i];
263  //Write the address to the descriptor entry
264  txBufferDesc[i].address = address;
265  //Initialize status field
266  txBufferDesc[i].status = GMAC_TX_USED;
267  }
268 
269  //Mark the last descriptor entry with the wrap flag
270  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
271  //Initialize TX buffer index
272  txBufferIndex = 0;
273 
274  //Initialize RX buffer descriptors
275  for(i = 0; i < SAMA5D3_GETH_RX_BUFFER_COUNT; i++)
276  {
277  //Calculate the address of the current RX buffer
278  address = (uint32_t) rxBuffer[i];
279  //Write the address to the descriptor entry
280  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
281  //Clear status field
282  rxBufferDesc[i].status = 0;
283  }
284 
285  //Mark the last descriptor entry with the wrap flag
286  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
287  //Initialize RX buffer index
288  rxBufferIndex = 0;
289 
290  //Start location of the TX descriptor list
291  GMAC->GMAC_TBQB = (uint32_t) txBufferDesc;
292  //Start location of the RX descriptor list
293  GMAC->GMAC_RBQB = (uint32_t) rxBufferDesc;
294 }
295 
296 
297 /**
298  * @brief SAMA5D3 Ethernet MAC timer handler
299  *
300  * This routine is periodically called by the TCP/IP stack to handle periodic
301  * operations such as polling the link state
302  *
303  * @param[in] interface Underlying network interface
304  **/
305 
307 {
308  //Valid Ethernet PHY or switch driver?
309  if(interface->phyDriver != NULL)
310  {
311  //Handle periodic operations
312  interface->phyDriver->tick(interface);
313  }
314  else if(interface->switchDriver != NULL)
315  {
316  //Handle periodic operations
317  interface->switchDriver->tick(interface);
318  }
319  else
320  {
321  //Just for sanity
322  }
323 }
324 
325 
326 /**
327  * @brief Enable interrupts
328  * @param[in] interface Underlying network interface
329  **/
330 
332 {
333  //Enable Ethernet MAC interrupts
334  AIC->AIC_SSR = ID_GMAC;
335  AIC->AIC_IECR = AIC_IECR_INTEN;
336 
337  //Valid Ethernet PHY or switch driver?
338  if(interface->phyDriver != NULL)
339  {
340  //Enable Ethernet PHY interrupts
341  interface->phyDriver->enableIrq(interface);
342  }
343  else if(interface->switchDriver != NULL)
344  {
345  //Enable Ethernet switch interrupts
346  interface->switchDriver->enableIrq(interface);
347  }
348  else
349  {
350  //Just for sanity
351  }
352 }
353 
354 
355 /**
356  * @brief Disable interrupts
357  * @param[in] interface Underlying network interface
358  **/
359 
361 {
362  //Disable Ethernet MAC interrupts
363  AIC->AIC_SSR = ID_GMAC;
364  AIC->AIC_IDCR = AIC_IDCR_INTD;
365 
366  //Valid Ethernet PHY or switch driver?
367  if(interface->phyDriver != NULL)
368  {
369  //Disable Ethernet PHY interrupts
370  interface->phyDriver->disableIrq(interface);
371  }
372  else if(interface->switchDriver != NULL)
373  {
374  //Disable Ethernet switch interrupts
375  interface->switchDriver->disableIrq(interface);
376  }
377  else
378  {
379  //Just for sanity
380  }
381 }
382 
383 
384 /**
385  * @brief SAMA5D3 Ethernet MAC interrupt service routine
386  **/
387 
389 {
390  bool_t flag;
391  volatile uint32_t isr;
392  volatile uint32_t tsr;
393  volatile uint32_t rsr;
394 
395  //Interrupt service routine prologue
396  osEnterIsr();
397 
398  //This flag will be set if a higher priority task must be woken
399  flag = FALSE;
400 
401  //Each time the software reads GMAC_ISR, it has to check the contents
402  //of GMAC_TSR, GMAC_RSR and GMAC_NSR
403  isr = GMAC->GMAC_ISR;
404  tsr = GMAC->GMAC_TSR;
405  rsr = GMAC->GMAC_RSR;
406  (void) isr;
407 
408  //Packet transmitted?
409  if((tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
410  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR)) != 0)
411  {
412  //Only clear TSR flags that are currently set
413  GMAC->GMAC_TSR = tsr;
414 
415  //Avoid DMA lockup by sending only one frame at a time (see errata 57.5.1)
416  if((txBufferDesc[0].status & GMAC_TX_USED) != 0 &&
417  (txBufferDesc[1].status & GMAC_TX_USED) != 0)
418  {
419  //Notify the TCP/IP stack that the transmitter is ready to send
420  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
421  }
422  }
423 
424  //Packet received?
425  if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
426  {
427  //Set event flag
428  nicDriverInterface->nicEvent = TRUE;
429  //Notify the TCP/IP stack of the event
430  flag |= osSetEventFromIsr(&netEvent);
431  }
432 
433  //Write AIC_EOICR register before exiting
434  AIC->AIC_EOICR = 0;
435 
436  //Interrupt service routine epilogue
437  osExitIsr(flag);
438 }
439 
440 
441 /**
442  * @brief SAMA5D3 Ethernet MAC event handler
443  * @param[in] interface Underlying network interface
444  **/
445 
447 {
448  error_t error;
449  uint32_t rsr;
450 
451  //Read receive status
452  rsr = GMAC->GMAC_RSR;
453 
454  //Packet received?
455  if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
456  {
457  //Only clear RSR flags that are currently set
458  GMAC->GMAC_RSR = rsr;
459 
460  //Process all pending packets
461  do
462  {
463  //Read incoming packet
464  error = sama5d3GigabitEthReceivePacket(interface);
465 
466  //No more data in the receive buffer?
467  } while(error != ERROR_BUFFER_EMPTY);
468  }
469 }
470 
471 
472 /**
473  * @brief Send a packet
474  * @param[in] interface Underlying network interface
475  * @param[in] buffer Multi-part buffer containing the data to send
476  * @param[in] offset Offset to the first data byte
477  * @param[in] ancillary Additional options passed to the stack along with
478  * the packet
479  * @return Error code
480  **/
481 
483  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
484 {
485  size_t length;
486 
487  //Retrieve the length of the packet
488  length = netBufferGetLength(buffer) - offset;
489 
490  //Check the frame length
492  {
493  //The transmitter can accept another packet
494  osSetEvent(&interface->nicTxEvent);
495  //Report an error
496  return ERROR_INVALID_LENGTH;
497  }
498 
499  //Make sure the current buffer is available for writing
500  if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) == 0)
501  {
502  return ERROR_FAILURE;
503  }
504 
505  //Copy user data to the transmit buffer
506  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
507 
508  //Set the necessary flags in the descriptor entry
509  if(txBufferIndex < (SAMA5D3_GETH_TX_BUFFER_COUNT - 1))
510  {
511  //Write the status word
512  txBufferDesc[txBufferIndex].status = GMAC_TX_LAST |
514 
515  //Point to the next buffer
516  txBufferIndex++;
517  }
518  else
519  {
520  //Write the status word
521  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP | GMAC_TX_LAST |
523 
524  //Wrap around
525  txBufferIndex = 0;
526  }
527 
528  //Set the TSTART bit to initiate transmission
529  GMAC->GMAC_NCR |= GMAC_NCR_TSTART;
530 
531  //Check whether the next buffer is available for writing
532  if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) != 0)
533  {
534  //The transmitter can accept another packet
535  osSetEvent(&interface->nicTxEvent);
536  }
537 
538  //Successful processing
539  return NO_ERROR;
540 }
541 
542 
543 /**
544  * @brief Receive a packet
545  * @param[in] interface Underlying network interface
546  * @return Error code
547  **/
548 
550 {
551  static uint8_t temp[ETH_MAX_FRAME_SIZE];
552  error_t error;
553  uint_t i;
554  uint_t j;
555  uint_t sofIndex;
556  uint_t eofIndex;
557  size_t n;
558  size_t size;
559  size_t length;
560 
561  //Initialize variables
562  size = 0;
563  sofIndex = UINT_MAX;
564  eofIndex = UINT_MAX;
565 
566  //Search for SOF and EOF flags
567  for(i = 0; i < SAMA5D3_GETH_RX_BUFFER_COUNT; i++)
568  {
569  //Point to the current entry
570  j = rxBufferIndex + i;
571 
572  //Wrap around to the beginning of the buffer if necessary
574  {
576  }
577 
578  //No more entries to process?
579  if((rxBufferDesc[j].address & GMAC_RX_OWNERSHIP) == 0)
580  {
581  //Stop processing
582  break;
583  }
584 
585  //A valid SOF has been found?
586  if((rxBufferDesc[j].status & GMAC_RX_SOF) != 0)
587  {
588  //Save the position of the SOF
589  sofIndex = i;
590  }
591 
592  //A valid EOF has been found?
593  if((rxBufferDesc[j].status & GMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
594  {
595  //Save the position of the EOF
596  eofIndex = i;
597  //Retrieve the length of the frame
598  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
599  //Limit the number of data to read
600  size = MIN(size, ETH_MAX_FRAME_SIZE);
601  //Stop processing since we have reached the end of the frame
602  break;
603  }
604  }
605 
606  //Determine the number of entries to process
607  if(eofIndex != UINT_MAX)
608  {
609  j = eofIndex + 1;
610  }
611  else if(sofIndex != UINT_MAX)
612  {
613  j = sofIndex;
614  }
615  else
616  {
617  j = i;
618  }
619 
620  //Total number of bytes that have been copied from the receive buffer
621  length = 0;
622 
623  //Process incoming frame
624  for(i = 0; i < j; i++)
625  {
626  //Any data to copy from current buffer?
627  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
628  {
629  //Calculate the number of bytes to read at a time
631  //Copy data from receive buffer
632  osMemcpy(temp + length, rxBuffer[rxBufferIndex], n);
633  //Update byte counters
634  length += n;
635  size -= n;
636  }
637 
638  //Mark the current buffer as free
639  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
640 
641  //Point to the following entry
642  rxBufferIndex++;
643 
644  //Wrap around to the beginning of the buffer if necessary
645  if(rxBufferIndex >= SAMA5D3_GETH_RX_BUFFER_COUNT)
646  {
647  rxBufferIndex = 0;
648  }
649  }
650 
651  //Any packet to process?
652  if(length > 0)
653  {
654  NetRxAncillary ancillary;
655 
656  //Additional options can be passed to the stack along with the packet
657  ancillary = NET_DEFAULT_RX_ANCILLARY;
658 
659  //Pass the packet to the upper layer
660  nicProcessPacket(interface, temp, length, &ancillary);
661  //Valid packet received
662  error = NO_ERROR;
663  }
664  else
665  {
666  //No more data in the receive buffer
667  error = ERROR_BUFFER_EMPTY;
668  }
669 
670  //Return status code
671  return error;
672 }
673 
674 
675 /**
676  * @brief Configure MAC address filtering
677  * @param[in] interface Underlying network interface
678  * @return Error code
679  **/
680 
682 {
683  uint_t i;
684  uint_t j;
685  uint_t k;
686  uint8_t *p;
687  uint32_t hashTable[2];
688  MacAddr unicastMacAddr[3];
689  MacFilterEntry *entry;
690 
691  //Debug message
692  TRACE_DEBUG("Updating MAC filter...\r\n");
693 
694  //Set the MAC address of the station
695  GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
696  GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
697 
698  //The MAC supports 3 additional addresses for unicast perfect filtering
699  unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
700  unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
701  unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
702 
703  //The hash table is used for multicast address filtering
704  hashTable[0] = 0;
705  hashTable[1] = 0;
706 
707  //The MAC address filter contains the list of MAC addresses to accept
708  //when receiving an Ethernet frame
709  for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
710  {
711  //Point to the current entry
712  entry = &interface->macAddrFilter[i];
713 
714  //Valid entry?
715  if(entry->refCount > 0)
716  {
717  //Multicast address?
718  if(macIsMulticastAddr(&entry->addr))
719  {
720  //Point to the MAC address
721  p = entry->addr.b;
722 
723  //Apply the hash function
724  k = (p[0] >> 6) ^ p[0];
725  k ^= (p[1] >> 4) ^ (p[1] << 2);
726  k ^= (p[2] >> 2) ^ (p[2] << 4);
727  k ^= (p[3] >> 6) ^ p[3];
728  k ^= (p[4] >> 4) ^ (p[4] << 2);
729  k ^= (p[5] >> 2) ^ (p[5] << 4);
730 
731  //The hash value is reduced to a 6-bit index
732  k &= 0x3F;
733 
734  //Update hash table contents
735  hashTable[k / 32] |= (1 << (k % 32));
736  }
737  else
738  {
739  //Up to 3 additional MAC addresses can be specified
740  if(j < 3)
741  {
742  //Save the unicast address
743  unicastMacAddr[j] = entry->addr;
744  }
745  else
746  {
747  //Point to the MAC address
748  p = entry->addr.b;
749 
750  //Apply the hash function
751  k = (p[0] >> 6) ^ p[0];
752  k ^= (p[1] >> 4) ^ (p[1] << 2);
753  k ^= (p[2] >> 2) ^ (p[2] << 4);
754  k ^= (p[3] >> 6) ^ p[3];
755  k ^= (p[4] >> 4) ^ (p[4] << 2);
756  k ^= (p[5] >> 2) ^ (p[5] << 4);
757 
758  //The hash value is reduced to a 6-bit index
759  k &= 0x3F;
760 
761  //Update hash table contents
762  hashTable[k / 32] |= (1 << (k % 32));
763  }
764 
765  //Increment the number of unicast addresses
766  j++;
767  }
768  }
769  }
770 
771  //Configure the first unicast address filter
772  if(j >= 1)
773  {
774  //The address is activated when SAT register is written
775  GMAC->GMAC_SA[1].GMAC_SAB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
776  GMAC->GMAC_SA[1].GMAC_SAT = unicastMacAddr[0].w[2];
777  }
778  else
779  {
780  //The address is deactivated when SAB register is written
781  GMAC->GMAC_SA[1].GMAC_SAB = 0;
782  }
783 
784  //Configure the second unicast address filter
785  if(j >= 2)
786  {
787  //The address is activated when SAT register is written
788  GMAC->GMAC_SA[2].GMAC_SAB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
789  GMAC->GMAC_SA[2].GMAC_SAT = unicastMacAddr[1].w[2];
790  }
791  else
792  {
793  //The address is deactivated when SAB register is written
794  GMAC->GMAC_SA[2].GMAC_SAB = 0;
795  }
796 
797  //Configure the third unicast address filter
798  if(j >= 3)
799  {
800  //The address is activated when SAT register is written
801  GMAC->GMAC_SA[3].GMAC_SAB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
802  GMAC->GMAC_SA[3].GMAC_SAT = unicastMacAddr[2].w[2];
803  }
804  else
805  {
806  //The address is deactivated when SAB register is written
807  GMAC->GMAC_SA[3].GMAC_SAB = 0;
808  }
809 
810  //The perfect MAC filter supports only 3 unicast addresses
811  if(j >= 4)
812  {
813  GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN;
814  }
815  else
816  {
817  GMAC->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN;
818  }
819 
820  //Configure the multicast hash table
821  GMAC->GMAC_HRB = hashTable[0];
822  GMAC->GMAC_HRT = hashTable[1];
823 
824  //Debug message
825  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC->GMAC_HRB);
826  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC->GMAC_HRT);
827 
828  //Successful processing
829  return NO_ERROR;
830 }
831 
832 
833 /**
834  * @brief Adjust MAC configuration parameters for proper operation
835  * @param[in] interface Underlying network interface
836  * @return Error code
837  **/
838 
840 {
841  uint32_t config;
842 
843  //Read network configuration register
844  config = GMAC->GMAC_NCFGR;
845 
846  //1000BASE-T operation mode?
847  if(interface->linkSpeed == NIC_LINK_SPEED_1GBPS)
848  {
849  config |= GMAC_NCFGR_GBE;
850  config &= ~GMAC_NCFGR_SPD;
851  }
852  //100BASE-TX operation mode?
853  else if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
854  {
855  config &= ~GMAC_NCFGR_GBE;
856  config |= GMAC_NCFGR_SPD;
857  }
858  //10BASE-T operation mode?
859  else
860  {
861  config &= ~GMAC_NCFGR_GBE;
862  config &= ~GMAC_NCFGR_SPD;
863  }
864 
865  //Half-duplex or full-duplex mode?
866  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
867  {
868  config |= GMAC_NCFGR_FD;
869  }
870  else
871  {
872  config &= ~GMAC_NCFGR_FD;
873  }
874 
875  //Write configuration value back to NCFGR register
876  GMAC->GMAC_NCFGR = config;
877 
878  //Successful processing
879  return NO_ERROR;
880 }
881 
882 
883 /**
884  * @brief Write PHY register
885  * @param[in] opcode Access type (2 bits)
886  * @param[in] phyAddr PHY address (5 bits)
887  * @param[in] regAddr Register address (5 bits)
888  * @param[in] data Register value
889  **/
890 
891 void sama5d3GigabitEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
892  uint8_t regAddr, uint16_t data)
893 {
894  uint32_t temp;
895 
896  //Valid opcode?
897  if(opcode == SMI_OPCODE_WRITE)
898  {
899  //Set up a write operation
900  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
901  //PHY address
902  temp |= GMAC_MAN_PHYA(phyAddr);
903  //Register address
904  temp |= GMAC_MAN_REGA(regAddr);
905  //Register value
906  temp |= GMAC_MAN_DATA(data);
907 
908  //Start a write operation
909  GMAC->GMAC_MAN = temp;
910  //Wait for the write to complete
911  while((GMAC->GMAC_NSR & GMAC_NSR_IDLE) == 0)
912  {
913  }
914  }
915  else
916  {
917  //The MAC peripheral only supports standard Clause 22 opcodes
918  }
919 }
920 
921 
922 /**
923  * @brief Read PHY register
924  * @param[in] opcode Access type (2 bits)
925  * @param[in] phyAddr PHY address (5 bits)
926  * @param[in] regAddr Register address (5 bits)
927  * @return Register value
928  **/
929 
930 uint16_t sama5d3GigabitEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
931  uint8_t regAddr)
932 {
933  uint16_t data;
934  uint32_t temp;
935 
936  //Valid opcode?
937  if(opcode == SMI_OPCODE_READ)
938  {
939  //Set up a read operation
940  temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
941  //PHY address
942  temp |= GMAC_MAN_PHYA(phyAddr);
943  //Register address
944  temp |= GMAC_MAN_REGA(regAddr);
945 
946  //Start a read operation
947  GMAC->GMAC_MAN = temp;
948  //Wait for the read to complete
949  while((GMAC->GMAC_NSR & GMAC_NSR_IDLE) == 0)
950  {
951  }
952 
953  //Get register value
954  data = GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk;
955  }
956  else
957  {
958  //The MAC peripheral only supports standard Clause 22 opcodes
959  data = 0;
960  }
961 
962  //Return the value of the PHY register
963  return data;
964 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:186
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
const MacAddr MAC_UNSPECIFIED_ADDR
Definition: ethernet.c:53
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:220
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:110
MacAddr
Definition: ethernet.h:193
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:314
uint16_t regAddr
uint8_t p
Definition: ndp.h:298
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:100
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
@ NIC_LINK_SPEED_1GBPS
Definition: nic.h:113
#define osMemcpy(dest, src, length)
Definition: os_port.h:143
#define MIN(a, b)
Definition: os_port.h:65
#define TRUE
Definition: os_port.h:52
#define FALSE
Definition: os_port.h:48
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
#define GMAC_RX_EOF
#define GMAC_TX_WRAP
#define GMAC_RX_SOF
#define GMAC_TX_LENGTH
#define GMAC_TX_LAST
#define GMAC_RX_OWNERSHIP
#define GMAC_TX_USED
#define GMAC_RX_WRAP
#define GMAC_RX_LENGTH
#define GMAC_RX_ADDRESS
uint16_t sama5d3GigabitEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t sama5d3GigabitEthReceivePacket(NetInterface *interface)
Receive a packet.
void sama5d3GigabitEthDisableIrq(NetInterface *interface)
Disable interrupts.
void sama5d3GigabitEthTick(NetInterface *interface)
SAMA5D3 Ethernet MAC timer handler.
__weak_func void sama5d3GigabitEthInitGpio(NetInterface *interface)
GPIO configuration.
const NicDriver sama5d3GigabitEthDriver
SAMA5D3 Ethernet MAC driver (GMAC instance)
error_t sama5d3GigabitEthInit(NetInterface *interface)
SAMA5D3 Ethernet MAC initialization.
void sama5d3GigabitEthEnableIrq(NetInterface *interface)
Enable interrupts.
void sama5d3GigabitEthIrqHandler(void)
SAMA5D3 Ethernet MAC interrupt service routine.
error_t sama5d3GigabitEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void sama5d3GigabitEthEventHandler(NetInterface *interface)
SAMA5D3 Ethernet MAC event handler.
void sama5d3GigabitEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t sama5d3GigabitEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t sama5d3GigabitEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void sama5d3GigabitEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
SAMA5D3 Gigabit Ethernet MAC driver (GMAC instance)
#define SAMA5D3_GETH_RX_BUFFER_COUNT
#define GMAC_RGMII_MASK
#define SAMA5D3_GETH_RX_BUFFER_SIZE
#define SAMA5D3_GETH_RAM_SECTION
#define SAMA5D3_GETH_TX_BUFFER_SIZE
#define SAMA5D3_GETH_TX_BUFFER_COUNT
#define SAMA5D3_GETH_IRQ_PRIORITY
MAC filter table entry.
Definition: ethernet.h:258
MacAddr addr
MAC address.
Definition: ethernet.h:259
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:260
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
Receive buffer descriptor.
Transmit buffer descriptor.
uint8_t length
Definition: tcp.h:366