32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "stm32f7xx.h"
36 #include "stm32f7xx_hal.h"
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 4
49 #pragma location = STM32F7XX_ETH_RAM_SECTION
52 #pragma data_alignment = 4
53 #pragma location = STM32F7XX_ETH_RAM_SECTION
56 #pragma data_alignment = 4
57 #pragma location = STM32F7XX_ETH_RAM_SECTION
60 #pragma data_alignment = 4
61 #pragma location = STM32F7XX_ETH_RAM_SECTION
124 TRACE_INFO(
"Initializing STM32F7 Ethernet MAC...\r\n");
127 nicDriverInterface = interface;
133 __HAL_RCC_ETHMAC_CLK_ENABLE();
134 __HAL_RCC_ETHMACTX_CLK_ENABLE();
135 __HAL_RCC_ETHMACRX_CLK_ENABLE();
138 __HAL_RCC_ETHMAC_FORCE_RESET();
139 __HAL_RCC_ETHMAC_RELEASE_RESET();
142 ETH->DMABMR |= ETH_DMABMR_SR;
144 while((ETH->DMABMR & ETH_DMABMR_SR) != 0)
149 ETH->MACMIIAR = ETH_MACMIIAR_CR_Div102;
152 if(interface->phyDriver != NULL)
155 error = interface->phyDriver->init(interface);
157 else if(interface->switchDriver != NULL)
160 error = interface->switchDriver->init(interface);
183 ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
186 ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_32Beat |
187 ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_32Beat | ETH_DMABMR_EDE;
194 ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
198 ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
201 ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
203 ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
213 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
215 ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
233 #if defined(USE_STM32756G_EVAL) || defined(USE_STM32F769I_EVAL)
234 GPIO_InitTypeDef GPIO_InitStructure;
237 __HAL_RCC_SYSCFG_CLK_ENABLE();
240 __HAL_RCC_GPIOA_CLK_ENABLE();
241 __HAL_RCC_GPIOC_CLK_ENABLE();
242 __HAL_RCC_GPIOE_CLK_ENABLE();
243 __HAL_RCC_GPIOG_CLK_ENABLE();
244 __HAL_RCC_GPIOH_CLK_ENABLE();
245 __HAL_RCC_GPIOI_CLK_ENABLE();
248 GPIO_InitStructure.Pin = GPIO_PIN_8;
249 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
250 GPIO_InitStructure.Pull = GPIO_NOPULL;
251 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
252 GPIO_InitStructure.Alternate = GPIO_AF0_MCO;
253 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
256 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
259 SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
262 if(interface->smiDriver == NULL)
265 GPIO_InitStructure.Pin = GPIO_PIN_2;
266 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
267 GPIO_InitStructure.Pull = GPIO_PULLUP;
268 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_MEDIUM;
269 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
270 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
273 GPIO_InitStructure.Pin = GPIO_PIN_1;
274 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
275 GPIO_InitStructure.Pull = GPIO_NOPULL;
276 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_MEDIUM;
277 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
278 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
282 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
283 GPIO_InitStructure.Pull = GPIO_NOPULL;
284 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
285 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
292 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_7;
293 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
297 GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
298 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
301 GPIO_InitStructure.Pin = GPIO_PIN_2;
302 HAL_GPIO_Init(GPIOE, &GPIO_InitStructure);
305 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
306 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
313 GPIO_InitStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
314 HAL_GPIO_Init(GPIOH, &GPIO_InitStructure);
321 #elif defined(USE_STM32746G_DISCO) || defined(USE_STM32F7508_DISCO)
322 GPIO_InitTypeDef GPIO_InitStructure;
325 __HAL_RCC_SYSCFG_CLK_ENABLE();
328 __HAL_RCC_GPIOA_CLK_ENABLE();
329 __HAL_RCC_GPIOC_CLK_ENABLE();
330 __HAL_RCC_GPIOG_CLK_ENABLE();
333 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
336 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
337 GPIO_InitStructure.Pull = GPIO_NOPULL;
338 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
339 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
342 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
343 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
346 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
347 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
351 GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
352 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
355 #elif defined(USE_STM32F769I_DISCO)
356 GPIO_InitTypeDef GPIO_InitStructure;
359 __HAL_RCC_SYSCFG_CLK_ENABLE();
362 __HAL_RCC_GPIOA_CLK_ENABLE();
363 __HAL_RCC_GPIOC_CLK_ENABLE();
364 __HAL_RCC_GPIOD_CLK_ENABLE();
365 __HAL_RCC_GPIOG_CLK_ENABLE();
368 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
371 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
372 GPIO_InitStructure.Pull = GPIO_NOPULL;
373 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
374 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
377 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
378 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
381 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
382 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
385 GPIO_InitStructure.Pin = GPIO_PIN_5;
386 HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
389 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
390 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
393 #elif defined(USE_STM32F7XX_NUCLEO_144)
394 GPIO_InitTypeDef GPIO_InitStructure;
397 __HAL_RCC_SYSCFG_CLK_ENABLE();
400 __HAL_RCC_GPIOA_CLK_ENABLE();
401 __HAL_RCC_GPIOB_CLK_ENABLE();
402 __HAL_RCC_GPIOC_CLK_ENABLE();
403 __HAL_RCC_GPIOG_CLK_ENABLE();
406 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
409 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
410 GPIO_InitStructure.Pull = GPIO_NOPULL;
411 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
412 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
415 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
416 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
419 GPIO_InitStructure.Pin = GPIO_PIN_13;
420 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
423 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
424 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
427 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
428 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
510 if(interface->phyDriver != NULL)
513 interface->phyDriver->tick(interface);
515 else if(interface->switchDriver != NULL)
518 interface->switchDriver->tick(interface);
535 NVIC_EnableIRQ(ETH_IRQn);
538 if(interface->phyDriver != NULL)
541 interface->phyDriver->enableIrq(interface);
543 else if(interface->switchDriver != NULL)
546 interface->switchDriver->enableIrq(interface);
563 NVIC_DisableIRQ(ETH_IRQn);
566 if(interface->phyDriver != NULL)
569 interface->phyDriver->disableIrq(interface);
571 else if(interface->switchDriver != NULL)
574 interface->switchDriver->disableIrq(interface);
602 if((status & ETH_DMASR_TS) != 0)
605 ETH->DMASR = ETH_DMASR_TS;
616 if((status & ETH_DMASR_RS) != 0)
619 ETH->DMASR = ETH_DMASR_RS;
622 nicDriverInterface->nicEvent =
TRUE;
628 ETH->DMASR = ETH_DMASR_NIS;
704 ETH->DMASR = ETH_DMASR_TBUS;
787 ETH->DMASR = ETH_DMASR_RBUS;
808 uint32_t hashTable[2];
816 if(interface->promiscuous)
819 ETH->MACFFR = ETH_MACFFR_PM;
824 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
825 ETH->MACA0HR = interface->macAddr.w[2];
841 entry = &interface->macAddrFilter[i];
854 k = (crc >> 26) & 0x3F;
857 hashTable[k / 32] |= (1 << (k % 32));
865 unicastMacAddr[j++] = entry->
addr;
875 ETH->MACA1LR = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
876 ETH->MACA1HR = unicastMacAddr[0].w[2] | ETH_MACA1HR_AE;
889 ETH->MACA2LR = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
890 ETH->MACA2HR = unicastMacAddr[1].w[2] | ETH_MACA2HR_AE;
903 ETH->MACA3LR = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
904 ETH->MACA3HR = unicastMacAddr[2].w[2] | ETH_MACA3HR_AE;
915 if(interface->acceptAllMulticast)
918 ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_PAM;
923 ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
926 ETH->MACHTLR = hashTable[0];
927 ETH->MACHTHR = hashTable[1];
930 TRACE_DEBUG(
" MACHTLR = %08" PRIX32
"\r\n", ETH->MACHTLR);
931 TRACE_DEBUG(
" MACHTHR = %08" PRIX32
"\r\n", ETH->MACHTHR);
956 config |= ETH_MACCR_FES;
960 config &= ~ETH_MACCR_FES;
966 config |= ETH_MACCR_DM;
970 config &= ~ETH_MACCR_DM;
998 temp = ETH->MACMIIAR & ETH_MACMIIAR_CR;
1000 temp |= ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
1002 temp |= (phyAddr << 11) & ETH_MACMIIAR_PA;
1004 temp |= (
regAddr << 6) & ETH_MACMIIAR_MR;
1007 ETH->MACMIIDR =
data & ETH_MACMIIDR_MD;
1010 ETH->MACMIIAR = temp;
1012 while((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
1041 temp = ETH->MACMIIAR & ETH_MACMIIAR_CR;
1043 temp |= ETH_MACMIIAR_MB;
1045 temp |= (phyAddr << 11) & ETH_MACMIIAR_PA;
1047 temp |= (
regAddr << 6) & ETH_MACMIIAR_MR;
1050 ETH->MACMIIAR = temp;
1052 while((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)
1057 data = ETH->MACMIIDR & ETH_MACMIIDR_MD;
1085 p = (uint8_t *)
data;
1090 for(i = 0; i <
length; i++)
1093 for(j = 0; j < 8; j++)
1096 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
1098 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ETH_MACCR_RESERVED15
void stm32f7xxEthTick(NetInterface *interface)
STM32F7 Ethernet MAC timer handler.
error_t stm32f7xxEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t stm32f7xxEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t stm32f7xxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
uint16_t stm32f7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
uint32_t stm32f7xxEthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t stm32f7xxEthReceivePacket(NetInterface *interface)
Receive a packet.
void stm32f7xxEthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void stm32f7xxEthEnableIrq(NetInterface *interface)
Enable interrupts.
void stm32f7xxEthEventHandler(NetInterface *interface)
STM32F7 Ethernet MAC event handler.
const NicDriver stm32f7xxEthDriver
STM32F7 Ethernet MAC driver.
void ETH_IRQHandler(void)
STM32F7 Ethernet MAC interrupt service routine.
__weak_func void stm32f7xxEthInitGpio(NetInterface *interface)
GPIO configuration.
void stm32f7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t stm32f7xxEthInit(NetInterface *interface)
STM32F7 Ethernet MAC initialization.
void stm32f7xxEthDisableIrq(NetInterface *interface)
Disable interrupts.
STM32F7 Ethernet MAC driver.
#define STM32F7XX_ETH_RX_BUFFER_COUNT
#define STM32F7XX_ETH_IRQ_GROUP_PRIORITY
#define STM32F7XX_ETH_IRQ_SUB_PRIORITY
#define STM32F7XX_ETH_IRQ_PRIORITY_GROUPING
#define STM32F7XX_ETH_TX_BUFFER_COUNT
#define STM32F7XX_ETH_RAM_SECTION
#define STM32F7XX_ETH_TX_BUFFER_SIZE
#define STM32F7XX_ETH_RX_BUFFER_SIZE
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.
Enhanced RX DMA descriptor.
Enhanced TX DMA descriptor.