mimxrt1020_eth_driver.c
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1 /**
2  * @file mimxrt1020_eth_driver.c
3  * @brief NXP i.MX RT1020 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 64
50 #pragma location = MIMXRT1020_ETH_RAM_SECTION
52 //RX buffer
53 #pragma data_alignment = 64
54 #pragma location = MIMXRT1020_ETH_RAM_SECTION
56 //TX buffer descriptors
57 #pragma data_alignment = 64
58 #pragma location = MIMXRT1020_ETH_RAM_SECTION
59 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 64
62 #pragma location = MIMXRT1020_ETH_RAM_SECTION
63 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(64), __section__(MIMXRT1020_ETH_RAM_SECTION)));
71 //RX buffer
73  __attribute__((aligned(64), __section__(MIMXRT1020_ETH_RAM_SECTION)));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1020_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(64), __section__(MIMXRT1020_ETH_RAM_SECTION)));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1020_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(64), __section__(MIMXRT1020_ETH_RAM_SECTION)));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1020 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1020 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1020 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1020EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1020_ETH_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //Valid Ethernet PHY or switch driver?
154  if(interface->phyDriver != NULL)
155  {
156  //Ethernet PHY initialization
157  error = interface->phyDriver->init(interface);
158  }
159  else if(interface->switchDriver != NULL)
160  {
161  //Ethernet switch initialization
162  error = interface->switchDriver->init(interface);
163  }
164  else
165  {
166  //The interface is not properly configured
167  error = ERROR_FAILURE;
168  }
169 
170  //Any error to report?
171  if(error)
172  {
173  return error;
174  }
175 
176  //Set the MAC address of the station (upper 16 bits)
177  value = interface->macAddr.b[5];
178  value |= (interface->macAddr.b[4] << 8);
179  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
180 
181  //Set the MAC address of the station (lower 32 bits)
182  value = interface->macAddr.b[3];
183  value |= (interface->macAddr.b[2] << 8);
184  value |= (interface->macAddr.b[1] << 16);
185  value |= (interface->macAddr.b[0] << 24);
186  ENET->PALR = ENET_PALR_PADDR1(value);
187 
188  //Hash table for unicast address filtering
189  ENET->IALR = 0;
190  ENET->IAUR = 0;
191  //Hash table for multicast address filtering
192  ENET->GALR = 0;
193  ENET->GAUR = 0;
194 
195  //Disable transmit accelerator functions
196  ENET->TACC = 0;
197  //Disable receive accelerator functions
198  ENET->RACC = 0;
199 
200  //Use enhanced buffer descriptors
201  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
202 
203  //Reset statistics counters
204  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
205  ENET->MIBC = 0;
206 
207  //Initialize buffer descriptors
208  mimxrt1020EthInitBufferDesc(interface);
209 
210  //Clear any pending interrupts
211  ENET->EIR = 0xFFFFFFFF;
212  //Enable desired interrupts
213  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
214 
215  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
216  NVIC_SetPriorityGrouping(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING);
217 
218  //Configure ENET interrupt priority
219  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING,
221 
222  //Enable Ethernet MAC
223  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
224  //Instruct the DMA to poll the receive descriptor list
225  ENET->RDAR = ENET_RDAR_RDAR_MASK;
226 
227  //Accept any packets from the upper layer
228  osSetEvent(&interface->nicTxEvent);
229 
230  //Successful initialization
231  return NO_ERROR;
232 }
233 
234 
235 /**
236  * @brief GPIO configuration
237  * @param[in] interface Underlying network interface
238  **/
239 
240 __weak_func void mimxrt1020EthInitGpio(NetInterface *interface)
241 {
242 //MIMXRT1020-EVK or MIMXRT1024-EVK evaluation board?
243 #if defined(USE_MIMXRT1020_EVK) || defined(USE_MIMXRT1024_EVK)
244  gpio_pin_config_t pinConfig;
245  clock_enet_pll_config_t pllConfig;
246 
247  //Configure ENET PLL (50MHz)
248  pllConfig.enableClkOutput = true;
249  pllConfig.enableClkOutput500M = false;
250  pllConfig.enableClkOutput25M = false;
251  pllConfig.loopDivider = 1;
252  pllConfig.src = 0;
253  CLOCK_InitEnetPll(&pllConfig);
254 
255  //Enable ENET1_TX_CLK output driver
256  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
257 
258  //Enable IOMUXC clock
259  CLOCK_EnableClock(kCLOCK_Iomuxc);
260 
261  //Configure GPIO_AD_B0_08 pin as ENET_REF_CLK1
262  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
263 
264  //Set GPIO_AD_B0_08 pad properties
265  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1,
266  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
267  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
268  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
269  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
270  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
271  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
272  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
273  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
274 
275  //Configure GPIO_AD_B0_09 pin as ENET_RDATA01
276  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
277 
278  //Set GPIO_AD_B0_09 pad properties
279  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01,
280  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
281  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
282  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
283  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
284  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
285  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
286  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
287  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
288 
289  //Configure GPIO_AD_B0_10 pin as ENET_RDATA00
290  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
291 
292  //Set GPIO_AD_B0_10 pad properties
293  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00,
294  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
295  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
296  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
297  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
298  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
299  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
300  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
301  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
302 
303  //Configure GPIO_AD_B0_11 pin as ENET_RX_EN
304  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
305 
306  //Set GPIO_AD_B0_11 pad properties
307  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN,
308  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
309  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
310  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
311  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
312  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
313  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
314  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
315  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
316 
317  //Configure GPIO_AD_B0_12 pin as ENET_RX_ER
318  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
319 
320  //Set GPIO_AD_B0_12 pad properties
321  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER,
322  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
323  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
324  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
325  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
326  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
327  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
328  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
329  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
330 
331  //Configure GPIO_AD_B0_13 pin as ENET_TX_EN
332  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
333 
334  //Set GPIO_AD_B0_13 pad properties
335  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN,
336  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
337  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
338  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
339  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
340  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
341  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
342  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
343  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
344 
345  //Configure GPIO_AD_B0_14 pin as ENET_TX_DATA00
346  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
347 
348  //Set GPIO_AD_B0_14 pad properties
349  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00,
350  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
351  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
352  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
353  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
354  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
355  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
356  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
357  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
358 
359  //Configure GPIO_AD_B0_15 pin as ENET_TX_DATA01
360  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
361 
362  //Set GPIO_AD_B0_15 pad properties
363  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01,
364  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
365  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
366  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
367  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
368  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
369  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
370  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
371  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
372 
373  //Configure GPIO_EMC_40 pin as ENET_MDIO
374  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
375 
376  //Set GPIO_EMC_40 pad properties
377  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO,
378  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
379  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
380  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
381  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
382  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
383  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
384  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
385  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
386 
387  //Configure GPIO_EMC_41 pin as ENET_MDC
388  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
389 
390  //Set GPIO_EMC_41 pad properties
391  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC,
392  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
393  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
394  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
395  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
396  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
397  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
398  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
399  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
400 
401  //Configure GPIO_AD_B0_04 pin as GPIO1_IO04
402  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0);
403 
404  //Set GPIO_AD_B0_09 pad properties
405  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04,
406  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
407  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
408  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
409  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
410  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
411  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
412  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
413  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
414 
415  //Configure GPIO_AD_B1_06 pin as GPIO1_IO22
416  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0);
417 
418  //Set GPIO_AD_B1_06 pad properties
419  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22,
420  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
421  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
422  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
423  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
424  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
425  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
426  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
427  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
428 
429  //Configure ENET_RST as an output
430  pinConfig.direction = kGPIO_DigitalOutput;
431  pinConfig.outputLogic = 0;
432  pinConfig.interruptMode = kGPIO_NoIntmode;
433  GPIO_PinInit(GPIO1, 4, &pinConfig);
434 
435  //Configure ENET_INT as an input
436  pinConfig.direction = kGPIO_DigitalInput;
437  pinConfig.outputLogic = 0;
438  pinConfig.interruptMode = kGPIO_NoIntmode;
439  GPIO_PinInit(GPIO1, 22, &pinConfig);
440 
441  //Reset PHY transceiver (hard reset)
442  GPIO_PinWrite(GPIO1, 4, 0);
443  sleep(10);
444  GPIO_PinWrite(GPIO1, 4, 1);
445  sleep(10);
446 #endif
447 }
448 
449 
450 /**
451  * @brief Initialize buffer descriptors
452  * @param[in] interface Underlying network interface
453  **/
454 
456 {
457  uint_t i;
458  uint32_t address;
459 
460  //Clear TX and RX buffer descriptors
461  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
462  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
463 
464  //Initialize TX buffer descriptors
465  for(i = 0; i < MIMXRT1020_ETH_TX_BUFFER_COUNT; i++)
466  {
467  //Calculate the address of the current TX buffer
468  address = (uint32_t) txBuffer[i];
469  //Transmit buffer address
470  txBufferDesc[i][1] = address;
471  //Generate interrupts
472  txBufferDesc[i][2] = ENET_TBD2_INT;
473  }
474 
475  //Mark the last descriptor entry with the wrap flag
476  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
477  //Initialize TX buffer index
478  txBufferIndex = 0;
479 
480  //Initialize RX buffer descriptors
481  for(i = 0; i < MIMXRT1020_ETH_RX_BUFFER_COUNT; i++)
482  {
483  //Calculate the address of the current RX buffer
484  address = (uint32_t) rxBuffer[i];
485  //The descriptor is initially owned by the DMA
486  rxBufferDesc[i][0] = ENET_RBD0_E;
487  //Receive buffer address
488  rxBufferDesc[i][1] = address;
489  //Generate interrupts
490  rxBufferDesc[i][2] = ENET_RBD2_INT;
491  }
492 
493  //Mark the last descriptor entry with the wrap flag
494  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
495  //Initialize RX buffer index
496  rxBufferIndex = 0;
497 
498  //Start location of the TX descriptor list
499  ENET->TDSR = (uint32_t) txBufferDesc;
500  //Start location of the RX descriptor list
501  ENET->RDSR = (uint32_t) rxBufferDesc;
502  //Maximum receive buffer size
503  ENET->MRBR = MIMXRT1020_ETH_RX_BUFFER_SIZE;
504 }
505 
506 
507 /**
508  * @brief i.MX RT1020 Ethernet MAC timer handler
509  *
510  * This routine is periodically called by the TCP/IP stack to handle periodic
511  * operations such as polling the link state
512  *
513  * @param[in] interface Underlying network interface
514  **/
515 
517 {
518  //Valid Ethernet PHY or switch driver?
519  if(interface->phyDriver != NULL)
520  {
521  //Handle periodic operations
522  interface->phyDriver->tick(interface);
523  }
524  else if(interface->switchDriver != NULL)
525  {
526  //Handle periodic operations
527  interface->switchDriver->tick(interface);
528  }
529  else
530  {
531  //Just for sanity
532  }
533 }
534 
535 
536 /**
537  * @brief Enable interrupts
538  * @param[in] interface Underlying network interface
539  **/
540 
542 {
543  //Enable Ethernet MAC interrupts
544  NVIC_EnableIRQ(ENET_IRQn);
545 
546  //Valid Ethernet PHY or switch driver?
547  if(interface->phyDriver != NULL)
548  {
549  //Enable Ethernet PHY interrupts
550  interface->phyDriver->enableIrq(interface);
551  }
552  else if(interface->switchDriver != NULL)
553  {
554  //Enable Ethernet switch interrupts
555  interface->switchDriver->enableIrq(interface);
556  }
557  else
558  {
559  //Just for sanity
560  }
561 }
562 
563 
564 /**
565  * @brief Disable interrupts
566  * @param[in] interface Underlying network interface
567  **/
568 
570 {
571  //Disable Ethernet MAC interrupts
572  NVIC_DisableIRQ(ENET_IRQn);
573 
574  //Valid Ethernet PHY or switch driver?
575  if(interface->phyDriver != NULL)
576  {
577  //Disable Ethernet PHY interrupts
578  interface->phyDriver->disableIrq(interface);
579  }
580  else if(interface->switchDriver != NULL)
581  {
582  //Disable Ethernet switch interrupts
583  interface->switchDriver->disableIrq(interface);
584  }
585  else
586  {
587  //Just for sanity
588  }
589 }
590 
591 
592 /**
593  * @brief Ethernet MAC interrupt
594  **/
595 
596 void ENET_IRQHandler(void)
597 {
598  bool_t flag;
599  uint32_t events;
600 
601  //Interrupt service routine prologue
602  osEnterIsr();
603 
604  //This flag will be set if a higher priority task must be woken
605  flag = FALSE;
606  //Read interrupt event register
607  events = ENET->EIR;
608 
609  //Packet transmitted?
610  if((events & ENET_EIR_TXF_MASK) != 0)
611  {
612  //Clear TXF interrupt flag
613  ENET->EIR = ENET_EIR_TXF_MASK;
614 
615  //Check whether the TX buffer is available for writing
616  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
617  {
618  //Notify the TCP/IP stack that the transmitter is ready to send
619  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
620  }
621 
622  //Instruct the DMA to poll the transmit descriptor list
623  ENET->TDAR = ENET_TDAR_TDAR_MASK;
624  }
625 
626  //Packet received?
627  if((events & ENET_EIR_RXF_MASK) != 0)
628  {
629  //Disable RXF interrupt
630  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
631 
632  //Set event flag
633  nicDriverInterface->nicEvent = TRUE;
634  //Notify the TCP/IP stack of the event
635  flag = osSetEventFromIsr(&netEvent);
636  }
637 
638  //System bus error?
639  if((events & ENET_EIR_EBERR_MASK) != 0)
640  {
641  //Disable EBERR interrupt
642  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
643 
644  //Set event flag
645  nicDriverInterface->nicEvent = TRUE;
646  //Notify the TCP/IP stack of the event
647  flag |= osSetEventFromIsr(&netEvent);
648  }
649 
650  //Interrupt service routine epilogue
651  osExitIsr(flag);
652 }
653 
654 
655 /**
656  * @brief i.MX RT1020 Ethernet MAC event handler
657  * @param[in] interface Underlying network interface
658  **/
659 
661 {
662  error_t error;
663  uint32_t status;
664 
665  //Read interrupt event register
666  status = ENET->EIR;
667 
668  //Packet received?
669  if((status & ENET_EIR_RXF_MASK) != 0)
670  {
671  //Clear RXF interrupt flag
672  ENET->EIR = ENET_EIR_RXF_MASK;
673 
674  //Process all pending packets
675  do
676  {
677  //Read incoming packet
678  error = mimxrt1020EthReceivePacket(interface);
679 
680  //No more data in the receive buffer?
681  } while(error != ERROR_BUFFER_EMPTY);
682  }
683 
684  //System bus error?
685  if((status & ENET_EIR_EBERR_MASK) != 0)
686  {
687  //Clear EBERR interrupt flag
688  ENET->EIR = ENET_EIR_EBERR_MASK;
689 
690  //Disable Ethernet MAC
691  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
692  //Reset buffer descriptors
693  mimxrt1020EthInitBufferDesc(interface);
694  //Resume normal operation
695  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
696  //Instruct the DMA to poll the receive descriptor list
697  ENET->RDAR = ENET_RDAR_RDAR_MASK;
698  }
699 
700  //Re-enable Ethernet MAC interrupts
701  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
702 }
703 
704 
705 /**
706  * @brief Send a packet
707  * @param[in] interface Underlying network interface
708  * @param[in] buffer Multi-part buffer containing the data to send
709  * @param[in] offset Offset to the first data byte
710  * @param[in] ancillary Additional options passed to the stack along with
711  * the packet
712  * @return Error code
713  **/
714 
716  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
717 {
718  static uint32_t temp[MIMXRT1020_ETH_TX_BUFFER_SIZE / 4];
719  size_t length;
720 
721  //Retrieve the length of the packet
722  length = netBufferGetLength(buffer) - offset;
723 
724  //Check the frame length
726  {
727  //The transmitter can accept another packet
728  osSetEvent(&interface->nicTxEvent);
729  //Report an error
730  return ERROR_INVALID_LENGTH;
731  }
732 
733  //Make sure the current buffer is available for writing
734  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
735  {
736  return ERROR_FAILURE;
737  }
738 
739  //Copy user data to the transmit buffer
740  netBufferRead(temp, buffer, offset, length);
741  osMemcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
742 
743  //Clear BDU flag
744  txBufferDesc[txBufferIndex][4] = 0;
745 
746  //Check current index
747  if(txBufferIndex < (MIMXRT1020_ETH_TX_BUFFER_COUNT - 1))
748  {
749  //Give the ownership of the descriptor to the DMA engine
750  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
752 
753  //Point to the next buffer
754  txBufferIndex++;
755  }
756  else
757  {
758  //Give the ownership of the descriptor to the DMA engine
759  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
761 
762  //Wrap around
763  txBufferIndex = 0;
764  }
765 
766  //Data synchronization barrier
767  __DSB();
768 
769  //Instruct the DMA to poll the transmit descriptor list
770  ENET->TDAR = ENET_TDAR_TDAR_MASK;
771 
772  //Check whether the next buffer is available for writing
773  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
774  {
775  //The transmitter can accept another packet
776  osSetEvent(&interface->nicTxEvent);
777  }
778 
779  //Successful processing
780  return NO_ERROR;
781 }
782 
783 
784 /**
785  * @brief Receive a packet
786  * @param[in] interface Underlying network interface
787  * @return Error code
788  **/
789 
791 {
792  static uint32_t temp[MIMXRT1020_ETH_RX_BUFFER_SIZE / 4];
793  error_t error;
794  size_t n;
795  NetRxAncillary ancillary;
796 
797  //Current buffer available for reading?
798  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
799  {
800  //The frame should not span multiple buffers
801  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
802  {
803  //Check whether an error occurred
804  if((rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG | ENET_RBD0_NO |
806  {
807  //Retrieve the length of the frame
808  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
809  //Limit the number of data to read
811 
812  //Copy data from the receive buffer
813  osMemcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
814 
815  //Additional options can be passed to the stack along with the packet
816  ancillary = NET_DEFAULT_RX_ANCILLARY;
817 
818  //Pass the packet to the upper layer
819  nicProcessPacket(interface, (uint8_t *) temp, n, &ancillary);
820 
821  //Valid packet received
822  error = NO_ERROR;
823  }
824  else
825  {
826  //The received packet contains an error
827  error = ERROR_INVALID_PACKET;
828  }
829  }
830  else
831  {
832  //The packet is not valid
833  error = ERROR_INVALID_PACKET;
834  }
835 
836  //Clear BDU flag
837  rxBufferDesc[rxBufferIndex][4] = 0;
838 
839  //Check current index
840  if(rxBufferIndex < (MIMXRT1020_ETH_RX_BUFFER_COUNT - 1))
841  {
842  //Give the ownership of the descriptor back to the DMA engine
843  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
844  //Point to the next buffer
845  rxBufferIndex++;
846  }
847  else
848  {
849  //Give the ownership of the descriptor back to the DMA engine
850  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
851  //Wrap around
852  rxBufferIndex = 0;
853  }
854 
855  //Instruct the DMA to poll the receive descriptor list
856  ENET->RDAR = ENET_RDAR_RDAR_MASK;
857  }
858  else
859  {
860  //No more data in the receive buffer
861  error = ERROR_BUFFER_EMPTY;
862  }
863 
864  //Return status code
865  return error;
866 }
867 
868 
869 /**
870  * @brief Configure MAC address filtering
871  * @param[in] interface Underlying network interface
872  * @return Error code
873  **/
874 
876 {
877  uint_t i;
878  uint_t k;
879  uint32_t crc;
880  uint32_t value;
881  uint32_t unicastHashTable[2];
882  uint32_t multicastHashTable[2];
883  MacFilterEntry *entry;
884 
885  //Debug message
886  TRACE_DEBUG("Updating MAC filter...\r\n");
887 
888  //Set the MAC address of the station (upper 16 bits)
889  value = interface->macAddr.b[5];
890  value |= (interface->macAddr.b[4] << 8);
891  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
892 
893  //Set the MAC address of the station (lower 32 bits)
894  value = interface->macAddr.b[3];
895  value |= (interface->macAddr.b[2] << 8);
896  value |= (interface->macAddr.b[1] << 16);
897  value |= (interface->macAddr.b[0] << 24);
898  ENET->PALR = ENET_PALR_PADDR1(value);
899 
900  //Clear hash table (unicast address filtering)
901  unicastHashTable[0] = 0;
902  unicastHashTable[1] = 0;
903 
904  //Clear hash table (multicast address filtering)
905  multicastHashTable[0] = 0;
906  multicastHashTable[1] = 0;
907 
908  //The MAC address filter contains the list of MAC addresses to accept
909  //when receiving an Ethernet frame
910  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
911  {
912  //Point to the current entry
913  entry = &interface->macAddrFilter[i];
914 
915  //Valid entry?
916  if(entry->refCount > 0)
917  {
918  //Compute CRC over the current MAC address
919  crc = mimxrt1020EthCalcCrc(&entry->addr, sizeof(MacAddr));
920 
921  //The upper 6 bits in the CRC register are used to index the
922  //contents of the hash table
923  k = (crc >> 26) & 0x3F;
924 
925  //Multicast address?
926  if(macIsMulticastAddr(&entry->addr))
927  {
928  //Update the multicast hash table
929  multicastHashTable[k / 32] |= (1 << (k % 32));
930  }
931  else
932  {
933  //Update the unicast hash table
934  unicastHashTable[k / 32] |= (1 << (k % 32));
935  }
936  }
937  }
938 
939  //Write the hash table (unicast address filtering)
940  ENET->IALR = unicastHashTable[0];
941  ENET->IAUR = unicastHashTable[1];
942 
943  //Write the hash table (multicast address filtering)
944  ENET->GALR = multicastHashTable[0];
945  ENET->GAUR = multicastHashTable[1];
946 
947  //Debug message
948  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
949  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
950  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
951  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
952 
953  //Successful processing
954  return NO_ERROR;
955 }
956 
957 
958 /**
959  * @brief Adjust MAC configuration parameters for proper operation
960  * @param[in] interface Underlying network interface
961  * @return Error code
962  **/
963 
965 {
966  //Disable Ethernet MAC while modifying configuration registers
967  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
968 
969  //10BASE-T or 100BASE-TX operation mode?
970  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
971  {
972  //100 Mbps operation
973  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
974  }
975  else
976  {
977  //10 Mbps operation
978  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
979  }
980 
981  //Half-duplex or full-duplex mode?
982  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
983  {
984  //Full-duplex mode
985  ENET->TCR |= ENET_TCR_FDEN_MASK;
986  //Receive path operates independently of transmit
987  ENET->RCR &= ~ENET_RCR_DRT_MASK;
988  }
989  else
990  {
991  //Half-duplex mode
992  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
993  //Disable reception of frames while transmitting
994  ENET->RCR |= ENET_RCR_DRT_MASK;
995  }
996 
997  //Reset buffer descriptors
998  mimxrt1020EthInitBufferDesc(interface);
999 
1000  //Re-enable Ethernet MAC
1001  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
1002  //Instruct the DMA to poll the receive descriptor list
1003  ENET->RDAR = ENET_RDAR_RDAR_MASK;
1004 
1005  //Successful processing
1006  return NO_ERROR;
1007 }
1008 
1009 
1010 /**
1011  * @brief Write PHY register
1012  * @param[in] opcode Access type (2 bits)
1013  * @param[in] phyAddr PHY address (5 bits)
1014  * @param[in] regAddr Register address (5 bits)
1015  * @param[in] data Register value
1016  **/
1017 
1018 void mimxrt1020EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
1019  uint8_t regAddr, uint16_t data)
1020 {
1021  uint32_t temp;
1022 
1023  //Valid opcode?
1024  if(opcode == SMI_OPCODE_WRITE)
1025  {
1026  //Set up a write operation
1027  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
1028  //PHY address
1029  temp |= ENET_MMFR_PA(phyAddr);
1030  //Register address
1031  temp |= ENET_MMFR_RA(regAddr);
1032  //Register value
1033  temp |= ENET_MMFR_DATA(data);
1034 
1035  //Clear MII interrupt flag
1036  ENET->EIR = ENET_EIR_MII_MASK;
1037  //Start a write operation
1038  ENET->MMFR = temp;
1039 
1040  //Wait for the write to complete
1041  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1042  {
1043  }
1044  }
1045  else
1046  {
1047  //The MAC peripheral only supports standard Clause 22 opcodes
1048  }
1049 }
1050 
1051 
1052 /**
1053  * @brief Read PHY register
1054  * @param[in] opcode Access type (2 bits)
1055  * @param[in] phyAddr PHY address (5 bits)
1056  * @param[in] regAddr Register address (5 bits)
1057  * @return Register value
1058  **/
1059 
1060 uint16_t mimxrt1020EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
1061  uint8_t regAddr)
1062 {
1063  uint16_t data;
1064  uint32_t temp;
1065 
1066  //Valid opcode?
1067  if(opcode == SMI_OPCODE_READ)
1068  {
1069  //Set up a read operation
1070  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
1071  //PHY address
1072  temp |= ENET_MMFR_PA(phyAddr);
1073  //Register address
1074  temp |= ENET_MMFR_RA(regAddr);
1075 
1076  //Clear MII interrupt flag
1077  ENET->EIR = ENET_EIR_MII_MASK;
1078  //Start a read operation
1079  ENET->MMFR = temp;
1080 
1081  //Wait for the read to complete
1082  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1083  {
1084  }
1085 
1086  //Get register value
1087  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1088  }
1089  else
1090  {
1091  //The MAC peripheral only supports standard Clause 22 opcodes
1092  data = 0;
1093  }
1094 
1095  //Return the value of the PHY register
1096  return data;
1097 }
1098 
1099 
1100 /**
1101  * @brief CRC calculation
1102  * @param[in] data Pointer to the data over which to calculate the CRC
1103  * @param[in] length Number of bytes to process
1104  * @return Resulting CRC value
1105  **/
1106 
1107 uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
1108 {
1109  uint_t i;
1110  uint_t j;
1111  uint32_t crc;
1112  const uint8_t *p;
1113 
1114  //Point to the data over which to calculate the CRC
1115  p = (uint8_t *) data;
1116  //CRC preset value
1117  crc = 0xFFFFFFFF;
1118 
1119  //Loop through data
1120  for(i = 0; i < length; i++)
1121  {
1122  //Update CRC value
1123  crc ^= p[i];
1124 
1125  //The message is processed bit by bit
1126  for(j = 0; j < 8; j++)
1127  {
1128  if((crc & 0x01) != 0)
1129  {
1130  crc = (crc >> 1) ^ 0xEDB88320;
1131  }
1132  else
1133  {
1134  crc = crc >> 1;
1135  }
1136  }
1137  }
1138 
1139  //Return CRC value
1140  return crc;
1141 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
#define ENET_RBD0_E
#define ENET_RBD0_DATA_LENGTH
#define ENET_TBD2_INT
#define ENET_TBD0_W
#define ENET_TBD0_R
#define ENET_RBD0_L
#define ENET_RBD0_NO
#define ENET_RBD0_W
#define ENET_RBD0_LG
#define ENET_TBD0_DATA_LENGTH
#define ENET_RBD2_INT
#define ENET_RBD0_OV
#define ENET_TBD0_TC
#define ENET_RBD0_CR
#define ENET_TBD0_L
#define ENET_RBD0_TR
void mimxrt1020EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t mimxrt1020EthCalcCrc(const void *data, size_t length)
CRC calculation.
__weak_func void mimxrt1020EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t mimxrt1020EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t mimxrt1020EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
error_t mimxrt1020EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mimxrt1020EthReceivePacket(NetInterface *interface)
Receive a packet.
const NicDriver mimxrt1020EthDriver
i.MX RT1020 Ethernet MAC driver
void mimxrt1020EthTick(NetInterface *interface)
i.MX RT1020 Ethernet MAC timer handler
void mimxrt1020EthDisableIrq(NetInterface *interface)
Disable interrupts.
void mimxrt1020EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t mimxrt1020EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t mimxrt1020EthInit(NetInterface *interface)
i.MX RT1020 Ethernet MAC initialization
void mimxrt1020EthEventHandler(NetInterface *interface)
i.MX RT1020 Ethernet MAC event handler
void mimxrt1020EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
NXP i.MX RT1020 Ethernet MAC driver.
#define MIMXRT1020_ETH_RX_BUFFER_SIZE
#define MIMXRT1020_ETH_IRQ_GROUP_PRIORITY
#define MIMXRT1020_ETH_RAM_SECTION
#define MIMXRT1020_ETH_TX_BUFFER_COUNT
#define MIMXRT1020_ETH_IRQ_SUB_PRIORITY
#define MIMXRT1020_ETH_IRQ_PRIORITY_GROUPING
#define MIMXRT1020_ETH_TX_BUFFER_SIZE
#define MIMXRT1020_ETH_RX_BUFFER_COUNT
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemset(p, value, length)
Definition: os_port.h:135
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint8_t value[]
Definition: tcp.h:369