mimxrt1050_eth_driver.c
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1 /**
2  * @file mimxrt1050_eth_driver.c
3  * @brief NXP i.MX RT1050 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 64
50 #pragma location = MIMXRT1050_ETH_RAM_SECTION
52 //RX buffer
53 #pragma data_alignment = 64
54 #pragma location = MIMXRT1050_ETH_RAM_SECTION
56 //TX buffer descriptors
57 #pragma data_alignment = 64
58 #pragma location = MIMXRT1050_ETH_RAM_SECTION
59 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 64
62 #pragma location = MIMXRT1050_ETH_RAM_SECTION
63 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(64), __section__(MIMXRT1050_ETH_RAM_SECTION)));
71 //RX buffer
73  __attribute__((aligned(64), __section__(MIMXRT1050_ETH_RAM_SECTION)));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1050_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(64), __section__(MIMXRT1050_ETH_RAM_SECTION)));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1050_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(64), __section__(MIMXRT1050_ETH_RAM_SECTION)));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1050 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1050 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1050 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1050EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1050_ETH_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //Valid Ethernet PHY or switch driver?
154  if(interface->phyDriver != NULL)
155  {
156  //Ethernet PHY initialization
157  error = interface->phyDriver->init(interface);
158  }
159  else if(interface->switchDriver != NULL)
160  {
161  //Ethernet switch initialization
162  error = interface->switchDriver->init(interface);
163  }
164  else
165  {
166  //The interface is not properly configured
167  error = ERROR_FAILURE;
168  }
169 
170  //Any error to report?
171  if(error)
172  {
173  return error;
174  }
175 
176  //Set the MAC address of the station (upper 16 bits)
177  value = interface->macAddr.b[5];
178  value |= (interface->macAddr.b[4] << 8);
179  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
180 
181  //Set the MAC address of the station (lower 32 bits)
182  value = interface->macAddr.b[3];
183  value |= (interface->macAddr.b[2] << 8);
184  value |= (interface->macAddr.b[1] << 16);
185  value |= (interface->macAddr.b[0] << 24);
186  ENET->PALR = ENET_PALR_PADDR1(value);
187 
188  //Hash table for unicast address filtering
189  ENET->IALR = 0;
190  ENET->IAUR = 0;
191  //Hash table for multicast address filtering
192  ENET->GALR = 0;
193  ENET->GAUR = 0;
194 
195  //Disable transmit accelerator functions
196  ENET->TACC = 0;
197  //Disable receive accelerator functions
198  ENET->RACC = 0;
199 
200  //Use enhanced buffer descriptors
201  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
202 
203  //Reset statistics counters
204  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
205  ENET->MIBC = 0;
206 
207  //Initialize buffer descriptors
208  mimxrt1050EthInitBufferDesc(interface);
209 
210  //Clear any pending interrupts
211  ENET->EIR = 0xFFFFFFFF;
212  //Enable desired interrupts
213  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
214 
215  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
216  NVIC_SetPriorityGrouping(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING);
217 
218  //Configure ENET interrupt priority
219  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING,
221 
222  //Enable Ethernet MAC
223  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
224  //Instruct the DMA to poll the receive descriptor list
225  ENET->RDAR = ENET_RDAR_RDAR_MASK;
226 
227  //Accept any packets from the upper layer
228  osSetEvent(&interface->nicTxEvent);
229 
230  //Successful initialization
231  return NO_ERROR;
232 }
233 
234 
235 /**
236  * @brief GPIO configuration
237  * @param[in] interface Underlying network interface
238  **/
239 
240 __weak_func void mimxrt1050EthInitGpio(NetInterface *interface)
241 {
242 //MIMXRT1050-EVKA or MIMXRT1050-EVKB evaluation board?
243 #if defined(USE_MIMXRT1050_EVKA) || defined(USE_MIMXRT1050_EVKB)
244  gpio_pin_config_t pinConfig;
245  clock_enet_pll_config_t pllConfig;
246 
247 #if (defined(CPU_MIMXRT1052CVL5A) || defined(CPU_MIMXRT1052DVL6A))
248  //Configure ENET PLL (50MHz)
249  pllConfig.enableClkOutput0 = true;
250  pllConfig.enableClkOutput1 = false;
251  pllConfig.enableClkOutput2 = false;
252  pllConfig.loopDivider0 = 1;
253  pllConfig.loopDivider1 = 0;
254  CLOCK_InitEnetPll(&pllConfig);
255 #else
256  //Configure ENET PLL (50MHz)
257  pllConfig.enableClkOutput = true;
258  pllConfig.enableClkOutput25M = false;
259  pllConfig.loopDivider = 1;
260  pllConfig.src = 0;
261  CLOCK_InitEnetPll(&pllConfig);
262 #endif
263 
264  //Enable ENET1_TX_CLK output driver
265  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
266 
267  //Enable IOMUXC clock
268  CLOCK_EnableClock(kCLOCK_Iomuxc);
269 
270  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
271  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
272 
273  //Set GPIO_B1_04 pad properties
274  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
275  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
276  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
277  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
281  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
282  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
283 
284  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
285  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
286 
287  //Set GPIO_B1_05 pad properties
288  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
289  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
290  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
291  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
293  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
295  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
296  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
297 
298  //Configure GPIO_B1_06 pin as ENET_RX_EN
299  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
300 
301  //Set GPIO_B1_06 pad properties
302  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
303  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
304  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
305  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
309  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
310  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
311 
312  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
313  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
314 
315  //Set GPIO_B1_07 pad properties
316  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
317  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
318  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
319  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
323  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
324  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
325 
326  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
327  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
328 
329  //Set GPIO_B1_08 pad properties
330  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
331  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
332  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
333  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
337  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
338  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
339 
340  //Configure GPIO_B1_09 pin as ENET_TX_EN
341  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
342 
343  //Set GPIO_B1_09 pad properties
344  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
345  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
346  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
347  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
348  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
350  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
351  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
352  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
353 
354  //Configure GPIO_B1_10 pin as ENET_REF_CLK
355  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
356 
357  //Set GPIO_B1_10 pad properties
358  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
359  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
360  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
361  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
362  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
363  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
364  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
365  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
366  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
367 
368  //Configure GPIO_B1_11 pin as ENET_RX_ER
369  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
370 
371  //Set GPIO_B1_11 pad properties
372  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
373  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
374  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
375  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
376  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
377  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
378  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
379  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
380  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
381 
382  //Configure GPIO_EMC_40 pin as ENET_MDC
383  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
384 
385  //Set GPIO_EMC_40 pad properties
386  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
387  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
388  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
389  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
390  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
391  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
392  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
393  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
394  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
395 
396  //Configure GPIO_EMC_41 pin as ENET_MDIO
397  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
398 
399  //Set GPIO_EMC_41 pad properties
400  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
401  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
402  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
403  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
404  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
405  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
406  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
407  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
408  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
409 
410  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
411  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
412 
413  //Set GPIO_AD_B0_09 pad properties
414  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
415  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
416  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
417  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
418  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
419  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
420  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
421  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
422  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
423 
424  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
425  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
426 
427  //Set GPIO_AD_B0_10 pad properties
428  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
429  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
430  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
431  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
432  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
433  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
434  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
435  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
436  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
437 
438  //Configure ENET_RST as an output
439  pinConfig.direction = kGPIO_DigitalOutput;
440  pinConfig.outputLogic = 0;
441  pinConfig.interruptMode = kGPIO_NoIntmode;
442  GPIO_PinInit(GPIO1, 9, &pinConfig);
443 
444  //Configure ENET_INT as an input
445  pinConfig.direction = kGPIO_DigitalInput;
446  pinConfig.outputLogic = 0;
447  pinConfig.interruptMode = kGPIO_NoIntmode;
448  GPIO_PinInit(GPIO1, 10, &pinConfig);
449 
450  //Reset PHY transceiver (hard reset)
451  GPIO_PinWrite(GPIO1, 9, 0);
452  sleep(10);
453  GPIO_PinWrite(GPIO1, 9, 1);
454  sleep(10);
455 #endif
456 }
457 
458 
459 /**
460  * @brief Initialize buffer descriptors
461  * @param[in] interface Underlying network interface
462  **/
463 
465 {
466  uint_t i;
467  uint32_t address;
468 
469  //Clear TX and RX buffer descriptors
470  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
471  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
472 
473  //Initialize TX buffer descriptors
474  for(i = 0; i < MIMXRT1050_ETH_TX_BUFFER_COUNT; i++)
475  {
476  //Calculate the address of the current TX buffer
477  address = (uint32_t) txBuffer[i];
478  //Transmit buffer address
479  txBufferDesc[i][1] = address;
480  //Generate interrupts
481  txBufferDesc[i][2] = ENET_TBD2_INT;
482  }
483 
484  //Mark the last descriptor entry with the wrap flag
485  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
486  //Initialize TX buffer index
487  txBufferIndex = 0;
488 
489  //Initialize RX buffer descriptors
490  for(i = 0; i < MIMXRT1050_ETH_RX_BUFFER_COUNT; i++)
491  {
492  //Calculate the address of the current RX buffer
493  address = (uint32_t) rxBuffer[i];
494  //The descriptor is initially owned by the DMA
495  rxBufferDesc[i][0] = ENET_RBD0_E;
496  //Receive buffer address
497  rxBufferDesc[i][1] = address;
498  //Generate interrupts
499  rxBufferDesc[i][2] = ENET_RBD2_INT;
500  }
501 
502  //Mark the last descriptor entry with the wrap flag
503  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
504  //Initialize RX buffer index
505  rxBufferIndex = 0;
506 
507  //Start location of the TX descriptor list
508  ENET->TDSR = (uint32_t) txBufferDesc;
509  //Start location of the RX descriptor list
510  ENET->RDSR = (uint32_t) rxBufferDesc;
511  //Maximum receive buffer size
512  ENET->MRBR = MIMXRT1050_ETH_RX_BUFFER_SIZE;
513 }
514 
515 
516 /**
517  * @brief i.MX RT1050 Ethernet MAC timer handler
518  *
519  * This routine is periodically called by the TCP/IP stack to handle periodic
520  * operations such as polling the link state
521  *
522  * @param[in] interface Underlying network interface
523  **/
524 
526 {
527  //Valid Ethernet PHY or switch driver?
528  if(interface->phyDriver != NULL)
529  {
530  //Handle periodic operations
531  interface->phyDriver->tick(interface);
532  }
533  else if(interface->switchDriver != NULL)
534  {
535  //Handle periodic operations
536  interface->switchDriver->tick(interface);
537  }
538  else
539  {
540  //Just for sanity
541  }
542 }
543 
544 
545 /**
546  * @brief Enable interrupts
547  * @param[in] interface Underlying network interface
548  **/
549 
551 {
552  //Enable Ethernet MAC interrupts
553  NVIC_EnableIRQ(ENET_IRQn);
554 
555  //Valid Ethernet PHY or switch driver?
556  if(interface->phyDriver != NULL)
557  {
558  //Enable Ethernet PHY interrupts
559  interface->phyDriver->enableIrq(interface);
560  }
561  else if(interface->switchDriver != NULL)
562  {
563  //Enable Ethernet switch interrupts
564  interface->switchDriver->enableIrq(interface);
565  }
566  else
567  {
568  //Just for sanity
569  }
570 }
571 
572 
573 /**
574  * @brief Disable interrupts
575  * @param[in] interface Underlying network interface
576  **/
577 
579 {
580  //Disable Ethernet MAC interrupts
581  NVIC_DisableIRQ(ENET_IRQn);
582 
583  //Valid Ethernet PHY or switch driver?
584  if(interface->phyDriver != NULL)
585  {
586  //Disable Ethernet PHY interrupts
587  interface->phyDriver->disableIrq(interface);
588  }
589  else if(interface->switchDriver != NULL)
590  {
591  //Disable Ethernet switch interrupts
592  interface->switchDriver->disableIrq(interface);
593  }
594  else
595  {
596  //Just for sanity
597  }
598 }
599 
600 
601 /**
602  * @brief Ethernet MAC interrupt
603  **/
604 
605 void ENET_IRQHandler(void)
606 {
607  bool_t flag;
608  uint32_t events;
609 
610  //Interrupt service routine prologue
611  osEnterIsr();
612 
613  //This flag will be set if a higher priority task must be woken
614  flag = FALSE;
615  //Read interrupt event register
616  events = ENET->EIR;
617 
618  //Packet transmitted?
619  if((events & ENET_EIR_TXF_MASK) != 0)
620  {
621  //Clear TXF interrupt flag
622  ENET->EIR = ENET_EIR_TXF_MASK;
623 
624  //Check whether the TX buffer is available for writing
625  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
626  {
627  //Notify the TCP/IP stack that the transmitter is ready to send
628  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
629  }
630 
631  //Instruct the DMA to poll the transmit descriptor list
632  ENET->TDAR = ENET_TDAR_TDAR_MASK;
633  }
634 
635  //Packet received?
636  if((events & ENET_EIR_RXF_MASK) != 0)
637  {
638  //Disable RXF interrupt
639  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
640 
641  //Set event flag
642  nicDriverInterface->nicEvent = TRUE;
643  //Notify the TCP/IP stack of the event
644  flag = osSetEventFromIsr(&netEvent);
645  }
646 
647  //System bus error?
648  if((events & ENET_EIR_EBERR_MASK) != 0)
649  {
650  //Disable EBERR interrupt
651  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
652 
653  //Set event flag
654  nicDriverInterface->nicEvent = TRUE;
655  //Notify the TCP/IP stack of the event
656  flag |= osSetEventFromIsr(&netEvent);
657  }
658 
659  //Interrupt service routine epilogue
660  osExitIsr(flag);
661 }
662 
663 
664 /**
665  * @brief i.MX RT1050 Ethernet MAC event handler
666  * @param[in] interface Underlying network interface
667  **/
668 
670 {
671  error_t error;
672  uint32_t status;
673 
674  //Read interrupt event register
675  status = ENET->EIR;
676 
677  //Packet received?
678  if((status & ENET_EIR_RXF_MASK) != 0)
679  {
680  //Clear RXF interrupt flag
681  ENET->EIR = ENET_EIR_RXF_MASK;
682 
683  //Process all pending packets
684  do
685  {
686  //Read incoming packet
687  error = mimxrt1050EthReceivePacket(interface);
688 
689  //No more data in the receive buffer?
690  } while(error != ERROR_BUFFER_EMPTY);
691  }
692 
693  //System bus error?
694  if((status & ENET_EIR_EBERR_MASK) != 0)
695  {
696  //Clear EBERR interrupt flag
697  ENET->EIR = ENET_EIR_EBERR_MASK;
698 
699  //Disable Ethernet MAC
700  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
701  //Reset buffer descriptors
702  mimxrt1050EthInitBufferDesc(interface);
703  //Resume normal operation
704  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
705  //Instruct the DMA to poll the receive descriptor list
706  ENET->RDAR = ENET_RDAR_RDAR_MASK;
707  }
708 
709  //Re-enable Ethernet MAC interrupts
710  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
711 }
712 
713 
714 /**
715  * @brief Send a packet
716  * @param[in] interface Underlying network interface
717  * @param[in] buffer Multi-part buffer containing the data to send
718  * @param[in] offset Offset to the first data byte
719  * @param[in] ancillary Additional options passed to the stack along with
720  * the packet
721  * @return Error code
722  **/
723 
725  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
726 {
727  static uint32_t temp[MIMXRT1050_ETH_TX_BUFFER_SIZE / 4];
728  size_t length;
729 
730  //Retrieve the length of the packet
731  length = netBufferGetLength(buffer) - offset;
732 
733  //Check the frame length
735  {
736  //The transmitter can accept another packet
737  osSetEvent(&interface->nicTxEvent);
738  //Report an error
739  return ERROR_INVALID_LENGTH;
740  }
741 
742  //Make sure the current buffer is available for writing
743  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
744  {
745  return ERROR_FAILURE;
746  }
747 
748  //Copy user data to the transmit buffer
749  netBufferRead(temp, buffer, offset, length);
750  osMemcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
751 
752  //Clear BDU flag
753  txBufferDesc[txBufferIndex][4] = 0;
754 
755  //Check current index
756  if(txBufferIndex < (MIMXRT1050_ETH_TX_BUFFER_COUNT - 1))
757  {
758  //Give the ownership of the descriptor to the DMA engine
759  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
761 
762  //Point to the next buffer
763  txBufferIndex++;
764  }
765  else
766  {
767  //Give the ownership of the descriptor to the DMA engine
768  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
770 
771  //Wrap around
772  txBufferIndex = 0;
773  }
774 
775  //Data synchronization barrier
776  __DSB();
777 
778  //Instruct the DMA to poll the transmit descriptor list
779  ENET->TDAR = ENET_TDAR_TDAR_MASK;
780 
781  //Check whether the next buffer is available for writing
782  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
783  {
784  //The transmitter can accept another packet
785  osSetEvent(&interface->nicTxEvent);
786  }
787 
788  //Successful processing
789  return NO_ERROR;
790 }
791 
792 
793 /**
794  * @brief Receive a packet
795  * @param[in] interface Underlying network interface
796  * @return Error code
797  **/
798 
800 {
801  static uint32_t temp[MIMXRT1050_ETH_RX_BUFFER_SIZE / 4];
802  error_t error;
803  size_t n;
804  NetRxAncillary ancillary;
805 
806  //Current buffer available for reading?
807  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
808  {
809  //The frame should not span multiple buffers
810  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
811  {
812  //Check whether an error occurred
813  if((rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG | ENET_RBD0_NO |
815  {
816  //Retrieve the length of the frame
817  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
818  //Limit the number of data to read
820 
821  //Copy data from the receive buffer
822  osMemcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
823 
824  //Additional options can be passed to the stack along with the packet
825  ancillary = NET_DEFAULT_RX_ANCILLARY;
826 
827  //Pass the packet to the upper layer
828  nicProcessPacket(interface, (uint8_t *) temp, n, &ancillary);
829 
830  //Valid packet received
831  error = NO_ERROR;
832  }
833  else
834  {
835  //The received packet contains an error
836  error = ERROR_INVALID_PACKET;
837  }
838  }
839  else
840  {
841  //The packet is not valid
842  error = ERROR_INVALID_PACKET;
843  }
844 
845  //Clear BDU flag
846  rxBufferDesc[rxBufferIndex][4] = 0;
847 
848  //Check current index
849  if(rxBufferIndex < (MIMXRT1050_ETH_RX_BUFFER_COUNT - 1))
850  {
851  //Give the ownership of the descriptor back to the DMA engine
852  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
853  //Point to the next buffer
854  rxBufferIndex++;
855  }
856  else
857  {
858  //Give the ownership of the descriptor back to the DMA engine
859  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
860  //Wrap around
861  rxBufferIndex = 0;
862  }
863 
864  //Instruct the DMA to poll the receive descriptor list
865  ENET->RDAR = ENET_RDAR_RDAR_MASK;
866  }
867  else
868  {
869  //No more data in the receive buffer
870  error = ERROR_BUFFER_EMPTY;
871  }
872 
873  //Return status code
874  return error;
875 }
876 
877 
878 /**
879  * @brief Configure MAC address filtering
880  * @param[in] interface Underlying network interface
881  * @return Error code
882  **/
883 
885 {
886  uint_t i;
887  uint_t k;
888  uint32_t crc;
889  uint32_t value;
890  uint32_t unicastHashTable[2];
891  uint32_t multicastHashTable[2];
892  MacFilterEntry *entry;
893 
894  //Debug message
895  TRACE_DEBUG("Updating MAC filter...\r\n");
896 
897  //Set the MAC address of the station (upper 16 bits)
898  value = interface->macAddr.b[5];
899  value |= (interface->macAddr.b[4] << 8);
900  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
901 
902  //Set the MAC address of the station (lower 32 bits)
903  value = interface->macAddr.b[3];
904  value |= (interface->macAddr.b[2] << 8);
905  value |= (interface->macAddr.b[1] << 16);
906  value |= (interface->macAddr.b[0] << 24);
907  ENET->PALR = ENET_PALR_PADDR1(value);
908 
909  //Clear hash table (unicast address filtering)
910  unicastHashTable[0] = 0;
911  unicastHashTable[1] = 0;
912 
913  //Clear hash table (multicast address filtering)
914  multicastHashTable[0] = 0;
915  multicastHashTable[1] = 0;
916 
917  //The MAC address filter contains the list of MAC addresses to accept
918  //when receiving an Ethernet frame
919  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
920  {
921  //Point to the current entry
922  entry = &interface->macAddrFilter[i];
923 
924  //Valid entry?
925  if(entry->refCount > 0)
926  {
927  //Compute CRC over the current MAC address
928  crc = mimxrt1050EthCalcCrc(&entry->addr, sizeof(MacAddr));
929 
930  //The upper 6 bits in the CRC register are used to index the
931  //contents of the hash table
932  k = (crc >> 26) & 0x3F;
933 
934  //Multicast address?
935  if(macIsMulticastAddr(&entry->addr))
936  {
937  //Update the multicast hash table
938  multicastHashTable[k / 32] |= (1 << (k % 32));
939  }
940  else
941  {
942  //Update the unicast hash table
943  unicastHashTable[k / 32] |= (1 << (k % 32));
944  }
945  }
946  }
947 
948  //Write the hash table (unicast address filtering)
949  ENET->IALR = unicastHashTable[0];
950  ENET->IAUR = unicastHashTable[1];
951 
952  //Write the hash table (multicast address filtering)
953  ENET->GALR = multicastHashTable[0];
954  ENET->GAUR = multicastHashTable[1];
955 
956  //Debug message
957  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
958  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
959  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
960  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
961 
962  //Successful processing
963  return NO_ERROR;
964 }
965 
966 
967 /**
968  * @brief Adjust MAC configuration parameters for proper operation
969  * @param[in] interface Underlying network interface
970  * @return Error code
971  **/
972 
974 {
975  //Disable Ethernet MAC while modifying configuration registers
976  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
977 
978  //10BASE-T or 100BASE-TX operation mode?
979  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
980  {
981  //100 Mbps operation
982  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
983  }
984  else
985  {
986  //10 Mbps operation
987  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
988  }
989 
990  //Half-duplex or full-duplex mode?
991  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
992  {
993  //Full-duplex mode
994  ENET->TCR |= ENET_TCR_FDEN_MASK;
995  //Receive path operates independently of transmit
996  ENET->RCR &= ~ENET_RCR_DRT_MASK;
997  }
998  else
999  {
1000  //Half-duplex mode
1001  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
1002  //Disable reception of frames while transmitting
1003  ENET->RCR |= ENET_RCR_DRT_MASK;
1004  }
1005 
1006  //Reset buffer descriptors
1007  mimxrt1050EthInitBufferDesc(interface);
1008 
1009  //Re-enable Ethernet MAC
1010  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
1011  //Instruct the DMA to poll the receive descriptor list
1012  ENET->RDAR = ENET_RDAR_RDAR_MASK;
1013 
1014  //Successful processing
1015  return NO_ERROR;
1016 }
1017 
1018 
1019 /**
1020  * @brief Write PHY register
1021  * @param[in] opcode Access type (2 bits)
1022  * @param[in] phyAddr PHY address (5 bits)
1023  * @param[in] regAddr Register address (5 bits)
1024  * @param[in] data Register value
1025  **/
1026 
1027 void mimxrt1050EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
1028  uint8_t regAddr, uint16_t data)
1029 {
1030  uint32_t temp;
1031 
1032  //Valid opcode?
1033  if(opcode == SMI_OPCODE_WRITE)
1034  {
1035  //Set up a write operation
1036  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
1037  //PHY address
1038  temp |= ENET_MMFR_PA(phyAddr);
1039  //Register address
1040  temp |= ENET_MMFR_RA(regAddr);
1041  //Register value
1042  temp |= ENET_MMFR_DATA(data);
1043 
1044  //Clear MII interrupt flag
1045  ENET->EIR = ENET_EIR_MII_MASK;
1046  //Start a write operation
1047  ENET->MMFR = temp;
1048 
1049  //Wait for the write to complete
1050  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1051  {
1052  }
1053  }
1054  else
1055  {
1056  //The MAC peripheral only supports standard Clause 22 opcodes
1057  }
1058 }
1059 
1060 
1061 /**
1062  * @brief Read PHY register
1063  * @param[in] opcode Access type (2 bits)
1064  * @param[in] phyAddr PHY address (5 bits)
1065  * @param[in] regAddr Register address (5 bits)
1066  * @return Register value
1067  **/
1068 
1069 uint16_t mimxrt1050EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
1070  uint8_t regAddr)
1071 {
1072  uint16_t data;
1073  uint32_t temp;
1074 
1075  //Valid opcode?
1076  if(opcode == SMI_OPCODE_READ)
1077  {
1078  //Set up a read operation
1079  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
1080  //PHY address
1081  temp |= ENET_MMFR_PA(phyAddr);
1082  //Register address
1083  temp |= ENET_MMFR_RA(regAddr);
1084 
1085  //Clear MII interrupt flag
1086  ENET->EIR = ENET_EIR_MII_MASK;
1087  //Start a read operation
1088  ENET->MMFR = temp;
1089 
1090  //Wait for the read to complete
1091  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
1092  {
1093  }
1094 
1095  //Get register value
1096  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1097  }
1098  else
1099  {
1100  //The MAC peripheral only supports standard Clause 22 opcodes
1101  data = 0;
1102  }
1103 
1104  //Return the value of the PHY register
1105  return data;
1106 }
1107 
1108 
1109 /**
1110  * @brief CRC calculation
1111  * @param[in] data Pointer to the data over which to calculate the CRC
1112  * @param[in] length Number of bytes to process
1113  * @return Resulting CRC value
1114  **/
1115 
1116 uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
1117 {
1118  uint_t i;
1119  uint_t j;
1120  uint32_t crc;
1121  const uint8_t *p;
1122 
1123  //Point to the data over which to calculate the CRC
1124  p = (uint8_t *) data;
1125  //CRC preset value
1126  crc = 0xFFFFFFFF;
1127 
1128  //Loop through data
1129  for(i = 0; i < length; i++)
1130  {
1131  //Update CRC value
1132  crc ^= p[i];
1133 
1134  //The message is processed bit by bit
1135  for(j = 0; j < 8; j++)
1136  {
1137  if((crc & 0x01) != 0)
1138  {
1139  crc = (crc >> 1) ^ 0xEDB88320;
1140  }
1141  else
1142  {
1143  crc = crc >> 1;
1144  }
1145  }
1146  }
1147 
1148  //Return CRC value
1149  return crc;
1150 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
#define ENET_RBD0_E
#define ENET_RBD0_DATA_LENGTH
#define ENET_TBD2_INT
#define ENET_TBD0_W
#define ENET_TBD0_R
#define ENET_RBD0_L
#define ENET_RBD0_NO
#define ENET_RBD0_W
#define ENET_RBD0_LG
#define ENET_TBD0_DATA_LENGTH
#define ENET_RBD2_INT
#define ENET_RBD0_OV
#define ENET_TBD0_TC
#define ENET_RBD0_CR
#define ENET_TBD0_L
#define ENET_RBD0_TR
uint16_t mimxrt1050EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mimxrt1050EthTick(NetInterface *interface)
i.MX RT1050 Ethernet MAC timer handler
void mimxrt1050EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t mimxrt1050EthReceivePacket(NetInterface *interface)
Receive a packet.
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
error_t mimxrt1050EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
__weak_func void mimxrt1050EthInitGpio(NetInterface *interface)
GPIO configuration.
void mimxrt1050EthEventHandler(NetInterface *interface)
i.MX RT1050 Ethernet MAC event handler
void mimxrt1050EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t mimxrt1050EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t mimxrt1050EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mimxrt1050EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mimxrt1050EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void mimxrt1050EthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver mimxrt1050EthDriver
i.MX RT1050 Ethernet MAC driver
error_t mimxrt1050EthInit(NetInterface *interface)
i.MX RT1050 Ethernet MAC initialization
NXP i.MX RT1050 Ethernet MAC driver.
#define MIMXRT1050_ETH_RAM_SECTION
#define MIMXRT1050_ETH_TX_BUFFER_SIZE
#define MIMXRT1050_ETH_RX_BUFFER_SIZE
#define MIMXRT1050_ETH_IRQ_SUB_PRIORITY
#define MIMXRT1050_ETH_RX_BUFFER_COUNT
#define MIMXRT1050_ETH_IRQ_PRIORITY_GROUPING
#define MIMXRT1050_ETH_TX_BUFFER_COUNT
#define MIMXRT1050_ETH_IRQ_GROUP_PRIORITY
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemset(p, value, length)
Definition: os_port.h:135
#define osMemcpy(dest, src, length)
Definition: os_port.h:141
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint8_t value[]
Definition: tcp.h:369