s32k1_eth_driver.c
Go to the documentation of this file.
1 /**
2  * @file s32k1_eth_driver.c
3  * @brief NXP S32K1 Ethernet MAC driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //TX buffer
47 #pragma data_alignment = 16
49 //RX buffer
50 #pragma data_alignment = 16
52 //TX buffer descriptors
53 #pragma data_alignment = 16
54 static uint32_t txBufferDesc[S32K1_ETH_TX_BUFFER_COUNT][8];
55 //RX buffer descriptors
56 #pragma data_alignment = 16
57 static uint32_t rxBufferDesc[S32K1_ETH_RX_BUFFER_COUNT][8];
58 
59 //ARM or GCC compiler?
60 #else
61 
62 //TX buffer
64  __attribute__((aligned(16)));
65 //RX buffer
67  __attribute__((aligned(16)));
68 //TX buffer descriptors
69 static uint32_t txBufferDesc[S32K1_ETH_TX_BUFFER_COUNT][8]
70  __attribute__((aligned(16)));
71 //RX buffer descriptors
72 static uint32_t rxBufferDesc[S32K1_ETH_RX_BUFFER_COUNT][8]
73  __attribute__((aligned(16)));
74 
75 #endif
76 
77 //TX buffer index
78 static uint_t txBufferIndex;
79 //RX buffer index
80 static uint_t rxBufferIndex;
81 
82 
83 /**
84  * @brief S32K1 Ethernet MAC driver
85  **/
86 
88 {
90  ETH_MTU,
101  TRUE,
102  TRUE,
103  TRUE,
104  FALSE
105 };
106 
107 
108 /**
109  * @brief S32K1 Ethernet MAC initialization
110  * @param[in] interface Underlying network interface
111  * @return Error code
112  **/
113 
115 {
116  error_t error;
117  uint32_t value;
118 
119  //Debug message
120  TRACE_INFO("Initializing S32K1 Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Disable MPU
126  MPU->CESR &= ~MPU_CESR_VLD_MASK;
127 
128  //Enable external reference clock
129  SIM->MISCTRL0 &= ~(SIM_MISCTRL0_RMII_CLK_SEL_MASK |
130  SIM_MISCTRL0_RMII_CLK_OBE_MASK);
131 
132  //Enable ENET peripheral clock
133  PCC->PCCn[PCC_ENET_INDEX] |= PCC_PCCn_CGC_MASK;
134 
135  //GPIO configuration
136  s32k1EthInitGpio(interface);
137 
138  //Reset ENET module
139  ENET->ECR = ENET_ECR_RESET_MASK;
140  //Wait for the reset to complete
141  while((ENET->ECR & ENET_ECR_RESET_MASK) != 0)
142  {
143  }
144 
145  //Receive control register
146  ENET->RCR = ENET_RCR_MAX_FL(S32K1_ETH_RX_BUFFER_SIZE) |
147  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
148 
149  //Transmit control register
150  ENET->TCR = 0;
151  //Configure MDC clock frequency
152  ENET->MSCR = ENET_MSCR_MII_SPEED(23);
153 
154  //Valid Ethernet PHY or switch driver?
155  if(interface->phyDriver != NULL)
156  {
157  //Ethernet PHY initialization
158  error = interface->phyDriver->init(interface);
159  }
160  else if(interface->switchDriver != NULL)
161  {
162  //Ethernet switch initialization
163  error = interface->switchDriver->init(interface);
164  }
165  else
166  {
167  //The interface is not properly configured
168  error = ERROR_FAILURE;
169  }
170 
171  //Any error to report?
172  if(error)
173  {
174  return error;
175  }
176 
177  //Set the MAC address of the station (upper 16 bits)
178  value = interface->macAddr.b[5];
179  value |= (interface->macAddr.b[4] << 8);
180  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
181 
182  //Set the MAC address of the station (lower 32 bits)
183  value = interface->macAddr.b[3];
184  value |= (interface->macAddr.b[2] << 8);
185  value |= (interface->macAddr.b[1] << 16);
186  value |= (interface->macAddr.b[0] << 24);
187  ENET->PALR = ENET_PALR_PADDR1(value);
188 
189  //Hash table for unicast address filtering
190  ENET->IALR = 0;
191  ENET->IAUR = 0;
192  //Hash table for multicast address filtering
193  ENET->GALR = 0;
194  ENET->GAUR = 0;
195 
196  //Disable transmit accelerator functions
197  ENET->TACC = 0;
198  //Disable receive accelerator functions
199  ENET->RACC = 0;
200 
201  //Use enhanced buffer descriptors
202  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
203 
204  //Reset statistics counters
205  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
206  ENET->MIBC = 0;
207 
208  //Initialize buffer descriptors
209  s32k1EthInitBufferDesc(interface);
210 
211  //Clear any pending interrupts
212  ENET->EIR = 0xFFFFFFFF;
213  //Enable desired interrupts
214  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
215 
216  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
217  NVIC_SetPriorityGrouping(S32K1_ETH_IRQ_PRIORITY_GROUPING);
218 
219  //Configure ENET transmit interrupt priority
220  NVIC_SetPriority(ENET_TX_IRQn, NVIC_EncodePriority(S32K1_ETH_IRQ_PRIORITY_GROUPING,
222 
223  //Configure ENET receive interrupt priority
224  NVIC_SetPriority(ENET_RX_IRQn, NVIC_EncodePriority(S32K1_ETH_IRQ_PRIORITY_GROUPING,
226 
227  //Configure ENET error interrupt priority
228  NVIC_SetPriority(ENET_ERR_IRQn, NVIC_EncodePriority(S32K1_ETH_IRQ_PRIORITY_GROUPING,
230 
231  //Enable Ethernet MAC
232  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
233  //Instruct the DMA to poll the receive descriptor list
234  ENET->RDAR = ENET_RDAR_RDAR_MASK;
235 
236  //Accept any packets from the upper layer
237  osSetEvent(&interface->nicTxEvent);
238 
239  //Successful initialization
240  return NO_ERROR;
241 }
242 
243 
244 /**
245  * @brief GPIO configuration
246  * @param[in] interface Underlying network interface
247  **/
248 
249 __weak_func void s32k1EthInitGpio(NetInterface *interface)
250 {
251 //S32K1-EVB-Q176 evaluation board?
252 #if defined(USE_S32K148_EVB_Q176)
253  //Enable PARTA, PORTB, PORTC and PORTD peripheral clocks
254  PCC->PCCn[PCC_PORTA_INDEX] = PCC_PCCn_CGC_MASK;
255  PCC->PCCn[PCC_PORTB_INDEX] = PCC_PCCn_CGC_MASK;
256  PCC->PCCn[PCC_PORTC_INDEX] = PCC_PCCn_CGC_MASK;
257  PCC->PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;
258 
259  //Configure RMII_RXD1 (PTC0)
260  PORTC->PCR[0] = PORT_PCR_MUX(4);
261  //Configure RMII_RXD0 (PTC1)
262  PORTC->PCR[1] = PORT_PCR_MUX(5);
263  //Configure RMII_TXD0 (PTC2)
264  PORTC->PCR[2] = PORT_PCR_MUX(5);
265  //Configure RMII_RXER (PTC16)
266  //PORTC->PCR[16] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK;
267  //Configure RMII_CRS_DV (PTC17)
268  PORTC->PCR[17] = PORT_PCR_MUX(5);
269  //Configure RMII_TXD1 (PTD7)
270  PORTD->PCR[7] = PORT_PCR_MUX(5);
271  //Configure RMII_REF_CLK (PTD11)
272  PORTD->PCR[11] = PORT_PCR_MUX(5);
273  //Configure RMII_TXEN (PTD12)
274  PORTD->PCR[12] = PORT_PCR_MUX(5);
275 
276  //Configure RMII_MDIO (PTB4)
277  PORTB->PCR[4] = PORT_PCR_MUX(5) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
278  //Configure RMII_MDC (PTB5)
279  PORTB->PCR[5] = PORT_PCR_MUX(7);
280 
281  //Configure ENET_RESET (PTA17) as an output
282  PORTA->PCR[17] = PORT_PCR_MUX(1);
283  PTA->PDDR |= (1 << 17);
284 
285  //Reset PHY transceiver
286  PTA->PCOR |= (1 << 17);
287  sleep(10);
288  PTA->PSOR |= (1 << 17);
289  sleep(10);
290 #endif
291 }
292 
293 
294 /**
295  * @brief Initialize buffer descriptors
296  * @param[in] interface Underlying network interface
297  **/
298 
300 {
301  uint_t i;
302  uint32_t address;
303 
304  //Clear TX and RX buffer descriptors
305  osMemset(txBufferDesc, 0, sizeof(txBufferDesc));
306  osMemset(rxBufferDesc, 0, sizeof(rxBufferDesc));
307 
308  //Initialize TX buffer descriptors
309  for(i = 0; i < S32K1_ETH_TX_BUFFER_COUNT; i++)
310  {
311  //Calculate the address of the current TX buffer
312  address = (uint32_t) txBuffer[i];
313  //Transmit buffer address
314  txBufferDesc[i][1] = address;
315  //Generate interrupts
316  txBufferDesc[i][2] = ENET_TBD2_INT;
317  }
318 
319  //Mark the last descriptor entry with the wrap flag
320  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
321  //Initialize TX buffer index
322  txBufferIndex = 0;
323 
324  //Initialize RX buffer descriptors
325  for(i = 0; i < S32K1_ETH_RX_BUFFER_COUNT; i++)
326  {
327  //Calculate the address of the current RX buffer
328  address = (uint32_t) rxBuffer[i];
329  //The descriptor is initially owned by the DMA
330  rxBufferDesc[i][0] = ENET_RBD0_E;
331  //Receive buffer address
332  rxBufferDesc[i][1] = address;
333  //Generate interrupts
334  rxBufferDesc[i][2] = ENET_RBD2_INT;
335  }
336 
337  //Mark the last descriptor entry with the wrap flag
338  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
339  //Initialize RX buffer index
340  rxBufferIndex = 0;
341 
342  //Start location of the TX descriptor list
343  ENET->TDSR = (uint32_t) txBufferDesc;
344  //Start location of the RX descriptor list
345  ENET->RDSR = (uint32_t) rxBufferDesc;
346  //Maximum receive buffer size
347  ENET->MRBR = S32K1_ETH_RX_BUFFER_SIZE;
348 }
349 
350 
351 /**
352  * @brief S32K1 Ethernet MAC timer handler
353  *
354  * This routine is periodically called by the TCP/IP stack to handle periodic
355  * operations such as polling the link state
356  *
357  * @param[in] interface Underlying network interface
358  **/
359 
360 void s32k1EthTick(NetInterface *interface)
361 {
362  //Valid Ethernet PHY or switch driver?
363  if(interface->phyDriver != NULL)
364  {
365  //Handle periodic operations
366  interface->phyDriver->tick(interface);
367  }
368  else if(interface->switchDriver != NULL)
369  {
370  //Handle periodic operations
371  interface->switchDriver->tick(interface);
372  }
373  else
374  {
375  //Just for sanity
376  }
377 }
378 
379 
380 /**
381  * @brief Enable interrupts
382  * @param[in] interface Underlying network interface
383  **/
384 
386 {
387  //Enable Ethernet MAC interrupts
388  NVIC_EnableIRQ(ENET_TX_IRQn);
389  NVIC_EnableIRQ(ENET_RX_IRQn);
390  NVIC_EnableIRQ(ENET_ERR_IRQn);
391 
392  //Valid Ethernet PHY or switch driver?
393  if(interface->phyDriver != NULL)
394  {
395  //Enable Ethernet PHY interrupts
396  interface->phyDriver->enableIrq(interface);
397  }
398  else if(interface->switchDriver != NULL)
399  {
400  //Enable Ethernet switch interrupts
401  interface->switchDriver->enableIrq(interface);
402  }
403  else
404  {
405  //Just for sanity
406  }
407 }
408 
409 
410 /**
411  * @brief Disable interrupts
412  * @param[in] interface Underlying network interface
413  **/
414 
416 {
417  //Disable Ethernet MAC interrupts
418  NVIC_DisableIRQ(ENET_TX_IRQn);
419  NVIC_DisableIRQ(ENET_RX_IRQn);
420  NVIC_DisableIRQ(ENET_ERR_IRQn);
421 
422  //Valid Ethernet PHY or switch driver?
423  if(interface->phyDriver != NULL)
424  {
425  //Disable Ethernet PHY interrupts
426  interface->phyDriver->disableIrq(interface);
427  }
428  else if(interface->switchDriver != NULL)
429  {
430  //Disable Ethernet switch interrupts
431  interface->switchDriver->disableIrq(interface);
432  }
433  else
434  {
435  //Just for sanity
436  }
437 }
438 
439 
440 /**
441  * @brief Ethernet MAC transmit interrupt
442  **/
443 
445 {
446  bool_t flag;
447 
448  //Interrupt service routine prologue
449  osEnterIsr();
450 
451  //This flag will be set if a higher priority task must be woken
452  flag = FALSE;
453 
454  //Packet transmitted?
455  if((ENET->EIR & ENET_EIR_TXF_MASK) != 0)
456  {
457  //Clear TXF interrupt flag
458  ENET->EIR = ENET_EIR_TXF_MASK;
459 
460  //Check whether the TX buffer is available for writing
461  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
462  {
463  //Notify the TCP/IP stack that the transmitter is ready to send
464  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
465  }
466 
467  //Instruct the DMA to poll the transmit descriptor list
468  ENET->TDAR = ENET_TDAR_TDAR_MASK;
469  }
470 
471  //Interrupt service routine epilogue
472  osExitIsr(flag);
473 }
474 
475 
476 /**
477  * @brief Ethernet MAC receive interrupt
478  **/
479 
481 {
482  bool_t flag;
483 
484  //Interrupt service routine prologue
485  osEnterIsr();
486 
487  //This flag will be set if a higher priority task must be woken
488  flag = FALSE;
489 
490  //Packet received?
491  if((ENET->EIR & ENET_EIR_RXF_MASK) != 0)
492  {
493  //Disable RXF interrupt
494  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
495 
496  //Set event flag
497  nicDriverInterface->nicEvent = TRUE;
498  //Notify the TCP/IP stack of the event
499  flag = osSetEventFromIsr(&netEvent);
500  }
501 
502  //Interrupt service routine epilogue
503  osExitIsr(flag);
504 }
505 
506 
507 /**
508  * @brief Ethernet MAC error interrupt
509  **/
510 
512 {
513  bool_t flag;
514 
515  //Interrupt service routine prologue
516  osEnterIsr();
517 
518  //This flag will be set if a higher priority task must be woken
519  flag = FALSE;
520 
521  //System bus error?
522  if((ENET->EIR & ENET_EIR_EBERR_MASK) != 0)
523  {
524  //Disable EBERR interrupt
525  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
526 
527  //Set event flag
528  nicDriverInterface->nicEvent = TRUE;
529  //Notify the TCP/IP stack of the event
530  flag |= osSetEventFromIsr(&netEvent);
531  }
532 
533  //Interrupt service routine epilogue
534  osExitIsr(flag);
535 }
536 
537 
538 /**
539  * @brief S32K1 Ethernet MAC event handler
540  * @param[in] interface Underlying network interface
541  **/
542 
544 {
545  error_t error;
546  uint32_t status;
547 
548  //Read interrupt event register
549  status = ENET->EIR;
550 
551  //Packet received?
552  if((status & ENET_EIR_RXF_MASK) != 0)
553  {
554  //Clear RXF interrupt flag
555  ENET->EIR = ENET_EIR_RXF_MASK;
556 
557  //Process all pending packets
558  do
559  {
560  //Read incoming packet
561  error = s32k1EthReceivePacket(interface);
562 
563  //No more data in the receive buffer?
564  } while(error != ERROR_BUFFER_EMPTY);
565  }
566 
567  //System bus error?
568  if((status & ENET_EIR_EBERR_MASK) != 0)
569  {
570  //Clear EBERR interrupt flag
571  ENET->EIR = ENET_EIR_EBERR_MASK;
572 
573  //Disable Ethernet MAC
574  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
575  //Reset buffer descriptors
576  s32k1EthInitBufferDesc(interface);
577  //Resume normal operation
578  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
579  //Instruct the DMA to poll the receive descriptor list
580  ENET->RDAR = ENET_RDAR_RDAR_MASK;
581  }
582 
583  //Re-enable Ethernet MAC interrupts
584  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
585 }
586 
587 
588 /**
589  * @brief Send a packet
590  * @param[in] interface Underlying network interface
591  * @param[in] buffer Multi-part buffer containing the data to send
592  * @param[in] offset Offset to the first data byte
593  * @param[in] ancillary Additional options passed to the stack along with
594  * the packet
595  * @return Error code
596  **/
597 
599  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
600 {
601  size_t length;
602 
603  //Retrieve the length of the packet
604  length = netBufferGetLength(buffer) - offset;
605 
606  //Check the frame length
608  {
609  //The transmitter can accept another packet
610  osSetEvent(&interface->nicTxEvent);
611  //Report an error
612  return ERROR_INVALID_LENGTH;
613  }
614 
615  //Make sure the current buffer is available for writing
616  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) != 0)
617  {
618  return ERROR_FAILURE;
619  }
620 
621  //Copy user data to the transmit buffer
622  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
623 
624  //Clear BDU flag
625  txBufferDesc[txBufferIndex][4] = 0;
626 
627  //Check current index
628  if(txBufferIndex < (S32K1_ETH_TX_BUFFER_COUNT - 1))
629  {
630  //Give the ownership of the descriptor to the DMA engine
631  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
633 
634  //Point to the next buffer
635  txBufferIndex++;
636  }
637  else
638  {
639  //Give the ownership of the descriptor to the DMA engine
640  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
642 
643  //Wrap around
644  txBufferIndex = 0;
645  }
646 
647  //Instruct the DMA to poll the transmit descriptor list
648  ENET->TDAR = ENET_TDAR_TDAR_MASK;
649 
650  //Check whether the next buffer is available for writing
651  if((txBufferDesc[txBufferIndex][0] & ENET_TBD0_R) == 0)
652  {
653  //The transmitter can accept another packet
654  osSetEvent(&interface->nicTxEvent);
655  }
656 
657  //Successful processing
658  return NO_ERROR;
659 }
660 
661 
662 /**
663  * @brief Receive a packet
664  * @param[in] interface Underlying network interface
665  * @return Error code
666  **/
667 
669 {
670  error_t error;
671  size_t n;
672  NetRxAncillary ancillary;
673 
674  //Current buffer available for reading?
675  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E) == 0)
676  {
677  //The frame should not span multiple buffers
678  if((rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L) != 0)
679  {
680  //Check whether an error occurred
681  if((rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG | ENET_RBD0_NO |
683  {
684  //Retrieve the length of the frame
685  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
686  //Limit the number of data to read
688 
689  //Additional options can be passed to the stack along with the packet
690  ancillary = NET_DEFAULT_RX_ANCILLARY;
691 
692  //Pass the packet to the upper layer
693  nicProcessPacket(interface, rxBuffer[rxBufferIndex], n, &ancillary);
694 
695  //Valid packet received
696  error = NO_ERROR;
697  }
698  else
699  {
700  //The received packet contains an error
701  error = ERROR_INVALID_PACKET;
702  }
703  }
704  else
705  {
706  //The packet is not valid
707  error = ERROR_INVALID_PACKET;
708  }
709 
710  //Clear BDU flag
711  rxBufferDesc[rxBufferIndex][4] = 0;
712 
713  //Check current index
714  if(rxBufferIndex < (S32K1_ETH_RX_BUFFER_COUNT - 1))
715  {
716  //Give the ownership of the descriptor back to the DMA engine
717  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
718  //Point to the next buffer
719  rxBufferIndex++;
720  }
721  else
722  {
723  //Give the ownership of the descriptor back to the DMA engine
724  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
725  //Wrap around
726  rxBufferIndex = 0;
727  }
728 
729  //Instruct the DMA to poll the receive descriptor list
730  ENET->RDAR = ENET_RDAR_RDAR_MASK;
731  }
732  else
733  {
734  //No more data in the receive buffer
735  error = ERROR_BUFFER_EMPTY;
736  }
737 
738  //Return status code
739  return error;
740 }
741 
742 
743 /**
744  * @brief Configure MAC address filtering
745  * @param[in] interface Underlying network interface
746  * @return Error code
747  **/
748 
750 {
751  uint_t i;
752  uint_t k;
753  uint32_t crc;
754  uint32_t value;
755  uint32_t unicastHashTable[2];
756  uint32_t multicastHashTable[2];
757  MacFilterEntry *entry;
758 
759  //Debug message
760  TRACE_DEBUG("Updating MAC filter...\r\n");
761 
762  //Set the MAC address of the station (upper 16 bits)
763  value = interface->macAddr.b[5];
764  value |= (interface->macAddr.b[4] << 8);
765  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
766 
767  //Set the MAC address of the station (lower 32 bits)
768  value = interface->macAddr.b[3];
769  value |= (interface->macAddr.b[2] << 8);
770  value |= (interface->macAddr.b[1] << 16);
771  value |= (interface->macAddr.b[0] << 24);
772  ENET->PALR = ENET_PALR_PADDR1(value);
773 
774  //Clear hash table (unicast address filtering)
775  unicastHashTable[0] = 0;
776  unicastHashTable[1] = 0;
777 
778  //Clear hash table (multicast address filtering)
779  multicastHashTable[0] = 0;
780  multicastHashTable[1] = 0;
781 
782  //The MAC address filter contains the list of MAC addresses to accept
783  //when receiving an Ethernet frame
784  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
785  {
786  //Point to the current entry
787  entry = &interface->macAddrFilter[i];
788 
789  //Valid entry?
790  if(entry->refCount > 0)
791  {
792  //Compute CRC over the current MAC address
793  crc = s32k1EthCalcCrc(&entry->addr, sizeof(MacAddr));
794 
795  //The upper 6 bits in the CRC register are used to index the
796  //contents of the hash table
797  k = (crc >> 26) & 0x3F;
798 
799  //Multicast address?
800  if(macIsMulticastAddr(&entry->addr))
801  {
802  //Update the multicast hash table
803  multicastHashTable[k / 32] |= (1 << (k % 32));
804  }
805  else
806  {
807  //Update the unicast hash table
808  unicastHashTable[k / 32] |= (1 << (k % 32));
809  }
810  }
811  }
812 
813  //Write the hash table (unicast address filtering)
814  ENET->IALR = unicastHashTable[0];
815  ENET->IAUR = unicastHashTable[1];
816 
817  //Write the hash table (multicast address filtering)
818  ENET->GALR = multicastHashTable[0];
819  ENET->GAUR = multicastHashTable[1];
820 
821  //Debug message
822  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
823  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
824  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
825  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
826 
827  //Successful processing
828  return NO_ERROR;
829 }
830 
831 
832 /**
833  * @brief Adjust MAC configuration parameters for proper operation
834  * @param[in] interface Underlying network interface
835  * @return Error code
836  **/
837 
839 {
840  //Disable Ethernet MAC while modifying configuration registers
841  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
842 
843  //10BASE-T or 100BASE-TX operation mode?
844  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
845  {
846  //100 Mbps operation
847  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
848  }
849  else
850  {
851  //10 Mbps operation
852  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
853  }
854 
855  //Half-duplex or full-duplex mode?
856  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
857  {
858  //Full-duplex mode
859  ENET->TCR |= ENET_TCR_FDEN_MASK;
860  //Receive path operates independently of transmit
861  ENET->RCR &= ~ENET_RCR_DRT_MASK;
862  }
863  else
864  {
865  //Half-duplex mode
866  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
867  //Disable reception of frames while transmitting
868  ENET->RCR |= ENET_RCR_DRT_MASK;
869  }
870 
871  //Reset buffer descriptors
872  s32k1EthInitBufferDesc(interface);
873 
874  //Re-enable Ethernet MAC
875  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
876  //Instruct the DMA to poll the receive descriptor list
877  ENET->RDAR = ENET_RDAR_RDAR_MASK;
878 
879  //Successful processing
880  return NO_ERROR;
881 }
882 
883 
884 /**
885  * @brief Write PHY register
886  * @param[in] opcode Access type (2 bits)
887  * @param[in] phyAddr PHY address (5 bits)
888  * @param[in] regAddr Register address (5 bits)
889  * @param[in] data Register value
890  **/
891 
892 void s32k1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
893  uint8_t regAddr, uint16_t data)
894 {
895  uint32_t temp;
896 
897  //Valid opcode?
898  if(opcode == SMI_OPCODE_WRITE)
899  {
900  //Set up a write operation
901  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
902  //PHY address
903  temp |= ENET_MMFR_PA(phyAddr);
904  //Register address
905  temp |= ENET_MMFR_RA(regAddr);
906  //Register value
907  temp |= ENET_MMFR_DATA(data);
908 
909  //Clear MII interrupt flag
910  ENET->EIR = ENET_EIR_MII_MASK;
911  //Start a write operation
912  ENET->MMFR = temp;
913 
914  //Wait for the write to complete
915  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
916  {
917  }
918  }
919  else
920  {
921  //The MAC peripheral only supports standard Clause 22 opcodes
922  }
923 }
924 
925 
926 /**
927  * @brief Read PHY register
928  * @param[in] opcode Access type (2 bits)
929  * @param[in] phyAddr PHY address (5 bits)
930  * @param[in] regAddr Register address (5 bits)
931  * @return Register value
932  **/
933 
934 uint16_t s32k1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
935  uint8_t regAddr)
936 {
937  uint16_t data;
938  uint32_t temp;
939 
940  //Valid opcode?
941  if(opcode == SMI_OPCODE_READ)
942  {
943  //Set up a read operation
944  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
945  //PHY address
946  temp |= ENET_MMFR_PA(phyAddr);
947  //Register address
948  temp |= ENET_MMFR_RA(regAddr);
949 
950  //Clear MII interrupt flag
951  ENET->EIR = ENET_EIR_MII_MASK;
952  //Start a read operation
953  ENET->MMFR = temp;
954 
955  //Wait for the read to complete
956  while((ENET->EIR & ENET_EIR_MII_MASK) == 0)
957  {
958  }
959 
960  //Get register value
961  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
962  }
963  else
964  {
965  //The MAC peripheral only supports standard Clause 22 opcodes
966  data = 0;
967  }
968 
969  //Return the value of the PHY register
970  return data;
971 }
972 
973 
974 /**
975  * @brief CRC calculation
976  * @param[in] data Pointer to the data over which to calculate the CRC
977  * @param[in] length Number of bytes to process
978  * @return Resulting CRC value
979  **/
980 
981 uint32_t s32k1EthCalcCrc(const void *data, size_t length)
982 {
983  uint_t i;
984  uint_t j;
985  uint32_t crc;
986  const uint8_t *p;
987 
988  //Point to the data over which to calculate the CRC
989  p = (uint8_t *) data;
990  //CRC preset value
991  crc = 0xFFFFFFFF;
992 
993  //Loop through data
994  for(i = 0; i < length; i++)
995  {
996  //Update CRC value
997  crc ^= p[i];
998 
999  //The message is processed bit by bit
1000  for(j = 0; j < 8; j++)
1001  {
1002  if((crc & 0x01) != 0)
1003  {
1004  crc = (crc >> 1) ^ 0xEDB88320;
1005  }
1006  else
1007  {
1008  crc = crc >> 1;
1009  }
1010  }
1011  }
1012 
1013  //Return CRC value
1014  return crc;
1015 }
#define rxBuffer
#define txBuffer
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
Debugging facilities.
#define TRACE_DEBUG(...)
Definition: debug.h:107
#define TRACE_INFO(...)
Definition: debug.h:95
uint8_t n
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
@ ERROR_BUFFER_EMPTY
Definition: error.h:141
@ NO_ERROR
Success.
Definition: error.h:44
@ ERROR_INVALID_PACKET
Definition: error.h:140
@ ERROR_INVALID_LENGTH
Definition: error.h:111
@ ERROR_FAILURE
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:133
#define ETH_MTU
Definition: ethernet.h:116
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:95
Ipv6Addr address[]
Definition: ipv6.h:316
#define ENET_RBD0_E
#define ENET_RBD0_DATA_LENGTH
#define ENET_TBD2_INT
#define ENET_TBD0_W
#define ENET_TBD0_R
#define ENET_RBD0_L
#define ENET_RBD0_NO
#define ENET_RBD0_W
#define ENET_RBD0_LG
#define ENET_TBD0_DATA_LENGTH
#define ENET_RBD2_INT
#define ENET_RBD0_OV
#define ENET_TBD0_TC
#define ENET_RBD0_CR
#define ENET_TBD0_L
#define ENET_RBD0_TR
#define MPU_CESR_VLD_MASK
#define MPU
uint16_t regAddr
uint8_t p
Definition: ndp.h:300
TCP/IP stack core.
#define NetInterface
Definition: net.h:36
#define netEvent
Definition: net_legacy.h:196
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:674
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
Definition: net_misc.c:101
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
Definition: nic.c:391
#define SMI_OPCODE_WRITE
Definition: nic.h:66
@ NIC_TYPE_ETHERNET
Ethernet interface.
Definition: nic.h:83
#define SMI_OPCODE_READ
Definition: nic.h:67
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
@ NIC_LINK_SPEED_100MBPS
Definition: nic.h:112
#define osMemset(p, value, length)
Definition: os_port.h:135
#define MIN(a, b)
Definition: os_port.h:63
#define TRUE
Definition: os_port.h:50
#define FALSE
Definition: os_port.h:46
#define sleep(delay)
Definition: os_port.h:301
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define osEnterIsr()
#define osExitIsr(flag)
void ENET_TX_IRQHandler(void)
Ethernet MAC transmit interrupt.
const NicDriver s32k1EthDriver
S32K1 Ethernet MAC driver.
void s32k1EthTick(NetInterface *interface)
S32K1 Ethernet MAC timer handler.
uint32_t s32k1EthCalcCrc(const void *data, size_t length)
CRC calculation.
error_t s32k1EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void s32k1EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
void s32k1EthDisableIrq(NetInterface *interface)
Disable interrupts.
void s32k1EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t s32k1EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void ENET_RX_IRQHandler(void)
Ethernet MAC receive interrupt.
__weak_func void s32k1EthInitGpio(NetInterface *interface)
GPIO configuration.
error_t s32k1EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t s32k1EthInit(NetInterface *interface)
S32K1 Ethernet MAC initialization.
void s32k1EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void ENET_ERR_IRQHandler(void)
Ethernet MAC error interrupt.
error_t s32k1EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void s32k1EthEventHandler(NetInterface *interface)
S32K1 Ethernet MAC event handler.
error_t s32k1EthReceivePacket(NetInterface *interface)
Receive a packet.
NXP S32K1 Ethernet MAC driver.
#define S32K1_ETH_RX_BUFFER_SIZE
#define S32K1_ETH_IRQ_PRIORITY_GROUPING
#define S32K1_ETH_IRQ_SUB_PRIORITY
#define S32K1_ETH_IRQ_GROUP_PRIORITY
#define S32K1_ETH_RX_BUFFER_COUNT
#define S32K1_ETH_TX_BUFFER_COUNT
#define S32K1_ETH_TX_BUFFER_SIZE
MAC filter table entry.
Definition: ethernet.h:262
MacAddr addr
MAC address.
Definition: ethernet.h:263
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:264
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368
uint8_t value[]
Definition: tcp.h:369