32 #define TRACE_LEVEL NIC_TRACE_LEVEL
45 #if defined(__ICCARM__)
48 #pragma data_alignment = 8
49 #pragma location = SAM9X60_ETH1_RAM_SECTION
52 #pragma data_alignment = 8
53 #pragma location = SAM9X60_ETH1_RAM_SECTION
56 #pragma data_alignment = 4
57 #pragma location = SAM9X60_ETH1_RAM_SECTION
60 #pragma data_alignment = 4
61 #pragma location = SAM9X60_ETH1_RAM_SECTION
83 static uint_t txBufferIndex;
85 static uint_t rxBufferIndex;
122 volatile uint32_t temp;
125 TRACE_INFO(
"Initializing SAM9X60 Ethernet MAC (EMAC0)...\r\n");
128 nicDriverInterface = interface;
131 PMC->PMC_PCR = PMC_PCR_PID(ID_EMAC0);
133 PMC->PMC_PCR = temp | PMC_PCR_CMD | PMC_PCR_EN;
142 EMAC0->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
144 EMAC0->EMAC_NCR |= EMAC_NCR_MPE;
147 if(interface->phyDriver != NULL)
150 error = interface->phyDriver->init(interface);
152 else if(interface->switchDriver != NULL)
155 error = interface->switchDriver->init(interface);
170 EMAC0->EMAC_SA[0].EMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
171 EMAC0->EMAC_SA[0].EMAC_SAT = interface->macAddr.w[2];
174 EMAC0->EMAC_SA[1].EMAC_SAB = 0;
175 EMAC0->EMAC_SA[2].EMAC_SAB = 0;
176 EMAC0->EMAC_SA[3].EMAC_SAB = 0;
183 EMAC0->EMAC_NCFGR |= EMAC_NCFGR_BIG | EMAC_NCFGR_MTI;
189 EMAC0->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
190 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
192 EMAC0->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
195 EMAC0->EMAC_IDR = 0xFFFFFFFF;
197 EMAC0->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
198 EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
201 temp = EMAC0->EMAC_ISR;
205 AIC->AIC_SSR = ID_EMAC0;
210 AIC->AIC_ICCR = (1 << ID_EMAC0);
213 EMAC0->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
231 #if defined(USE_SAM9X60_EK)
235 PMC->PMC_PCR = PMC_PCR_PID(ID_PIOB);
237 PMC->PMC_PCR = temp | PMC_PCR_CMD | PMC_PCR_EN;
250 EMAC0->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
289 rxBufferDesc[i].
status = 0;
298 EMAC0->EMAC_TBQP = (uint32_t) txBufferDesc;
300 EMAC0->EMAC_RBQP = (uint32_t) rxBufferDesc;
316 if(interface->phyDriver != NULL)
319 interface->phyDriver->tick(interface);
321 else if(interface->switchDriver != NULL)
324 interface->switchDriver->tick(interface);
341 AIC->AIC_SSR = AIC_SSR_INTSEL(ID_EMAC0);
342 AIC->AIC_IECR = AIC_IECR_INTEN;
345 if(interface->phyDriver != NULL)
348 interface->phyDriver->enableIrq(interface);
350 else if(interface->switchDriver != NULL)
353 interface->switchDriver->enableIrq(interface);
370 AIC->AIC_SSR = AIC_SSR_INTSEL(ID_EMAC0);
371 AIC->AIC_IDCR = AIC_IDCR_INTD;
374 if(interface->phyDriver != NULL)
377 interface->phyDriver->disableIrq(interface);
379 else if(interface->switchDriver != NULL)
382 interface->switchDriver->disableIrq(interface);
398 volatile uint32_t isr;
399 volatile uint32_t tsr;
400 volatile uint32_t rsr;
410 isr = EMAC0->EMAC_ISR;
411 tsr = EMAC0->EMAC_TSR;
412 rsr = EMAC0->EMAC_RSR;
416 if((tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
417 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR)) != 0)
420 EMAC0->EMAC_TSR = tsr;
423 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
431 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
434 nicDriverInterface->nicEvent =
TRUE;
439 #if (NET_RTOS_SUPPORT == DISABLED)
460 rsr = EMAC0->EMAC_RSR;
463 if((rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA)) != 0)
466 EMAC0->EMAC_RSR = rsr;
508 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) == 0)
537 EMAC0->EMAC_NCR |= EMAC_NCR_TSTART;
540 if((txBufferDesc[txBufferIndex].status &
EMAC_TX_USED) != 0)
578 j = rxBufferIndex + i;
601 if((rxBufferDesc[j].status &
EMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
615 if(eofIndex != UINT_MAX)
619 else if(sofIndex != UINT_MAX)
632 for(i = 0; i < j; i++)
635 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
695 uint32_t hashTable[2];
703 EMAC0->EMAC_SA[0].EMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
704 EMAC0->EMAC_SA[0].EMAC_SAT = interface->macAddr.w[2];
720 entry = &interface->macAddrFilter[i];
732 k = (
p[0] >> 6) ^
p[0];
733 k ^= (
p[1] >> 4) ^ (
p[1] << 2);
734 k ^= (
p[2] >> 2) ^ (
p[2] << 4);
735 k ^= (
p[3] >> 6) ^
p[3];
736 k ^= (
p[4] >> 4) ^ (
p[4] << 2);
737 k ^= (
p[5] >> 2) ^ (
p[5] << 4);
743 hashTable[k / 32] |= (1 << (k % 32));
751 unicastMacAddr[j++] = entry->
addr;
761 EMAC0->EMAC_SA[1].EMAC_SAB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
762 EMAC0->EMAC_SA[1].EMAC_SAT = unicastMacAddr[0].w[2];
767 EMAC0->EMAC_SA[1].EMAC_SAB = 0;
774 EMAC0->EMAC_SA[2].EMAC_SAB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
775 EMAC0->EMAC_SA[2].EMAC_SAT = unicastMacAddr[1].w[2];
780 EMAC0->EMAC_SA[2].EMAC_SAB = 0;
787 EMAC0->EMAC_SA[3].EMAC_SAB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
788 EMAC0->EMAC_SA[4].EMAC_SAT = unicastMacAddr[2].w[2];
793 EMAC0->EMAC_SA[3].EMAC_SAB = 0;
797 EMAC0->EMAC_HRB = hashTable[0];
798 EMAC0->EMAC_HRT = hashTable[1];
801 TRACE_DEBUG(
" HRB = %08" PRIX32
"\r\n", EMAC0->EMAC_HRB);
802 TRACE_DEBUG(
" HRT = %08" PRIX32
"\r\n", EMAC0->EMAC_HRT);
820 config = EMAC0->EMAC_NCFGR;
825 config |= EMAC_NCFGR_SPD;
829 config &= ~EMAC_NCFGR_SPD;
835 config |= EMAC_NCFGR_FD;
839 config &= ~EMAC_NCFGR_FD;
843 EMAC0->EMAC_NCFGR = config;
867 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
869 temp |= EMAC_MAN_PHYA(phyAddr);
871 temp |= EMAC_MAN_REGA(
regAddr);
873 temp |= EMAC_MAN_DATA(
data);
876 EMAC0->EMAC_MAN = temp;
878 while((EMAC0->EMAC_NSR & EMAC_NSR_IDLE) == 0)
907 temp = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
909 temp |= EMAC_MAN_PHYA(phyAddr);
911 temp |= EMAC_MAN_REGA(
regAddr);
914 EMAC0->EMAC_MAN = temp;
916 while((EMAC0->EMAC_NSR & EMAC_NSR_IDLE) == 0)
921 data = EMAC0->EMAC_MAN & EMAC_MAN_DATA_Msk;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define ETH_MAX_FRAME_SIZE
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EMAC_RX_OWNERSHIP
void sam9x60Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void sam9x60Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
const NicDriver sam9x60Eth1Driver
SAM9X60 Ethernet MAC driver (EMAC0 instance)
error_t sam9x60Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
__weak_func void sam9x60Eth1InitGpio(NetInterface *interface)
GPIO configuration.
error_t sam9x60Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void sam9x60Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
void sam9x60Eth1IrqHandler(void)
SAM9X60 Ethernet MAC interrupt service routine.
error_t sam9x60Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
void sam9x60Eth1EventHandler(NetInterface *interface)
SAM9X60 Ethernet MAC event handler.
void sam9x60Eth1Tick(NetInterface *interface)
SAM9X60 Ethernet MAC timer handler.
error_t sam9x60Eth1Init(NetInterface *interface)
SAM9X60 Ethernet MAC initialization.
uint16_t sam9x60Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void sam9x60Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t sam9x60Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
SAM9X60 Ethernet MAC driver (EMAC0 instance)
#define SAM9X60_ETH1_RX_BUFFER_SIZE
#define SAM9X60_ETH1_TX_BUFFER_COUNT
#define SAM9X60_ETH1_RX_BUFFER_COUNT
#define SAM9X60_ETH1_RAM_SECTION
#define SAM9X60_ETH1_IRQ_PRIORITY
#define SAM9X60_ETH1_TX_BUFFER_SIZE
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.
Receive buffer descriptor.
Transmit buffer descriptor.