sama5d3_eth2_driver.c

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/**
 * @file sama5d3_eth2_driver.c
 * @brief SAMA5D3 Gigabit Ethernet MAC driver (GMAC instance)
 *
 * @section License
 *
 * SPDX-License-Identifier: GPL-2.0-or-later
 *
 * Copyright (C) 2010-2026 Oryx Embedded SARL. All rights reserved.
 *
 * This file is part of CycloneTCP Open.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * @author Oryx Embedded SARL (www.oryx-embedded.com)
 * @version 2.6.0
 **/
 
//Switch to the appropriate trace level
#define TRACE_LEVEL NIC_TRACE_LEVEL
 
//Dependencies
#include <limits.h>
#include "chip.h"
#include "barriers.h"
#include "core/net.h"
#include "drivers/mac/sama5d3_eth2_driver.h"
#include "debug.h"
 
//Underlying network interface
static NetInterface *nicDriverInterface;
 
//IAR EWARM compiler?
#if defined(__ICCARM__)
 
//TX buffer
#pragma data_alignment = 8
#pragma location = SAMA5D3_ETH2_RAM_SECTION
static uint8_t txBuffer[SAMA5D3_ETH2_TX_BUFFER_COUNT][SAMA5D3_ETH2_TX_BUFFER_SIZE];
//RX buffer
#pragma data_alignment = 8
#pragma location = SAMA5D3_ETH2_RAM_SECTION
static uint8_t rxBuffer[SAMA5D3_ETH2_RX_BUFFER_COUNT][SAMA5D3_ETH2_RX_BUFFER_SIZE];
//TX buffer descriptors
#pragma data_alignment = 8
#pragma location = SAMA5D3_ETH2_RAM_SECTION
static Sama5d3Eth2TxBufferDesc txBufferDesc[SAMA5D3_ETH2_TX_BUFFER_COUNT];
//RX buffer descriptors
#pragma data_alignment = 8
#pragma location = SAMA5D3_ETH2_RAM_SECTION
static Sama5d3Eth2RxBufferDesc rxBufferDesc[SAMA5D3_ETH2_RX_BUFFER_COUNT];
 
//GCC compiler?
#else
 
//TX buffer
static uint8_t txBuffer[SAMA5D3_ETH2_TX_BUFFER_COUNT][SAMA5D3_ETH2_TX_BUFFER_SIZE]
   __attribute__((aligned(8), __section__(SAMA5D3_ETH2_RAM_SECTION)));
//RX buffer
static uint8_t rxBuffer[SAMA5D3_ETH2_RX_BUFFER_COUNT][SAMA5D3_ETH2_RX_BUFFER_SIZE]
   __attribute__((aligned(8), __section__(SAMA5D3_ETH2_RAM_SECTION)));
//TX buffer descriptors
static Sama5d3Eth2TxBufferDesc txBufferDesc[SAMA5D3_ETH2_TX_BUFFER_COUNT]
   __attribute__((aligned(8), __section__(SAMA5D3_ETH2_RAM_SECTION)));
//RX buffer descriptors
static Sama5d3Eth2RxBufferDesc rxBufferDesc[SAMA5D3_ETH2_RX_BUFFER_COUNT]
   __attribute__((aligned(8), __section__(SAMA5D3_ETH2_RAM_SECTION)));
 
#endif
 
//TX buffer index
static uint_t txBufferIndex;
//RX buffer index
static uint_t rxBufferIndex;
 
 
/**
 * @brief SAMA5D3 Ethernet MAC driver (GMAC instance)
 **/
 
const NicDriver sama5d3Eth2Driver =
{
   NIC_TYPE_ETHERNET,
   ETH_MTU,
   sama5d3Eth2Init,
   sama5d3Eth2Tick,
   sama5d3Eth2EnableIrq,
   sama5d3Eth2DisableIrq,
   sama5d3Eth2EventHandler,
   sama5d3Eth2SendPacket,
   sama5d3Eth2UpdateMacAddrFilter,
   sama5d3Eth2UpdateMacConfig,
   sama5d3Eth2WritePhyReg,
   sama5d3Eth2ReadPhyReg,
   TRUE,
   TRUE,
   TRUE,
   FALSE
};
 
 
/**
 * @brief SAMA5D3 Ethernet MAC initialization
 * @param[in] interface Underlying network interface
 * @return Error code
 **/
 
error_t sama5d3Eth2Init(NetInterface *interface)
{
   error_t error;
   volatile uint32_t status;
 
   //Debug message
   TRACE_INFO("Initializing SAMA5D3 Ethernet MAC (GMAC)...\r\n");
 
   //Save underlying network interface
   nicDriverInterface = interface;
 
   //Enable GMAC peripheral clock
   PMC->PMC_PCER1 = (1 << (ID_GMAC0 - 32));
   //Enable IRQ controller peripheral clock
   PMC->PMC_PCER1 = (1 << (ID_AIC - 32));
 
   //Disable transmit and receive circuits
   GMAC0->GMAC_NCR = 0;
 
   //GPIO configuration
   sama5d3Eth2InitGpio(interface);
 
   //Configure MDC clock speed
   GMAC0->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
   //Enable management port (MDC and MDIO)
   GMAC0->GMAC_NCR |= GMAC_NCR_MPE;
 
   //Valid Ethernet PHY or switch driver?
   if(interface->phyDriver != NULL)
   {
      //Ethernet PHY initialization
      error = interface->phyDriver->init(interface);
   }
   else if(interface->switchDriver != NULL)
   {
      //Ethernet switch initialization
      error = interface->switchDriver->init(interface);
   }
   else
   {
      //The interface is not properly configured
      error = ERROR_FAILURE;
   }
 
   //Any error to report?
   if(error)
   {
      return error;
   }
 
   //Set the MAC address of the station
   GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
   GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
 
   //The MAC supports 3 additional addresses for unicast perfect filtering
   GMAC0->GMAC_SA[1].GMAC_SAB = 0;
   GMAC0->GMAC_SA[2].GMAC_SAB = 0;
   GMAC0->GMAC_SA[3].GMAC_SAB = 0;
 
   //Initialize hash table
   GMAC0->GMAC_HRB = 0;
   GMAC0->GMAC_HRT = 0;
 
   //Configure the receive filter
   GMAC0->GMAC_NCFGR |= GMAC_NCFGR_MAXFS | GMAC_NCFGR_MTIHEN;
 
   //Initialize buffer descriptors
   sama5d3Eth2InitBufferDesc(interface);
 
   //Clear transmit status register
   GMAC0->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP |
      GMAC_TSR_TFC | GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL |
      GMAC_TSR_UBR;
 
   //Clear receive status register
   GMAC0->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC |
      GMAC_RSR_BNA;
 
   //First disable all GMAC interrupts
   GMAC0->GMAC_IDR = 0xFFFFFFFF;
 
   //Only the desired ones are enabled
   GMAC0->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP |
      GMAC_IER_TFC | GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR |
      GMAC_IER_RCOMP;
 
   //Read GMAC_ISR register to clear any pending interrupt
   status = GMAC0->GMAC_ISR;
   (void) status;
 
   //Configure interrupt controller
   AIC->AIC_SSR = ID_GMAC0;
   AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH2_IRQ_PRIORITY);
   AIC->AIC_SVR = (uint32_t) sama5d3Eth2IrqHandler;
 
   //Enable the GMAC to transmit and receive data
   GMAC0->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
 
   //Accept any packets from the upper layer
   osSetEvent(&interface->nicTxEvent);
 
   //Successful initialization
   return NO_ERROR;
}
 
 
/**
 * @brief GPIO configuration
 * @param[in] interface Underlying network interface
 **/
 
__weak_func void sama5d3Eth2InitGpio(NetInterface *interface)
{
//SAMA5D3-Xplained, SAMA5D3-EDS or EVB-KSZ9477 evaluation board?
#if defined(CONFIG_BOARD_SAMA5D3_XPLAINED)
   uint32_t mask;
 
   //Enable PIO peripheral clock
   PMC->PMC_PCER0 = (1 << ID_PIOB);
 
   //Configure RGMII pins
   mask = PIO_PB18A_G125CK | PIO_PB17A_GMDIO | PIO_PB16A_GMDC |
      PIO_PB13A_GRXER | PIO_PB12A_GRXDV | PIO_PB11A_GRXCK | PIO_PB9A_GTXEN |
      PIO_PB8A_GTXCK | PIO_PB7A_GRX3 | PIO_PB6A_GRX2 | PIO_PB5A_GRX1 |
      PIO_PB4A_GRX0 | PIO_PB3A_GTX3 | PIO_PB2A_GTX2 | PIO_PB1A_GTX1 |
      PIO_PB0A_GTX0;
 
   //Disable pull-up resistors on RGMII pins
   PIOB->PIO_PUDR = mask;
   //Disable interrupts-on-change
   PIOB->PIO_IDR = mask;
   //Assign MII pins to peripheral A function
   PIOB->PIO_ABCDSR[0] &= ~mask;
   PIOB->PIO_ABCDSR[1] &= ~mask;
   //Disable the PIO from controlling the corresponding pins
   PIOB->PIO_PDR = mask;
 
   //Select RGMII operation mode
   GMAC0->GMAC_UR = GMAC_UR_RGMII;
#endif
}
 
 
/**
 * @brief Initialize buffer descriptors
 * @param[in] interface Underlying network interface
 **/
 
void sama5d3Eth2InitBufferDesc(NetInterface *interface)
{
   uint_t i;
   uint32_t address;
 
   //Initialize TX buffer descriptors
   for(i = 0; i < SAMA5D3_ETH2_TX_BUFFER_COUNT; i++)
   {
      //Calculate the address of the current TX buffer
      address = (uint32_t) txBuffer[i];
      //Write the address to the descriptor entry
      txBufferDesc[i].address = address;
      //Initialize status field
      txBufferDesc[i].status = GMAC_TX_USED;
   }
 
   //Mark the last descriptor entry with the wrap flag
   txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
   //Initialize TX buffer index
   txBufferIndex = 0;
 
   //Initialize RX buffer descriptors
   for(i = 0; i < SAMA5D3_ETH2_RX_BUFFER_COUNT; i++)
   {
      //Calculate the address of the current RX buffer
      address = (uint32_t) rxBuffer[i];
      //Write the address to the descriptor entry
      rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
      //Clear status field
      rxBufferDesc[i].status = 0;
   }
 
   //Mark the last descriptor entry with the wrap flag
   rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
   //Initialize RX buffer index
   rxBufferIndex = 0;
 
   //Start location of the TX descriptor list
   GMAC0->GMAC_TBQB = (uint32_t) txBufferDesc;
   //Start location of the RX descriptor list
   GMAC0->GMAC_RBQB = (uint32_t) rxBufferDesc;
}
 
 
/**
 * @brief SAMA5D3 Ethernet MAC timer handler
 *
 * This routine is periodically called by the TCP/IP stack to handle periodic
 * operations such as polling the link state
 *
 * @param[in] interface Underlying network interface
 **/
 
void sama5d3Eth2Tick(NetInterface *interface)
{
   //Valid Ethernet PHY or switch driver?
   if(interface->phyDriver != NULL)
   {
      //Handle periodic operations
      interface->phyDriver->tick(interface);
   }
   else if(interface->switchDriver != NULL)
   {
      //Handle periodic operations
      interface->switchDriver->tick(interface);
   }
   else
   {
      //Just for sanity
   }
}
 
 
/**
 * @brief Enable interrupts
 * @param[in] interface Underlying network interface
 **/
 
void sama5d3Eth2EnableIrq(NetInterface *interface)
{
   //Enable Ethernet MAC interrupts
   AIC->AIC_SSR = ID_GMAC0;
   AIC->AIC_IECR = AIC_IECR_INTEN;
 
   //Valid Ethernet PHY or switch driver?
   if(interface->phyDriver != NULL)
   {
      //Enable Ethernet PHY interrupts
      interface->phyDriver->enableIrq(interface);
   }
   else if(interface->switchDriver != NULL)
   {
      //Enable Ethernet switch interrupts
      interface->switchDriver->enableIrq(interface);
   }
   else
   {
      //Just for sanity
   }
}
 
 
/**
 * @brief Disable interrupts
 * @param[in] interface Underlying network interface
 **/
 
void sama5d3Eth2DisableIrq(NetInterface *interface)
{
   //Disable Ethernet MAC interrupts
   AIC->AIC_SSR = ID_GMAC0;
   AIC->AIC_IDCR = AIC_IDCR_INTD;
 
   //Valid Ethernet PHY or switch driver?
   if(interface->phyDriver != NULL)
   {
      //Disable Ethernet PHY interrupts
      interface->phyDriver->disableIrq(interface);
   }
   else if(interface->switchDriver != NULL)
   {
      //Disable Ethernet switch interrupts
      interface->switchDriver->disableIrq(interface);
   }
   else
   {
      //Just for sanity
   }
}
 
 
/**
 * @brief SAMA5D3 Ethernet MAC interrupt service routine
 **/
 
void sama5d3Eth2IrqHandler(void)
{
   bool_t flag;
   volatile uint32_t isr;
   volatile uint32_t tsr;
   volatile uint32_t rsr;
 
   //Interrupt service routine prologue
   osEnterIsr();
 
   //This flag will be set if a higher priority task must be woken
   flag = FALSE;
 
   //Each time the software reads GMAC_ISR, it has to check the contents
   //of GMAC_TSR, GMAC_RSR and GMAC_NSR
   isr = GMAC0->GMAC_ISR;
   tsr = GMAC0->GMAC_TSR;
   rsr = GMAC0->GMAC_RSR;
   (void) isr;
 
   //Packet transmitted?
   if((tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
      GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR)) != 0)
   {
      //Only clear TSR flags that are currently set
      GMAC0->GMAC_TSR = tsr;
 
      //Avoid DMA lockup by sending only one frame at a time (see errata 57.5.1)
      if((txBufferDesc[0].status & GMAC_TX_USED) != 0 &&
         (txBufferDesc[1].status & GMAC_TX_USED) != 0)
      {
         //Notify the TCP/IP stack that the transmitter is ready to send
         flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
      }
   }
 
   //Packet received?
   if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
   {
      //Set event flag
      nicDriverInterface->nicEvent = TRUE;
      //Notify the TCP/IP stack of the event
      flag |= osSetEventFromIsr(&nicDriverInterface->netContext->event);
   }
 
   //Write AIC_EOICR register before exiting
   AIC->AIC_EOICR = 0;
 
   //Interrupt service routine epilogue
   osExitIsr(flag);
}
 
 
/**
 * @brief SAMA5D3 Ethernet MAC event handler
 * @param[in] interface Underlying network interface
 **/
 
void sama5d3Eth2EventHandler(NetInterface *interface)
{
   error_t error;
   uint32_t rsr;
 
   //Read receive status
   rsr = GMAC0->GMAC_RSR;
 
   //Packet received?
   if((rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) != 0)
   {
      //Only clear RSR flags that are currently set
      GMAC0->GMAC_RSR = rsr;
 
      //Process all pending packets
      do
      {
         //Read incoming packet
         error = sama5d3Eth2ReceivePacket(interface);
 
         //No more data in the receive buffer?
      } while(error != ERROR_BUFFER_EMPTY);
   }
}
 
 
/**
 * @brief Send a packet
 * @param[in] interface Underlying network interface
 * @param[in] buffer Multi-part buffer containing the data to send
 * @param[in] offset Offset to the first data byte
 * @param[in] ancillary Additional options passed to the stack along with
 *   the packet
 * @return Error code
 **/
 
error_t sama5d3Eth2SendPacket(NetInterface *interface,
   const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
{
   size_t length;
 
   //Retrieve the length of the packet
   length = netBufferGetLength(buffer) - offset;
 
   //Check the frame length
   if(length > SAMA5D3_ETH2_TX_BUFFER_SIZE)
   {
      //The transmitter can accept another packet
      osSetEvent(&interface->nicTxEvent);
      //Report an error
      return ERROR_INVALID_LENGTH;
   }
 
   //Make sure the current buffer is available for writing
   if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) == 0)
   {
      return ERROR_FAILURE;
   }
 
   //Copy user data to the transmit buffer
   netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
 
   //Set the necessary flags in the descriptor entry
   if(txBufferIndex < (SAMA5D3_ETH2_TX_BUFFER_COUNT - 1))
   {
      //Write the status word
      txBufferDesc[txBufferIndex].status = GMAC_TX_LAST |
         (length & GMAC_TX_LENGTH);
 
      //Point to the next buffer
      txBufferIndex++;
   }
   else
   {
      //Write the status word
      txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP | GMAC_TX_LAST |
         (length & GMAC_TX_LENGTH);
 
      //Wrap around
      txBufferIndex = 0;
   }
 
   //Data synchronization barrier
   dsb();
 
   //Set the TSTART bit to initiate transmission
   GMAC0->GMAC_NCR |= GMAC_NCR_TSTART;
 
   //Check whether the next buffer is available for writing
   if((txBufferDesc[txBufferIndex].status & GMAC_TX_USED) != 0)
   {
      //The transmitter can accept another packet
      osSetEvent(&interface->nicTxEvent);
   }
 
   //Successful processing
   return NO_ERROR;
}
 
 
/**
 * @brief Receive a packet
 * @param[in] interface Underlying network interface
 * @return Error code
 **/
 
error_t sama5d3Eth2ReceivePacket(NetInterface *interface)
{
   static uint32_t temp[ETH_MAX_FRAME_SIZE / 4];
   error_t error;
   uint_t i;
   uint_t j;
   uint_t sofIndex;
   uint_t eofIndex;
   size_t n;
   size_t size;
   size_t length;
 
   //Initialize variables
   size = 0;
   sofIndex = UINT_MAX;
   eofIndex = UINT_MAX;
 
   //Search for SOF and EOF flags
   for(i = 0; i < SAMA5D3_ETH2_RX_BUFFER_COUNT; i++)
   {
      //Point to the current entry
      j = rxBufferIndex + i;
 
      //Wrap around to the beginning of the buffer if necessary
      if(j >= SAMA5D3_ETH2_RX_BUFFER_COUNT)
      {
         j -= SAMA5D3_ETH2_RX_BUFFER_COUNT;
      }
 
      //No more entries to process?
      if((rxBufferDesc[j].address & GMAC_RX_OWNERSHIP) == 0)
      {
         //Stop processing
         break;
      }
 
      //A valid SOF has been found?
      if((rxBufferDesc[j].status & GMAC_RX_SOF) != 0)
      {
         //Save the position of the SOF
         sofIndex = i;
      }
 
      //A valid EOF has been found?
      if((rxBufferDesc[j].status & GMAC_RX_EOF) != 0 && sofIndex != UINT_MAX)
      {
         //Save the position of the EOF
         eofIndex = i;
         //Retrieve the length of the frame
         size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
         //Limit the number of data to read
         size = MIN(size, ETH_MAX_FRAME_SIZE);
         //Stop processing since we have reached the end of the frame
         break;
      }
   }
 
   //Determine the number of entries to process
   if(eofIndex != UINT_MAX)
   {
      j = eofIndex + 1;
   }
   else if(sofIndex != UINT_MAX)
   {
      j = sofIndex;
   }
   else
   {
      j = i;
   }
 
   //Total number of bytes that have been copied from the receive buffer
   length = 0;
 
   //Process incoming frame
   for(i = 0; i < j; i++)
   {
      //Any data to copy from current buffer?
      if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
      {
         //Calculate the number of bytes to read at a time
         n = MIN(size, SAMA5D3_ETH2_RX_BUFFER_SIZE);
         //Copy data from receive buffer
         osMemcpy((uint8_t *) temp + length, rxBuffer[rxBufferIndex], n);
         //Update byte counters
         length += n;
         size -= n;
      }
 
      //Mark the current buffer as free
      rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
 
      //Point to the following entry
      rxBufferIndex++;
 
      //Wrap around to the beginning of the buffer if necessary
      if(rxBufferIndex >= SAMA5D3_ETH2_RX_BUFFER_COUNT)
      {
         rxBufferIndex = 0;
      }
   }
 
   //Any packet to process?
   if(length > 0)
   {
      NetRxAncillary ancillary;
 
      //Additional options can be passed to the stack along with the packet
      ancillary = NET_DEFAULT_RX_ANCILLARY;
 
      //Pass the packet to the upper layer
      nicProcessPacket(interface, (uint8_t *) temp, length, &ancillary);
      //Valid packet received
      error = NO_ERROR;
   }
   else
   {
      //No more data in the receive buffer
      error = ERROR_BUFFER_EMPTY;
   }
 
   //Return status code
   return error;
}
 
 
/**
 * @brief Configure MAC address filtering
 * @param[in] interface Underlying network interface
 * @return Error code
 **/
 
error_t sama5d3Eth2UpdateMacAddrFilter(NetInterface *interface)
{
   uint_t i;
   uint_t j;
   uint_t k;
   uint8_t *p;
   uint32_t hashTable[2];
   MacAddr unicastMacAddr[3];
   MacFilterEntry *entry;
 
   //Debug message
   TRACE_DEBUG("Updating MAC filter...\r\n");
 
   //Set the MAC address of the station
   GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
   GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
 
   //The MAC supports 3 additional addresses for unicast perfect filtering
   unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR;
   unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR;
   unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR;
 
   //The hash table is used for multicast address filtering
   hashTable[0] = 0;
   hashTable[1] = 0;
 
   //The MAC address filter contains the list of MAC addresses to accept
   //when receiving an Ethernet frame
   for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++)
   {
      //Point to the current entry
      entry = &interface->macAddrFilter[i];
 
      //Valid entry?
      if(entry->refCount > 0)
      {
         //Multicast address?
         if(macIsMulticastAddr(&entry->addr))
         {
            //Point to the MAC address
            p = entry->addr.b;
 
            //Apply the hash function
            k = (p[0] >> 6) ^ p[0];
            k ^= (p[1] >> 4) ^ (p[1] << 2);
            k ^= (p[2] >> 2) ^ (p[2] << 4);
            k ^= (p[3] >> 6) ^ p[3];
            k ^= (p[4] >> 4) ^ (p[4] << 2);
            k ^= (p[5] >> 2) ^ (p[5] << 4);
 
            //The hash value is reduced to a 6-bit index
            k &= 0x3F;
 
            //Update hash table contents
            hashTable[k / 32] |= (1 << (k % 32));
         }
         else
         {
            //Up to 3 additional MAC addresses can be specified
            if(j < 3)
            {
               //Save the unicast address
               unicastMacAddr[j] = entry->addr;
            }
            else
            {
               //Point to the MAC address
               p = entry->addr.b;
 
               //Apply the hash function
               k = (p[0] >> 6) ^ p[0];
               k ^= (p[1] >> 4) ^ (p[1] << 2);
               k ^= (p[2] >> 2) ^ (p[2] << 4);
               k ^= (p[3] >> 6) ^ p[3];
               k ^= (p[4] >> 4) ^ (p[4] << 2);
               k ^= (p[5] >> 2) ^ (p[5] << 4);
 
               //The hash value is reduced to a 6-bit index
               k &= 0x3F;
 
               //Update hash table contents
               hashTable[k / 32] |= (1 << (k % 32));
            }
 
            //Increment the number of unicast addresses
            j++;
         }
      }
   }
 
   //Configure the first unicast address filter
   if(j >= 1)
   {
      //The address is activated when SAT register is written
      GMAC0->GMAC_SA[1].GMAC_SAB = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
      GMAC0->GMAC_SA[1].GMAC_SAT = unicastMacAddr[0].w[2];
   }
   else
   {
      //The address is deactivated when SAB register is written
      GMAC0->GMAC_SA[1].GMAC_SAB = 0;
   }
 
   //Configure the second unicast address filter
   if(j >= 2)
   {
      //The address is activated when SAT register is written
      GMAC0->GMAC_SA[2].GMAC_SAB = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
      GMAC0->GMAC_SA[2].GMAC_SAT = unicastMacAddr[1].w[2];
   }
   else
   {
      //The address is deactivated when SAB register is written
      GMAC0->GMAC_SA[2].GMAC_SAB = 0;
   }
 
   //Configure the third unicast address filter
   if(j >= 3)
   {
      //The address is activated when SAT register is written
      GMAC0->GMAC_SA[3].GMAC_SAB = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
      GMAC0->GMAC_SA[3].GMAC_SAT = unicastMacAddr[2].w[2];
   }
   else
   {
      //The address is deactivated when SAB register is written
      GMAC0->GMAC_SA[3].GMAC_SAB = 0;
   }
 
   //The perfect MAC filter supports only 3 unicast addresses
   if(j >= 4)
   {
      GMAC0->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN;
   }
   else
   {
      GMAC0->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN;
   }
 
   //Configure the multicast hash table
   GMAC0->GMAC_HRB = hashTable[0];
   GMAC0->GMAC_HRT = hashTable[1];
 
   //Debug message
   TRACE_DEBUG("  HRB = 0x%08" PRIX32 "\r\n", GMAC0->GMAC_HRB);
   TRACE_DEBUG("  HRT = 0x%08" PRIX32 "\r\n", GMAC0->GMAC_HRT);
 
   //Successful processing
   return NO_ERROR;
}
 
 
/**
 * @brief Adjust MAC configuration parameters for proper operation
 * @param[in] interface Underlying network interface
 * @return Error code
 **/
 
error_t sama5d3Eth2UpdateMacConfig(NetInterface *interface)
{
   uint32_t config;
 
   //Read network configuration register
   config = GMAC0->GMAC_NCFGR;
 
   //1000BASE-T operation mode?
   if(interface->linkSpeed == NIC_LINK_SPEED_1GBPS)
   {
      config |= GMAC_NCFGR_GBE;
      config &= ~GMAC_NCFGR_SPD;
   }
   //100BASE-TX operation mode?
   else if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
   {
      config &= ~GMAC_NCFGR_GBE;
      config |= GMAC_NCFGR_SPD;
   }
   //10BASE-T operation mode?
   else
   {
      config &= ~GMAC_NCFGR_GBE;
      config &= ~GMAC_NCFGR_SPD;
   }
 
   //Half-duplex or full-duplex mode?
   if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
   {
      config |= GMAC_NCFGR_FD;
   }
   else
   {
      config &= ~GMAC_NCFGR_FD;
   }
 
   //Write configuration value back to NCFGR register
   GMAC0->GMAC_NCFGR = config;
 
   //Successful processing
   return NO_ERROR;
}
 
 
/**
 * @brief Write PHY register
 * @param[in] opcode Access type (2 bits)
 * @param[in] phyAddr PHY address (5 bits)
 * @param[in] regAddr Register address (5 bits)
 * @param[in] data Register value
 **/
 
void sama5d3Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
   uint8_t regAddr, uint16_t data)
{
   uint32_t temp;
 
   //Valid opcode?
   if(opcode == SMI_OPCODE_WRITE)
   {
      //Set up a write operation
      temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
      //PHY address
      temp |= GMAC_MAN_PHYA(phyAddr);
      //Register address
      temp |= GMAC_MAN_REGA(regAddr);
      //Register value
      temp |= GMAC_MAN_DATA(data);
 
      //Start a write operation
      GMAC0->GMAC_MAN = temp;
      //Wait for the write to complete
      while((GMAC0->GMAC_NSR & GMAC_NSR_IDLE) == 0)
      {
      }
   }
   else
   {
      //The MAC peripheral only supports standard Clause 22 opcodes
   }
}
 
 
/**
 * @brief Read PHY register
 * @param[in] opcode Access type (2 bits)
 * @param[in] phyAddr PHY address (5 bits)
 * @param[in] regAddr Register address (5 bits)
 * @return Register value
 **/
 
uint16_t sama5d3Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
   uint8_t regAddr)
{
   uint16_t data;
   uint32_t temp;
 
   //Valid opcode?
   if(opcode == SMI_OPCODE_READ)
   {
      //Set up a read operation
      temp = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
      //PHY address
      temp |= GMAC_MAN_PHYA(phyAddr);
      //Register address
      temp |= GMAC_MAN_REGA(regAddr);
 
      //Start a read operation
      GMAC0->GMAC_MAN = temp;
      //Wait for the read to complete
      while((GMAC0->GMAC_NSR & GMAC_NSR_IDLE) == 0)
      {
      }
 
      //Get register value
      data = GMAC0->GMAC_MAN & GMAC_MAN_DATA_Msk;
   }
   else
   {
      //The MAC peripheral only supports standard Clause 22 opcodes
      data = 0;
   }
 
   //Return the value of the PHY register
   return data;
}